Abstract: A method of manufacturing a wireless suspension blank is a method of manufacturing a wireless blank in which three-layered laminate formed of a metallic layer having the spring property and a conductive layer laminated on the metallic layer through an electrically insulating layer are used, wherein as the laminate used is a laminate in which an insulating layer is formed of core-insulating layer and adhesive layers laminated on both sides of the core-insulating layer, and the ratio of higher etching rate to lower etching rate of the respective layers of the insulating layer is between 6:1 and 1:1. By the photo etching method processed are the metallic layer and the conductive layer. The insulating layer is processed by the wet etching method.

Abstract: A process for forming an inorganic material layer pattern on a substrate. The process includes the steps of transferring an inorganic powder dispersed paste layer supported on a support film to the surface of the substrate to form the inorganic powder dispersed paste layer on the substrate; forming a resist film on the inorganic powder dispersed paste layer transferred to the surface of the substrate; exposing the resist film to light through a mask to form a latent image of a resist pattern; developing the exposed resist film to form the resist pattern; etching exposed portions of the inorganic powder dispersed paste layer to form an inorganic powder dispersed paste layer pattern corresponding to the resist pattern; and baking the pattern to form an inorganic material layer pattern.

Abstract: A new pattern is provided for the bus lines that are used to facilitate plating of layers of electrical lines that form a Printed Circuit Board. Where Prior Art bus lines have a straight-line geometry, the bus lines of the invention have any geometry that is not a straight-line geometry. The geometry of the bus lines of the invention can be of any design as long as this design allows for interrupted cutting of the bus line, that is the cutting tool does not, during the process of cutting the bus line, make constant and continuous contact with the bus line.

Abstract: A semiconductor element mounting interposer is produced by (A) forming a conducting circuit that comprises motherboard connecting electrodes 2 and plated leads 3 on an insulating base film 1; (B) forming a patterning resin layer 5 over the conducting circuit 4; (C) etching patterning resin layer 5 so as to expose the motherboard connecting electrodes 2 and plated leads 3; (D) masking plated leads 3 with an electroplating resist layer 6; (E) depositing an electroplated metal layer 7 over the exposed motherboard connecting electrodes 2; (F) removing the electroplating resist layer 6; (G) removing the exposed plated leads 3 through etching; and (H) where the patterning resin layer 5 is a polyimide precursor layer, bringing about complete imidation of the polyimide precursor layer.

Abstract: A process for the preparation of an electrode, which comprises: (1) transferring a conductive paste layer supported on a base film to a substrate to form the conductive paste layer on the substrate; (2) forming a resist film on the conductive paste layer transferred to the substrate; (3) exposing the resist film through a mask to form a resist pattern latent image; (4) developing the exposed resist film to form a resist pattern; (5) etching exposed portions of the conductive paste layer to form a conductive paste layer pattern corresponding to the resist pattern; and (6) thermosetting the pattern to form a conductive layer pattern.

Abstract: A method for producing a foil circuit board including a plurality of flexible electrically non-conductive and flexible conductive layers, which are laminated together. The non-conductive layers are positioned between the conductive layers and two of the conductive layers are the outermost surface layers of the foil circuit board. The circuit board includes flexible areas and rigid areas, and the flexible areas are provided by etching the board to remove at least part of one of the outermost surface layers and an adjacent underlying non-conductive layer.

Abstract: A leadless integrated circuit package, comprising an exposed semiconductor die and contact pads embedded in an over mold, and wires interconnecting the semiconductor die and contact pads.

Abstract: A circuit board having a structure including a permanent photoimageable dielectric material suitable for fabrication of vias both by laser ablation, plasma ablation, or mechanical drilling techniques and by photoimaging techniques. A process is also disclosed for the manufacture of a multi-level circuit on a substrate having a first-level circuitry pattern on at least one side. The process comprises applying a permanent photoimageable dielectric over the first-level circuitry pattern; exposing the permanent photoimageable dielectric to radiation; laminating a conductive metal layer to the dielectric; making holes in the conductive metal layer and dielectric by mechanical drilling or by laser or plasma ablation; and making a second-level circuitry pattern and filling the holes with a conductive material to electrically connect the first and second layers of circuitry.

Abstract: A multilayer rigid flex printed circuit board wherein the board laminate comprises a basestock composite containing a flexible core, formed by laminating a first conductive layer to a flexible insulator layer, a second insulator layer affixed to the basestock, said second insulator layer having a cutout region proximate to the flexible core of the basestock composite to expose a portion of said first conducting layer on said flexible core, a second conductive layer attached to said second insulator layer said second conductive layer having a cutout region proximate to the flexible core of the basestock composite, and a photo-imageable soldermask applied to the exposed portion said first conducting layer, and to the second conductive layer, wherein said photoimageable soldermask allows for photo definition of openings on the conductive layers to which it is applied.

Abstract: The present invention is for a method wherein a printed circuit board can be fabricated in an electroless process with a minimum number of manufacturing steps using mild etchant conditions on an intermediary seed layer to produce low-defect, fine conductive line printed circuit boards.

Abstract: A method for preparing a semiconductor member comprises: forming a substrate having a non-porous silicon monocrystalline layer and a porous silicon layer; bonding another substrate having a surface made of an insulating material to the surface of the monocrystalline layer; and etching to remove the porous silicon layer by immersing in an etching solution.

Abstract: A method for preparing a semiconductor member comprises: forming a substrate having a non-porous silicon monocrystalline layer and a porous silicon layer; bonding another substrate having a surface made of an insulating material to the surface of the monocrystalline layer; and etching to remove the porous silicon layer by immersing in an etching solution.

Abstract: Resistors are formed by selective etching from layered thin film material comprising an insulating substrate, a resistive material which is a mixture of a zero valence metal and a dielectric material, and a layer of conductive material.

Abstract: A method for contacting at least one printed circuit board or at least one punched grid and at least one hybrid includes the steps of: forming contact elements in a contacting foil, positioning the contacting foil over the hybrid in such a way that the contact elements are arranged at preselected positions between the printed circuit traces of the hybrid and the printed circuit traces of the printed circuit board, and etching away at least a portion of the contacting foil, such that the contact elements are at least partially freely accessible.

Abstract: A process for fabricating and releasing a thin-film structure from a primary carrier for further processing. The thin-film structure is built on a metal interconnect disposed on a dielectric layer which, in turn, is deposited on a primary carrier. The thin-film structure and metal interconnect are released from the dielectric layer and primary carrier along a release interface defined between the metal interconnect and the dielectric film. Release is accomplished by disturbing the interface, either by laser ablation or dicing.

Abstract: A package for a microelectronic element is made by making a microelectronic component, including embossing a metal sheet to form thin and thick regions, then etching or otherwise removing metal from the sheet in a nonselective removal process and arresting the removal process when the thin regions are removed but before the thick regions are removed. A base material may be applied to the metal sheet to form a dielectric layer for the component. The component is assembled with a microelectronic element to form the package.

Abstract: A process for making a printed circuit board is provided. The process employs a noble metal as an etch mask for subtractive circuitization and as a seed layer for secondary finishing. In a preferred embodiment of the invention, a dielectric is covered by a conductive layer of metal such as copper, a patterned photoresist is applied, additional copper is deposited on areas not covered by the photoresist, and a palladium etch mask/seed layer is deposited on the copper. The palladium layer remains sufficiently active for deposition of nickel or gold on the circuitry for purposes such as wire bonding.

Abstract: The multilayer foil circuit board according to the invention has rigid (s) and flexible (f) areas and in the rigid areas has more foil layers than in the flexible areas. The foil circuit board according to the invention is produced so that in the intended flexible areas (f) at least on one side at least the outermost foil layer (1.2) is removed by etching. By a corresponding etching mask design, it is possible to allow the flexible areas (f) to pass continuously into the rigid areas (s) in that the removal of the layers in the marginal areas (u) is less than in the center (z) of the flexible area (f), so that there are no marginal areas which have a tendency to break. The etching of the flexible areas can be performed in the same method stage as the etching of the plated through holes through the corresponding foil layer (1.2) or in a separate etching stage.

Abstract: A method for forming a through-via in a laminated substrate by laser drilling the through-via in a laminated substrate from a top exposed surface of the substrate to a bottom exposed surface of the substrate using a plurality of laser pulses that are trepanned in a first predetermined pattern. Each pulse trepanned in the first predetermined pattern has a first energy density per pulse. Then, the through-via is laser drilled using a plurality of laser pulses that are trepanned in a second predetermined pattern. Each pulse trepanned in the second predetermined pattern has a second energy density per pulse that is greater than the first energy density per pulse. The second predetermined pattern is within the first predetermined pattern.

Abstract: A method of making a laminated substrate by forming a registration mark on a core layer of the substrate. Then, forming a first layer on the core layer using the registration mark as a fiducial registration point. The first layer is laser drilled through to expose the registration mark on the core layer. A second layer is then formed on the first layer using the registration mark as a fiducial point.

Abstract: A method of forming a multi-layer laminate from a plurality of individual laminates comprised of copper clad on a polyimide.

Abstract: In a rigid/flex circuit board and fabricating process, patterns of electrical traces are formed by etching conductive layers on outer surfaces of a flexible multi-layer circuit structure. A protective barrier material is deposited on the etched traces using an "electroless" process, such as immersion of the flexible circuit board in an aqueous solution containing ionic tin. The protective barrier material adheres to and encapsulates the copper traces. An outer circuit structure including a bondfilm of epoxy-impregnated fiberglass ("prepreg" bondfilm) and a copper foil layer is laminated onto the flexible circuit structure. The prepreg bondfilm has a window area removed by routing or an equivalent process prior to being laminated to the flexible structure. The window area defines a flex area of the rigid/flex circuit board that will be relatively flexible.

Abstract: A method for fabricating an SOI substrate is provided, which has an active substrate formed as a thin film. The method comprises the steps of: using a both-side polishing apparatus to polish both sides of a supporting substrate 1; bonding an active substrate 2 onto the supporting substrate 1. to form a bonded-wafer; removing an unbonded portion formed at the circumference of the bonded-wafer; flat grinding the active substrate 2 to reduce the thickness thereof; etching the active substrate 2 by spin etching; and processing the active substrate to be a thin film by PACE processing.

Abstract: This invention relates to an aqueous etching composition for etching metallic copper comprising(a) an acid,(b) a copper complexing agent,(c) a metal capable of having a multiplicity of oxidation states which is present in one of its higher positive oxidation states and which metal forms a composition soluble salt, and(d) oxygen wherein the concentration of the higher positive oxidation state metal in the composition is greater than about 4 grams/liter of composition.The invention also relates to a process for etching metallic copper comprising contacting the surface of a copper substrate with the aqueous etching compositions of the invention. A method of regenerating a spent aqueous etching composition of the invention which has been used for etching metallic copper also is described.

Abstract: A semiconductor package includes a laminate of substrates having a cavity 16, through-holes 25 and circuit patterns, wherein the through-holes 45 and some of the circuit patterns 18 are coated with a plated nickel/gold coating 50.

Abstract: The present invention comprises methods of contact printing of patterned, self-assembling monolayers of alkanethiolates, carboxylic acids, hydroxamic acids, and phosphonic acids on metallized thermoplastic films, the compositions produced thereby, and the use of these compositions. Patterned self-assembling monolayers allow for the controlled placement of fluids thereon which contain a chemically reactive, indicator functionality. The optical sensing devices produced thereby when the film is exposed to an analyte and light, can produce optical diffraction patterns which differ depending on the reaction of the self-assembling monolayer with the analyte of interest. The light can be in the visible spectrum, and be either reflected from the film, or transmitted through it, and the analyte can be any compound reacting with the fluid on the self-assembling monolayer. The present invention also provides a flexible support for a self-assembling monolayer on gold or another suitable metal.

Abstract: A process for fabricating and releasing a thin-film structure from a primary carrier for further processing. The thin-film structure is built on a metal interconnect disposed on a dielectric layer which, in turn, is deposited on a primary carrier. The thin-film structure and metal interconnect are released from the dielectric layer and primary carrier along a release interface defined between the metal interconnect and the dielectric film. Release is accomplished by disturbing the interface, either by laser ablation or dicing.

Abstract: A single step electroplating process for interconnect via fill and metal line formation on a semiconductor substrate is disclosed. In this process, a barrier layer is formed onto a surface of a substrate that has at least one via and then a conductive layer is formed onto the barrier layer. Next, a photoresist layer is applied and patterned on top of the conductive layer. The via plugs and metal lines are then deposited on the substrate simultaneously using an electroplating process. After the electroplating process is completed, the photoresist and the conductive layer between the deposited metal lines are removed. The process provides a simple, economical and highly controllable means of forming metal interconnect systems while avoiding the difficulties associated with depositing and patterning metal by traditional semiconductor fabrication techniques.

Abstract: Method of fabricating high density multilayer interconnect structures or flexible HDMI decals. The methods secure a top surface of an HDMI decal fabricated on a rigid substrate to a protective film layer which is in turn adhesively secured to a flat carrier. This structure is then demounted or delaminated from the rigid substrate. The bottom of the HDMI decal, with the protective film layer and flat carrier attached thereto, is secured to a mounting substrate using a relatively thick adhesive layer. After the HDMI decal is adhesively secured to the mounting substrate, the carrier and protective film layer are removed. The top surface of the HDMI decal thus remains flat after it is secured to the mounting substrate, and therefore connection of integrated circuit chips to contact pads on the top surface of the decal is ensured because this surface is flat. The carrier and protective film layer also protects the top surface of the decal while it is secured to the mounting substrate.

Abstract: A structure includes a support layer formed of a conductive material, such as a sheet of copper. The support layer has a number of conductive islands isolated from other portions of the support layer by isolation gaps. The support layer is sandwiched between two compound layers each of which is formed of a dielectric layer having a number of via holes and conductive elements located in the via holes. The conductive elements are formed at predetermined locations such that a conductive element in each compound layer contacts a conductive island in the support layer. The structure also includes two conductive layers formed on the two respective compound layers such that a trace in a first conductive layer is coupled to a trace in a second conductive layer through two conductive elements in the respective two compound layers and an island in the support layer. Such a structure can be formed by a number of processes.

Abstract: Photoimageable dielectric materials are coated on substrates, selectively exposed and developed, whereby small vias and interconnection openings are formed between adjacently spaced circuit layers. A conductive paste may be used to provide sequential layer interconnection and surface planarization. No adhesives are required in the manufacture of a circuit assembly having multiple circuit and dielectric layers, and the manufacturing method avoids the requirement for drilled through holes and blind vias.

Abstract: A method of forming a conductive network, having relatively flexible electrical conductor areas integral with relatively rigid electrically conductor areas including (a) providing a relatively rigid laminate having a dielectric lamina supporting, at least in part, a first electrically conductive lamina which is in electrically conductive intimate contact with a second electrically conductive lamina by way of an electrically conductive barrier layer, the first and second conductive laminae being of a material etchable by an etchant which is not an etchant for the barrier layer; (b) selectively etching desired portions of the aid second electrically conductive lamina to the barrier layer in at least the relatively flexible areas using the etchant; and (c) selectively etching desired exposed metallic portions of the laminate down to the dielectric lamina to form the conductive network using an etchant, the etchant chosen to etch both the conductive lamina and the barrier layer.

Abstract: A printed circuit board to support an integrated circuit and provide thermal dissipation. A layer of thermally conductive material is disposed between lower and upper dielectric layers. Above this structure is disposed another layer of thermally conductive material to be thermally coupled to an integrated circuit. A thermal via couples the two layers of thermally conductive material to each other.

Abstract: A method of manufacturing a multilayer circuit substrate includes a process of forming via holes in an insulating film, a process of applying an electrically conducting paste obtained by having ultra-fine metal particles disperse in a solvent onto an insulating film, and a process of forming vias composed of a sintered product of ultra-fine metal particles in the via holes by removing the solvent and also sintering the ultra-fine metal particles. The sintered products of the ultra-fine metal particles on the insulating layer is removed (or patterned) by peeling off the protective film stuck to the insulating layer.

Abstract: A method of manufacturing an improved multi-layer printed circuit assembly having at least two conductor patterns. The method includes providing a first layer having a first metal surface a second layer having a second metal surface. A thin flexible carrier is placed between the first and second layers. The first and second layers are attached to opposite surfaces of the carrier. The first and second metal surfaces are etched to form first and second conductor patterns. The conductor patterns form the electrical traces interconnecting components on an electronic circuit assembly. The first and second conductor patterns are electrically connected to form an electronic circuit assembly that includes electronic traces on both sides of the circuit board.

Abstract: A method and apparatus for coupling high speed data components using imbedded PCB AC coupling capacitors is disclosed. The capacitor comprises a first and a second conductive plate of polygonal shape coupled to surrounding circuitry at the polygonal vertices of the polygonal plates. This configuration results in improved capacitor performance, particularly with respect to capacitive impedance and reflected waves for high bandwidth signals at the frequency ranges of interest.

Abstract: Applique circuits suitable for advanced packaging applications are introduced. These structures are particularly suited for the simple integration of large amounts (many nanoFarads) of capacitance into conventional integrated circuit and multichip packaging technology. In operation, applique circuits are bonded to the integrated circuit or other appropriate structure at the point where the capacitance is required, thereby minimizing the effects of parasitic coupling. An immediate application is to problems of noise reduction and control in modern high-frequency circuitry.

Abstract: A resin composition comprising (a) an epoxy resin having a number average molecular weight of 1200 or less, (b) a carboxylic acid-containing acrylic or acrylonitrile-butadiene rubber, (c) a curing agent for the epoxy resin, and (d) a curing accelerator is easily chemically etched and suitable as an insulating adhesive for producing multilayer printed circuit boards.

Abstract: A desired circuit wiring pattern is formed by plating a conductive layer having excellent resistance at least to an etching solution on a metal layer which is removed in the post-process by etching. A surface protective layer having a hole for exposing part of the circuit wiring pattern is formed on both sides of the circuit wiring pattern at a predetermined position as an external connection terminal portion. The circuit wiring pattern can be formed in multiple layers by coating the conductive layer with a circuit wiring layer of another conductive material and a bump is formed to fill the hole as required.

Abstract: A method for forming a blind-via in a laminated substrate by laser drilling a blind-via from a top surface of the substrate toward a bottom surface of the substrate using a first laser and a first trepanning motion of a laser focal spot of the first laser. Then, the via is laser drilled from the top surface toward the bottom surface using a second laser and a second trepanning motion of a laser focal spot of the second laser.

Abstract: A composition for reducing a copper oxide layer to metallic copper so as to facilitate bonding a resin to the metallic copper is disclosed. The composition is an aqueous reducing solution containing a cyclic borane compound. Examples of such cyclic borane compounds include those having nitrogen or sulfur as a ring-forming member, such as morpholine borane, piperidine borane, pyridine borane, piperazine borane, 2,6-Iutidine borane, 4-methylmorpholine borane, and 1,4-oxathiane borane, and also N,N-diethylaniline borane.

Abstract: An apparatus for retaining a workpiece and a method of fabricating same. The apparatus contains an electrostatic chuck having a workpiece support surface. The workpiece support surface has protruded regions and non-protruded regions, where a total surface area of the protruded regions is less than a total surface area of the non-protruded regions. The apparatus contains a pedestal having a surface that supports a flex circuit. The topography of the chuck is formed by either machining the surface of the pedestal prior to adhering and conforming the flex circuit to the surface or sculpting the surface of an electrode within the flex circuit.

Abstract: A multilayer printed circuit board small in interlayer thickness, capable of fine wiring, minimized in IVH and BVH diameters, high in strength and also excellent in wire bonding workability can be produced by a process comprising the steps of coating a thermosetting resin varnish compounded with electrically insulating whiskers on a roughened side of a copper foil, semi-curing the resin by heating to form a thermosetting resin layer, integrally laminating it on an interlayer board in which plated through-holes and conductor circudits have been formed, and roughening the cured thermosetting resin layer on the via hole wall surfaces with a roughening agent.

Abstract: A multilayered printed circuit board is produced by (a) forming a resin layer on an inner circuit substrate and abrading it to expose the circuit conductors, (b) contacting a copper foil having a layer of insulating adhesive composed of an epoxy resin, a carboxylic acid-containing acrylic or acrylonitrile-butadiene rubber, a curing agent and accelerator with the resin layer and exposed circuit conductors, (c) removing portions necessary for connection with the copper foil and insulating adhesive exposed to the holes by etching, (d) connecting the copper foil with circuits exposed to the holes and forming a surface circuit by processing the outer layer of the copper foil, and (e) repeating steps (a) to (d) to obtained a multilayered structure.

Abstract: A method of forming a via in a laminated substrate by placing a first mask between an output optics of a laser and an exposed surface of a laminated substrate. The first mask has a first aperture corresponding to a location of a via in the substrate. A second mask is placed between the first mask and the output optics of the laser. The second mask has a second aperture disposed within a main beam of a laser beam output from the laser and blocks side lobes of the laser beam from reaching the exposed surface of the substrate.

Abstract: A metalization structure having a first conductor layer on the surface of an underlying layer and, further, a second conductor layer connected conductively with the first conductor layer in which a polyimide insulative film of low thermal expansion coefficient is present between at least an end of a pattern of the second conductor layer and the first conductor layer, for stably obtaining a metalization structure of high reliability and free from the worry of peeling of the conductor portion from a substrate or occurrence of cracking to the underlying layer.

Abstract: A method of manufacturing TAB tapes comprising the steps of (1) to (5):(1) laminating a protection film-covered adhesive layer on the entire surface of at least one face of a base film except both the edge portions thereof thereby to obtain a laminated portion, the base film being enough wide to provide a base film for each of the intended plural TAB tapes each having a desired width;(2) drilling sprocket holes in the thus obtained laminated portion comprising the base film and the protection film-covered adhesive layer and in both the edge portions of said base film and drilling device holes in said laminated portion;(3) peeling said protection film off the adhesive layer, and adhering a copper foil to said adhesive layer;(4) applying a photoresist to said copper foil, exposing and developing the photoresist-applied copper foil and then etching the photoresist-developed copper foil to form wiring patterns thereby to obtain a wide TAB tape in which plural strips of TAB tape having the disired width are origin

Abstract: The present invention in one embodiment provides a metal detector comprising a coil, a circuit board on which the coil is etched, a digital signal processor, and a warning circuit, and battery power source. When a sufficient amount of metal is near the coil, the digital signal processor activates a device or devices in the warning circuit. In another embodiment the circuit board on which the coil is placed is used in conjunction with a one piece molded housing. In another embodiment the present invention, provides a metal detector comprising an elongated coil etched onto an elongated circuit board. At least one active device, which is part of detection circuitry is also preferably placed on the elongated circuit board. The detection circuitry in one embodiment, includes circuitry which together with the elongated coil forms an oscillator circuit. The elongated covering case in one embodiment is molded substantially seamlessly by blowmold, extrusion, or injection mold.

Abstract: The present invention provides a process for fabricating an SOI substrate with no peripheral scratches and with enhanced fabrication efficiency. The present process includes bonding a semiconductor wafer of an active substrate 1 and a semiconductor base wafer 2 to form a bonded wafer 4; surface-grinding the active substrate 1; spin etching the surface-ground active substrate 1; and PACE processing the etched active substrate 1 to form the active substrate into a thin film and simultaneously, to remove the non-bonded peripheral portion of the bonded wafer 4.

Abstract: This invention describes a new process for the selective isolation of through holes in the production of a multi-layer printed circuit card which allows for substantially smaller holes through reference layers to be built, leading to substantially better electrical isolation of signal traces on adjacent wiring layers, and for substantially improved current carrying capacity in the reference layers. This invention also describes a process to allow reference layers of different thickness from adjacent signal layers, even if they are part of the same `core`. Several different process flows are disclosed, leading to substantially the same structure but with varying degrees of complexity and quality of the finished product.