Etching Of Semiconductor Material To Produce An Article Having A Nonelectrical Function Patents (Class 216/2)
  • Patent number: 10768202
    Abstract: The presently disclosed subject matter provides systems and methods for generating nanostructures from tribological films. A probe tip can be immersed in a liquid mixture comprising a plurality of ink particles suspended in a medium. A substrate on which the tribological film is to be generated can also be immersed in the liquid mixture. A processor controlling movement of the probe tip can be configured to cause the probe tip to slide along the substrate in a shape of a desired pattern of the nanostructure with a contact force to cause one or more ink particles of the plurality of ink particles compressed underneath the probe tip to be transformed into a tribological film onto the substrate in the shape of the desired pattern of the nanostructure.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: September 8, 2020
    Assignee: THE TRUSTEES OF THE UNIVERSITY OF PENNSYLVANIA
    Inventors: Robert W. Carpick, Harmandeep S. Khare, Nitya Nand Gosvami, Imene Lahouij
  • Patent number: 10745273
    Abstract: MEMS switches and methods of manufacturing MEMS switches is provided. The MEMS switch having at least two cantilevered electrodes having ends which overlap and which are structured and operable to contact one another upon an application of a voltage by at least one fixed electrode.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: August 18, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen E. Luce, Anthony K. Stamper
  • Patent number: 10741398
    Abstract: A method for forming reliefs on a face of a substrate is provided, successively including forming a protective screen for protecting at least a first zone of the face; an implanting to introduce at least one species comprising carbon into the substrate from the face of the substrate, the forming of the protective screen and the implanting being configured to form, in the substrate, at least one carbon modified layer having a concentration of implanted carbon greater than or equal to an etching threshold only from a second zone of the face of the substrate not protected by the protective screen; removing the protective screen; and etching the substrate from the first zone selectively with respect to the second zone.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: August 11, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Lamia Nouri, Stefan Landis, Nicolas Posseme
  • Patent number: 10737936
    Abstract: A method of fabricating a semiconductor structure includes: providing a first wafer; providing a second wafer having a first surface and a second surface opposite to the first surface; contacting the first surface of the second wafer with the first wafer; and forming a plurality of scribe lines on the second surface of the second wafer; wherein the plurality of scribe lines protrudes from a third surface of the second wafer, and the third surface is between the first surface and the second surface.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: August 11, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wei-Cheng Shen, Yi-Hsien Chang, Yi-Heng Tsai, Chun-Ren Cheng
  • Patent number: 10743109
    Abstract: An acoustic liquid transfer system that includes a processor; a source holding component configured to hold a source microplate; a destination holding component configured to hold a destination microplate; an acoustic transducer configured to cause liquid to transfer between the source and destination microplates; and a controller configured to direct movements, according to an ordered picklist, of one or more of the: source holding component, destination holding component, and acoustic transducer.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: August 11, 2020
    Assignee: Recursion Pharmaceuticals, Inc.
    Inventors: Nicholas Campbell, Charles Baker
  • Patent number: 10679846
    Abstract: The present disclosure involves forming a porous low-k dielectric structure. A plurality of conductive elements is formed over the substrate. The conductive elements are separated from one another by a plurality of openings. A barrier layer is formed over the conductive elements. The barrier layer is formed to cover sidewalls of the openings. A treatment process is performed to the barrier layer. The barrier layer becomes hydrophilic after the treatment process is performed. A dielectric material is formed over the barrier layer after the treatment process has been performed. The dielectric material fills the openings and contains a plurality of porogens.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: June 9, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Bo-Jiun Lin, Hai-Ching Chen, Tien-I Bao
  • Patent number: 10668436
    Abstract: Provided are monolithic structures comprising one or more suspended, nanoporous membranes that are in contact with one or more fluidic cavities, methods of making same, and exemplary uses of same. The monolithic structures can be formed using a transmembrane etch. The monolithic structures can be used, as examples, as filters and filtration modules in microfluidic devices, dialysis devices, and concentration devices in laboratory, industrial, and medical processes.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: June 2, 2020
    Assignee: SiMPore Inc.
    Inventors: Christopher C. Striemer, Joshua J. Miller, Jon-Paul S. Desormeaux, James A. Roussie
  • Patent number: 10649338
    Abstract: The present invention has an object of providing a stepped wafer that can prevent a resist from remaining after development, and a method for manufacturing the stepped wafer. The stepped wafer according to the present invention is a stepped wafer having a step and whose main surface is thinner in a center portion and is thicker in an outer periphery. The step includes a curved surface with a radius of curvature ranging from 300 ?m to 1800 ?m.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: May 12, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventor: Naoyuki Takeda
  • Patent number: 10625445
    Abstract: Disclosed is a method for manufacturing a substrate-integrated gasket using screen printing. The method includes: a step for forming, on a surface of a substrate by means of screen printing, a coating layer of a paste for forming a gasket; and a step for hardening the coating layer by pressing, at a predetermined height, a coating layer correction member to the coating layer. The cross-sectional shape of the coating layer formed on the surface of the substrate is corrected by means of the coating layer correction member, and in such state, the coating layer hardens to be a gasket, thereby forming a gasket having a highly accurate cross-sectional shape.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: April 21, 2020
    Assignee: NOK CORPORATION
    Inventors: Hajime Yui, Tetsuya Urakawa, Kenichi Oba
  • Patent number: 10622247
    Abstract: A cost effective process flow for manufacturing semiconductor on insulator structures is parallel is provided. Each of the multiple semiconductor-on-insulator composite structures prepared in parallel includes a charge trapping layer (CTL).
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: April 14, 2020
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Igor Peidous, Andrew M Jones, Srikanth Kommu, Horacio Josue Mendez
  • Patent number: 10611631
    Abstract: In described examples, a cavity is formed between a substrate and a cap. One or more access holes are formed through the cap for removing portions of a sacrificial layer from within the cavity. A cover is supported by the cap, where the cover is for occulting the one or more access holes along a perspective. An encapsulant seals the cavity, where the encapsulant encapsulates the cover and the one or more access holes.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: April 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Jose Antonio Martinez
  • Patent number: 10589988
    Abstract: A mechanical component has: a mounting; a movable part which, with the aid of at least one first spring and one second spring, is connected to the mounting in such a way that the movable part is movable about a rotational axis extending through a first anchoring area of the first spring on the mounting and a second anchoring area of the second spring on the mounting; a first sensor device with at least one first resistor which is situated on and/or in the first spring; and a second sensor device with at least one second resistor situated on and/or in the second spring. The first sensor device includes a first Wheatstone half bridge and the second sensor device includes a second Wheatstone half bridge. The first and second Wheatstone half bridges are connected to form a Wheatstone full bridge.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: March 17, 2020
    Assignee: Robert Bosch GmbH
    Inventors: Wolfgang Heinzelmann, Mohamad Iyad Al Dibs, Rainer Straub, Stefan Pinter, Frederic Njikam Njimonzie, Joerg Muchow, Helmut Grutzeck, Simon Armbruster, Sebastian Reiss
  • Patent number: 10589992
    Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: March 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael T. Brigham, Christopher V. Jahnes, Cameron E. Luce, Jeffrey C. Maling, William J. Murphy, Anthony K. Stamper, Eric J. White
  • Patent number: 10582617
    Abstract: A circuit module includes a plurality of electronic components and a single-layer conductive package substrate. The single-layer conductive package substrate is adapted to physically support and electrically interconnect the electronic components. The substrate has a peripheral portion and an interior portion. The peripheral portion includes a plurality of peripheral contact pads coupled to corresponding electronic components. The interior portion includes a plurality of floating contact pads that are electrically isolated from the peripheral contact pads and are coupled to corresponding electronic components.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: March 3, 2020
    Assignee: Intersil Americas LLC
    Inventors: Jian Yin, Nikhil Kelkar, Loyde M. Carpenter, Jr., Nattorn Pongratananukul, Patrick J. Selby, Steven R. Rivet, Michael W. Althar
  • Patent number: 10570011
    Abstract: A method for fabricating a microelectromechanical system device. Submerging a microelectromechanical system device in water. The microelectromechanical system devices include a sacrificial layer deposited on the surface of a substrate between the portion of a structural layer to be freed for movement and a base. Anodically etching the sacrificial layer from the microelectromechanical device to free the portion of the structural layer for movement. A system comprising a solution of water, a microelectromechanical system device including a sacrificial layer of chromium deposited on the surface of a substrate between a portion of a structural layer and a base. The microelectromechanical system device is submerged in the solution of water. An electrode is submerged in the water. The electrode provides a negative bias. A voltage source provides a positive bias to the sacrificial layer of chromium, anodically etching the sacrificial layer of chromium and freeing the portion of the structural layer.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: February 25, 2020
    Assignee: United States of America as represented by Secretary of the Navy
    Inventors: Paul D. Swanson, Andrew Wang
  • Patent number: 10563307
    Abstract: A method for manufacturing a substrate with less warpage includes a step of forming SiC film 121 on a surface of Si substrate 11, a step of removing bottom surface RG2 which is at least a part of the Si substrate 11 contacting with the SiC film 121, and a step of forming another SiC film on a surface of SiC film 121 after the step of removing the bottom surface RG2.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: February 18, 2020
    Assignee: AIR WATER INC.
    Inventors: Hidehiko Oku, Ichiro Hide
  • Patent number: 10558169
    Abstract: A method for manufacturing a micromechanical timepiece part starting from a silicon-based substrate, including, forming pores on the surface of at least one part of a surface of said silicon-based substrate of a determined depth, entirely filling the pores with a material chosen from diamond, diamond-like carbon, silicon oxide, silicon nitride, ceramics, polymers and mixtures thereof, in order to form, in the pores, a layer of the material of a thickness at least equal to the depth of the pores. A micromechanical timepiece part including a silicon-based substrate which has, on the surface of at least one part of a surface of the silicon-based substrate, pores of a determined depth, the pores being filled entirely with a layer of a material chosen from diamond, diamond-like carbon, silicon oxide, silicon nitride, ceramics, polymers and mixtures thereof, of a thickness at least equal to the depth of the pores.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: February 11, 2020
    Assignee: Nivarox-FAR S.A.
    Inventor: Philippe Dubois
  • Patent number: 10553499
    Abstract: A method can be used for fabricating first and second semiconductor regions separated by isolating trenches. A semiconductor substrate is covered with silicon nitride. The silicon nitride situated above the first region is doped by ion implantation. Trenches are etched through the silicon nitride and the doped silicon nitride is partially etching in an isotropic manner. The trenches are filled with an insulator to a level situated above that of the first region. The silicon nitride is removed resulting in the edges of the first region only being covered with an insulator annulus.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: February 4, 2020
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Franck Julien, Frédéric Chairat, Noémie Blanc, Emmanuel Blot, Philippe Roux, Gerald Theret
  • Patent number: 10522575
    Abstract: Methods of forming integrated circuit devices include forming a sacrificial layer on a handling substrate and forming a semiconductor active layer on the sacrificial layer. The semiconductor active layer and the sacrificial layer may be selectively etched in sequence to define an semiconductor-on-insulator (SOI) substrate, which includes a first portion of the semiconductor active layer. A multi-layer electrical interconnect network may be formed on the SOI substrate. This multi-layer electrical interconnect network may be encapsulated by an inorganic capping layer that contacts an upper surface of the first portion of the semiconductor active layer. The capping layer and the first portion of the semiconductor active layer may be selectively etched to thereby expose the sacrificial layer.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: December 31, 2019
    Assignee: X-Celeprint Limited
    Inventors: Christopher Bower, Etienne Menard, Matthew Meitl, Joseph Carr
  • Patent number: 10504738
    Abstract: A method includes mounting a wafer on a chuck disposed within a chamber of an etching system, the wafer being encircled by a focus ring. While etching portions of the wafer, an etch direction is adjusted to a first desired etch direction by adjusting a vertical position of the focus ring relative to the wafer to a first desired vertical position. While etching portions of the wafer, the etch direction is adjusted to a second desired etch direction by adjusting the vertical position of the focus ring relative to the wafer to a second desired vertical position. The second desired vertical position is different from the first desired vertical position. The second desired etch direction is different from the first desired etch direction.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chi Lin, Chin-Hsing Lin, Hung Jui Chang, Yi-Wei Chiu, Yu-Wei Kuo, Yu-Lun Ke
  • Patent number: 10497564
    Abstract: An apparatus for nano-imprinting using a high-pressure crystal phase transformation, includes: a stamp configured to perform nano-imprinting, the stamp comprising a pedestal and a base, wherein the pedestal is shaped to match an intended shape of a device to be fabricated; a tool chuck physically connected to the stamp, the tool chuck configured to allow a user to apply one or more of pressure and temperature to the film; a substrate upon which the device can be fabricated; a thin film physically connected to the substrate; and a tool stage physically connected to the substrate, the tool stage configured to allow a user to apply one or more of pressure and temperature to the film.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: December 3, 2019
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Vincent Gambin, Loan T. Le, Benjamin Poust
  • Patent number: 10466695
    Abstract: Methods and systems are described for new paradigms for user interaction with an unmanned aerial vehicle (referred to as a flying digital assistant or FDA) using a portable multifunction device (PMD) such as smart phone. In some embodiments, a user may control image capture from an FDA by adjusting the position and orientation of a PMD. In other embodiments, a user may input a touch gesture via a touch display of a PMD that corresponds with a flight path to be autonomously flown by the FDA.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: November 5, 2019
    Assignee: SKYDIO, INC.
    Inventors: Abraham Bachrach, Adam Bry, Matthew Donahoe
  • Patent number: 10458012
    Abstract: A method for manufacturing a component is provided. The method includes providing one or more notches on a surface of the component. Further, depositing a coating on the surface to provide a thickness of the coating on the surface, is performed. The method also includes removing, at least partially, the coating from the surface such that the thickness of the coating over the notches is different from the thickness of the coating on the surface adjacent to the notches.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: October 29, 2019
    Assignee: Caterpillar Inc.
    Inventors: Andrew Douglas Steinmetz, Douglas Trent Weaver, Roger Lee Recker
  • Patent number: 10450190
    Abstract: In a MEMS device, an oxide layer is disposed between first and second semiconductor layers and MEMS resonator is formed within a cavity in the first semiconductor layer. A first electrically conductive feature functionally coupled to the MEMS resonator is exposed at a surface of the first semiconductor layer, and an insulating region is exposed at the surface of the first semiconductor layer adjacent the first electrically conductive feature. A semiconductor cover layer is bonded to the surface of the first semiconductor layer to hermetically seal the MEMS resonator within the cavity. A second electrically conductive feature extends through the semiconductor cover layer to contact the first electrically conductive feature, and an isolation trench extends through the semiconductor cover layer to the insulating region to electrically isolate a conductive path formed by the first and second electrically conductive features.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: October 22, 2019
    Assignee: SiTime Corporation
    Inventors: Aaron Partridge, Markus Lutz, Pavan Gupta
  • Patent number: 10453996
    Abstract: A method of forming a semiconductor structure includes providing a substrate comprising a first material portion and a single crystal silicon layer on the first material portion. The substrate further comprises a major front surface, a major backside surface opposing the major front surface, and a plurality of grooves positioned in the major front surface. A buffer layer is deposited in one or more of the plurality of grooves. A semiconductor material is epitaxially grown over the buffer layer and in the one or more plurality of grooves, the epitaxially grown semiconductor material comprising a hexagonal crystalline phase layer and a cubic crystalline phase structure disposed over the hexagonal crystalline phase.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: October 22, 2019
    Assignee: STC.UNM
    Inventors: Steven R. J. Brueck, Seung-Chang Lee, Christian Wetzel, Mark Durniak
  • Patent number: 10446447
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a shallow trench isolation (STI) around the fin-shaped structure; forming a liner on the fin-shaped structure; and removing the liner and part of the fin-shaped structure so that a sidewall of the fin-shaped structure comprises a curve. Moreover, the method includes forming an epitaxial layer around the sidewall of the fin-shaped structure while a top surface of the fin-shaped structure is exposed.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: October 15, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Fan Li, I-Cheng Hu, Chun-Jen Chen, Tien-I Wu, Yu-Shu Lin, Chun-Yuan Wu
  • Patent number: 10410874
    Abstract: In a plasma processing method, a substrate is loaded onto a substrate electrode within a chamber, the substrate having an object layer to be etched thereon. A plasma generating power output is applied to form plasma within the chamber. A first bias power output is applied to the substrate electrode to perform a first etch stage on the object layer. A second bias power output having a nonsinusoidal voltage waveform is applied to the substrate electrode to perform a second etch stage on the object layer.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: September 10, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Beom Jin Yoo, Sang Ki Nam, Kwang-Youb Heo, Jehun Woo, Sang-Heon Lee, Masahiko Tomita, Vasily Pashkovskiy
  • Patent number: 10410832
    Abstract: A substrate support in a substrate processing system includes an inner portion and an outer portion. The inner portion is positioned below a gas distribution device configured to direct first process gases toward the inner portion. The outer portion includes an edge ring positioned around an outer perimeter of the inner portion to at least partially surround the inner portion and a substrate arranged on the inner portion. The edge ring is configured to be raised and lowered relative to the inner portion, and to direct second process gases toward the inner portion. A controller determines distribution of material deposited on the substrate during processing and, based on the determined distribution, selectively adjusts a position of the edge ring and selectively adjusts flow of at least one of the first process gases and the second process gases.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: September 10, 2019
    Assignee: Lam Research Corporation
    Inventors: Yiting Zhang, Saravanapriyan Sriraman, Alex Paterson
  • Patent number: 10352963
    Abstract: Implementations include a dynamic sweep-plow microcantilever (DSPM) device for nano-machining, nano-manufacturing, and nano-imaging using SPMs (e.g., an AFM). The DSPM device includes two elongated cantilevered arms that are spaced apart at their proximal ends and on which a piezoelectric layer is disposed. The distal ends of the arms are coupled together, and a distal tip is coupled to the distal ends and extends below a plane that includes a lower surface of the arms. The DSPM device is mounted on the AFM and applies nano-machining force through vibration that is induced by the piezoelectric layers on the arms. The DSPM device can vibrate such that the tip undergoes one or both of bending and torsional vibrations, which allows the DSPM device to perform both plowing and/or sweeping in nano-scale. The piezoelectric layers can be used for sensing by collecting vibrational feedback at the distal tip using a laser sensor.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: July 16, 2019
    Assignee: The Board of Trustees of The University of Alabama
    Inventors: Ehsan Omidi, Nima Mahmoodi
  • Patent number: 10343399
    Abstract: A liquid jetting apparatus includes: a channel substrate having a pressure chamber which is long in a first direction; an insulating film provided on the channel substrate to cover the pressure chamber; a piezoelectric film overlapping with the insulating film and having first and second portions, the first portion overlapping with a central portion of the pressure chamber in the first direction, the second portion extending from the first portion in the first direction beyond the pressure chamber, the first portion having a width in a second direction which is smaller than a width of the pressure chamber in the second direction; a first electrode arranged between the insulating film and the piezoelectric film; and a second electrode facing the first electrode with the piezoelectric film being sandwiched therebetween. The insulating film has a thin-walled portion formed at a portion overlapping with the second portion of the piezoelectric film.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: July 9, 2019
    Assignee: BROTHER KOGYO KABUSHIKI KAISHA
    Inventor: Kyohei Naito
  • Patent number: 10336090
    Abstract: A fluid ejection device may include a discharge port, an energy generating element to discharge liquid through the discharge port, a first liquid supply on a first side of the discharge port, a second liquid supply on a second side of the discharge port opposite the first side, a first liquid flow path extending from the first liquid supply to the discharge port, a second liquid flow path extending from the second liquid supply to the discharge port and a fluid displacement actuator in the first liquid flow path.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: July 2, 2019
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Alexander Govyadinov, Craig Olbrich, Brian M. Taff
  • Patent number: 10315421
    Abstract: A fluid ejector includes a nozzle layer, a body, an actuator and a membrane. The body includes a pumping chamber, a return channel, and a first passage fluidically connecting the pumping chamber to an entrance of the nozzle. A second passage fluidically connects the entrance of the nozzle to the return channel. The actuator is configured to cause fluid to flow out of the pumping chamber such that actuation of the actuator causes fluid to be ejected from the nozzle. The membrane is formed across and partially blocks at least one of the first passage, the second passage or the entrance of the nozzle. The membrane has at least one hole therethrough such that in operation of the fluid ejector fluid flows through the at least one hole in the membrane.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: June 11, 2019
    Assignee: FUJIFILM Dimatix, Inc.
    Inventors: Christoph Menzel, Darren Imai
  • Patent number: 10288874
    Abstract: A mirror micromechanical structure has a mobile mass carrying a mirror element. The mass is drivable in rotation for reflecting an incident light beam with a desired angular range. The mobile mass is suspended above a cavity obtained in a supporting body. The cavity is shaped so that the supporting body does not hinder the reflected light beam within the desired angular range. In particular, the cavity extends as far as a first side edge wall of the supporting body of the mirror micromechanical structure. The cavity is open towards, and in communication with, the outside of the mirror micromechanical structure at the first side edge wall.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: May 14, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventors: Roberto Carminati, Sebastiano Conti, Sonia Constantini
  • Patent number: 10276450
    Abstract: One aspect of the present disclosure is a method of fabricating metal gate by forming special layers in place of traditional TiN hard mask over the ILD0 layer to avoid ILD0 losses due to conventional ILD0 CMP. The method can comprise: after the ILD0 CMP, forming a first thin ashable film layer over the ILD0 layer; then forming a second thin dielectric layer over the first layer; during the aluminum CMP process for a first region (PMOS or NMOS), removing the second layer through polishing until the top surface of the first ashable film layer; and then removing first ashable film layer through an ashing method such as burning. In this way, ILD0 loss can be reduced during the first aluminum CMP step and thus can reduce initial height of ILD0, which in turn can reduce the height of initial dummy gate filled in the cavity.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: April 30, 2019
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: Tong Lei, Yongyue Chen, Haifeng Zhou
  • Patent number: 10262943
    Abstract: A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: April 16, 2019
    Assignee: Lam Research Corporation
    Inventors: Artur Kolics, William T. Lee, Larry Zhao, Derek Wong, Praveen Nalla, Kaihan Ashtiani, Patrick A. Van Cleemput, Yezdi Dordi
  • Patent number: 10246319
    Abstract: A method of forming a Micro-Electro-Mechanical System (MEMS) includes forming a lower electrode on a first insulator layer within a cavity of the MEMS. The method further includes forming an upper electrode over another insulator material on top of the lower electrode which is at least partially in contact with the lower electrode. The forming of the lower electrode and the upper electrode includes adjusting a metal volume of the lower electrode and the upper electrode to modify beam bending.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: April 2, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christopher V. Jahnes, Anthony K. Stamper
  • Patent number: 10242839
    Abstract: Performance of a multi-electron-beam system can be improved by reducing Coulomb effects in the illumination path of a multi-beam inspection system. A beam-limiting aperture with multiple holes can be positioned between an electron beam source and a multi-lens array, such as in a field-free region. The beam-limiting aperture is configured to reduce Coulomb interactions between the electron beam source and the multi-lens array. An electron beam system with the beam-limiting aperture can be used in a scanning electron microscope.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: March 26, 2019
    Assignee: KLA-Tencor Corporation
    Inventor: Alan D. Brodie
  • Patent number: 10228466
    Abstract: Techniques are described herein that are capable of forming a depth map and/or projecting an image onto object(s) based on the depth map. A depth map is a three-dimensional representation of an environment. Forming the depth map may utilize a progressive resolution refinement technique. For example, locating information may be determined in accordance with the progressive resolution refinement technique in response to performing a scan of a current point over a field of view. The current point is a point, selected from a plurality of points (e.g., a grid of points) in the field of view, to which a detection beam of light is directed at a respective time as the scan is performed over the field of view. In accordance with this example, the locating information may be coordinated with the scan to form the depth map.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: March 12, 2019
    Assignee: Mezmeriz, Inc.
    Inventors: Clifford A. Lardin, Shahyaan Desai, Scott G. Adams
  • Patent number: 10214416
    Abstract: A method of forming a Micro-Electro-Mechanical System (MEMS) includes forming a lower electrode on a first insulator layer within a cavity of the MEMS. The method further includes forming an upper electrode over another insulator material on top of the lower electrode which is at least partially in contact with the lower electrode. The forming of the lower electrode and the upper electrode includes adjusting a metal volume of the lower electrode and the upper electrode to modify beam bending.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: February 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christopher V. Jahnes, Anthony K. Stamper
  • Patent number: 10207916
    Abstract: A flexible film including one or more MEMS elements and articles including the flexible film are described. The flexible film includes a polymer layer between two metal layers with one of the metal layers containing a perforation. The polymer layer includes voided regions that allow for relative movement of the two metal layers.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: February 19, 2019
    Assignee: 3M INNOVATIVE PROPERTIES COMPANY
    Inventors: Phillip J. Bergeron, Brent D. Lunceford, John D. Geissinger, Douglas B. Gundel, Justine A. Mooney, Ravi Palaniswamy, Siang Sin Foo
  • Patent number: 10209408
    Abstract: The invention provides an optical component, an infrared camera including the optical component, and a method for manufacturing the optical component. Antireflection materials 3A are formed on a chalcogenide glass 2 of which a compositional ratio of germanium and selenium is 60 percent or greater. With respect to the antireflection materials 3A, an extinction coefficient to light of 10.5 ?m is 0.01 or less, and a refractive index to light having a wavelength of 10.5 ?m are greater than 1 and 2.6 or less. The antireflection materials 3A are formed on a surface of a chalcogenide glass 2 at an interval of 0.5 ?m to 2.0 ?m, so as to form an antireflection film 3. Adhesiveness of the antireflection film 3 is higher than that In a case where the surface of the chalcogenide glass 2 is evenly coated with the antireflection materials 3A.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: February 19, 2019
    Assignee: FUJIFILM Corporation
    Inventors: Hiroki Takahashi, Mototaka Kanaya
  • Patent number: 10183155
    Abstract: Devices for the local delivery of microdose amounts of one or more active agents, alone or in combination, in one or more dosages, to selected tissue of a patient are described. The devices generally include multiple microwells arranged on or within a support structure and contain one or more active agents, alone or in combination, in one or more dosages and/or release pharmacokinetics. In an exemplary embodiment, the device has a cylindrical shape, having symmetrical wells on the outside of the device, each well containing one or more drugs, at one or more concentrations, sized to permit placement using a catheter, cannula, or stylet. Optionally, the device has a guidewire, and fiber optics, sensors and/or interactive features such as remote accessibility to provide for in situ retrieval of information and modification of device release properties. In a preferred embodiment, the fiber optics and/or sensors are individually accessible to discrete wells.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: January 22, 2019
    Assignees: Kibur Medical, Inc., Massachusetts Institute of Technology
    Inventors: Robert I. Tepper, Jason Fuller, Oliver Jonas, John Santini
  • Patent number: 10155656
    Abstract: The present disclosure relates to micro-electromechanical system (MEMS) package that uses polysilicon inter-tier connections to provide for a low parasitic capacitance in MEM device signals, and a method of formation. In some embodiments, the MEMS package has a CMOS substrate with one or more semiconductor devices arranged within a semiconductor body. A MEMS substrate having an ambulatory element is connected to the CMOS substrate by a conductive bonding structure. The conductive bonding structure is arranged on a front-side of the MEMS substrate at a location laterally offset from the ambulatory element. One or more polysilicon vias extend through the conductive MEMS substrate to the bonding structure. The one or more polysilicon vias are configured to electrically couple the MEMS substrate to the CMOS substrate. By connecting the MEMS substrate to the CMOS substrate using the polysilicon vias, the parasitic capacitance and form factor of the MEMS package are reduced.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shyh-Wei Cheng, Chih-Yu Wang, Hsi-Cheng Hsu, Ji-Hong Chiang, Jui-Chun Weng, Shiuan-Jeng Lin, Wei-Ding Wu, Ching-Hsiang Hu
  • Patent number: 10149066
    Abstract: Disclosed are a microphone and a manufacturing method thereof. The microphone includes a substrate with a through portion formed in a central portion thereof, a vibration membrane disposed on the substrate and covering the through portion, a fixed membrane installed above the vibration membrane and spaced apart from the vibration membrane with an air layer interposed therebetween, and including a plurality of air inlets perforated in a direction toward the air layer, a support layer supporting the fixed membrane installed above the vibration membrane and spaced apart from the vibration membrane, a back plate formed on the fixed membrane and the support layer and having the air inlet formed to extend in a central portion thereof, and an air outflow part allowing air of the air layer to flow to an outer area of an edge of a sensing area of the fixed membrane on the back plate.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: December 4, 2018
    Assignee: HYUNDAI MOTOR COMPANY
    Inventor: Ilseon Yoo
  • Patent number: 10141195
    Abstract: There is provided a substrate processing method performed on a substrate having a recess formed in a surface thereof, a first silicon-containing film formed on a bottom surface of the recess, a second silicon-containing film formed on both sides of the recess, the method including: depositing a carbon-based deposit on the surface of the substrate; removing the first silicon-containing film by performing a COR (Chemical Oxide Removal) process in which a silicon-containing film is modified to a reaction product using a processing gas, on the substrate; and removing the deposited carbon-based deposit.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: November 27, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Muneyuki Imai, Noriyuki Kobayashi
  • Patent number: 10128405
    Abstract: A method of producing an optoelectronic component, comprising the method steps: A) providing a growth substrate (1); B) growing at least one semiconductor layer (2) epitaxially, to produce an operationally active zone; C) applying a metallic mirror layer (3) to the semiconductor layer (2); D) applying at least one contact layer (8) for electronic contacting of the component; E) detaching the growth substrate (1) from the semiconductor layer (2), so exposing a surface of the semiconductor layer (2); and F) structuring the semiconductor layer (2) by means of an etching method from the side of the surface which was exposed in method step E).
    Type: Grant
    Filed: June 3, 2009
    Date of Patent: November 13, 2018
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Stephan Kaiser, Andreas Ploessl
  • Patent number: 10112823
    Abstract: A method for forming a MEMS device is provided. The method includes providing a first wafer and a second wafer. The first wafer has a trench on a top surface of the first wafer and a fixed electrode on the bottom of the trench, and the second wafer has a polishing stop layer, a sacrificial layer, and a movable electrode. The method also includes bonding the first wafer and the second wafer with the top surface of the first wafer facing the top surface of the second wafer and the movable electrode on the second wafer located above the trench on the first wafer; removing the second wafer by polishing the second wafer from a backside of the second wafer until reaching the polishing stop layer; and releasing the movable electrode by removing a portion of the polishing stop layer and the sacrificial layer to form the MEMS device.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: October 30, 2018
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Chao Zheng, Wei Wang
  • Patent number: 10109496
    Abstract: The present invention relates to fluoroolefin compositions useful as gases for CVD semiconductor manufacture, particularly for etching applications including methods for removing surface deposits from the interior of a chemical vapor deposition chamber by using an activated gas mixture, and methods for etching the surface of a semiconductor.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: October 23, 2018
    Assignee: THE CHEMOURS COMPANY FC, LLC
    Inventors: Sheng Peng, Gary Loh, Yoshimasa Oosaki
  • Patent number: 10106400
    Abstract: A method for fabrication of a micromechanical part made of a one-piece synthetic carbon allotrope based material, the method including: forming a substrate with a negative cavity of the micromechanical part to be fabricated; coating the negative cavity of the substrate with a layer of the synthetic carbon allotrope based material in a smaller thickness than the depth of the negative cavity; and removing the substrate to release the one-piece micromechanical part formed in the negative cavity.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: October 23, 2018
    Assignee: Nivarox-FAR S.A.
    Inventors: Philippe Dubois, Sebastiano Merzaghi, Christian Charbon
  • Patent number: 10099917
    Abstract: After forming a microelectromechanical-system (MEMS) resonator within a silicon-on-insulator (SOI) wafer, a complementary metal oxide semiconductor (CMOS) cover wafer is bonded to the SOI wafer via one or more eutectic solder bonds that implement respective paths of electrical conductivity between the two wafers and hermetically seal the MEMS resonator within a chamber.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: October 16, 2018
    Assignee: SiTime Corporation
    Inventors: Aaron Partridge, Markus Lutz, Pavan Gupta