Etching Of Semiconductor Material To Produce An Article Having A Nonelectrical Function Patents (Class 216/2)
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Patent number: 10522575Abstract: Methods of forming integrated circuit devices include forming a sacrificial layer on a handling substrate and forming a semiconductor active layer on the sacrificial layer. The semiconductor active layer and the sacrificial layer may be selectively etched in sequence to define an semiconductor-on-insulator (SOI) substrate, which includes a first portion of the semiconductor active layer. A multi-layer electrical interconnect network may be formed on the SOI substrate. This multi-layer electrical interconnect network may be encapsulated by an inorganic capping layer that contacts an upper surface of the first portion of the semiconductor active layer. The capping layer and the first portion of the semiconductor active layer may be selectively etched to thereby expose the sacrificial layer.Type: GrantFiled: November 15, 2018Date of Patent: December 31, 2019Assignee: X-Celeprint LimitedInventors: Christopher Bower, Etienne Menard, Matthew Meitl, Joseph Carr
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Patent number: 10504738Abstract: A method includes mounting a wafer on a chuck disposed within a chamber of an etching system, the wafer being encircled by a focus ring. While etching portions of the wafer, an etch direction is adjusted to a first desired etch direction by adjusting a vertical position of the focus ring relative to the wafer to a first desired vertical position. While etching portions of the wafer, the etch direction is adjusted to a second desired etch direction by adjusting the vertical position of the focus ring relative to the wafer to a second desired vertical position. The second desired vertical position is different from the first desired vertical position. The second desired etch direction is different from the first desired etch direction.Type: GrantFiled: April 30, 2018Date of Patent: December 10, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chi Lin, Chin-Hsing Lin, Hung Jui Chang, Yi-Wei Chiu, Yu-Wei Kuo, Yu-Lun Ke
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Patent number: 10497564Abstract: An apparatus for nano-imprinting using a high-pressure crystal phase transformation, includes: a stamp configured to perform nano-imprinting, the stamp comprising a pedestal and a base, wherein the pedestal is shaped to match an intended shape of a device to be fabricated; a tool chuck physically connected to the stamp, the tool chuck configured to allow a user to apply one or more of pressure and temperature to the film; a substrate upon which the device can be fabricated; a thin film physically connected to the substrate; and a tool stage physically connected to the substrate, the tool stage configured to allow a user to apply one or more of pressure and temperature to the film.Type: GrantFiled: February 26, 2019Date of Patent: December 3, 2019Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATIONInventors: Vincent Gambin, Loan T. Le, Benjamin Poust
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Patent number: 10466695Abstract: Methods and systems are described for new paradigms for user interaction with an unmanned aerial vehicle (referred to as a flying digital assistant or FDA) using a portable multifunction device (PMD) such as smart phone. In some embodiments, a user may control image capture from an FDA by adjusting the position and orientation of a PMD. In other embodiments, a user may input a touch gesture via a touch display of a PMD that corresponds with a flight path to be autonomously flown by the FDA.Type: GrantFiled: October 23, 2017Date of Patent: November 5, 2019Assignee: SKYDIO, INC.Inventors: Abraham Bachrach, Adam Bry, Matthew Donahoe
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Patent number: 10458012Abstract: A method for manufacturing a component is provided. The method includes providing one or more notches on a surface of the component. Further, depositing a coating on the surface to provide a thickness of the coating on the surface, is performed. The method also includes removing, at least partially, the coating from the surface such that the thickness of the coating over the notches is different from the thickness of the coating on the surface adjacent to the notches.Type: GrantFiled: May 3, 2016Date of Patent: October 29, 2019Assignee: Caterpillar Inc.Inventors: Andrew Douglas Steinmetz, Douglas Trent Weaver, Roger Lee Recker
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Patent number: 10450190Abstract: In a MEMS device, an oxide layer is disposed between first and second semiconductor layers and MEMS resonator is formed within a cavity in the first semiconductor layer. A first electrically conductive feature functionally coupled to the MEMS resonator is exposed at a surface of the first semiconductor layer, and an insulating region is exposed at the surface of the first semiconductor layer adjacent the first electrically conductive feature. A semiconductor cover layer is bonded to the surface of the first semiconductor layer to hermetically seal the MEMS resonator within the cavity. A second electrically conductive feature extends through the semiconductor cover layer to contact the first electrically conductive feature, and an isolation trench extends through the semiconductor cover layer to the insulating region to electrically isolate a conductive path formed by the first and second electrically conductive features.Type: GrantFiled: August 21, 2018Date of Patent: October 22, 2019Assignee: SiTime CorporationInventors: Aaron Partridge, Markus Lutz, Pavan Gupta
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Patent number: 10453996Abstract: A method of forming a semiconductor structure includes providing a substrate comprising a first material portion and a single crystal silicon layer on the first material portion. The substrate further comprises a major front surface, a major backside surface opposing the major front surface, and a plurality of grooves positioned in the major front surface. A buffer layer is deposited in one or more of the plurality of grooves. A semiconductor material is epitaxially grown over the buffer layer and in the one or more plurality of grooves, the epitaxially grown semiconductor material comprising a hexagonal crystalline phase layer and a cubic crystalline phase structure disposed over the hexagonal crystalline phase.Type: GrantFiled: December 9, 2016Date of Patent: October 22, 2019Assignee: STC.UNMInventors: Steven R. J. Brueck, Seung-Chang Lee, Christian Wetzel, Mark Durniak
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Patent number: 10446447Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a shallow trench isolation (STI) around the fin-shaped structure; forming a liner on the fin-shaped structure; and removing the liner and part of the fin-shaped structure so that a sidewall of the fin-shaped structure comprises a curve. Moreover, the method includes forming an epitaxial layer around the sidewall of the fin-shaped structure while a top surface of the fin-shaped structure is exposed.Type: GrantFiled: July 16, 2018Date of Patent: October 15, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-Fan Li, I-Cheng Hu, Chun-Jen Chen, Tien-I Wu, Yu-Shu Lin, Chun-Yuan Wu
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Patent number: 10410832Abstract: A substrate support in a substrate processing system includes an inner portion and an outer portion. The inner portion is positioned below a gas distribution device configured to direct first process gases toward the inner portion. The outer portion includes an edge ring positioned around an outer perimeter of the inner portion to at least partially surround the inner portion and a substrate arranged on the inner portion. The edge ring is configured to be raised and lowered relative to the inner portion, and to direct second process gases toward the inner portion. A controller determines distribution of material deposited on the substrate during processing and, based on the determined distribution, selectively adjusts a position of the edge ring and selectively adjusts flow of at least one of the first process gases and the second process gases.Type: GrantFiled: August 19, 2016Date of Patent: September 10, 2019Assignee: Lam Research CorporationInventors: Yiting Zhang, Saravanapriyan Sriraman, Alex Paterson
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Patent number: 10410874Abstract: In a plasma processing method, a substrate is loaded onto a substrate electrode within a chamber, the substrate having an object layer to be etched thereon. A plasma generating power output is applied to form plasma within the chamber. A first bias power output is applied to the substrate electrode to perform a first etch stage on the object layer. A second bias power output having a nonsinusoidal voltage waveform is applied to the substrate electrode to perform a second etch stage on the object layer.Type: GrantFiled: January 10, 2018Date of Patent: September 10, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Beom Jin Yoo, Sang Ki Nam, Kwang-Youb Heo, Jehun Woo, Sang-Heon Lee, Masahiko Tomita, Vasily Pashkovskiy
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Patent number: 10352963Abstract: Implementations include a dynamic sweep-plow microcantilever (DSPM) device for nano-machining, nano-manufacturing, and nano-imaging using SPMs (e.g., an AFM). The DSPM device includes two elongated cantilevered arms that are spaced apart at their proximal ends and on which a piezoelectric layer is disposed. The distal ends of the arms are coupled together, and a distal tip is coupled to the distal ends and extends below a plane that includes a lower surface of the arms. The DSPM device is mounted on the AFM and applies nano-machining force through vibration that is induced by the piezoelectric layers on the arms. The DSPM device can vibrate such that the tip undergoes one or both of bending and torsional vibrations, which allows the DSPM device to perform both plowing and/or sweeping in nano-scale. The piezoelectric layers can be used for sensing by collecting vibrational feedback at the distal tip using a laser sensor.Type: GrantFiled: December 22, 2016Date of Patent: July 16, 2019Assignee: The Board of Trustees of The University of AlabamaInventors: Ehsan Omidi, Nima Mahmoodi
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Patent number: 10343399Abstract: A liquid jetting apparatus includes: a channel substrate having a pressure chamber which is long in a first direction; an insulating film provided on the channel substrate to cover the pressure chamber; a piezoelectric film overlapping with the insulating film and having first and second portions, the first portion overlapping with a central portion of the pressure chamber in the first direction, the second portion extending from the first portion in the first direction beyond the pressure chamber, the first portion having a width in a second direction which is smaller than a width of the pressure chamber in the second direction; a first electrode arranged between the insulating film and the piezoelectric film; and a second electrode facing the first electrode with the piezoelectric film being sandwiched therebetween. The insulating film has a thin-walled portion formed at a portion overlapping with the second portion of the piezoelectric film.Type: GrantFiled: September 29, 2017Date of Patent: July 9, 2019Assignee: BROTHER KOGYO KABUSHIKI KAISHAInventor: Kyohei Naito
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Patent number: 10336090Abstract: A fluid ejection device may include a discharge port, an energy generating element to discharge liquid through the discharge port, a first liquid supply on a first side of the discharge port, a second liquid supply on a second side of the discharge port opposite the first side, a first liquid flow path extending from the first liquid supply to the discharge port, a second liquid flow path extending from the second liquid supply to the discharge port and a fluid displacement actuator in the first liquid flow path.Type: GrantFiled: March 14, 2018Date of Patent: July 2, 2019Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.Inventors: Alexander Govyadinov, Craig Olbrich, Brian M. Taff
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Patent number: 10315421Abstract: A fluid ejector includes a nozzle layer, a body, an actuator and a membrane. The body includes a pumping chamber, a return channel, and a first passage fluidically connecting the pumping chamber to an entrance of the nozzle. A second passage fluidically connects the entrance of the nozzle to the return channel. The actuator is configured to cause fluid to flow out of the pumping chamber such that actuation of the actuator causes fluid to be ejected from the nozzle. The membrane is formed across and partially blocks at least one of the first passage, the second passage or the entrance of the nozzle. The membrane has at least one hole therethrough such that in operation of the fluid ejector fluid flows through the at least one hole in the membrane.Type: GrantFiled: December 30, 2016Date of Patent: June 11, 2019Assignee: FUJIFILM Dimatix, Inc.Inventors: Christoph Menzel, Darren Imai
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Patent number: 10288874Abstract: A mirror micromechanical structure has a mobile mass carrying a mirror element. The mass is drivable in rotation for reflecting an incident light beam with a desired angular range. The mobile mass is suspended above a cavity obtained in a supporting body. The cavity is shaped so that the supporting body does not hinder the reflected light beam within the desired angular range. In particular, the cavity extends as far as a first side edge wall of the supporting body of the mirror micromechanical structure. The cavity is open towards, and in communication with, the outside of the mirror micromechanical structure at the first side edge wall.Type: GrantFiled: October 13, 2016Date of Patent: May 14, 2019Assignee: STMicroelectronics S.r.l.Inventors: Roberto Carminati, Sebastiano Conti, Sonia Constantini
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Patent number: 10276450Abstract: One aspect of the present disclosure is a method of fabricating metal gate by forming special layers in place of traditional TiN hard mask over the ILD0 layer to avoid ILD0 losses due to conventional ILD0 CMP. The method can comprise: after the ILD0 CMP, forming a first thin ashable film layer over the ILD0 layer; then forming a second thin dielectric layer over the first layer; during the aluminum CMP process for a first region (PMOS or NMOS), removing the second layer through polishing until the top surface of the first ashable film layer; and then removing first ashable film layer through an ashing method such as burning. In this way, ILD0 loss can be reduced during the first aluminum CMP step and thus can reduce initial height of ILD0, which in turn can reduce the height of initial dummy gate filled in the cavity.Type: GrantFiled: February 10, 2017Date of Patent: April 30, 2019Assignee: Shanghai Huali Microelectronics CorporationInventors: Tong Lei, Yongyue Chen, Haifeng Zhou
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Patent number: 10262943Abstract: A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.Type: GrantFiled: January 23, 2018Date of Patent: April 16, 2019Assignee: Lam Research CorporationInventors: Artur Kolics, William T. Lee, Larry Zhao, Derek Wong, Praveen Nalla, Kaihan Ashtiani, Patrick A. Van Cleemput, Yezdi Dordi
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Patent number: 10246319Abstract: A method of forming a Micro-Electro-Mechanical System (MEMS) includes forming a lower electrode on a first insulator layer within a cavity of the MEMS. The method further includes forming an upper electrode over another insulator material on top of the lower electrode which is at least partially in contact with the lower electrode. The forming of the lower electrode and the upper electrode includes adjusting a metal volume of the lower electrode and the upper electrode to modify beam bending.Type: GrantFiled: November 3, 2017Date of Patent: April 2, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christopher V. Jahnes, Anthony K. Stamper
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Patent number: 10242839Abstract: Performance of a multi-electron-beam system can be improved by reducing Coulomb effects in the illumination path of a multi-beam inspection system. A beam-limiting aperture with multiple holes can be positioned between an electron beam source and a multi-lens array, such as in a field-free region. The beam-limiting aperture is configured to reduce Coulomb interactions between the electron beam source and the multi-lens array. An electron beam system with the beam-limiting aperture can be used in a scanning electron microscope.Type: GrantFiled: May 5, 2017Date of Patent: March 26, 2019Assignee: KLA-Tencor CorporationInventor: Alan D. Brodie
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Patent number: 10228466Abstract: Techniques are described herein that are capable of forming a depth map and/or projecting an image onto object(s) based on the depth map. A depth map is a three-dimensional representation of an environment. Forming the depth map may utilize a progressive resolution refinement technique. For example, locating information may be determined in accordance with the progressive resolution refinement technique in response to performing a scan of a current point over a field of view. The current point is a point, selected from a plurality of points (e.g., a grid of points) in the field of view, to which a detection beam of light is directed at a respective time as the scan is performed over the field of view. In accordance with this example, the locating information may be coordinated with the scan to form the depth map.Type: GrantFiled: June 29, 2015Date of Patent: March 12, 2019Assignee: Mezmeriz, Inc.Inventors: Clifford A. Lardin, Shahyaan Desai, Scott G. Adams
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Patent number: 10214416Abstract: A method of forming a Micro-Electro-Mechanical System (MEMS) includes forming a lower electrode on a first insulator layer within a cavity of the MEMS. The method further includes forming an upper electrode over another insulator material on top of the lower electrode which is at least partially in contact with the lower electrode. The forming of the lower electrode and the upper electrode includes adjusting a metal volume of the lower electrode and the upper electrode to modify beam bending.Type: GrantFiled: November 3, 2017Date of Patent: February 26, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christopher V. Jahnes, Anthony K. Stamper
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Patent number: 10209408Abstract: The invention provides an optical component, an infrared camera including the optical component, and a method for manufacturing the optical component. Antireflection materials 3A are formed on a chalcogenide glass 2 of which a compositional ratio of germanium and selenium is 60 percent or greater. With respect to the antireflection materials 3A, an extinction coefficient to light of 10.5 ?m is 0.01 or less, and a refractive index to light having a wavelength of 10.5 ?m are greater than 1 and 2.6 or less. The antireflection materials 3A are formed on a surface of a chalcogenide glass 2 at an interval of 0.5 ?m to 2.0 ?m, so as to form an antireflection film 3. Adhesiveness of the antireflection film 3 is higher than that In a case where the surface of the chalcogenide glass 2 is evenly coated with the antireflection materials 3A.Type: GrantFiled: August 23, 2016Date of Patent: February 19, 2019Assignee: FUJIFILM CorporationInventors: Hiroki Takahashi, Mototaka Kanaya
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Patent number: 10207916Abstract: A flexible film including one or more MEMS elements and articles including the flexible film are described. The flexible film includes a polymer layer between two metal layers with one of the metal layers containing a perforation. The polymer layer includes voided regions that allow for relative movement of the two metal layers.Type: GrantFiled: May 11, 2015Date of Patent: February 19, 2019Assignee: 3M INNOVATIVE PROPERTIES COMPANYInventors: Phillip J. Bergeron, Brent D. Lunceford, John D. Geissinger, Douglas B. Gundel, Justine A. Mooney, Ravi Palaniswamy, Siang Sin Foo
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Patent number: 10183155Abstract: Devices for the local delivery of microdose amounts of one or more active agents, alone or in combination, in one or more dosages, to selected tissue of a patient are described. The devices generally include multiple microwells arranged on or within a support structure and contain one or more active agents, alone or in combination, in one or more dosages and/or release pharmacokinetics. In an exemplary embodiment, the device has a cylindrical shape, having symmetrical wells on the outside of the device, each well containing one or more drugs, at one or more concentrations, sized to permit placement using a catheter, cannula, or stylet. Optionally, the device has a guidewire, and fiber optics, sensors and/or interactive features such as remote accessibility to provide for in situ retrieval of information and modification of device release properties. In a preferred embodiment, the fiber optics and/or sensors are individually accessible to discrete wells.Type: GrantFiled: May 18, 2016Date of Patent: January 22, 2019Assignees: Kibur Medical, Inc., Massachusetts Institute of TechnologyInventors: Robert I. Tepper, Jason Fuller, Oliver Jonas, John Santini
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Patent number: 10155656Abstract: The present disclosure relates to micro-electromechanical system (MEMS) package that uses polysilicon inter-tier connections to provide for a low parasitic capacitance in MEM device signals, and a method of formation. In some embodiments, the MEMS package has a CMOS substrate with one or more semiconductor devices arranged within a semiconductor body. A MEMS substrate having an ambulatory element is connected to the CMOS substrate by a conductive bonding structure. The conductive bonding structure is arranged on a front-side of the MEMS substrate at a location laterally offset from the ambulatory element. One or more polysilicon vias extend through the conductive MEMS substrate to the bonding structure. The one or more polysilicon vias are configured to electrically couple the MEMS substrate to the CMOS substrate. By connecting the MEMS substrate to the CMOS substrate using the polysilicon vias, the parasitic capacitance and form factor of the MEMS package are reduced.Type: GrantFiled: December 28, 2015Date of Patent: December 18, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shyh-Wei Cheng, Chih-Yu Wang, Hsi-Cheng Hsu, Ji-Hong Chiang, Jui-Chun Weng, Shiuan-Jeng Lin, Wei-Ding Wu, Ching-Hsiang Hu
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Patent number: 10149066Abstract: Disclosed are a microphone and a manufacturing method thereof. The microphone includes a substrate with a through portion formed in a central portion thereof, a vibration membrane disposed on the substrate and covering the through portion, a fixed membrane installed above the vibration membrane and spaced apart from the vibration membrane with an air layer interposed therebetween, and including a plurality of air inlets perforated in a direction toward the air layer, a support layer supporting the fixed membrane installed above the vibration membrane and spaced apart from the vibration membrane, a back plate formed on the fixed membrane and the support layer and having the air inlet formed to extend in a central portion thereof, and an air outflow part allowing air of the air layer to flow to an outer area of an edge of a sensing area of the fixed membrane on the back plate.Type: GrantFiled: November 30, 2016Date of Patent: December 4, 2018Assignee: HYUNDAI MOTOR COMPANYInventor: Ilseon Yoo
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Patent number: 10141195Abstract: There is provided a substrate processing method performed on a substrate having a recess formed in a surface thereof, a first silicon-containing film formed on a bottom surface of the recess, a second silicon-containing film formed on both sides of the recess, the method including: depositing a carbon-based deposit on the surface of the substrate; removing the first silicon-containing film by performing a COR (Chemical Oxide Removal) process in which a silicon-containing film is modified to a reaction product using a processing gas, on the substrate; and removing the deposited carbon-based deposit.Type: GrantFiled: August 23, 2017Date of Patent: November 27, 2018Assignee: Tokyo Electron LimitedInventors: Muneyuki Imai, Noriyuki Kobayashi
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Patent number: 10128405Abstract: A method of producing an optoelectronic component, comprising the method steps: A) providing a growth substrate (1); B) growing at least one semiconductor layer (2) epitaxially, to produce an operationally active zone; C) applying a metallic mirror layer (3) to the semiconductor layer (2); D) applying at least one contact layer (8) for electronic contacting of the component; E) detaching the growth substrate (1) from the semiconductor layer (2), so exposing a surface of the semiconductor layer (2); and F) structuring the semiconductor layer (2) by means of an etching method from the side of the surface which was exposed in method step E).Type: GrantFiled: June 3, 2009Date of Patent: November 13, 2018Assignee: OSRAM Opto Semiconductors GmbHInventors: Stephan Kaiser, Andreas Ploessl
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Patent number: 10112823Abstract: A method for forming a MEMS device is provided. The method includes providing a first wafer and a second wafer. The first wafer has a trench on a top surface of the first wafer and a fixed electrode on the bottom of the trench, and the second wafer has a polishing stop layer, a sacrificial layer, and a movable electrode. The method also includes bonding the first wafer and the second wafer with the top surface of the first wafer facing the top surface of the second wafer and the movable electrode on the second wafer located above the trench on the first wafer; removing the second wafer by polishing the second wafer from a backside of the second wafer until reaching the polishing stop layer; and releasing the movable electrode by removing a portion of the polishing stop layer and the sacrificial layer to form the MEMS device.Type: GrantFiled: November 5, 2015Date of Patent: October 30, 2018Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventors: Chao Zheng, Wei Wang
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Patent number: 10106400Abstract: A method for fabrication of a micromechanical part made of a one-piece synthetic carbon allotrope based material, the method including: forming a substrate with a negative cavity of the micromechanical part to be fabricated; coating the negative cavity of the substrate with a layer of the synthetic carbon allotrope based material in a smaller thickness than the depth of the negative cavity; and removing the substrate to release the one-piece micromechanical part formed in the negative cavity.Type: GrantFiled: October 6, 2014Date of Patent: October 23, 2018Assignee: Nivarox-FAR S.A.Inventors: Philippe Dubois, Sebastiano Merzaghi, Christian Charbon
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Patent number: 10109496Abstract: The present invention relates to fluoroolefin compositions useful as gases for CVD semiconductor manufacture, particularly for etching applications including methods for removing surface deposits from the interior of a chemical vapor deposition chamber by using an activated gas mixture, and methods for etching the surface of a semiconductor.Type: GrantFiled: December 22, 2014Date of Patent: October 23, 2018Assignee: THE CHEMOURS COMPANY FC, LLCInventors: Sheng Peng, Gary Loh, Yoshimasa Oosaki
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Patent number: 10099917Abstract: After forming a microelectromechanical-system (MEMS) resonator within a silicon-on-insulator (SOI) wafer, a complementary metal oxide semiconductor (CMOS) cover wafer is bonded to the SOI wafer via one or more eutectic solder bonds that implement respective paths of electrical conductivity between the two wafers and hermetically seal the MEMS resonator within a chamber.Type: GrantFiled: August 25, 2017Date of Patent: October 16, 2018Assignee: SiTime CorporationInventors: Aaron Partridge, Markus Lutz, Pavan Gupta
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Patent number: 10096570Abstract: An object of the invention is to provide: a manufacturing method for a highly reliable power semiconductor device which prevents breakage of an conductor pattern and an insulating layer, and has bonding strength higher than that by the conventional bonding between the electrode terminal and the conductor pattern; and that power semiconductor device. Breakage of the conductor pattern and the insulating layer is prevented due to inclusion of: a step of laying an electrode terminal on a protrusion provided on a conductor pattern placed on a circuit-face side of a ceramic board so that a center portion of a surface to be bonded of the electrode terminal makes contact with a head portion of the protrusion; a step of pressurizing and ultrasonically vibrating a surface opposite to the surface to be bonded, of the electrode terminal, using an ultrasonic horn, to thereby bond the electrode terminal to the conductor pattern.Type: GrantFiled: May 31, 2016Date of Patent: October 9, 2018Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Yutaka Yoneda, Junji Fujino, Kazuyoshi Shige, Yoichi Hironaka
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Patent number: 10095056Abstract: Embodiments include a method and associated apparatuses for phase-shifting an optical signal. The method comprises receiving, at a first end of an optical waveguide formed in a semiconductor layer and extending along a first axis, an optical signal having a first phase. The method further comprises transmitting, at a second end of the optical waveguide opposite the first end, a modified optical signal having a second phase different than the first phase. Transmitting a modified optical signal comprises applying a voltage signal between a first contact region and a second contact region formed in the semiconductor layer apart from the first axis. Applying a voltage signal causes an electrical current to be conducted along a dimension of the optical waveguide. The electrical current causes resistive heating of the optical waveguide and a desired phase shift between the first phase and the second phase.Type: GrantFiled: April 26, 2017Date of Patent: October 9, 2018Assignee: Cisco Technology, Inc.Inventors: Sean P. Anderson, Donald Adams
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Patent number: 10095106Abstract: A nanoimprint lithography method to remove uncured pretreatment composition from an imprinted nanoimprint lithography substrate. The method includes disposing a pretreatment composition on a nanoimprint lithography substrate to form a pretreatment coating and disposing discrete portions of imprint resist on the pretreatment coating, each discrete portion of the imprint resist covering a target area of the nanoimprint lithography substrate. A composite polymerizable coating is formed on the nanoimprint lithography substrate as each discrete portion of the imprint resist spreads beyond its target area, and the composite polymerizable coating is contacted with a nanoimprint lithography template. The composite polymerizable coating is polymerized to yield a composite polymeric layer and an uncured portion of the pretreatment coating on the nanoimprint lithography substrate, and the uncured portion of the pretreatment coating is removed from the nanoimprint lithography substrate.Type: GrantFiled: January 30, 2017Date of Patent: October 9, 2018Assignee: Canon Kabushiki KaishaInventors: Timothy Brian Stachowiak, Weijun Liu, Niyaz Khusnatdinov, Zhengmao Ye, Toshiki Ito
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Patent number: 10081538Abstract: The present invention discloses a Micro-Electro-Mechanical System (MEMS) acoustic pressure sensor device and a method for making same. The MEMS device includes: a substrate; a fixed electrode provided on the substrate; and a multilayer structure, which includes multiple metal layers and multiple metal plugs, wherein the multiple metal layers are connected by the multiple metal plugs. A cavity is formed between the multilayer structure and the fixed electrode. Each metal layer in the multilayer structure includes multiple metal sections. The multiple metal sections of one metal layer and those of at least another metal layer are staggered to form a substantially blanket surface as viewed from a moving direction of an acoustic wave.Type: GrantFiled: April 23, 2017Date of Patent: September 25, 2018Assignee: PIXART IMAGING INCORPORATIONInventor: Chuan-Wei Wang
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Patent number: 10073093Abstract: The present disclosure provides methods and systems for assaying a sample. A microfluidic device to perform an assay of a sample (e.g., biological sample) is described having a sample application site, a porous component and a flow channel. The porous component provides for uniform dissolution of a reagent and mixing of the sample and reagent without filtering the sample.Type: GrantFiled: September 13, 2017Date of Patent: September 11, 2018Assignee: Becton, Dickinson and CompanyInventors: Scott Joseph Bornheimer, Jeffrey Sugarman, Wei Huang, Edward Michael Goldberg, Ming Tan
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Patent number: 10037980Abstract: A fabricating method of a semiconductor light emitting device includes disposing a plurality of non-conductive walls on a substrate. An alignment position is formed between every two adjacent non-conductive walls. A plurality of semiconductor light emitting units on a first carrier board are respectively aligned to the alignment positions. The semiconductor light emitting units are divided into a plurality of groups. The semiconductor light emitting units in one of the groups are dissociated from the first carrier board. Thus, the semiconductor light emitting units in the group fall into the corresponding alignment positions due to gravity. Each of the semiconductor light emitting units is electrically connected with the substrate through a first electrode. A conductive layer is formed on the semiconductor light emitting units. Accordingly, the semiconductor light emitting units are electrically connected together to the conductive layer through second electrodes.Type: GrantFiled: June 26, 2017Date of Patent: July 31, 2018Assignee: Industrial Technology Research InstituteInventors: Yu-Wei Huang, Tao-Chih Chang, Chih-Ming Shen
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Patent number: 10005082Abstract: A microfluidic circuit element comprising a microfluidic main channel and nano interstices is disclosed. The nano interstices are formed at both sides of the main channel and are in fluid communication with the main channel. The nano interstices have a height less than that of the main channel, gives more driving force of the microfluidic channel and provides stable flow of a fluid. The microfluidic circuit element may be made from a plastic material having a contact angle of 90 degrees or less. The microfluidic circuit element is particularly useful when filling a liquid sample to the channel which is empty or filled with air and shows greatly improved a storage stability.Type: GrantFiled: October 23, 2015Date of Patent: June 26, 2018Assignee: INCYTO CO., LTD.Inventors: Sin Kil Cho, Seok Chung
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Patent number: 10004453Abstract: A neural probe structure has a probe having a microfluidic channel. The probe is inserted into an inside of a subject. A body to which the probe is fixed has a fluid entrance communicating with the microfluidic channel. A cover element is fixed to the body to cover the fluid entrance. The cover element has a connecting opening to which an external conduit is connected, and a fluid delivery channel extending such that the connecting opening and the fluid entrance are in fluid communication. A fluid fed from the external conduit flows along the fluid delivery channel, goes into the fluid entrance, and is delivered to the subject through the microfluidic channel.Type: GrantFiled: August 29, 2016Date of Patent: June 26, 2018Assignee: Korea Institute of Science and TechnologyInventors: Il-Joo Cho, Eui Sung Yoon, Hyogeun Shin, Uikyu Chae, Hyunjoo Jenny Lee
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Patent number: 9999943Abstract: A method of manufacturing a mask includes forming a first hole in a base material using a laser, the first hole penetrating through the base material from a first surface to a second surface different than the first surface, and expanding the first hole using an etchant to form a second hole.Type: GrantFiled: April 6, 2016Date of Patent: June 19, 2018Assignee: Samsung Display Co., LTd.Inventors: Youngmin Moon, Sungsoon Im, Minho Moon, Soonchul Chang
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Patent number: 9995155Abstract: A lock apparatus securing a blade to a hub, the lock apparatus comprising a planar element having a spring actuable between an expanded position and a compressed position without deviation from the plane of the element, wherein in the expanded position of the spring the planar element is partly located in a slot provided in the blade, the spring being compressible to its compressed position to disengage the planar element from the slot.Type: GrantFiled: September 14, 2015Date of Patent: June 12, 2018Assignee: ROLLS-ROYCE plcInventor: David Alan Carnell
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Patent number: 9991164Abstract: Methods of singulating semiconductor die. Specific implementations may include: providing a semiconductor wafer including a plurality of die located on a first side of the semiconductor wafer where the plurality of die include a desired thickness. The method may include etching a plurality of trenches into the semiconductor wafer from the first side of the semiconductor wafer where the plurality of trenches is located adjacent to a perimeter of the plurality of die. A depth of the plurality of trenches may be greater than the desired thickness of the plurality of die. The method may also include mounting the first side of the semiconductor wafer to a tape, thinning a second side of the semiconductor wafer, exposing the plurality of trenches while thinning the second side, and singulating the plurality of die through exposing the plurality of trenches.Type: GrantFiled: June 22, 2016Date of Patent: June 5, 2018Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Michael John Seddon
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Patent number: 9972531Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.Type: GrantFiled: October 12, 2016Date of Patent: May 15, 2018Assignee: SOCIONEXT INC.Inventor: Kenichi Watanabe
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Patent number: 9965846Abstract: A method and apparatus for detecting crystal orientation of a silicon wafer is proposed. The detection method uses a camera shooting device to irradiate the silicon wafer in a rotation manner in different angular directions and obtains the corresponding reflection intensities, based on which a reflection curve is drawn for a grain of interest in a polar coordinate system; normal directions of three or more faces of a regular octahedron of a grain <111> are determined by identifying a pixel brightness extreme value in the reflection curve, and then all normal vectors of the regular octahedron are calculated, so that a crystal orientation of the grain of interest may be calculated. The camera shooting device has a light source and one or more camera shooting probes.Type: GrantFiled: May 13, 2014Date of Patent: May 8, 2018Assignee: Trina Solar Co., LtdInventors: Shaoyong Fu, Zhen Xiong
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Patent number: 9931600Abstract: A mixing assembly includes an inlet, an outlet and a mixing chamber, the inlet is fluidly connected to the outlet through a plurality of micro fluid flow paths in a direction perpendicular from the inlet. The micro fluid flow paths fluidly connect to the perpendicular inlet via a transition portion. The micro fluid flow paths are constructed radially inwardly to a concentration area in the mixing chamber. By directing multiple fluid flows to a concentrated area within the mixing chamber at high speeds, the energy dissipated at the point of collision is maximized, which helps to increase consistency and quality of mixing, and to reduce particle size of the fluid in the mixing chamber.Type: GrantFiled: July 10, 2015Date of Patent: April 3, 2018Assignee: MICROFLUIDICS INTERNATIONAL CORPORATIONInventors: Renqiang Xiong, John Michael Bernard
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Patent number: 9932225Abstract: A method of forming a Micro-Electro-Mechanical System (MEMS) includes forming a lower electrode on a first insulator layer within a cavity of the MEMS. The method further includes forming an upper electrode over another insulator material on top of the lower electrode which is at least partially in contact with the lower electrode. The forming of the lower electrode and the upper electrode includes adjusting a metal volume of the lower electrode and the upper electrode to modify beam bending.Type: GrantFiled: May 6, 2016Date of Patent: April 3, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christopher V. Jahnes, Anthony K. Stamper
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Patent number: 9914295Abstract: A method for manufacturing a structure having a substrate in which holes are formed and a photosensitive resin layer provided on the substrate in such a manner as to cover at least a part of the holes includes a process of preparing a substrate in which holes formed by a surface in which a wavelike shape is formed and a photosensitive resin layer provided on the substrate in such a manner as to cover at least a part of the holes and an exposure process of exposing the photosensitive resin layer on the substrate.Type: GrantFiled: March 2, 2016Date of Patent: March 13, 2018Assignee: Canon Kabushiki KaishaInventors: Hiroshi Higuchi, Masataka Kato, Yoshinao Ogata, Toshiyasu Sakai, Takayuki Kamimura, Tetsushi Ishikawa, Atsunori Terasaki, Masahiko Kubota, Ryoji Kanri, Yoshiyuki Fukumoto, Yasuaki Tominaga, Tamaki Sato, Masafumi Morisue
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Patent number: 9897798Abstract: An electro-optical device is configured by a laminated body of a second conductive layer and a reflective layer for a mirror. The second conductive layer includes a mirror support post facing a concave portion at a side opposite to a substrate, and a flat plate which extends from an end portion of the mirror support post and faces the substrate. The concave portion is filled with the resin. Surfaces of the flat plate and the resin configure a continuous plane. The reflective layer for a mirror is laminated on a surface of the resin at a side opposite to the substrate, and a surface of the flat plate of the second conductive layer at a side opposite to the substrate.Type: GrantFiled: March 3, 2016Date of Patent: February 20, 2018Assignee: SEIKO EPSON CORPORATIONInventor: Satoshi Ito
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Patent number: 9890035Abstract: A method is provided for manufacturing a micromechanical component including a substrate and including a cap, which is connected to the substrate and, together with the substrate, encloses a first cavity, a first pressure prevailing and a first gas mixture having a first chemical composition being enclosed in the first cavity. A first crystalline layer or a first amorphous layer or a first nanocrystalline layer or a first polycrystalline layer is deposited on or grown on a surface of the substrate or of the cap. A recess is introduced into the substrate or into the cap for accommodating the first crystalline layer or the first amorphous layer or the first nanocrystalline layer or the first polycrystalline layer.Type: GrantFiled: January 9, 2017Date of Patent: February 13, 2018Assignee: ROBERT BOSCH GMBHInventors: Achim Breitling, Frank Reichenbach, Jochen Reinmuth, Julia Amthor