Abstract: A method for manufacturing a printing plate to acheive a precise and fine pattern by minimizing a variation of etching critical dimension is disclosed. The method uses a hard mask having an opening on an insulating substrate to form a first trench having a first depth in the insulating substrate. A first etching stopper and a first photoresist may be applied on a surface of the insulating substrate including the first trench for patterning the first photoresist by exposing the first photoresist. Likewise, a second and third trench may be formed.

Abstract: Devices based on spinodally decomposed periodic structures and their fabrication techniques.

Abstract: Broadly speaking, methods and an apparatus are provided for removing an inorganic material from a substrate. More specifically, the methods provide for removing the inorganic material from the substrate through exposure to a high density plasma generated using an inductively coupled etching apparatus. The high density plasma is set and controlled to isotropically contact particular regions of the inorganic material to allow for trimming and control of a critical dimension associated with the inorganic material.

Abstract: A plasma etching method etches an organic film formed on a target substrate by using a plasma of a processing gas via a silicon-containing mask. The processing gas is a gaseous mixture of an oxygen-containing gas, a rare gas and a carbon fluoride gas. A computer-executable control program controls a plasma etching apparatus to perform the plasma etching method. A computer-readable storage medium stores therein a computer-executable control program.

Abstract: Method and apparatus for etching a metal layer disposed on a substrate, such as a photolithographic reticle, are provided. In one embodiment, a method is provided for processing a substrate including positioning a substrate having a metal photomask layer disposed on a optically transparent material in a processing chamber, introducing a processing gas processing gas comprising an oxygen containing gas, a chlorine containing gas, at least one of trifluoromethane (CHF3), sulfur hexafluoride (SF6), hexafluoroethane (C2F6) or ammonia (NH3) and optionally a chlorine-free halogen containing gas and/or an insert gas, into the processing chamber, generating a plasma of the processing gas in the processing chamber, and etching exposed portions of the metal layer disposed on the substrate.

Abstract: A plasma etching method includes accommodating a target substrate in a processing chamber; supplying a processing gas from a processing gas supplying mechanism disposed to face the target substrate and configured to be able to supply different processing gases to a central portion and a peripheral portion of the target substrate; and generating a plasma of the processing gas to perform a plasma etching on a lower organic resist film formed on the target substrate by using, as a mask, an intermediate layer made of an inorganic material and an upper photosensitive resist film that are formed on the lower organic resist film. As the processing gas, a gas containing CH4 gas is supplied, and a flow rate of the CH4 gas supplied to the peripheral portion is set to be higher than a flow rate of the CH4 gas supplied to the central portion.

Abstract: Method for fabricating a semiconductor device in which a by-product of etching is deposited on a photoresist film for using as a mask. The method for fabricating a semiconductor device includes the steps of depositing a polysilicon, and a bottom anti-refection coating on an entire surface of a substrate in succession, forming a photoresist film pattern on a predetermined portion of the bottom anti-refection coating, etching the bottom anti-refection coating by using the photoresist film pattern to deposit by-product of the etching on sidewalls of the photoresist pattern to form spacers, and etching the polysilicon by using the photoresist film pattern and the spacers, to form a line.

Abstract: A method of cleaning a wafer after an etching process is provided. A substrate having an etching stop layer, a dielectric layer, a patterned metal hard mask sequentially formed thereon is provided. Using the patterned metal hard mask, an opening is defined in the dielectric layer. The opening exposes a portion of the etching stop layer. A dry etching process is performed in the environment of helium to remove the etching stop layer exposed by the opening. A dry cleaning process is performed on the wafer surface using a mixture of nitrogen and hydrogen as the reactive gases. A wet cleaning process is performed on the wafer surface using a cleaning solution containing a trace amount of hydrofluoric acid.

Abstract: A method for sidewall etching includes providing a substrate having a trench defined therein, with the trench having fill material disposed over a bottom thereof, along a sidewall thereof, and at the trench opening. The fill material along the sidewall of the trench and at the trench opening is removed without removing the fill material disposed over the bottom of the trench. The fill material along the sidewall and at the trench opening may be removed without removing the fill material disposed over the bottom of the trench by inhibiting a reaction between an etchant and the fill material over the bottom of the trench. The reaction between the etchant and the fill material may be inhibited by causing an air bubble to form at the bottom of the trench. The air bubble may be formed by inverting the substrate, and immersing the inverted substrate in an etchant.

Abstract: A method for removing photoresist is described. A substrate having a photoresist to be removed thereon is provided, and then an ashing process is performed to remove most of the photoresist. The substrate is then subjected to a surface treatment that provides sufficient energy for the extra electrons caused by the ashing process to escape from the substrate, and the remaining photoresist and polymer are stripped with stripping solvents after the surface treatment.

Abstract: A plasma processing method performs a plasma processing on a substrate mounted on a mounting table installed in an airtight processing chamber, the mounting table having a smaller size than the substrate. The substrate having a surface, on which a resist mark is formed, is mounted on the mounting table and then electrostatically adsorbed on the mounting table by applying a voltage to an electrostatic chuck. The surface of the substrate is etched by using a plasma of an etching gas while the substrate is cooled through a heat transfer between the substrate and the mounting table via a thermally conductive gas supplied between a top surface of the mounting table and a bottom surface of the substrate. The supply of the thermally conductive gas is stopped, and the resist mask on the substrate is ashed by using a plasma of an ashing gas containing O2.

Abstract: In a plasma processing system, including a plasma processing chamber, a method of optimizing the etch resistance of a substrate material is described. The method includes flowing pre-coat gas mixture into the plasma processing chamber, wherein the pre-coat gas mixture has an affinity for a etchant gas flow mixture; striking a first plasma from the pre-coat gas mixture; and introducing a substrate comprising the substrate material. The method also includes flowing the etchant gas mixture into the plasma processing chamber; striking a second plasma from the etchant gas mixture; and etching the substrate with the second plasma. Wherein the first plasma creates a pre-coat residual on a set of exposed surfaces in the plasma processing chamber, and the etch resistance of the substrate material is maintained.

Abstract: A fin mask for forming saddle type fins in each of active regions formed in an island shape having a certain size with a major axis and a minor axis includes a first fin mask of a line type, and a second fin mask of an island type, wherein the first fin mask and the second fin mask in combination expose saddle type fin regions and cover ends of the neighboring active regions along the major axis.

Abstract: A semiconductor device fabrication method comprises (1) forming a patterned mask layer on an oxide layer of a Mn-containing perovskite type oxide; (2) heat-treating the oxide layer; and (3) patterning the oxide layer with an etching solution containing at least one of hydrochloric acid, sulfuric acid, and nitric acid after the heat treatment of the oxide layer.

Abstract: An emitter array produced using etch mask and a method for making such an etch mask. The emitter comprises a substrate, forming a conducting layer on the substrate, forming an emitting layer on the conducting layer, forming an etch mask having a controlled distribution of a plurality of mask sizes over the emitting layer, and forming at least one emitter by removing portions of the emitting layer using the etch mask. The method for making the etch mask comprises forming an etch mask layer over an emitting layer, forming a patterning layer having a controlled distribution of mask sizes over the etch mask layer, and forming the etch mask by removing portions of the etch mask layer using the controlled distribution of mask sizes in the patterning layer.

Abstract: A microneedle array module is disclosed comprising a multiplicity of microneedles affixed to and protruding outwardly from a front surface of a substrate to form the array, each microneedle of the array having a hollow section which extends through its center to an opening in the tip thereof. A method of fabricating the microneedle array module is also disclosed comprising the steps of: providing etch resistant mask layers to one and another opposite surfaces of a substrate to predetermined thicknesses; patterning the etch resistant mask layer of the one surface for outer dimensions of the microneedles of the array; patterning the etch resistant mask layer of the other surface for inner dimensions of the microneedles of the array; etching unmasked portions of the substrate from one and the other surfaces to first and second predetermined depths, respectively; and removing the mask layers from the one and the other surfaces.

Abstract: The present invention illustrates a bulk silicon etching technique that yields straight sidewalls, through wafer structures in very short times using standard silicon wet etching techniques. The method of the present invention employs selective porous silicon formation and dissolution to create high aspect ratio structures with straight sidewalls for through wafer MEMS processing.

Abstract: A new method is provided for the creation of an inductor. Layers of pad oxide, a thick layer of dielectric and an etch stop layer are successively created over the surface of a substrate. The layers of etch stop material and dielectric are patterned and etched, creating an inductor pattern whereby the inductor pattern created in the layer of dielectric is located close to the surface of the layer of dielectric. Optionally, support pillars for the inductor can be created at this time through the layer of dielectric. The inductor pattern in the layer of dielectric is filled with metal, the etch stop layer and the layer of dielectric is removed from above the metal fill, additionally exposing the layer of dielectric. The additionally exposed layer of dielectric is etched using a slope etcher.

Abstract: A selective etching method with lateral protection function is provided. The steps includes: (a) providing a substrate; (b) forming a plurality of tunnels; (c) forming a lateral strengthening structure at a peripheral wall of the tunnels; (d) removing a bottom portion of the lateral strengthening structure, and a part of the substrate by an etching process so as to form a lower structure and expose an unstrengthened structure; and (f) etching the unstrengthened structure laterally so as to form an upper structure.

Abstract: A manufacturing method of a magnetic head includes a process for forming a lift-off mask pattern on a magnetoresistance effect element, such that the upper part of the lift-off mask pattern is larger in size than the lower part, a process for forming a couple of electrodes on the magnetoresistance effect element using the lift-off mask pattern as a mask, and a process for removing the lift-off mask pattern. The process for forming the lift-off mask pattern is performed according to a dry etching process.

Abstract: The described embodiments relate to a slotted substrate and methods of forming same. One exemplary method patterns a hardmask on a first substrate surface sufficient to expose a first area of the first surface and forms a slot portion in the substrate through less than an entirety of the first area of the first surface. The slot portion has a cross-sectional area at the first surface that is less than a cross-sectional area of the first area. After forming the slot portion, the method etches the substrate to remove material from within the first area to form a fluid-handling slot.

Abstract: An improved method is provided for fabricating a polarisation rotator in a rib waveguide having a propagation axis and opposite side walls. The method includes etching a pit in the substrate surface to form a recess in one of the side walls of the waveguide, during formation of the waveguide on the substrate surface, so as to provide an asymmetric waveguide section for imparting polarisation rotation to radiation propagated along the propagation axis. Preferably the pit is formed by a wet etching step forming an upper side surface within the recess that is inclined relative the waveguide side walls, and the waveguide side walls are formed by a dry etching step to extend perpendicularly to the substrate surface. In addition the dry etching step forms a lower side surface adjoining the upper side surface within the recess and tilted relative to the upper side surface.

Abstract: A mask frame assembly for evaporation includes a mask and a frame which supports the mask. The mask includes a metal layer having a predetermined pattern, and a coating layer which is formed on a surface of the metal layer so as to increase a precision of the predetermined pattern and a surface roughness of the mask.

Abstract: According to a method for producing a solid body (1) including a microstructure (2), the surface of a substrate (3) is provided with a masking layer (6) that is impermeable to a substance to be applied. The substance is then incorporated into the substrate regions not covered by the masking layer (6). A heat treatment is used to diffuse the substance into a substrate region covered by the masking layer (6) such that a concentration gradient of the substance is created in the substrate region covered by the masking layer (6), proceeding from the edge of the masking layer (6) inward with increasing distance from the edge. The masking layer (6) is then removed to expose the substrate region under this layer, and a near-surface layer of the substrate (3) in the exposed substrate region is converted by a chemical conversion reaction into a coating (9) which has a layer thickness profile corresponding to the concentration gradient of the substance contained in this near-surface layer.

Abstract: New methods for fabrication of silicon microstructures have been developed. In these methods, an etching delay layer is deposited and patterned so as to provide differential control on the depth of features being etched into a substrate material. Compensation for etching-related structural artifacts can be accomplished by proper use of such an etching delay layer.

Abstract: In a mass flow sensor having a layered structure on the upper side of a silicon substrate (1), and having at least one heating element (8) patterned out of a conductive layer in the layered structure, thermal insulation between the heating element (8) and the silicon substrate (1) is achieved by way of a silicon dioxide block (5) which is produced beneath the heating element (8) either in the layered structure on the silicon substrate (1) or in the upper side of the silicon substrate (1). As a result, the sensor can be manufactured by surface micromechanics, i.e. without wafer back-side processes.

Abstract: A method of easily manufacturing a nano-gap electrode by using a focused ion beam lithography includes a layer depositing step of depositing an electrode layer and a metal mask layer in this order on an insulating substrate, a mask pattern forming step of etching the metal mask layer by using the focused ion beam and thereby forming a mask pattern, a dry etching step of transferring a pattern to the electrode layer by dry etching, and a wet etching step of removing the metal mask layer by using a solution that selectively dissolves the metal mask layer compared to the electrode layer.

Abstract: A metal hardmask for use with a Dual Damascene process used in the manufacturing of semiconductor devices. The metal hardmask has advantageous translucent characteristics to facilitate alignment between levels while fabricating a semiconductor device and avoids the formation of metal oxide residue deposits. The metal hardmask comprises a first or primary layer of TiN (titanium nitride) and a second or capping layer of TaN (tantalum nitride).

Abstract: A method for forming optical devices on-planar substrates, as well as optical devices formed by the method are described. The method uses a linear injection APCVD process to form optical waveguide devices on planar substrates. The method is performed at approximately atmospheric pressure. According to the method, a wafer with a lower cladding layer already formed by either CVD or oxidation is placed on a conveyer, which may include a heating element. The heated wafer is transported underneath a linear injector such that the chemicals from the linear injector react on the wafer surface to form a core layer. After the core layer is formed, photoresist is spun on the surface of the wafer, and then standard lithography is used to pattern the optical devices. Next, reactive ion etching (RIE) is used to form waveguide lines. The remaining photoresist is then removed. An upper cladding layer is formed to substantially cover the core regions.

Abstract: The present invention provides a method for forming a via (e.g., a trench, via or contact) in a substrate. The method, in one embodiment of the invention, includes patterning an opening 220 in a photoresist layer 210 located over an intermediate layer located over a substrate. In that particular embodiment the opening 220 has a predetermined width 230. The method may further include etching into the intermediate layer 120 such that an intermediate opening 310 is formed, the intermediate opening 310 having a decreasing width that terminates at a targeted width 320 less than the predetermined width 230. Additionally, the method may include continuing the etching within the intermediate opening 310 and at least partially into the substrate 110 to form a via opening 510 in the substrate. In this particular embodiment, the width 520 of the via opening 510 is substantially equal to the targeted width 320.

Abstract: A method for etching a silicon on insulator (SOI) substrate includes opening a hardmask layer formed on an SOI layer, and etching through the SOI layer, a buried insulator layer underneath the SOI layer, and a bulk silicon layer beneath the buried insulator layer using a single etch step.

Abstract: A method for forming fine grooves including forming a first silicon-nitride layer on a substrate, forming a first poly-silicon layer on the first silicon-nitride layer, forming a second silicon-nitride layer on the first poly-silicon layer, patterning the second silicon-nitride layer, etching the first poly-silicon layer using the patterned second silicon-nitride layer as a mask, forming at least one patterned oxidized portion of the first poly-silicon layer by oxidizing the substrate, first silicon-nitride layer, etched first poly-silicon layer, and patterned second silicon-nitride layer, removing the patterned second silicon-nitride layer and etched first poly-silicon layer such that the first silicon-nitride layer and at least one patterned oxidized portion of the first poly-silicon layer remain on the substrate, and forming a plurality of fine grooves over the substrate by plasma etching the first silicon-nitride layer using the at least one patterned oxidized portion of the first poly-silicon layer as a

Abstract: A chromeless phase lithography mask (30) that does not require photoresist to manufacture has a quartz substrate (32) is etched by using a plasma (38) containing one of a nitrogen augmented hydro-fluorocarbon oxygen mixture and a nitrogen augmented fluorocarbon oxygen mixture. Various hydro-fluorocarbons or fluorocarbons may be used. The nitrogen addition results in etched openings in the quartz substrate that have substantially vertical sidewalls in a uniform manner across the substrate. Surface roughness is minimized and edges of the openings are well-defined with minimal rounding. The etch rate is rendered controllable by reducing bias power without degrading a desired vertical sidewall profile.

Abstract: Lines are fabricated by patterning a hard mask to provide a line segment, the line segment having a first dimension measured across the line segment; reacting a surface layer of the line segment to form a layer of a reaction product on a remaining portion of the line segment; and removing the reaction product without attacking the remaining portion of the line segment and without attacking the substrate to form the line segment with a dimension across the line segment that is smaller than the first dimension.

Abstract: There are provided a method of processing an amorphous material which is capable of forming surface projections of uniform height in desired positions on the amorphous material, and a magnetic disk substrate using the amorphous material. A predetermined pressure is applied to parts of a surface of an amorphous material to form high-density compressed layers, and a surface layer of the amorphous material is removed using a treatment agent that has a different removal capacity in the compressed layers and a remaining uncompressed layer, thus making the compressed layers project out. For example, the treatment agent may be an etching solution having a different etching rate in the compressed layers and the uncompressed layer.

Abstract: A method for fabricating a magnetic memory element structure comprises providing a dielectric layer having a conducting via. A first magnetic layer is formed overlying the dielectric layer and is in electrical communication with the conducting via. A non-magnetic layer and a second magnetic layer are formed overlying the first magnetic layer. A first conductive layer is deposited overlying the second magnetic layer and is patterned. A portion of the second magnetic layer is exposed and is transformed to form an inactive portion and an active portion. The active portion comprises a portion of a memory element and the inactive portion comprises an insulator. A sidewall spacer is formed about at least one sidewall of the first conductive layer and a masking tab is formed that overlies a portion of the memory element and extends to overlie at least a portion of the conducting via.

Abstract: A method for making an emitter for a display device, an emitter array produced by such method, an etch mask used during such method, and a method for making such an etch mask are disclosed. The method for making the emitter comprises providing a substrate, forming a conducting layer on the substrate, forming an emitting layer on the conducting layer, forming an etch mask having a controlled distribution of a plurality of mask sizes over the emitting layer, and forming at least one emitter by removing portions of the emitting layer using the etch mask. The method for making the etch mask comprises forming an etch mask layer over an emitting layer, forming a patterning layer having a controlled distribution of mask sizes over the etch mask layer, and forming the etch mask by removing portions of the etch mask layer using the controlled distribution of mask sizes in the patterning layer.

Abstract: Form an opening in a dielectric layer formed on a substrate comprises depositing a hard mask composed of an etch resistant material over a dielectric layer, e.g. a silicon oxide. Use a photoresist mask to expose the hard mask. Use a fluorocarbon plasma to etch through the window to form an opening through the hard mask. Then etch through the hard mask opening to pattern the dielectric layer. The hard mask comprises an RCH/RCHX material with the structural formula R:C:H or R:C:H:X, where R is selected from Si, Ge, B, Sn, Fe, Ti and X is selected from O, N, S and F. The plasma etching process employs a) a gas mixture comprising N2; fluorocarbon (CHF3, C4F8, C4F6, CF4, CH2F2, CH3F); an oxidizer (O2, CO2), and a noble diluent (Ar, He); b) a high DC bias (500-3000 Volts bias on the wafer); 3) medium pressure (20-100 mT.; and d) moderate temperatures (?20 to 60°).

Abstract: A method of forming a fluid ejecting device such as an ink jet printing device that includes forming a plurality of fluid drop generators on a first surface of a silicon substrate, forming a partial fluid feed slot in the silicon substrate by deep reactive ion etching, and forming a fluid feed slot by wet etching the partial fluid feed slot.

Abstract: A process of using a-C:H layer as a hardmask material with tunable etch resistivity in a RIE process that alleviates the addition of a layer forming gas to the etchant when making a semiconductor device, comprising: a) providing a semiconductor substrate; b) forming a hardmask of amorphous carbon-hydrogen (a-C:H) layer by plasma enhancement over the semiconductor substrate; c) forming an opening in the hardmask layer to form an exposed surface portion of the hardmask layer; and d) etching the exposed surface portion of the hardmask layer without the addition of a layer forming gas using RIE to form a trench feature with sufficient masking and side wall protection.

Abstract: A method of forming small features, comprising the following steps. A substrate having a dielectric layer formed thereover is provided. A spacing layer is formed over the dielectric layer. The spacing layer has a thickness equal to the thickness of the small feature to be formed. A patterned, re-flowable masking layer is formed over the spacing layer. The masking layer having a first opening with a width “L”. The patterned, re-flowable masking layer is re-flowed to form a patterned, re-flowed masking layer having a re-flowed first opening with a lower width “1”. The re-flowed first opening lower width “1” being less than the pre-reflowed first opening width “L”. The spacing layer is etched down to the dielectric layer using the patterned, re-flowed masking layer as a mask to form a second opening within the etched spacing layer having a width equal to the re-flowed first opening lower width “1”. Removing the patterned, re-flowed masking layer.

Abstract: A method for making an emitter for a display device, an emitter array produced by such method, an etch mask used during such method, and a method for making such an etch mask. The method for making the emitter comprising providing a substrate, forming a conducting layer on the substrate, forming an emitting layer on the conducting layer, forming an etch mask having a controlled distribution of a plurality of mask sizes over the emitting layer, and forming at least one emitter by removing portions of the emitting layer using the etch mask. The method for making the etch mask comprising forming an etch mask layer over an emitting layer, forming a patterning layer having a controlled distribution of mask sizes over the etch mask layer, and forming the etch mask by removing portions of the etch mask layer using the controlled distribution of mask sizes in the patterning layer.

Abstract: Three fundamental and three derived aspects of the present invention are disclosed. The three fundamental aspects each disclose a process sequence that may be integrated in a full process. The first aspect, designated as “latent masking”, defines a mask in a persistent material like silicon oxide that is held abeyant after definition while intervening processing operations are performed. The latent oxide pattern is then used to mask an etch. The second aspect, designated as “simultaneous multi-level etching (SMILE)”, provides a process sequence wherein a first pattern may be given an advanced start relative to a second pattern in etching into an underlying material, such that the first pattern may be etched deeper, shallower, or to the same depth as the second pattern. The third aspect, designated as “delayed LOCOS”, provides a means of defining a contact hole pattern at one stage of a process, then using the defined pattern at a later stage to open the contact holes.

Abstract: A method for correcting characteristics of an attenuated phase-shift mask having an attenuated layer including (a) storing a data in a memory, which shows a correlation between characteristics and process conditions, (b) measuring the characteristics of the attenuated phase-shift mask, (c) calculating a appropriate process condition from the result of the step (b) and the data stored in the memory; and (d) soaking the attenuated phase-shift mask into a liquid solution for a certain time-that is calculated in the step (c) to change thickness and composition of the attenuated layer.

Abstract: A method for forming a microstructure from a substrate is provided. The method includes providing a monocrystalline substrate having a (100) orientation and subjecting a first portion of the substrate to ion bombardment to effect ion implantation to a desired penetration depth. A second portion of the substrate is etched to a depth at least as great as the desired penetration depth. The substrate then is thermally treated to form a microstructure at a surface of the substrate and to effect at least partial separation between the microstructure and the substrate.

Abstract: A microneedle array module is disclosed comprising a multiplicity of microneedles affixed to and protruding outwardly from a front surface of a substrate to form the array, each microneedle of the array having a hollow section which extends through its center to an opening in the tip thereof. A method of fabricating the microneedle array module is also disclosed comprising the steps of: providing etch resistant mask layers to one and another opposite surfaces of a substrate to predetermined thicknesses; patterning the etch resistant mask layer of the one surface for outer dimensions of the microneedles of the array; patterning the etch resistant mask layer of the other surface for inner dimensions of the microneedles of the array; etching unmasked portions of the substrate from one and the other surfaces to first and second predetermined depths, respectively; and removing the mask layers from the one and the other surfaces.

Abstract: A method and device can be used to pattern both regions of a printed circuit board which are provided for coarse conductor structures and regions which are provided for relatively fine conductor structures of the printed circuit board. In each case, this can be done via laser processing. Both regions are firstly coated with a continuous metallization layer and covered with an etch resistor. The coarse conductor structures are predefined with a laser beam with a relatively long wavelength by exposing the metal surfaces which are not required. In addition, the fine conductor structures are also pre-shaped by processing the etch resist with a laser beam with a relatively short wavelength. Then, in a common etching process, all the exposed surface regions of the metal layer are etched away so that only the coarse and fine conductor track structures which are covered by the remaining etch resist are left.

Abstract: Complex features and fine details are created in a carbon containing work piece by photolithography. A mask layer is deposited by evaporation onto the work piece. A desired pattern is created on the mask layer. The pattern is etched into the work piece and the remaining portion of the mask layer is dissolved.

Abstract: A method of etching a trench in a substrate using a dry plasma etch technique that allows precise control of lateral undercut. The method includes optionally forming at least one on-chip device or micro-machined structure in a surface of a silicon substrate, and covering the surface with a masking layer. A trench pattern is then imaged in or transferred to the masking layer for subsequent etching of the substrate. Upper portions of the trench are anisotropically etched in the substrate. The trench is then semi-anisotropically etched and isotropically etched in the substrate. By modifying isotropic etching time, a controlled lateral undercut can be achieved as the trench is etched vertically in the substrate.

Abstract: A method of forming a conductive device includes forming a conductive layer on a substrate; etching the conductive layer to form a plurality of conductive traces; etching the conductive layer to form at least one mask feature; and removing substrate material that is not covered by the at least one mask feature so as to form at least one mechanical alignment feature.