Mask Resist Contains Inorganic Material Patents (Class 216/51)
  • Patent number: 6696222
    Abstract: A dual damascene process is provided on a semiconductor substrate, having a conductive structure and a low-k dielectric layer covering the conductive structure. A first hard mask and a second hard mask are sequentially formed on the low-k dielectric layer, in which at least the hard mask contacting the low-k dielectric layer is of metallic material. Next, a first opening is formed in the second hard mask over the conductive structure, and a second opening is then formed in the first hard mask under the first opening. Afterward, the low-k dielectric layer that is not covered by the first hard mask is removed, thus a via hole is formed. Thereafter, the first hard mask that is not covered by the second hard mask is removed, and then the exposed low-k dielectric layer is removed. Thereby, a trench is formed over the via hole.
    Type: Grant
    Filed: July 24, 2001
    Date of Patent: February 24, 2004
    Assignee: Silicon Integrated Systems Corp.
    Inventors: Chen-Chiu Hsue, Shyh-Dar Lee
  • Patent number: 6689282
    Abstract: A method of forming emitter tips for use in a field emission array is disclosed. The tips are formed by utilizing a polymer residue that forms during the dry etch sharpening step to hold the mask caps in place on the emitter tips. The residue polymer continues to support the mask caps as the tips are over-etched, enabling the tips to be etched past sharp without losing their shape and sharpness. The dry etch utilizes an etchant comprised of fluorine and chlorine gases. The mask caps and residue polymer are easily removed after etching by washing the wafers in a wash of deionized water, or Buffered Oxide Etch.
    Type: Grant
    Filed: July 19, 2002
    Date of Patent: February 10, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Aaron R. Wilson
  • Patent number: 6679998
    Abstract: A method of forming a pattern in a layer of material on a substrate, comprising providing a plurality of spheres, covering the layer on the substrate with the plurality of spheres to form a mask, reducing the diameter of at least one sphere of the plurality of spheres, etching the layer on the substrate using at least one sphere having a reduced diameter as a mask, and etching the substrate.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: January 20, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Eric J. Knappenberger, Aaron R. Wilson
  • Patent number: 6679997
    Abstract: The present invention enables reduction of a film thickness of a protection film so as to eliminate destruction caused by stress of the protection film; to increase a film thickness of an organic insulation film so as to exhibit the function of the organic insulation film sufficiently; and to reduce irregularities of the protection film thickness. In the organic insulation film 18 formation method according to the present invention, an organic insulation film 18, a protection film 20, and a metal film are successively formed in this order on a substrate 10. On the metal film, a patterned photo-resist is formed so as to be used as a mask for etching the metal film. The remaining metal film is used as a mask when etching the protection film 20 and the organic insulation film 18. The protection film 20 can significantly reduce its thickness because the protection film 20 need not be used as a mask. The organic insulation film 18 can be set to an arbitrary thickness regardless of the protection film 20.
    Type: Grant
    Filed: August 11, 1999
    Date of Patent: January 20, 2004
    Assignee: NEC Compound Semiconductor Devices, Ltd.
    Inventor: Michihisa Kohno
  • Patent number: 6673719
    Abstract: A method for physical etching using a multilevel hard mask. A substrate having a multilayer structure thereon is provided. A BPSG layer, a masking material layer and a patterned photoresist layer are sequentially formed on the multilayer structure, wherein the masking material layer has a high selective etching ratio for the BPSG layer. A pattern of the patterned photoresist layer is transferred to the masking material layer, and then transferred to the BPSG layer. The masking material layer and the BPSG layer, which function as a multilevel hard mask, are used to physically etch the multilayer structure to form a trench therein.
    Type: Grant
    Filed: November 12, 2001
    Date of Patent: January 6, 2004
    Assignee: Nanya Technology Corporation
    Inventor: Kuen-Chi Ho
  • Patent number: 6664032
    Abstract: Disclosed is a method of producing a two-dimensional phase type optical element, wherein a first mask and a second mask made of different materials and both having a stripe-like shape are superposedly formed on a substrate, along different directions, respectively, and wherein positions of all levels to be defined are determined on the basis of at least one of the first and second masks.
    Type: Grant
    Filed: February 15, 2000
    Date of Patent: December 16, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventor: Ichiro Tanaka
  • Patent number: 6660173
    Abstract: A method of forming emitter tips for use in a field emission array is disclosed. The tips are formed by utilizing a polymer residue that forms during the dry etch sharpening step to hold the mask caps in place on the emitter tips. The residue polymer continues to support the mask caps as the tips are over-etched, enabling the tips to be etched past sharp without losing their shape and sharpness. The dry etch utilizes an etchant comprised of fluorine and chlorine gases. The mask caps and residue polymer are easily removed after etching by washing the wafers in a wash of deionized water, or Buffered Oxide Etch.
    Type: Grant
    Filed: May 22, 2002
    Date of Patent: December 9, 2003
    Assignee: Micron Technology, Inc.
    Inventor: Aaron R. Wilson
  • Publication number: 20030209517
    Abstract: A maskant plate is described which allows for protection of textured, diffusion-hardened surfaces on prosthetic devices while not interfering with common post-oxidation mass finishing procedures which are often used to form the finished product after surface oxidation.
    Type: Application
    Filed: May 8, 2002
    Publication date: November 13, 2003
    Inventors: Brian McGehee, Les Darby
  • Patent number: 6638441
    Abstract: A method for pitch reduction is disclosed. The method can form a pattern with a pitch ⅓ the original pitch formed by available photolithography technologies by only using one photo mask or one pattern transfer process, self-aligned etching back processes, and conventional deposition processes. By choosing appropriate layers to be deposited and etched, the pattern can be an etching mask or it can be a device structure itself.
    Type: Grant
    Filed: January 7, 2002
    Date of Patent: October 28, 2003
    Assignee: Macronix International Co., Ltd.
    Inventors: Ching-Yu Chang, Wei-Ming Chung
  • Patent number: 6635184
    Abstract: A method for pattern-etching thick alumina layers in the manufacture of thin film heads (TFH) by using compatible metallic mask layers and a wet chemical etchant. The deep alumina etching facilitates a studless TFH device where the coil and bonding pads are deposited and patterned simultaneously, and vias are later etched through the alumina overcoat layer to expose the bonding pads. The method also enables the etching of scribe-line grooves of street and alleys across the wafer for sawing and machining of sliders. These grooves eliminate most alumina chipping due to stress and damage introduced by the sawing and machining operations. Similarly, pattern-etching of the alumina undercoat facilitates the formation of precise craters for recessed structures. These can improve planarity and alleviate problems related to adverse topography and elevated features of TFH devices.
    Type: Grant
    Filed: April 21, 2000
    Date of Patent: October 21, 2003
    Inventors: Uri Cohen, Gene Patrick Bonnie
  • Patent number: 6602427
    Abstract: A method for fabricating a micromachined optical mechanical modulator based WDM transmitter/receiver module is described. The Fabry-Perot cavity of the mechanical modulator is structured from a three-polysilicon-layer stack formed on the surface of a single crystalline silicon substrate. The polysilicon membrane and its supporting polysilicon beams of the cavity are cut from the top polysilicon layer of the stack and are released by selective etching of their underlying polysilicon. The etched underlying polysilicon layer is heavily doped and then converted into porous polysilicon by anodization in HF solution. The polysilicon membrane and its supporting polysilicon are finally released using a reactive ion etch process to avoid stiction often generated in a wet etch process. A conic hole is formed on the backside of the single crystalline silicon substrate for receiving an optical fiber that can be passively aligned with the Fabry-Perot cavity.
    Type: Grant
    Filed: August 28, 2000
    Date of Patent: August 5, 2003
    Inventor: Xiang Zheng Tu
  • Patent number: 6589433
    Abstract: A process for fabricating an accelerometer, which includes providing a substrate with a layer of electrically conductive material on the substrate, micromachining the substrate to form a central electrical heater, a pair of temperature sensitive elements, and a cavity beneath the heater and the temperature sensing elements. Each temperature sensing element is spaced apart from said heater a distance in the range of 75 to 400 microns. The temperature sensing elements are located on opposite sides of the heater, thereby forming an accelerometer.
    Type: Grant
    Filed: April 30, 2001
    Date of Patent: July 8, 2003
    Assignee: Simon Fraser University
    Inventor: Albert M. Leung
  • Patent number: 6550131
    Abstract: A method for making a thin-film magnetic head with a magnetoresistive layer having a desired shaped to facilitate narrowing of the track width, wherein the surface, in the depth direction, is not curved, and wherein the shape and magnetic anisotropy of each sublayer of the magnetoresistive layer is stabilized to ensure improved reading characteristics.
    Type: Grant
    Filed: June 9, 2000
    Date of Patent: April 22, 2003
    Assignee: Alps Electric Co., Ltd.
    Inventor: Kiyoshi Sato
  • Publication number: 20030071018
    Abstract: A method for correcting characteristics of an attenuated phase-shift mask having an attenuated layer including (a) storing a data in a memory, which shows a correlation between characteristics and process conditions, (b) measuring the characteristics of the attenuated phase-shift mask, (c) calculating a appropriate process condition from the result of the step (b) and the data stored in the memory; and (d) soaking the attenuated phase-shift mask into a liquid solution for a certain time-that is calculated in the step (c) to change thickness and composition of the attenuated layer.
    Type: Application
    Filed: November 21, 2002
    Publication date: April 17, 2003
    Inventor: Katsuhiro Takushima
  • Patent number: 6547976
    Abstract: A method of manufacturing a planar or integrated optical circuit in which a core layer (20) is formed on a substrate (10) and patterned to define optical features (such as waveguides) using a mask having a first portion (30) defining the desired core patterns (20a) and a second portion (35) corresponding to one or more alignment marks (20b). After etching the core layer, only the first portion (30) of the mask is removed, the second portion (35) of the mask being left to provide alignment marks (20b) which are highly visible through the subsequently-deposited overclad layer (40). The alignment marks (20b) are very accurately positioned with respect to the core patterns (20a), thus enabling further optical devices to be overlaid on the existing structure with accurate alignment to the underlying core patterns. The mask material (35) left on the alignment marks (20b) may be partially oxidized before the overclad is deposited.
    Type: Grant
    Filed: December 13, 2000
    Date of Patent: April 15, 2003
    Assignee: Corning Incorporated
    Inventor: Alain M. J. Beguin
  • Publication number: 20030052082
    Abstract: Optical waveguides can be made accurately using conventional semiconductor processing and equipment by forming an opening in a suitable substrate, conformally depositing a first cladding layer in the opening, filling the opening with a core material, removing excess core material, as by chemical mechanical polishing, and depositing a second cladding layer thereover, said first and second cladding layers and said core material each having a different index of refraction. Such optical waveguides can be connected, horizontally and/or vertically, to other devices formed in or on the substrate.
    Type: Application
    Filed: September 19, 2001
    Publication date: March 20, 2003
    Inventors: Anisul Khan, Ajay Kumar, Sanjay Thekdi
  • Patent number: 6519822
    Abstract: A method for producing an electronic component includes placing an enclosed frame on a baseplate. A chip is provided to be fitted within the frame, forming a first given space between the chip and the baseplate and forming a second given space between the chip and the frame. The first given space is enclosed in a hermetically sealed manner by pressing a film onto the chip, except on a surface of the chip facing the baseplate, such that the film surrounds the chip and at least reaches the surface of the baseplate. The second given space is filled with a casting compound. The film is then removed at surface regions of the film being free of the casting compound. Finally, a cover composed of an electrically conductive material is applied on the chip, the casting compound and the frame.
    Type: Grant
    Filed: October 30, 2000
    Date of Patent: February 18, 2003
    Assignee: EPCOS AG
    Inventors: Alois Stelzl, Hans Krüger
  • Publication number: 20030029832
    Abstract: A method for forming ultra-fine width lines on a substrate avoids occurrence of overetch/underetch defects in the many etching steps, as solder layer or copper film etching steps. With the present method the line shape is able to be achieved close to an ideal shape, so that the quality of the lines is high and the integration of the substrate is also high.
    Type: Application
    Filed: August 13, 2001
    Publication date: February 13, 2003
    Applicant: Compeq Manufacturing Company Limited
    Inventor: Ting-Hao Lin
  • Patent number: 6518194
    Abstract: A method for using intermediate transfer layers for transferring nanoscale patterns to substrates and forming nanostructures on substrates. An intermediate transfer layer is applied to a substrate surface, and one or more mask templates are then applied to the intermediate transfer layer. Holes are etched through the intermediate transfer layer, and material may be deposited into the etched holes.
    Type: Grant
    Filed: December 28, 2000
    Date of Patent: February 11, 2003
    Inventors: Thomas Andrew Winningham, Kenneth Douglas
  • Patent number: 6514674
    Abstract: The back surface of a BOE (binary optical element) having a binary optical structure formed thereon is coated with a resist film. Chromium is then deposited on the BOE by means of electron beam evaporation so as to form an island structure with an island size of about 50 nm and an island-to-island distance of about 80 nm. The BOE is then etched with an etchant to a depth of 55 nm using the island structure as a mask thereby forming a pillar-shaped microstructure. The island structure used as the mask is removed by means of wet etching using an etchant, and the resist film on the back surface of the BOE is removed using a resist remover. Thus, a microstructure is obtained which has antireflection capability allowing suppression of reflection to a level of 1% or less for a wavelength of 248 nm.
    Type: Grant
    Filed: March 8, 2000
    Date of Patent: February 4, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yuichi Iwasaki
  • Patent number: 6508949
    Abstract: A method for correcting characteristics of an attenuated phase-shift mask having an attenuated layer including (a) storing a data in a memory, which shows a correlation between characteristics and process conditions, (b) measuring the characteristics of the attenuated phase-shift mask, (c) calculating a appropriate process condition from the result of the step (b) and the data stored in the memory; and (d) soaking the attenuated phase-shift mask into a liquid solution for a certain time that is calculated in the step (c) to change thickness and composition of the attenuated layer.
    Type: Grant
    Filed: July 18, 2000
    Date of Patent: January 21, 2003
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Katsuhiro Takushima
  • Patent number: 6503406
    Abstract: The invention relates to a method for producing magnetic sliders having a permanent protective coating of carbon over the air bearing surface. The method comprises the steps of: (a) depositing a temporary protective coating on a surface of the slider, the temporary protective coating comprising a layer carbon; (b) depositing a photoresist layer onto the temporary protective coating; (c) imagewise exposing the photoresist layer to radiation; (d) developing the image in the photoresist layer to expose the temporary protective coating; (e) transferring the image through the temporary protective coating and into the slider to form the air bearing pattern in the slider; (f) removing the temporary protective coating using nonreactive plasma; and (g) depositing a permanent protective coating comprising a layer of carbon.
    Type: Grant
    Filed: August 7, 2000
    Date of Patent: January 7, 2003
    Assignee: International Business Machines Corporation
    Inventors: Yiping Hsiao, Cherngye Hwang, Ciaran A. Fox, Richard Hsiao
  • Patent number: 6491835
    Abstract: The present disclosure provides a method for etching trenches, contact vias, or similar features to a depth of 100 &mgr;m and greater while permitting control of the etch profile (the shape of the sidewalls surrounding the etched opening). The method requires the use of a metal-comprising masking material in combination with a fluorine-comprising plasma etchant. The byproduct produced by a combination of the metal with reactive fluorine species must be essentially non-volatile under etch process conditions, and sufficiently non-corrosive to features on the substrate being etched, that the substrate remains unharmed by the etch process. Although aluminum is a preferred metal for the metal-comprising mask, other metals can be used for the masking material, so long as they produce an essentially non-volatile, non-corrosive etch byproduct under etch process conditions.
    Type: Grant
    Filed: December 20, 1999
    Date of Patent: December 10, 2002
    Assignee: Applied Materials, Inc.
    Inventors: Ajay Kumar, Anisul Khan, Wei Liu, John Chao, Jeff Chinn
  • Publication number: 20020175142
    Abstract: A method of forming a capacitor element is provided. After the barrier layer is formed on the dielectric layer, the lower electrode layer, the ferroelectric layer, and the upper electrode layer are formed on the barrier layer in this order. Thereafter, the etching mask having a pattern for a desired capacitor element is formed on the upper electrode layer. Using the etching mask, the upper electrode layer, the ferroelectric layer, the lower electric layer, and the barrier layer are selectively removed by dry etching. The etching gas containing fluorine (F) as one of its constituent elements is used in the step of selectively removing the barrier layer. The mask layer is etched back by an etching action in the same step, thereby eliminating the mask layer. The aspect ratio of the contact hole that exposes the upper capacitor electrode can be decreased by the thickness of the remaining mask layer. Therefore, a desired capacitor element can be formed by using a process (e.g.
    Type: Application
    Filed: March 15, 2002
    Publication date: November 28, 2002
    Applicant: NEC Corporation
    Inventor: Yukihiko Maejima
  • Patent number: 6485655
    Abstract: An internal coating on an internal passage wall exposed at a passage opening through an article external surface is protected from removal during repair of the article, including removal of at least a portion of an external coating, by a masking assembly disposed about the passage opening. The masking assembly comprises a masking member and a substantially flexible seal, substantially inert to a coating removal medium for the external coating. The masking member is shaped for disposition about the passage opening across a gap between the external surface and the masking member. The substantially flexible seal is disposed across the gap substantially to seal the gap.
    Type: Grant
    Filed: August 2, 2001
    Date of Patent: November 26, 2002
    Assignee: General Electric Company
    Inventors: Nripendra Nath Das, Stephen Joseph Ferrigno, Jim Dean Reeves, Michael Glenn Gordon
  • Publication number: 20020172897
    Abstract: Complex features and fine details are created in a carbon containing work piece by photolithography. A mask layer is deposited by evaporation onto the work piece. A desired pattern is created on the mask layer. The pattern is etched into the work piece and the remaining portion of the mask layer is dissolved.
    Type: Application
    Filed: May 17, 2001
    Publication date: November 21, 2002
    Inventor: Ilan Golecki
  • Publication number: 20020158044
    Abstract: A method for magnetic patterning of conductors includes imparting a pattern of magnetization into a magnetic material and depositing a substance onto the magnetic material that preferentially gathers according to the pattern in the magnetic material. A set of conductors are then formed such that the substance controls a pattern for the conductors.
    Type: Application
    Filed: April 26, 2001
    Publication date: October 31, 2002
    Inventor: Richard H. Henze
  • Patent number: 6464890
    Abstract: A method of forming a pattern in a layer of material on a substrate, comprising providing a plurality of spheres, covering the layer on the substrate with the plurality of spheres to form a mask, reducing the diameter of at least one sphere of the plurality of spheres, etching the layer on the substrate using at least one sphere having a reduced diameter as a mask, and etching the substrate.
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: October 15, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Eric J. Knappenberger, Aaron R. Wilson
  • Patent number: 6461526
    Abstract: A method of forming emitter tips for use in a field emission array is disclosed. The tips are formed by utilizing a polymer residue that forms during the dry etch sharpening step to hold the mask caps in place on the emitter tips. The residue polymer continues to support the mask caps as the tips are over-etched, enabling the tips to be etched past sharp without losing their shape and sharpness. The dry etch utilizes an etchant comprised of fluorine and chlorine gases. The mask caps and residue polymer are easily removed after etching by washing the wafers in a wash of deionized water, or Buffered Oxide Etch.
    Type: Grant
    Filed: August 14, 2000
    Date of Patent: October 8, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Aaron R. Wilson
  • Patent number: 6458284
    Abstract: A TiSiN (titanium silicon nitride) film or a multilayered film comprised of a TiSiN film and a TiSi film is used as a hard mask. The TiSiN film (1a) has good adherence to and a high etch selectivity to metal (2), and TiSi is a material having a higher etch selectivity to metal than TiSiN. The use of these materials as an etch mask solves problems with a conventional hard mask such as an SiO2 film. The use of the TiSiN film also as a barrier metal layer (3) allows the process to proceed rapidly in the steps of forming and removing the hard mask and the barrier metal layer. An etching method uses the hard mask made of the material which has good adherence to and a high etch selectivity to an electrode material and which requires the uncomplicated steps of forming and removing the same.
    Type: Grant
    Filed: February 1, 2000
    Date of Patent: October 1, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Keiichiro Kashihara
  • Patent number: 6432317
    Abstract: This is a method for masking a structure 12 for patterning micron and submicron features, the method comprises: forming at least one monolayer 32 of adsorbed molecules on the structure; prenucleating portions 46,48 of the adsorbed layer by exposing the portions corresponding to a desired pattern 36 of an energy source 42; and selectively forming build-up layers 66,68 over the prenucleated portions to form a mask over the structure to be patterned. Other methods are also disclosed.
    Type: Grant
    Filed: August 4, 1994
    Date of Patent: August 13, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Monte A. Douglas, Richard A. Stoltz
  • Publication number: 20020096493
    Abstract: A dry etching is performed using a mask made of a tantalum or a tantalum nitride under a reaction gas of a carbon monoxide with an additive of a nitrogen containing compound gas.
    Type: Application
    Filed: March 26, 2001
    Publication date: July 25, 2002
    Inventor: Kazuhiro Hattori
  • Patent number: 6420099
    Abstract: A method for patterning an aluminum-containing layer. A tungsten-containing layer is provided over an aluminum-containing layer. The tungsten-containing layer is patterned to form an opening therein, so that the opening exposes an underlying portion of the aluminum-containing layer. The patterned tungsten-containing layer is exposed to an etch having a substantially higher etch rate of the aluminum-containing layer than of the tungsten-containing layer to remove the exposed portion of the aluminum-containing layer.
    Type: Grant
    Filed: August 2, 1999
    Date of Patent: July 16, 2002
    Assignees: Infineon Technologies AG, International Business Machines Corporation
    Inventors: Martin Gutsche, Satish D. Athavale
  • Publication number: 20020074308
    Abstract: A method of manufacturing a planar or integrated optical circuit in which a core layer (20) is formed on a substrate (10) and patterned to define optical features (such as waveguides) using a mask having a first portion (30) defining the desired core patterns (20a) and a second portion (35) corresponding to one or more alignment marks (20b). After etching the core layer, only the first portion (30) of the mask is removed, the second portion (35) of the mask being left to provide alignment marks (20b) which are highly visible through the subsequently-deposited overclad layer (40). The alignment marks (20b) are very accurately positioned with respect to the core patterns (20a), thus enabling further optical devices to be overlaid on the existing structure with accurate alignment to the underlying core patterns. The mask material (35) left on the alignment marks (20b) may be partially oxidized before the overclad is deposited.
    Type: Application
    Filed: December 13, 2000
    Publication date: June 20, 2002
    Inventor: Alain M.J. Beguin
  • Publication number: 20020074307
    Abstract: In order to manufacture an integrated optical circuit, a first mask is formed on a first region of a substrate and defines the shape of at least one optical device (such as a waveguide). A second mask is formed on a second region of the substrate and corresponds to an optical structure (such as a periodic array structure or photonic crystal) to be formed in a second region of the substrate distinct from the first region. The first mask and the second mask are each made of a material which substantially resists a predetermined etching gas. The second mask may formed, patterned, and etched without adversely affecting the characteristics of the first mask.
    Type: Application
    Filed: December 5, 2000
    Publication date: June 20, 2002
    Inventors: Jean-Charles J.C. Cotteverte, Fernando Dias-Costa, Christophe F.P. Renvaze, Dusan Nedeljkovic
  • Publication number: 20020063110
    Abstract: Lines are fabricated by patterning a hard mask to provide a line segment, the line segment having a first dimension measured across the line segment; reacting a surface layer of the line segment to form a layer of a reaction product on a remaining portion of the line segment; and removing the reaction product without attacking the remaining portion of the line segment and without attacking the substrate to form the line segment with a dimension across the line segment that is smaller than the first dimension.
    Type: Application
    Filed: November 30, 2000
    Publication date: May 30, 2002
    Inventors: Marc W. Cantell, Wesley Natzle, Steven M. Ruegsegger
  • Patent number: 6391216
    Abstract: The invention provides a method for reactive-ion etching a magnetic material with a plasma of a mixed gas of carbon monoxide and a nitrogen-containing compound, the method comprising a step, in which a multilayered film comprising a magnetic material thin film having thereon a resist film formed on a substrate is exposed to an electron beam and then developed, to form a pattern on the resist film, a step, in which a mask material is vacuum deposited, a step, in which the resist is dissolved, to form a mask, and a step, in which a part of the magnetic material thin film that is not covered with the mask is removed by reactive ion etching with a plasma of a mixed gas of carbon monoxide and a nitrogen-containing compound, to form a pattern on the magnetic material thin film, and thus obtaining the magnetic material thin film finely worked.
    Type: Grant
    Filed: September 21, 1998
    Date of Patent: May 21, 2002
    Assignees: National Research Institute for Metals, Japan Science and Technology Corporation
    Inventor: Isao Nakatani
  • Patent number: 6387819
    Abstract: A method of etching an organic dielectric layer 10 on a substrate 15 with a high etching rate and a high etching selectivity ratio. The organic dielectric layer 10 comprises a low k dielectric material, such as a silicon-containing organic polymer, for example, benzocyclobutene. A patterned mask layer is formed on the organic dielectric layer 10, and the substrate 15 is placed in a process zone 35 of a process chamber 30. An energized process gas introduced into the process zone 35, comprises an oxygen-containing gas for etching the organic dielectric layer 10, a non-reactive gas for removing dissociated material to enhance the etching rate, and optionally, passivating gas for forming passivating deposits on sidewalls 90 of freshly etched features to promote anisotropic etching. Preferably, during etching, the temperature of substrate 15 is maintained at a low temperature of from about 15° C. of 80° C. to enhance the rate of etching of the dielectric layer.
    Type: Grant
    Filed: April 29, 1998
    Date of Patent: May 14, 2002
    Assignee: Applied Materials, Inc.
    Inventor: Min Yu
  • Patent number: 6387771
    Abstract: A method for forming a valve metal oxide for semiconductor fabrication in accordance with the present invention is disclosed and claimed. The method includes the steps of providing a semiconductor wafer, depositing a valve metal on the wafer, placing the wafer in an electrochemical cell such that a solution including electrolytes interacts with the valve metal to form a metal oxide when a potential difference is provided between the valve metal and the solution and processing the wafer using the metal oxide layer.
    Type: Grant
    Filed: June 8, 1999
    Date of Patent: May 14, 2002
    Assignee: Infineon Technologies AG
    Inventors: Oliver Genz, Alexander Michaelis
  • Patent number: 6379568
    Abstract: A diamond field emitter and a fabrication method thereof, in which a pretreatment is performed on a surface of an Si substrate in order that diamond nuclei are uniformly formed on the Si substrate during a diamond deposition, an oxide film such as an SiO2 film is deposited on the pretreated surface of the Si substrate and removed after an etching process so that diamond powder can be selectively remained during the etching process, thus the effect of the surface pretreatment of the Si substrate remains in the selected portion during the etching process, and it is also possible to uniformly deposit the diamond in said portion. According to the present invention, the diamond field emitter having excellent and uniform field emission characteristic can be manufactured because the field emission is easily achieved at a tip shaped field emission section, and, moreover, the diamond placed on an upper end portion of the tip increases electron emission effect.
    Type: Grant
    Filed: May 15, 2000
    Date of Patent: April 30, 2002
    Assignee: Korea Institute of Science and Technology
    Inventors: Young-Joon Baik, Joo-Yong Lee, Dong-Ryul Jeon
  • Publication number: 20020040884
    Abstract: A probe tip configuration, being part of a probe (FIG. 2) for use in a scanning proximity microscope, is disclosed, comprising a cantilever beam (1) and a probe tip. Said tip comprises a first portion of a tip (2) and at least one second portion of a tip (5). Said first portion of a tip is connected to said cantilever beam whereas said second portion of a tip is placed on said first portion of a tip. Cantilever beam, first portion of a tip and second portion(s) of a tip can be composed of different materials and can be isolated each from another which makes an easy adjustement of the maximum penetration depth of the tip possible without limiting the resolution and makes it also possible to detect more than one signal of a sample at the same time using one cantilever beam.
    Type: Application
    Filed: December 3, 2001
    Publication date: April 11, 2002
    Inventors: Thomas Hantschel, Wilfried Vandervorst
  • Patent number: 6368982
    Abstract: In a method for patterning a target material on a semiconductor substrate, a first hardmask material is deposited on the target material and a second hardmask material is deposited on the first hardmask material. The first hardmask material is different from the target material, and the second hardmask material is different from the first hardmask material. A patterned structure of a patterning material such a photoresist material is formed on the second hardmask material. Any exposed region of the second hardmask material is etched such that a second hardmask structure is formed from the second hardmask material remaining under the patterned structure. The etching reactant for etching the second hardmask material to form the second hardmask structure substantially does not etch the first hardmask material. The second hardmask structure is trimmed to reduce the length at each side of the second hardmask structure.
    Type: Grant
    Filed: November 15, 2000
    Date of Patent: April 9, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Bin Yu
  • Patent number: 6368519
    Abstract: A magnetic gap is formed to be vertical to the film forming surface of a substrate with high accuracy by a simple method. The method comprises a non-magnetic film forming step of forming a non-magnetic film made of the non-magnetic material on the substrate, a high selectivity film forming step of forming a high selectivity film made of a material which has a higher selectivity ratio with respect to reactive ion etching than the non-magnetic material, on the non-magnetic film formed, a patterning step of patterning the high-selectivity film into a predetermined shape, and an etching step of etching the non-magnetic film by reactive ion etching, using the high selectivity film as a mask.
    Type: Grant
    Filed: December 9, 1999
    Date of Patent: April 9, 2002
    Assignee: Sony Corporation
    Inventors: Toru Katakura, Teiichi Miyauchi, Yuko Takanashi
  • Patent number: 6365055
    Abstract: A process for producing a sensor membrane substrate, in particular, for a mass flow sensor or a pressure sensor, the substrate having on its front a membrane, which is fixed at the edge of an opening that is etched free from the back. The process includes the following steps: providing a substrate; local thickening the substrate in an area on the front opposite the edge, the thickened portion having a continuous transition to the substrate; depositing a membrane layer on the front having the locally oxidized area; and etching free the opening from the back to clear the membrane in such a way that the edge is located underneath the thickened area.
    Type: Grant
    Filed: May 26, 1999
    Date of Patent: April 2, 2002
    Assignee: Robert Bosch GmbH
    Inventors: Heribert Weber, Steffen Schmidt
  • Publication number: 20020030034
    Abstract: A phase shifting mask repair process is described. The process uses an etching gas or a hydrofluoric acid solution to etch the quartz substrate and the characteristics of the phase shifter layer being only slightly etched when clean with a NH3/H2O2/H2O2 solution to calculate and adjust the respective processing time accordingly. As a result, the phase difference between the quartz substrate and the MoSiON phase shifter layer stays relatively the same before and after the repair process.
    Type: Application
    Filed: November 30, 2000
    Publication date: March 14, 2002
    Inventor: Ching-Yu Chang
  • Publication number: 20020028359
    Abstract: A dry etching is performed using a mask made of a titanium nitride under a reaction gas of a carbon monoxide with an additive of a nitrogen containing compound gas.
    Type: Application
    Filed: March 26, 2001
    Publication date: March 7, 2002
    Applicant: TDK CORPORATION
    Inventors: Kazuhiro Hattori, Kenji Uchiyama
  • Publication number: 20020011461
    Abstract: The processes allow structuring of a metal-containing layer. The metal-containing layer is etched, using an etching mask, in a plasma-assisted etching gas atmosphere at a temperature of over 130° C. and in the presence of at least one halogen compound and at least one oxidizing agent. The concentration of the oxidizing agent is thereby set higher than the concentration of the halogen compound.
    Type: Application
    Filed: June 4, 2001
    Publication date: January 31, 2002
    Inventors: Stephan Wege, Kerstin Krahl
  • Publication number: 20020008080
    Abstract: Etching method applicable to a semiconductor device fabrication and an MEMS(Micro-Electro-Mechanical System) process, including the steps of forming an etching mask on a substrate, forming a plurality of patterns in the etching mask corresponding to depths of the plurality of trenches; and etching the substrate using the etching mask having the plurality of patterns formed therein, whereby eliminating an alignment error in respective photolithography, that permits to form a precise structure, simplify a fabrication process, and reduce a production cost.
    Type: Application
    Filed: April 27, 2000
    Publication date: January 24, 2002
    Inventors: Ki Chang Song, Jong Uk Bu, Chil Keun Park
  • Patent number: 6338938
    Abstract: In one aspect the invention includes a method of forming a semiconductor device, comprising: a) forming a layer over a substrate; b) forming a plurality of openings extending into the layer; c) depositing particles on the layer; d) collecting the particles within the openings; and e) using the collected particles as a mask during etching of the underlying substrate to define features of the semiconductor device. In another aspect, the invention includes a method of forming a field emission display, comprising: a) forming a silicon dioxide layer over a conductive substrate; b) forming a plurality of openings extending into the silicon dioxide layer; c) depositing particles on the silicon dioxide layer; d) collecting the particles within the openings; e) while using the collected particles as a mask, etching the conductive substrate to form a plurality of conically shaped emitters from the conductive substrate; and f) forming a display screen spaced from said emitters.
    Type: Grant
    Filed: January 25, 2000
    Date of Patent: January 15, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Eric A. Lahaug
  • Publication number: 20020001778
    Abstract: A method for forming a patterned amorphous carbon layer in a semiconductor stack, including forming an amorphous carbon layer on a substrate and forming a silicon containing photoresist layer on top of the amorphous carbon layer. Thereafter, the method includes developing a pattern transferred into the resist layer with a photolithographic process and etching through the amorphous carbon layer in at least one region defined by the pattern in the resist layer, wherein a resist layer hard mask is formed in an outer portion of the photoresist layer during etching.
    Type: Application
    Filed: August 2, 2001
    Publication date: January 3, 2002
    Applicant: Applied Materials, Inc.
    Inventors: Ian Latchford, Christopher Dennis Bencher, Yuxiang Wang, Mario Dave Silvetti