With Measuring, Testing, Or Inspecting Patents (Class 216/59)
  • Patent number: 10296698
    Abstract: Various embodiments include approaches for designing through-silicon vias (TSVs) in integrated circuits (ICs). In some cases, a method includes: identifying types of through-silicon vias (TSVs) for placement within an integrated circuit (IC) design based upon an electrical requirement for the TSVs, wherein the IC design includes distinct types of TSVs; calculating etch and fill rates for the IC design with the distinct types of TSVs with common etching and filling processes; and providing fabrication instructions to form the distinct types of TSVs according to the calculated etch and fill rates in the common processes.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: May 21, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Mukta G. Farooq, Troy L. Graves-Abe
  • Patent number: 10262910
    Abstract: Methods and systems for using a time-series of spectra to identify endpoint of an etch process. One method includes accessing a virtual carpet that is formed from a time-series of spectra for the etch process collected during a training operation. And, running a fabrication etch process on a fabrication wafer, such that while the fabrication etch process is performed portions of a carpet defined from a time-series of spectral is generated for the fabrication etch process. Then, comparing the portions of the carpet of the fabrication etch process to the virtual carpet. End pointing is processed for the fabrication etch process when said comparing indicates that a desired metric has been reached for the fabrication wafer. In one example, said portions of the carpet include a current frame of captured spectra and at least one previous frame of captured spectra.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: April 16, 2019
    Assignee: Lam Research Corporation
    Inventors: Ye Feng, Prashanth Kumar, Andrew D. Bailey, III
  • Patent number: 10243536
    Abstract: In an elastic wave device, a multilayer film including a piezoelectric thin film is provided on a support substrate, an interdigital transducer electrode is provided on one surface of the piezoelectric thin film, a wiring electrode is connected to the interdigital transducer electrode, the wiring electrode includes a lead electrode portion and a pad electrode portion, an external connection terminal is located above the pad electrode portion, the external connection terminal is electrically connected to the pad electrode portion, and the external connection terminal is bonded onto the pad electrode portion on the support substrate so that at least the piezoelectric thin film of the multilayer film is not present below the pad electrode portion.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: March 26, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Shin Saijo, Hisashi Yamazaki, Koji Yamamoto, Seiji Kai, Munehisa Watanabe
  • Patent number: 10226852
    Abstract: A surface planarization system is presented. The system comprises an external energy source for generating a localized energy distribution within a processing region, and a control unit for operating the external energy source to create, by the localized energy distribution, a predetermined temperature pattern within the processing region such that different locations of the processing region are subjected to different temperatures. This provides that when a sample (e.g. semiconductor wafer) during its interaction with an etching material composition is located in the processing region, the temperature pattern at different locations of the sample's surface creates different material removal rates by the etching material composition (different etch rates).
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: March 12, 2019
    Assignee: NOVA MEASURING INSTRUMENTS LTD.
    Inventor: Igor Turovets
  • Patent number: 10157804
    Abstract: The invention relates to a method for determining a critical dimension variation of a photolithographic mask which comprises (a) using layout data of the photolithographic mask to determine at least two sub-areas of the photolithographic mask, each sub-area comprising a group of features, (b) measuring a distribution of a transmission of each sub-area, (c) determining a deviation of the transmission from a mean transmission value for each sub-area, (d) determining a constant specific for each sub-area, and (e) determining the critical dimension variation of the photolithographic mask by combining for each sub-area the deviation of the transmission and the sub-area specific constant.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: December 18, 2018
    Assignee: Carl Zeiss SMS Ltd.
    Inventor: Rainer Pforr
  • Patent number: 10147618
    Abstract: A time-dependent substrate temperature to be applied during a plasma process is determined. The time-dependent substrate temperature at any given time is determined based on control of a sticking coefficient of a plasma constituent at the given time. A time-dependent temperature differential between an upper plasma boundary and a substrate to be applied during the plasma process is also determined. The time-dependent temperature differential at any given time is determined based on control of a flux of the plasma constituent directed toward the substrate at the given time. The time-dependent substrate temperature and time-dependent temperature differential are stored in a digital format suitable for use by a temperature control device defined and connected to direct temperature control of the upper plasma boundary and the substrate. A system is also provided for implementing upper plasma boundary and substrate temperature control during the plasma process.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: December 4, 2018
    Assignee: Lam Research Corporation
    Inventor: Rajinder Dhindsa
  • Patent number: 10078266
    Abstract: Processes for removing a photoresist from a substrate after, for instance, ion implantation are provided. In one example implementation, a process can include placing a substrate having a bulk photoresist and a crust formed on the bulk photoresist in a processing chamber. The process can include initiating a first strip process in the processing chamber. The process can include accessing an optical emission signal associated with a plasma during the first strip process. The process can include identifying an endpoint for the first strip process based at least in part on the optical emission signal. The process can include terminating the first strip process based at least in part on the endpoint. The process can include initiating a second strip process to remove the photoresist from the substrate.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: September 18, 2018
    Assignee: Mattson Technology, Inc.
    Inventors: Wei-Hua Liou, Chun-Yen Kang, Vijay M. Vaniapura, Hai-Au M. Phan-Vu, Shawming Ma
  • Patent number: 10054802
    Abstract: A method and system for generating a three-dimensional model of a contact lens with a front and a back surface, in which the entire back surface consists of an array of independent data points shaped to conform to three-dimensional data provided by an ocular topographer. The sampling density is sufficiently high to characterize anomalies or injuries anywhere in the eye to optimize comfort and fit. The methods and systems also include modeling a scleral lens which rests either solely on the sclera, or straddles the limbus extending partially into the cornea is described. The resting surface conforms to the topology of the underlying ocular surface with topology guiding the design. Additional methods and systems model scleral lens optics without the use of trial lenses. The lens models can be used to machine or 3D print a lens that fits the patient. Such lenses benefit patients that suffer from dry eyes or whose eyes are not normally dry, but feel dry after wearing conventional contact lenses.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: August 21, 2018
    Assignee: Eydeal Scanning, LLC
    Inventors: Robert P. Bishop, Michael T. Sullivan, Steve Auger
  • Patent number: 10002804
    Abstract: Described is a method for determining an endpoint of an etch process using optical emission spectroscopy (OES) data as an input. Optical emission spectroscopy (OES) data are acquired by a spectrometer attached to a plasma etch processing tool. The acquired time-evolving spectral data are first filtered and demeaned, and thereafter transformed into transformed spectral data, or trends, using multivariate analysis such as principal components analysis, in which previously calculated principal component weights are used to accomplish the transform. A functional form incorporating multiple trends may be used to more precisely determine the endpoint of an etch process. A method for calculating principal component weights prior to actual etching, based on OES data collected from previous etch processing, is disclosed, which method facilitates rapid calculation of trends and functional forms involving multiple trends, for efficient and accurate in-line determination of etch process endpoint.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: June 19, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Yan Chen, Vi Vuong, Serguei Komarov
  • Patent number: 9978584
    Abstract: A method for treating a substrate, in which a supercritical fluid is supplied into a chamber, in which the substrate is carried, to treat the substrate, the method including a supply step of supplying the supercritical fluid into the chamber until a pressure of the interior of the chamber reaches a preset pressure, and a substrate treating step of performing a supercritical process while repeating supply and exhaust of the supercritical fluid into and out of the interior of the chamber after the supply step, wherein a flow rate of the supercritical fluid supplied into the chamber in the supply step is variable.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: May 22, 2018
    Assignee: SEMES CO., LTD.
    Inventors: Young Hun Lee, Eui Sang Lim, Min Jun Cho, Jae Myoung Lee
  • Patent number: 9925571
    Abstract: A method of cleaning a substrate processing apparatus including a gas supply part configured to eject a process gas via gas passages formed in the gas supply part, and divided into first and second regions corresponding to first and second in-plane positions of a substrate, respectively, includes cleaning a first one of the gas passages corresponding to the first region with the plasma of the process gas by causing a first flow rate of the process gas supplied to the first region to be lower than a second flow rate of the process gas supplied to the second region and cleaning a second one of the gas passages corresponding to the second region with the plasma by causing a third flow rate of the process gas supplied to the first region to be higher than a fourth flow rate of the process gas supplied to the second region.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: March 27, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Akihiro Kikuchi, Mitsuhiro Tomura
  • Patent number: 9889597
    Abstract: An imprint lithography apparatus is disclosed that includes a support structure configured to hold an imprint template. The apparatus further includes an actuator located between the support structure and a side of the imprint template, when the imprint template is held by the support structure, configured to apply a force to the imprint template and a force sensor between the support structure and a side of the imprint template, when the imprint template is held by the support structure.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: February 13, 2018
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Yvonne Wendela Kruijt-Stegeman, Raymond Jacobus Wilhelmus Knaapen, Johan Frederik Dijksman, Sander Frederik Wuister, Ivar Schram, Raymond Wilhelmus Louis Lafarre
  • Patent number: 9716022
    Abstract: A method of determining thermal stability of an upper surface of a substrate support assembly comprises recording time resolved pre-process temperature data of the substrate before performing a plasma processing process while powering an array of thermal control elements to achieve a desired spatial and temporal temperature of the upper surface. A substrate is processed while powering the array of thermal control elements to achieve a desired spatial and temporal temperature of the upper surface of the assembly, and time resolved post-process temperature data of the assembly is recorded after processing the substrate. The post-process temperature data is recorded while powering the thermal control elements to achieve a desired spatial and temporal temperature of the upper surface. The post-process temperature data is compared to the pre-process temperature data to determine whether the data is within a desired tolerance range.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: July 25, 2017
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Ole Waldmann, Eric A. Pape, Carlos Leal-Verdugo, Keith William Gaff
  • Patent number: 9640371
    Abstract: A system and method of identifying a selected process point in a multi-mode pulsing process includes applying a multi-mode pulsing process to a selected wafer in a plasma process chamber, the multi-mode pulsing process including multiple cycles, each one of the cycles including at least one of multiple, different phases. At least one process output variable is collected for a selected at least one of the phases, during multiple cycles for the selected wafer. An envelope and/or a template of the collected at least one process output variable can be used to identify the selected process point. A first trajectory for the collected process output variable of a previous phase can be compared to a second trajectory of the process output variable of the selected phase. A multivariate analysis statistic of the second trajectory can be calculated and used to identify the selected process point.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: May 2, 2017
    Assignee: Lam Research Corporation
    Inventors: Yassine Kabouzi, Jorge Luque, Andrew D. Bailey, III, Mehmet Derya Tetiker, Ramkumar Subramanian, Yoko Yamaguchi
  • Patent number: 9620402
    Abstract: An alignment apparatus for aligning a wafer includes a mounting unit, an imaging unit, an elevation unit, and a controlling unit. The control unit outputs a control signal for controlling the elevation unit such that a luminance variation between the outer side and the inner side of the wafer obtained by the imaging unit becomes the same as a luminance variation obtained when the imaging unit is focused, for estimating a warpage state of the wafer based on an amount of relative movement of the imaging unit and the mounting unit with respect to a relative height position of the imaging unit and the mounting unit obtained when the imaging unit is focused on a reference wafer having no warpage, and for detecting the alignment mark of the wafer by the imaging unit by rotating the mounting unit in a state where the imaging unit is focused.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: April 11, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Toshiaki Kodama, Toru Yamauchi
  • Patent number: 9472415
    Abstract: A method of forming a trench in an oxide layer; where the oxide layer is formed on top of a nitride layer. The trench is formed using an iterative etching technique until the nitride layer is exposed, each iterative etching step includes; using an isotropic etching technique to remove a portion of the oxide layer, the isotropic etching technique produces a byproduct that remains along a sidewall and a bottom of the trench, then using an anisotropic etching technique to remove the salt from the bottom of the trench, leaving salt on the sidewalls of the trench.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: October 18, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Emre Alptekin, Sivananda K. Kanakasabapathy, Ahmet S. Ozcan, Viraj Y. Sardesai, Cung D. Tran
  • Patent number: 9431310
    Abstract: A simulation method includes acquiring processing conditions for performing an etching process using plasma on a surface of a wafer covered by a mask having a predetermined mask thickness and aperture ratio, calculating, based on the conditions, a flux amount of a reaction product that enters the surface, calculating, based on mask information including the thickness and the aperture ratio and the flux amount, an etching rate of the wafer, calculating, based on the conditions and the etching rate, a dissociation fraction of the product, calculating, based on the information and the etching rate, a solid angle at a predetermined evaluation point set on the surface, the solid angle corresponding to a view area in which plasma space can be seen from the evaluation point, and calculating, based on the etching rate, the dissociation fraction, the solid angle, and the aperture ratio, a control index for evaluating a surface shape.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: August 30, 2016
    Assignee: Sony Corporation
    Inventors: Nobuyuki Kuboi, Takashi Kinoshita
  • Patent number: 9416787
    Abstract: A method and arrangement for determining the flow rate (Q) produced by a pump, when the pump is controlled with a frequency converter, which produces estimates for rotational speed and torque of the pump, and the characteristic curves of the pump are known. The method includes determining the shape of a QH curve of the pump, dividing the QH curve into two or more regions depending on the shape of the QH curve, determining on which region of the QH curve the pump is operating, and determining the flow rate (Q) of the pump using the determined operating region of the characteristic curve.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: August 16, 2016
    Assignee: ABB Technology Oy
    Inventors: Jussi Tamminen, Tero Ahonen, Jero Ahola
  • Patent number: 9336998
    Abstract: In one embodiment a method of etching a substrate includes directing a first ion beam to the substrate through an extraction plate of a processing apparatus using a first set of control settings of the processing apparatus. The method may further include detecting a signal from the substrate that indicates a change in material being etched by the first ion beam from a first material to a second material, adjusting control settings of the processing apparatus to a second set of control settings different from the first set of control settings based on the second material, and directing a second ion beam to the substrate through the extraction plate using the second set of control settings.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: May 10, 2016
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Ludovic Godet, Daniel Distaso, Nini Munoz, Tristan Ma, Yu Liu
  • Patent number: 9330990
    Abstract: Disclosed is a method for determining an endpoint of an etch process using optical emission spectroscopy (OES) data as an input. Optical emission spectroscopy (OES) data are acquired by a spectrometer attached to a plasma etch processing tool. The acquired time-evolving spectral data are first filtered and demeaned, and thereafter transformed into transformed spectral data, or trends, using multivariate analysis such as principal components analysis, in which previously calculated principal component weights are used to accomplish the transform. A functional form incorporating multiple trends may be used to more precisely determine the endpoint of an etch process. A method for calculating principal component weights prior to actual etching, based on OES data collected from previous etch processing, is disclosed, which method facilitates rapid calculation of trends and functional forms involving multiple trends, for efficient and accurate in-line determination of etch process endpoint.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: May 3, 2016
    Assignee: Tokyo Electron Limited
    Inventors: Yan Chen, Serguei Komarov, Vi Vuong
  • Patent number: 9318368
    Abstract: In a method for manufacturing a dual shallow trench isolation structure, a substrate is provided, and a mask layer is formed on the substrate. The mask layer is patterned by using a photomask to form at least one first hole and at least one second hole in the mask layer, in which a depth of the at least one first hole is different from a depth of the at least one second hole. The mask layer and the substrate are etched to form at least one first trench having a first depth and at least one second trench having a second depth, in which the first depth is different from the second depth. The remaining mask layer is removed. A first isolation layer and A second isolation layer are respectively formed in the at least one first trench and the at least one second trench.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: April 19, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fu-Cheng Chang, Chai-Der Yen, Fu-Tsun Tsai, Chi-Cherng Jeng, Chih-Mu Huang
  • Patent number: 9305805
    Abstract: Provided are methods of etching a substrate using atomic layer deposition apparatus. Atomic layer deposition apparatus including a gas distribution plate with a thermal element and remote plasma are discussed. The thermal element is capable of locally changing the temperature of a portion of the surface of the substrate to vaporize an etch layer deposited on the substrate.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: April 5, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Mei Chang, Joseph Yudovsky
  • Patent number: 9190337
    Abstract: There is provided an etching method. A temperature at a plurality of predetermined positions on an upper surface of an Si substrate is measured during the etching processing. The etching processing includes supplying an etching solution to the upper surface of the Si substrate. An exothermic reaction occurs in the etching processing. The upper surface is heated or cooled depending on the measured value.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: November 17, 2015
    Assignee: TOHOKU UNIVERSITY
    Inventors: Takeshi Sakai, Tatsuro Yoshida, Kazuhiro Yoshikawa, Shigetoshi Sugawa
  • Patent number: 9099284
    Abstract: A reactive correction to chamber impedance changes without the need to change the process recipe is disclosed. The reactive correction may be done automatically and repeatedly during processing. A control of RF power application to a plasma processing chamber is performed, so as to minimize reflected power and efficiently apply the RF power to the plasma. Autotuning of the RF power application is enabled without modifying a qualified process recipe. The autotuning can be applied using frequency matching and RF matching network tuning.
    Type: Grant
    Filed: December 26, 2011
    Date of Patent: August 4, 2015
    Assignee: ADVANCED MICRO-FABRICATION EQUIPMENT, INC. ASIA
    Inventors: James Yang, Stanley Liu, ZhaoHui Xi
  • Patent number: 9087793
    Abstract: A method for etching a target layer of a semiconductor device in an etching apparatus is provided. To form an element, the method includes forming a photoresist pattern on the target layer of the semiconductor device, in which the photoresist pattern has an after-develop-inspection critical dimension (ADI CD). A target after-etch-inspection critical dimension (AEI CD) of the element is provided, as well as a trim time of the target layer. The etching apparatus is provided and a formation time of a protective layer on an inner wall of the etching apparatus is determined based on the ADI CD, the target AEI CD and the trim time. The protective layer for the predetermined formation time is formed to perform a trimming process on the target layer for the trim time by using the photoresist pattern as a mask, so as to form the element.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: July 21, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Han-Wen Liao, Wei-Tai Lin, Wen-Sheng Wang, Chih-Yu Lin, Cherng-Chang Tsuei, Chen-Hsiang Lu
  • Patent number: 9039907
    Abstract: A method is described for improving the uniformity over a predetermined substrate area of a spectral response of photonic devices fabricated in a thin device layer. The method includes (i) establishing an initial device layer thickness map for the predetermined area, (ii) establishing a linewidth map for the predetermined area, and (iii) establishing an etch depth map for the predetermined area. The method further includes, based on the initial device layer thickness map, the linewidth map and the etch depth map, calculating an optimal device layer thickness map and a corresponding thickness correction map for the predetermined substrate area taking into account photonic device design data. Still further, the method includes performing a location specific corrective etch process in accordance with the thickness correction map.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: May 26, 2015
    Assignees: IMEC, Universiteit Gent
    Inventors: Philippe Absil, Shankar Kumar Selvaraja
  • Patent number: 9002493
    Abstract: A semiconductor processing apparatus includes a semiconductor processing station for a semiconductor wafer, and an endpoint detector associated with the semiconductor processing station. The endpoint detector includes a non-contact probe configured to probe the semiconductor wafer, an optical transmitter configured to transmit an optical signal to the non-contact probe, and an optical receiver configured to receive a reflected optical signal from the non-contact probe. The controller controls the semiconductor processing station based on the reflected optical signal.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: April 7, 2015
    Assignee: STMicroelectronics, Inc.
    Inventors: John H. Zhang, Cindy Goldberg
  • Publication number: 20150053644
    Abstract: Methods and apparatus for modifying RF current path lengths are disclosed. Apparatus includes a plasma processing system having an RF power supply and a lower electrode having a conductive portion. There is included an insulative component disposed in an RF current path between the RF power supply and the conductive portion. There are included a plurality of RF path modifiers disposed within the insulative component, the plurality of RF path modifiers being disposed at different angular positions relative to a reference angle drawn from a center of the insulative component, whereby at least a first one of the plurality of RF path modifiers is electrically connected to the conductive portion and at least a second one of the plurality of the plurality of RF path modifiers is not electrically connected to the conductive portion.
    Type: Application
    Filed: November 3, 2014
    Publication date: February 26, 2015
    Inventors: Sang Ki Nam, Rajinder Dhindsa, Alexei Marakhtanov
  • Patent number: 8945411
    Abstract: The present invention is to achieve a reduction both in size of a plasma processing apparatus and an installation area thereof. A dry etching apparatus includes a stock unit that includes a cassette storing a tray that can be conveyed and that stores substrates. In a conveying unit storing a conveying apparatus of the tray, a rotary stage is provided. Rotational angular position adjustment of the tray is performed by rotating the rotary stage placed on the tray before being subjected to dry etching and detecting a notch by a notch detecting sensor.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: February 3, 2015
    Assignee: Panasonic Corporation
    Inventor: Tetsuhiro Iwai
  • Publication number: 20150011088
    Abstract: Methods are disclosed for depositing material onto and/or etching material from a substrate in a surface processing tool having a processing chamber, a controller and one or more devices for adjusting the process parameters within the chamber. The method comprises: the controller instructing the one or more devices according to a series of control steps, each control step specifying a defined set of process parameters that the one or more devices are instructed to implement, wherein at least one of the control steps comprises the controller instructing the one or more devices to implement a defined set of constant process parameters for the duration of the step, including at least a chamber pressure and gas flow rate through the chamber, which duration is less than the corresponding gas residence time (Tgr) of the processing chamber for the step.
    Type: Application
    Filed: February 27, 2013
    Publication date: January 8, 2015
    Inventors: Mark Edward McNie, Michael Joseph Cooke, Leslie Michael Lea
  • Patent number: 8916055
    Abstract: A processing method and apparatus uses at least one electric field applicator (34) biased to produce a spatial-temporal electric field to affect a processing medium (26), suspended nano-objects (28) or the substrate (30) in processing, interacting with the dipole properties of the medium (26) or particles to construct structure on the substrate (30). The apparatus may include a magnetic field, an acoustic field, an optical force, or other generation device. The processing may affect selective localized layers on the substrate (30) or may control orientation of particles in the layers, control movement of dielectrophoretic particles or media, or cause suspended particles of different properties to follow different paths in the processing medium (26). Depositing or modifying a layer on the substrate (30) may be carried out.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: December 23, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Jozef Brcka, Jacques Faguet, Eric M. Lee, Hongyu Yue
  • Patent number: 8900469
    Abstract: A method and apparatus for etching a photomask substrate with enhanced process monitoring is provided. In one embodiment, a method of determining an etching endpoint includes performing an etching process on a first tantalum containing layer through a patterned mask layer, directing a radiation source having a first wavelength from about 200 nm and about 800 nm to an area uncovered by the patterned mask layer, collecting an optical signal reflected from the area covered by the patterned mask layer, analyzing a waveform obtained the reflected optical signal reflected from the substrate from a first time point to a second time point, and determining a first endpoint of the etching process when a slope of the waveform is changed about 5 percent from the first time point to the second time point.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: December 2, 2014
    Assignee: Applied Materials, Inc.
    Inventor: Michael Grimbergen
  • Patent number: 8900398
    Abstract: An arrangement for performing pressure control within a processing chamber substrate processing is provided. The arrangement includes a peripheral ring configured at least for surrounding a confined chamber volume that is configured for sustaining a plasma for etching the substrate during substrate processing. The peripheral ring includes a plurality of slots that is configured at least for exhausting processed byproduct gas from the confined chamber volume during substrate processing. The arrangement also includes a conductive control ring that is positioned next to the peripheral ring and is configured to include plurality of slots. The pressure control is achieved by moving the conductive control ring relative to the peripheral ring such that a first slot on the peripheral ring and a second slot on the conductive control ring are offset with respect to one another in a range of zero offset to full offset.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: December 2, 2014
    Assignee: Lam Research Corporation
    Inventors: Rajinder Dhindsa, Michael C. Kellogg, Babak Kadkhodayan, Andrew D. Bailey, III
  • Patent number: 8900470
    Abstract: A method for etching a layer is provided. A substrate is provided in a chamber. An etch plasma for etching a layer on the substrate is generated. Light from a first region of the chamber is measured to provide a first signal. Light from a second region of the chamber is measured to provide a second signal. The first signal with the second signal are compared to determine an etch endpoint.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: December 2, 2014
    Assignee: Lam Research Corporation
    Inventor: Evelio Sevillano
  • Patent number: 8894804
    Abstract: An arrangement within a plasma reactor for detecting a plasma unconfinement event is provided. The arrangement includes a sensor, which is a capacitive-based sensor implemented within the plasma reactor. The sensor is implemented outside of a plasma confinement region and is configured to produce a transient current when the sensor is exposed to plasma associated with the plasma unconfinement event. The sensor has at least one electrically insulative layer oriented toward the plasma associated with the plasma unconfined event. The arrangement also includes a detection circuit, which is electrically connected to the sensor for converting the transient current into a transient voltage signal and for processing the transient voltage signal to ascertain whether the plasma unconfinement event exists.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: November 25, 2014
    Assignee: Lam Research Corporation
    Inventors: Jean-Paul Booth, Alexei Marakhtanov, Rajinder Dhindsa, Luc Albarede, Seyed Jafar Jafarian-Tehrani
  • Publication number: 20140339193
    Abstract: Method for carrying out plasma processing on a wafer under Run-to-Run control by using a plasma processing apparatus having a plasma processing chamber, a process monitor which monitors a condition in the plasma processing chamber, and an actuator which controls parameters which are constituent elements of a plasma processing condition. The method includes the steps of making one of the parameters a (N?1)th manipulated variable, calculating a first difference between a process monitor value in the plasma processing obtained by the process monitor and a desired value of the process monitor value in the plasma processing, calculating a correction amount of the (N?1)th manipulated variable on the basis of the first difference and a previously obtained correlation between the process monitor value in the plasma processing and the (N?1)th manipulated variable, wherein N is a natural number equal to or larger than 2.
    Type: Application
    Filed: August 1, 2014
    Publication date: November 20, 2014
    Inventors: Akira Kagoshima, Daisuke Shiraishi, Yuji Nagatani
  • Patent number: 8889021
    Abstract: A sensing device for measuring a plasma process parameter in a plasma chamber for processing workpieces may include a substrate with one or more sensor embedded in the substrate. The substrate can have a surface made of substantially the same material as workpieces that are plasma processed in the plasma chamber. Each sensor can include a collector portion made of substantially the same material as the substrate surface. The collector portion includes a surface that is level with the surface of the substrate. Sensor electronics are embedded into the substrate and coupled to the collector portion. When the substrate surface is exposed to a plasma one or more signals resulting from the plasma can be measured with the sensor(s).
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: November 18, 2014
    Assignee: KLA-Tencor Corporation
    Inventors: Earl Jensen, Mei Sun
  • Patent number: 8883024
    Abstract: The invention provide apparatus and methods for creating gate structures on a substrate in real-time using Vacuum Ultra-Violet (VUV) data and Electron Energy Distribution Function (EEDƒ) data and associated (VUV/EEDƒ)-related procedures in (VUV/EEDƒ) etch systems. The (VUV/EEDƒ)-related procedures can include multi-layer-multi-step processing sequences and (VUV/EEDƒ)-related models that can include Multi-Input/Multi-Output (MIMO) models.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: November 11, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Lee Chen, Jianping Zhao
  • Patent number: 8884406
    Abstract: A semiconductor device wafer includes a test structure. The test structure includes a layer of material having an angle-shaped test portion disposed on at least a portion of a surface of the semiconductor wafer. A ruler marking on the surface of the semiconductor wafer proximate the test portion is adapted to facilitate measurement of a change in length of the test portion.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: November 11, 2014
    Assignee: Alpha & Omega Semiconductor Ltd
    Inventors: Yingying Lou, Tiesheng Li, Yu Wang, Anup Bhalla
  • Patent number: 8877079
    Abstract: The present invention relates to a method of manufacturing a semiconductor device wherein etching is performed on films on a wafer using a plasma treatment apparatus. In the manufacturing method according to the present invention, a change in the difference between the emission intensities of a first wavelength component and a second wavelength component in plasma is monitored during etching. If the amount of change in the difference per unit time exceeds a predetermined threshold a given number of times in a row, then the flow rate of oxygen introduced to the plasma treatment apparatus is increased or, if the amount of change exceeding the predetermined threshold has not been seen, then the oxygen flow rate is set back to the original value thereof. This series of actions is repeated all the time during a set period of time.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: November 4, 2014
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Yasuhiko Ueda
  • Patent number: 8877080
    Abstract: The invention provides an apparatus and methods for creating gate structures on a substrate in real-time using Vacuum Ultra-Violet (VUV) data and Electron Energy Distribution Function (EEDf) data and associated (VUV/EEDf)-related procedures in (VUV/EEDf) etch systems. The (VUV/EEDf)-related procedures can include multi-layer-multi-step processing sequences and (VUV/EEDf)-related models that can include Multi-Input/Multi-Output (MIMO) models.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: November 4, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Lee Chen, Jianping Zhao
  • Patent number: 8865597
    Abstract: Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the dielectric layer. In the preferred embodiments, the present invention uses XeF2 selective gas phase etching as alternatives to Ta—TaN Chemical Mechanical Polishing (CMP) as a basic “liner removal process” and as a “selective cap plating base removal process.” In this first use, XeF2 is used to remove the metal liner, TaN—Ta, after copper CMP. In the second use, the XeF2 etch is used to selectively remove a plating base (TaN—Ta) that was used to form a metal cap layer over the copper conductor.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: October 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: John M. Cotte, Nils Hoivik, Christopher V. Jahnes, Robert L. Wisnieff
  • Publication number: 20140299577
    Abstract: The invention relates to an apparatus for surface processing on a substrate, for example for applying a coating to the substrate or for removing a coating from the substrate, wherein the apparatus comprises: a chamber enclosing an interior and serving for arranging the substrate for the surface processing, a process gas analyser for detecting at least one gaseous constituent of a residual gas atmosphere formed in the interior, wherein the process gas analyser comprises an ion trap for storing the gaseous constituent to be detected, and an ionization device for ionizing the gaseous constituent. The invention also relates to an associated method for monitoring surface processing on a substrate.
    Type: Application
    Filed: June 23, 2014
    Publication date: October 9, 2014
    Inventors: Hin Yiu Anthony Chung, Michel Aliman, Gennady Fedosenko, Albrecht Ranck, Leonid Gorkhover
  • Patent number: 8845913
    Abstract: An ion radiation damage prediction method includes a parameter computation step of computing the incidence energy and incidence angle of an incident ion hitting a fabricated object, and a step of searching for data in databases created in advance on the basis of the computed incidence energy and angle, the databases storing distributions of quantities of crystalline defects having an effect on the fabricated object, ion reflection probabilities and ion penetration depths. The method also includes finding the penetration depth and location of the incident ion based on the data found in the searching step and based on the computed incidence energy and angle, and computing a quantity of defects in the fabricated object from the penetration depth and location. A distribution of defects may be computed by performing the aforementioned steps for many incident ions.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: September 30, 2014
    Assignee: Sony Corporation
    Inventors: Nobuyuki Kuboi, Shoji Kobayashi
  • Patent number: 8846539
    Abstract: A plasma processing apparatus includes a heater in thermal contact with a showerhead electrode, and a temperature controlled top plate in thermal contact with the heater to maintain a desired temperature of the showerhead electrode during semiconductor substrate processing. A gas distribution member supplies a process gas and radio frequency (RF) power to the showerhead electrode.
    Type: Grant
    Filed: February 22, 2010
    Date of Patent: September 30, 2014
    Assignee: Lam Research Corporation
    Inventors: Rajinder Dhindsa, Eric Lenz
  • Patent number: 8828259
    Abstract: A method for automatically performing power matching using a mechanical RF match during substrate processing is provided. The method includes providing a plurality of parameters for the substrate processing wherein the plurality of parameters including at least a predefined number of learning cycles. The method also includes setting the mechanical RF match to operate in a mechanical tuning mode. The method further includes providing a first set of instructions to the substrate processing to ignore a predefined number of cycles of Rapid Alternating Process RAP steps. The method yet also includes operating the mechanical RF match in the mechanical tuning mode for the predefined number of learning cycles. The method yet further includes determining a set of optimal capacitor values. The method moreover includes providing a second set of instructions to a power generator to operate in a frequency tuning mode.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: September 9, 2014
    Assignee: Lam Research Corporation
    Inventor: Arthur H. Sato
  • Patent number: 8815746
    Abstract: An apparatus and the use of such an apparatus and method for producing microcomponents with component structures are presented which are generated in a process chamber on a substrate according to the LIGA method for example and are stripped from the enclosing photoresist with the help of a cooled remote plasma source.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: August 26, 2014
    Assignee: R3T GmbH Rapid Reactive Radicals Technology
    Inventor: Josef Mathuni
  • Patent number: 8815107
    Abstract: An aspect of the present invention relates to a method of etching a surface layer portion of a silicon wafer comprising: positioning the silicon wafer within a sealed vessel containing a mixed acid A of hydrofluoric acid and sulfuric acid so that the silicon wafer is not in contact with mixed acid A; introducing a solution B in the form of nitric acid containing nitrogen oxides into the sealed vessel and causing solution B to mix with mixed acid A; and vapor phase decomposing the surface layer portion of the silicon wafer within the sealed vessel within which mixed acid A and solution B have been mixed.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: August 26, 2014
    Assignee: Sumco Corporation
    Inventors: Jiahong Wu, Shabani B. Mohammad
  • Patent number: 8808559
    Abstract: A method and apparatus for etching a photomask substrate with enhanced process monitoring, for example, by providing for optical monitoring at different regions of the photomask to obtain desired etch rate or thickness loss is provided. In one embodiment, the method includes performing an etching process on a reflective multi-material layer that includes at least one molybdenum layer and one silicon layer through a patterned mask, directing radiation having a wavelength from about 170 nm and about 800 nm to an area of the multi-material layer uncovered by the patterned mask, collecting an optical signal reflected from the area uncovered by the patterned mask, analyzing a waveform obtained from the reflected optical signal, and determining a first endpoint of the etching process when an intensity of the reflected optical signal is between about 60 percent and about 90 percent less than an initial reflected optical signal.
    Type: Grant
    Filed: July 8, 2012
    Date of Patent: August 19, 2014
    Assignee: Applied Materials, Inc.
    Inventor: Michael Grimbergen
  • Patent number: 8808557
    Abstract: In one embodiment, a pattern forming method includes forming a physical guide that includes a first pattern in a first region and a second pattern in a second region on an underlying film, embedding a polymer material into a concave portion of the physical guide, microphase-separating the polymer material, to form a self-assembly pattern having a first and a second polymer sections, observing the self-assembly pattern in the second region, to determine from an observation result whether or not the self-assembly pattern in the first region has a predetermined shape, and selectively removing the first polymer section in the case of determining that the self-assembly pattern in the first region has the predetermined shape. The second pattern includes a pattern with a larger coverage ratio than the first pattern and a pattern with a smaller coverage ratio than the first pattern.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: August 19, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuriko Seino, Hiroki Yonemitsu