Abstract: A process involving vapor etching of nuclear tracks in dielectric materials for creating high aspect ratio (i.e., length much greater than diameter), isolated cylindrical holes in dielectric materials that have been exposed to high-energy atomic particles. The process includes cleaning the surface of the tracked material and exposing the cleaned surface to a vapor of a suitable etchant. Independent control of the temperatures of the vapor and the tracked materials provide the means to vary separately the etch rates for the latent track region and the non-tracked material. As a rule, the tracked regions etch at a greater rate than the non-tracked regions. In addition, the vapor-etched holes can be enlarged and smoothed by subsequent dipping in a liquid etchant.

Abstract: A method for stripping an ion implanted photoresist layer from a substrate. There is first provided a substrate. There is then formed over the substrate an ion implanted photoresist layer. There is then treated the ion implated photoresist layer with a first plasma employing a first etchant gas composition comprising a fluorine containing species to form a fluorine plasma treated ion implanted photoresist layer. Finally, there is then stripped from the substrate the fluorine plasma treated ion implanted photoresist layer with a second plasma employing a second etchant gas composition comprising an oxygen containing species without the fluorine containing species. The ion implanted photoresist layer is stripped from the substrate without plasma induced damage to the substrate.

Abstract: In order to study an etching rate difference of a layer formed mainly with silicon dioxide on a wafer, a thermal oxide film (113) and layers of BSG (117), BPSG (125), and PSG (129) are laminated on a wafer and are etched in a gaseous etching atmosphere consisting essentially of hydrogen fluoride or a mixture of hydrogen fluoride and water vapor. The layers are etched with various etching rates which are higher than that of the thermal oxide film. The etching rate difference is a difference between the etching rate of each layer and an etching rate of the thermal oxide film. The layers may include impurities, such as boron and phosphorus, collectively as a part of a layer material of each layer. The etching rate difference depends on the layer material. Preferably, the gaseous etching atmosphere should have a reduced pressure. Alternatively, a water vapor partial pressure should not be greater than 2000 Pa. As a further alternative, either the layer or the gaseous etching atmosphere should be heated.

Abstract: A lithographic process for device fabrication is disclosed in which a hydrogen fluoride vapor is used to develop a pattern from an image introduced into an energy sensitive resist material. A class of silicon-containing materials display excellent sensitivity in the ultraviolet and deep ultraviolet for the formation of patterns by radiation induced conversion into glassy compounds. When these materials are patternwise exposed to radiation in the presence of oxygen, the oxygen content of the unexposed region is significantly different from the oxygen content in the exposed region. The pattern is developed using HF because the higher oxygen content material is etched at a faster rate by HF than the lower oxygen content material. Materials are deposited from the vapor phase and show excellent promise for use as resists in the fabrication of electronic and optical devices.

Abstract: This invention discloses a method of planarizing a top surface with variations of profile heights above a substrate of a semiconductor chip. The method includes a step producing a polish-differentiating surface which has polishing rates proportional to the variations of the profile heights of the polish-differentiating surface above the substrate provided for performing a planarization process by applying a polishing process thereon. With the polishing differentiating surface the dishing effects of the semiconductor chip is substantially reduced when a one-time chemical mechanical polishing (CMP) process is applied for semiconductor chip planarization.

Abstract: Microchannels for conducting and expelling a fluid are embedded in a surface of a silicon substrate. A channel seal is made of plural cross structures formed integrally with the silicon substrate. The cross structures are arranged sequentially over each channel, each cross structure having a chevron shape. The microchannel is sealed by oxidizing at least partially the cross structures, whereby the spaces therebetween are filled. A dielectric seal which overlies the thermally oxidized cross structures forms a complete seal and a substantially planar top surface to the silicon substrate. The dielectric seal is formed of a low pressure chemical vapor deposition (LPCVD) dielectric layer. The channel is useful in the production of an ink jet print in head, and has a polysilicon heater overlying the dielectric seal. A current passing through the heater causes a corresponding increase in the temperature of the ink in the microchannel, causing same to be expelled therefreom.

Abstract: A pattern forming method using an improved charged particle beam process, and a charged particle beam processing system prevent effectively the corrosion of a workpiece by a reactive gas adsorbed by and adhering to the surface of the workpiece when the workpiece is taken out into the atmosphere after pattern formation. The charged particle beam processing system comprises, as principal components, an ion beam chamber provided with an ion beam optical system, a processing chamber (18) provided with a gas nozzle through which a reactive gas is blown against a workpiece, a load-lock chamber connected through a gate valve to the processing chamber. The load-lock chamber is capable of producing a plasma of an inert gas for processing the surface of the workpiece by sputtering.

Abstract: Provided is a method of etching an etch layer using a polycarbonate layer as a mask. The method includes placing an etch structure in a reaction chamber, the etch structure including an etch layer underlying a polycarbonate layer, the polycarbonate layer having apertures. The etch layer is then etched using a low pressure-high density plasma generate at a pressure in the range of approximately 1 to 30 millitorr where the ionized particle concentration is at least 10.sup.11 ions/cm.sup.3 and where the ionized particle concentration is substantially equal throughout the volume of the reaction chamber. To increase the etch rate, the etch structure can be heated or biased. To decrease the etch rate, an inert gas can be added to the process gas mixture used to form the plasma.

Abstract: The uniformity of SiO.sub.2 etching over the surface area of a substrate using a conventional SiO.sub.2 etching reaction, such as a HF/ROH reaction where R is H or alkyl, is improved when the substrate is pretreated before the etch reaction. In the pretreatment the substrate within a process chamber is exposed to UV illuminated halogen gas. Suitable halogen gases are fluorine and chlorine. Oxygen may optionally also be included with the halogen gas. The pretreatment renders the etching uniformity results substantially independent of the storage history of the wafer.

Abstract: A method of fabricating an integrated circuit device is described in which fluorine ions are implanted into the patterned photoresist and the exposed polysilicon layer prior to etching the polysilicon. The ion implantation minimizes the chemical reaction between the photoresist and etchant, thereby significantly reducing the formation of polysilicon etch delta, and also significantly reducing etch delta variation due to pattern density variations.

Abstract: A method of manufacturing a semiconductor device comprises the steps of introducing a first gas containing steam or alcohol into a processing vessel housing a semiconductor substrate, and introducing a hydrogen fluoride gas as a second gas into the processing vessel after stopping introduction of the first gas into the process chamber.

Abstract: The present invention is related to a method for increasing utilzable surface area of a rugged polysilicon layer in a semiconductor device. The present method includes steps of: (a) providing a pre-grown rugged polysilicon layer which is composed of polysilicon with first dopants doped therein; (b) forming another polyslicon layer on the pre-grown rugged polysilicon layer; (c) removing a portion of the another polysilicon layer by an anisotropic etching process to expose an upper surface of the pre-grown rugged polysilicon layer; and (d) etching the resulting pre-grown rugged polysilicon layer which an etching selectivity ratio of the pre-grown rugged polysilicon layer to the another polysilicon layer being greater than one, to obtain the rugged polysilicon layer having increasing utilizable surface area. A semiconductor device containing the rugged polysilicon layer created according to the present invention can work well in a relatively dense and small semiconductor chip.

Abstract: A processing method is described which has a first step of depositing on a substrate a specimen film which may be any one of a semiconductor, a metal and a insulator.In a second step, the surface of the specimen film deposited in the first step, is irradiated with an ion beam to produce a physical damage on the surface, next, in a third step, the damaged specimen film surface is selectively irradiated with the light to partially cause a photochemical reaction so that a mask pattern, which depends on the desired device structure, is formed on the film surface. Finally, in a fourth step, photoetching is performed using the mask pattern formed in the third step as a shielding member.

Abstract: A method of fabricating a resonant micromesh filter having conductive antenna elements sized on the order of microns. The steps comprise of first creating an exposure mask having absorbing portions capable of stopping incident ions completely and transmitting portions incapable of stopping incident ions and through which incident ions can pass. The absorbing and transmitting portions form in the mask in the pattern of the antenna elements to be fabricated. Second, an exposure mask confronting an unpatterned filter is positioned. The unpatterned filter includes: a substrate, a thin metal foil mounted on the substrate, and a resist material covering the metal flow. Third, ions are passed through the exposure mask. The absorbing portions of the mask stop the ions and the transmitting portions allow the ions to pass through the mask and expose the section of the resist material of the filter in the pattern of the antenna elements.

Abstract: A semiconductor processing method of forming a contact opening includes providing a substrate having a node location to which electrical connection is to be made. A layer comprising doped silicon dioxide is formed over the node location. Thereafter, both O.sub.2 and O.sub.3 are flowed simultaneously to the substrate along with tetraethylorthosilicate to the substrate to form a continuous layer comprising undoped silicon dioxide on the layer comprising doped silicon dioxide. During the flowing, a ratio of O.sub.3 to O.sub.2 flows is increased to form an outer portion of the continuous layer comprising undoped silicon dioxide to have a higher etch rate for a selected wet etch chemistry than an inner portion of said continuous layer. A common contact opening is anisotropically dry etched into the layer comprising undoped silicon dioxide and into the layer comprising doped silicon dioxide over the node location to outwardly expose the node location.

Abstract: A method for dry etching of transition metals. The method for dry etching of a transition metal (or a transition metal alloy such as a silicide) on a substrate comprises providing at least one nitrogen- or phosphorous-containing .pi.-acceptor ligand in proximity to the transition metal, and etching the transition metal to form a volatile transition metal/.pi.-acceptor ligand complex. The dry etching may be performed in a plasma etching system such as a reactive ion etching (RIE) system, a downstream plasma etching system (i.e. a plasma afterglow), a chemically-assisted ion beam etching (CAIBE) system or the like. The dry etching may also be performed by generating the .pi.-acceptor ligands directly from a ligand source gas (e.g. nitrosyl ligands generated from nitric oxide), or from contact with energized particles such as photons, electrons, ions, atoms, or molecules.

Abstract: This process for producing a structure incorporating a substrate (2), a thin surface film (16) made from a non-conducting material joined to one face (1) of the substrate (2), said substrate (2) having cavities (10) flush with said face (1), comprises the following successive stages:etching cavities (10) in one face (1) of a substrate, the cavities having in the plane of the substrate face at least one dimension which is a function of the thickness of the surface film, in order to correctly secure the latter,joining a non-conducting material wafer (12) to the face (1) of the substrate (2),thinning the wafer (12) to obtain the thin surface film.

Abstract: A method for attaining a uniform roughening of a silicon semiconductor surface with a microscopic amount of roughness at the .ANG. level, wherein the amount of roughness may be accurately and precisely controlled without complicating the manufacturing processes and increasing the manufacturing cost, and regardless of the shape of the silicon surface area of the substrate. The substrate with the silicon surface area is immersed in a cleansing solution, such as SC1 for example, containing a metallic substance, such as Fe, Ni, Cu, Zn, Al, and Cr, for example, at the ppb level to wash the surface. Then, a silicon oxide film uniformly containing the metallic substance is formed on the silicon surface of the substrate after drying, and isotropic etching is performed on the surface of the substrate formed with the silicon oxide film by etching Si from the silicon oxide film at a high ratio of selectivity to form microscopic irregularities.

Abstract: A process for ablation etching through one or more layers of dielectric materials while not etching an underlying conductive material layer comprises selecting parameters whereby the ablation process automatically stops when the conductive material layer is reached, or monitoring the process for end point detection of the desired degree of ablation. Parameters selected are the absorptivity of the dielectric layer versus that of the conductive material layer. End point detection comprises monitoring radiant energy reflected from the workpiece or the content of the materials being ablated from the workpiece.

Abstract: Method for creating a doped polysilicon layer of accurate shape on a sidewall of a semiconductor structure. According to the present method, a doped polysilicon film covering at least part of said semiconductor structure and of said sidewall is formed. This polysilicon film then undergoes a reactive ion etching (RIE) process providing for a high etch rate of said polysilicon film to approximately define the shape of the polysilicon layer on said sidewall. Then, said polysilicon film undergoes a second reactive ion etching process. This second reactive ion etching process is a low polysilicon etch rate process such that non-uniformities of the surface of said polysilicon film are removed by sputtering.

Abstract: A processing method comprises:a first step of depositing on a substrate which is a specimen a film of any one of a semiconductor, a metal and an insulator;a second step of subjecting the surface of the film deposited in the first step, to irradiation with a beam having a given energy to produce a physical damage on the surface;a third step of subjecting the film surface on which the physical damage is produced in the second step, to selective irradiation with light to partially cause a photochemical reaction so that a mask pattern depending on the desired device structure is formed on the film surface; anda fourth step of carrying out photoetching using as a shielding member the mask pattern formed in the third step.

Abstract: A surface type acceleration sensor includes a p-type single crystal silicon base plate, a cantilever functioning as a cantilever structure portion, and a plurality of strain gauges. The cantilever is disposed in a recess portion formed on the front face of the p-type single crystal silicon base plate so that the cantilever can be displaced in the upward and downward direction. The cantilever includes an epitaxial growth layer principally made of n-type single crystal silicon. The strain gauge is made of p-type silicon and formed on an upper face of the base end portion of the cantilever.

Abstract: A process is disclosed for forming trenches having high surface-area sidewalls with undulating profiles. Such trenches are formed by first implanting multiple vertically separated layers of dopant in a substrate beneath a region where the trench is to be formed. Next, the trench is formed under conditions chosen to selectively attack highly doped substrate regions (i.e., substrate regions where the dopant has been implanted). The resulting trench sidewalls will have undulations corresponding to the positions of the implanted regions. In one case, the implanted layers contain germanium ions, and a trench is aniostropically etched through the layers of germanium. Thereafter, the trench is subjected to oxidizing conditions to form regions of germanium oxide. Finally, the trench is exposed to an aqueous solvent which dissolves germanium oxide, disrupting the silicon lattice, and leaving gaps or undulations in the sidewall.

Abstract: A hybrid thermal imaging system (20, 120) often includes a focal plane array (30, 130), a thermal isolation structure (50, 150) and an integrated circuit substrate (60, 160). The focal plane array (30, 130) includes thermal sensitive elements (42, 142) formed from a pyroelectric film layer (82), such as barium strontium titanate (BST). One side of the thermal sensitive elements (42, 142) may be coupled to a contact pad (62, 162) disposed on the integrated circuit substrate (60, 160) through a mesa strip conductor (56, 150) of the thermal isolation structure (50, 150). The other side of the thermal sensitive elements (42, 142) may be coupled to an electrode (36, 136). The various components of the focal plane array (30, 130) may be fabricated from multiple heterogenous layers (74, 34, 36, 82, 84) formed on a carrier substrate (70).

Abstract: A monolithic, micromechanical vibrating beam accelerometer with a trimmable resonant frequency is fabricated from a silicon substrate which has been selectively etched to provide a resonant structure suspended over an etched pit. The resonant structure comprises an acceleration sensitive mass and at least two flexible elements having resonant frequencies. Each of the flexible elements is disposed generally collinear with at least one acceleration sensitive axis of the accelerometer. One end of at least one of the flexible elements is attached to a tension relief beam for providing stress relief of tensile forces created during the fabrication process. Mass support beams having a high aspect ratio support the mass over the etched pit while allowing the mass to move freely in the direction collinear with the flexible elements. Also disclosed is a method for fabricating such an accelerometer.

Abstract: The present invention discloses a method for constructing a completely micromachined MCP that is activated with thin-film dynodes wherein the interchannel regions are first dry etched in the substrate, resulting in channel pillars. The etched portions of the substrate are then back filled and the channel pillars are thereafter removed to produce a micromachined perforated microchannel plate. The technique may be employed to produce an active element for an integrated image tube or photomultiplier tube.

Abstract: A Reactive Ion Etch (RIE) plasma method for removing from semiconductor substrates oxidized organic residues such as oxidized photoresist residues, and the Reactive Ion Etch (RIE) plasma which is employed within the Reactive Ion Etch (RIE) plasma method. A semiconductor substrate upon whose surface resides an oxidized organic residue such as an oxidized photoresist residue is provided into a Reactive Ion Etch (RIE) plasma chamber. Also provided into the chamber is a concentration of oxygen and a concentration of moisture. Finally, a radio frequency excitation of sufficient magnitude is provided to the concentration of oxygen and the concentration of moisture to form a plasma. The oxidized organic residue which resides upon the semiconductor substrate is then removed through etching in the Reactive Ion Etch (RIE) plasma.

Abstract: A method for processing a low dielectric constant material includes dispersing an additive material in a porous low dielectric constant layer, fabricating a desired electronic structure, and then removing the additive material from the pores of the low dielectric constant layer. The removal of the additive material from the pores can be accomplished by sublimation, evaporation, and diffusion. Applications for the low dielectric constant layer include the use as an overlay layer for interconnecting a circuit chip supported by a substrate and the use as printed circuit board material.

Abstract: A gimballed vibrating wheel gyroscope for detecting rotational rates in inertial space. The gyroscope includes a support oriented in a first plane and a wheel assembly disposed over the support parallel to the first plane. The wheel assembly is adapted for vibrating rotationally at a predetermined frequency in the first plane and is responsive to rotational rates about a coplanar input axis for providing an output torque about a coplanar output axis. The gyroscope also includes a post assembly extending between the support and the wheel assembly for supporting the wheel assembly. The wheel assembly has an inner hub, an outer wheel, and spoke flexures extending between the inner hub and the outer wheel and being stiff along both the input and output axes. A flexure is incorporated in the post assembly between the support and the wheel assembly inner hub and is relatively flexible along the output axis and relatively stiff along the input axis.

Abstract: An interconnection in a semiconductor device is made of a conductive laminate including a Ti film, a TiN film and an aluminium alloy film consecutively formed on a SiO.sub.2 film grown on a Si substrate. A heat treatment of the conductive layer is performed at 450.degree.-600.degree. C. before plasma-etching to introduce nitrogen and oxygen atoms from TiN film and SiO.sub.2 film, respectively, into the Ti film. The nitrogen and oxygen atoms prevent the side-etching of the Ti film during a plasma etching of the laminate using a plasma containing chlorine atoms. An interconnection having a high reliability is obtained with a high productivity.

Abstract: A method of manufacturing a semiconductor device, where on top of a substrate having already-completed circuit elements and wiring, etc., an insulation underlayer a, Pt layer for a bottom electrode, a dielectric film and a Pt layer for a top electrode are shaped.A top electrode, capacitance insulation film and bottom electrode are formed by etching the Pt layer for the top electrode or the Pt layer for the bottom electrode using an etching gas contained an S component while composing a Pt and S compound. Alternatively the Pt and S compound can be composed first, and then the compound can be etched.

Abstract: A method for preventing cross-contamination of semiconductor wafers during processing comprising covering a surface portion of a support assembly with a process compatible material, engaging a semiconductor wafer with the support assembly, processing the wafer while it is engaged with the support member, and removing the process compatible material from the support assembly after said material is considered to be contaminated. A shield particularly adapted for this process includes a shield portion made from a process compatible material and a process-compatible adhesive for attaching the shield portion to the support assembly.

Abstract: The present invention features a process and a resulting article in which copper-based multilevel interconnects are fabricated. The copper-based multilevel interconnect formed by the inventive process first includes the process step of depositing a pattern of copper lines upon or in an applicable substrate, such as silicon dioxide. The copper lines are approximately one micron thick. The lines are coated with approximately 50 to 100 nm of titanium by sputter deposition, and undergo subsequent annealing at approximately 300.degree. C. to 400.degree. C. in an argon ambient. The titanium and copper layers are annealed to provide a Cu.sub.3 Ti alloy at the copper/titanium junction. The unreacted titanium between the copper features is then stripped away by dry etching with fluorine-based etch. The remaining Cu.sub.3 Ti alloy is subsequently transformed into TiN(O) and copper by a rapid thermal annealing in an NH.sub.3 atmosphere at an approximate temperature of below 650.degree. C.

Abstract: A method of processing a sample using a charged beam and reactive gases and a system employing the same, the method and system being able to perform the reactive etching and the beam assisted deposition using a charged particle detector free from the degradation of the performance due to the reactive gas. The system is designed in such a way that a shutter mechanism is provided in the form of the charged particle detector, and a chamber for accommodating the charged particle detector can be evacuated. In the observation of the sample, the charged particle detector is turned on to open the shutter mechanism, and in the processing of the sample, the charged particle detector is turned off or left as it is to shut the shutter mechanism to evacuate the inside of the charged particle detector.

Abstract: A pattern formation material capable of keeping dimensional accuracy of a pattern at a desired level even after a polymer is left standing for a long time after exposure and before baking, and a method of forming such a pattern formation material, which comprises a copolymer containing units containing a polycyclic aromatic ring, a condensed ring having at least one aromatic ring, or an aromatic ring having, as a substitution group, an alicyclic group, a branched alkyl or a halogen, and units from a monomer containing a photosensitive group, and a compound generating an acid by irradiation to ultraviolet rays.

Abstract: Bodies of at least one material are held in a contacting holder 12 in a vacuum chamber. The surfaces of the bodies are cleaned by a low energy ion etching. Water vapor from a pure water bottle is supplied through a nozzle as a water molecule beam so that water molecules and hydroxide groups are chemically adsorbed on the surfaces of the bodies. A plasma beam or microwaves are applied to the surfaces of the bodies to remove the water molecules and leave only hydroxide groups remaining on the surfaces. The holder is operated to bring the surfaces of the bodies into contact with each other, to thereby obtain direct bonding of the bodies.

Abstract: An improved process for fabricating a planar field oxide structure on a silicon substrate was achieved. The process involves forming the field oxide by using the LOCal Oxidation of Silicon (LOCOS) process in which the device area is protected from oxidation by a silicon nitride layer. A sacrificial implant layer, such as CVD oxide, oxynitride or an anti-reflective coating (ARC) layer is used to fill in the gap between the silicon nitride and the field oxide structure and make more planar the substrate surface. The substrate surface is then implanted with As.sup.75 or p.sup.31 ions penetrating the sacrificial implant layer and forming a implant damaged layer on the field oxide. The implant damaged layer which etches faster in a wet etch in removed selectively thereby making a more planar field oxide structure. The method does not require a recess to be etched in the silicon substrate and therefore, has certain reliability and cost advantages.

Abstract: A non-photographic diffusion patterning method for making patterns in organic films utilizing a screen having a plurality of recessed polygon-shaped apertures.