Irradiating, Ion Implanting, Alloying, Diffusing, Or Chemically Reacting The Substrate Prior To Etching To Change Properties Of Substrate Toward The Etchant Patents (Class 216/62)
  • Patent number: 6582617
    Abstract: Provided is a method of etching an etch layer using a polycarbonate layer as a mask. The method includes placing an etch structure in a reaction chamber, the etch structure including an etch layer underlying a polycarbonate layer, the polycarbonate layer having apertures. The etch layer is then etched using a low-pressure high density plasma generate at a pressure in the range of approximately 1 to 30 millitorr where the ionized particle concentration is at least 1011 ions/cm3 and where the ionized particle concentration is substantially equal throughout the volume of the reaction chamber. To increase the etch rate, the etch structure can be cooled or biased. To decrease the etch rate, an inert gas can be added to the process gas mixture used to form the plasma.
    Type: Grant
    Filed: April 29, 1999
    Date of Patent: June 24, 2003
    Assignee: Candescent Technologies Corporation
    Inventor: Chungdee Pong
  • Publication number: 20030098291
    Abstract: A layer-by-layer etching apparatus and an etching method using a neutral beam which enables to control etching depth to an atomic level by controlling the etching of each atom of a material layer to be etched under precise control of the supply of an etching gas and irradiation of the neutral beam and enables to minimize etching damage. In the layer-by-layer etching method, a substrate to be etched, on which a layer to be etched is exposed, is loaded on a stage in a reaction chamber. An etching gas is supplied into the reaction chamber to adsorb the etching gas on the surface of an exposed portion of the layer to be etched. Excessive etching gas remaining after being adsorbed is removed. A neutral beam is irradiated on the layer to be etched on which the etching gas is adsorbed. Etch by-products generated by the irradiation of the neutral beam is removed.
    Type: Application
    Filed: February 28, 2002
    Publication date: May 29, 2003
    Inventors: Geun-Young Yeom, Min-Jae Chung, Do-Haing Lee, Sung-Min Cho, Sae-Hoon Chung
  • Patent number: 6564439
    Abstract: A method of manufacturing a surface acoustic wave element includes the steps of providing a piezoelectric body having an interdigital transducer, where the interdigital transducer is made of a metal having a higher density than the piezoelectric body, and performing ion bombardment of the interdigital transducer and the piezoelectric body simultaneously so as to reduce the thickness of the interdigital transducer and the piezoelectric body.
    Type: Grant
    Filed: April 10, 2000
    Date of Patent: May 20, 2003
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Eiichi Takata, Yasuji Yamamoto, Toshimaro Yoneda, Michio Kadota
  • Patent number: 6565764
    Abstract: Molded products may be made by a process comprising preparing a structure comprising a block copolymer or a graft copolymer having two or more phases, wherein each phase is comprised of polymer chains, decomposing the polymer chains of at least one phase of the structure, and cleaning the structure with a supercritical fluid or a sub-critical fluid, thereby removing the decomposed polymer chains from the structure. Molded products made by this method have very low levels of residual solvents, can be manufactured at a relatively low temperature in a short period of time without using large amounts of organic solvents, and without discharging large amounts of liquid waste.
    Type: Grant
    Filed: August 13, 2001
    Date of Patent: May 20, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiro Hiraoka, Koji Asakawa, Yasuyuki Hotta
  • Patent number: 6544431
    Abstract: A method of forming thin film waveguide regions in lithium niobate uses an ion implant process to create an etch stop at a predetermined distance below the lithium niobate surface. Subsequent to the ion implantation, a heat treatment process is used to modify the etch rate of the implanted layer to be in the range of about 20 times slower than the bulk lithium niobate material. A conventional etch process (such as a wet chemical etch) can then be used to remove the virgin substrate material and will naturally stop when the implanted material is reached. By driving the ions only a shallow distance into the substrate, a backside etch can be used to remove most of the lithium niobate material and thus form an extremely thin film waveguide that is defined by the depth of the ion implant. Other structural features (e.g., ridge waveguides) may also be formed using this method.
    Type: Grant
    Filed: January 16, 2001
    Date of Patent: April 8, 2003
    Assignee: TriQuint Technology Holding Co.
    Inventors: Douglas M. Gill, Dale Conrad Jacobson
  • Patent number: 6540827
    Abstract: A method is provided for detaching a single-crystal film from an epilayer/substrate or bulk crystal structure. The method includes the steps of implanting ions into the crystal structure to form a damage layer within the crystal structure at an implantation depth below a top surface of the crystal structure, and chemically etching the damage layer to effect detachment the single-crystal film from the crystal structure. The thin film may be detached by subjecting the crystal structure with the ion implanted damage layer to a rapid temperature increase without chemical etching. The method of the present invention is especially useful for detaching single-crystal metal oxide films from metal oxide crystal structures. Methods for enhancing the crystal slicing etch-rate are also disclosed.
    Type: Grant
    Filed: July 18, 2000
    Date of Patent: April 1, 2003
    Assignee: Trustees of Columbia University in the City of New York
    Inventors: Miguel Levy, Richard M. Osgood, Jr., Antonije M. Radojevic
  • Patent number: 6527967
    Abstract: A method of forming a thin-piece sample for use in an electron microscope. The ion beam scanning used for etching a sample block to form a thin-wall portion is initiated from the outer perimeter of two opposite sides of the sample block to be formed, one side at a time, and the ion beam is directed from the outer perimeter of the sample block inwards towards the center of the sample block. When the two sides of the sample block are etched from the outside into the sample block, a thin wall is produced at the interior portion of the sample block. Also, a plurality of samples may be set in a known positional relationship, and a series of forming functions, including ion beam scanning, may be programmed for automation, allowing a plurality of samples to be formed all at one time easily and efficiently.
    Type: Grant
    Filed: July 16, 1999
    Date of Patent: March 4, 2003
    Assignee: Seiko Instruments, Inc.
    Inventor: Hidekazu Suzuki
  • Patent number: 6511777
    Abstract: A method for fabricating a phase shift photomask (10) includes providing a photomask (12) having a substantially opaque layer (16) on a surface (14) of a substantially transparent substrate (18). The opaque layer (14) includes a removed portion to define a light transmitting pattern (20) of the photomask (12). The method also includes depositing an implant (22) in a portion of the substrate (18). The implanted portion (24) of the substrate (18) includes an etch rate different than an etch rate of an unimplanted portion (32) of the substrate (18). The method includes initiating an etch of the substrate (18) corresponding to the light transmitting pattern (20) and monitoring a rate of the etch. The method further includes terminating the etch in response to detecting a change in the rate of the etch.
    Type: Grant
    Filed: September 21, 2000
    Date of Patent: January 28, 2003
    Assignee: Texas Instruments Incorporated
    Inventor: Sylvia D. Pas
  • Patent number: 6509138
    Abstract: Processes for patterning radiation sensitive layers are disclosed. In one embodiment, the process includes depositing a radiation sensitive material on a substrate by chemical vapor deposition. The radiation sensitive material is exposed to radiation to form a pattern and the pattern is developed using a supercritical fluid (SCF).
    Type: Grant
    Filed: January 12, 2000
    Date of Patent: January 21, 2003
    Assignees: Semiconductor Research Corporation, Cornell Research Foundation, Inc., Massachusetts Institute of Technology
    Inventors: Karen K. Gleason, Christopher Ober, Daniel Herr
  • Patent number: 6503409
    Abstract: A new class of silicon-based lithographically defined nanoapertures and processes for their fabrication using conventional silicon microprocessing technology have been invented. The new ability to create and control such structures should significantly extend our ability to design and implement chemically selective devices and processes.
    Type: Grant
    Filed: May 25, 2000
    Date of Patent: January 7, 2003
    Assignee: Sandia Corporation
    Inventor: James G. Fleming
  • Publication number: 20020195422
    Abstract: A process for milling copper metal from a substrate having an exposed copper surface includes absorbing a halogen gas onto the exposed copper surface to generate reaction products of copper and the halogen gas; removing unreacted halogen gas from the surface; and directing a focused ion beam onto the surface to selectively remove a portion of the surface comprising the reaction products.
    Type: Application
    Filed: June 22, 2001
    Publication date: December 26, 2002
    Applicant: International Business Machines Corporation
    Inventors: Michael R. Sievers, Steven B. Herschbein, Aaron D. Shore
  • Publication number: 20020185151
    Abstract: A process for removing polymers formed during etching and etch residues from a semiconductor substrate by exposing the substrate to plasmas of neutral chemistry. The plasma generates atomic hydrogen species and atomic oxygen species in about equal amounts that react with and remove the polymers and etch residues from the substrate. The process is especially suitable for use with semiconductor substrates comprising low k dielectric materials and/or copper interconnects.
    Type: Application
    Filed: May 23, 2001
    Publication date: December 12, 2002
    Inventors: Han Qingyuan, Carlo Waldfried, Orlando Escorcia, Gary Dahrooge, Ivan Berry
  • Publication number: 20020182877
    Abstract: The present Invention provides a method of photo-processing of materials in the presence of a reactive fluid which involves using light selected on the basis that the material has a long absorption for the wavelength of emission of the light. The present invention teaches photo-processing of semiconductors such as silicon using infrared radiation and is very advantageous since, in those materials to be processed having a very long absorption for the wavelength of emission of the light, one obtains volume absorption deep under the surface of the illuminated region so that the material under the surface is heated. The material is irradiated with the light beam in the presence of a reactive gas, the light beam having a wavelength in an infrared portion of the electromagnetic spectrum wherein the irradiated selected region of the solid is heated and reacts with the reactive gas to remove atoms or molecules of the material from the irradiated region.
    Type: Application
    Filed: April 9, 2002
    Publication date: December 5, 2002
    Inventors: Marc Nantel, Yuri Yashkir
  • Publication number: 20020182546
    Abstract: A process for producing an optical disk master, comprises the steps of forming a photoresist layer on a glass master, cutting the photoresist layer by projecting light beam onto the glass master having the photoresist layer thereon to expose the photoresist layer to light, developing the photoresist layer after the cutting step to form a hollow portion corresponding to the light-exposed portion, and carrying out an ion treatment by projecting ions onto the developed photoresist layer to decrease the thickness of the photoresist layer at the developed hollow portion to reach the prescribed depth by the ion-treatment.
    Type: Application
    Filed: March 28, 2002
    Publication date: December 5, 2002
    Inventors: Masahito Konishi, Keiji Nishikiori, Koujiro Tanaka
  • Patent number: 6471878
    Abstract: A method for forming a radio frequency responsive target formed of a pattern of thin dipoles, each of which has a position and angular orientation within the pattern, which produce a composite analog radio frequency signal in response to an interrogating signal. A first metallic film layer is deposited on top of a non-conductive substrate, an etchant resistant pattern correspondent to the thin dipole pattern is deposited on top of the first metallic film layer, and a second metallic layer occupying the first metallic layer in at least one area without etchant is applied on top of the first metallic film layer. The etchant resistant pattern is removed to expose portions of the first metallic film layer, and the second metallic layer and the exposed portions of the first metallic film layer are etched simultaneously.
    Type: Grant
    Filed: June 9, 1999
    Date of Patent: October 29, 2002
    Assignee: Gordion Holding Corporation
    Inventors: Morton Greene, G. William Hurley
  • Patent number: 6465363
    Abstract: A vacuum processing apparatus produces fluorine radicals by activating a fluorinating gas containing at least fluorine atoms and fluorinates the surface of a component formed of an organic material (32) exposed to an atmosphere of a processing chamber (2) before carrying an object (S) into the processing chamber (2). The object (S) is carried into the processing chamber (2) after the completion of a fluorinating process. The object (S) is processed with a processing gas containing at least oxygen radicals. Etching of the component formed of the organic material (32) can be prevented by the fluorination of surface of the component formed of the organic material (32) and exposed to an atmosphere in the processing chamber (2).
    Type: Grant
    Filed: October 28, 1999
    Date of Patent: October 15, 2002
    Assignee: Shibaura Mechatronics Corporation
    Inventor: Masaru Kasai
  • Publication number: 20020139773
    Abstract: A process for forming sub-lithographic features in an integrated circuit is disclosed herein. The process includes modifying a photoresist layer after patterning and development but before it is utilized to pattern the underlying layers. The modified photoresist layer has different etch rates in the vertical and horizontal directions. The modified photoresist layer is trimmed with a plasma etch. A feature included in the trimmed photoresist layer has a sub-lithographic lateral dimension.
    Type: Application
    Filed: March 28, 2001
    Publication date: October 3, 2002
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Calvin T. Gabriel, Harry J. Levinson, Uzodinma Okoroanyanwu
  • Publication number: 20020125511
    Abstract: In a semiconductor device in which a switching element for allowing a current to flow to a load and a circuit for driving the switching element are formed on a common substrate, the switching element is formed of a DMOS transistor, and the circuit for driving the switching element includes an MOS transistor having a characteristic different from that of the DMOS transistor.
    Type: Application
    Filed: February 8, 2002
    Publication date: September 12, 2002
    Inventor: Mineo Shimotsusa
  • Patent number: 6444136
    Abstract: Fabrication of improved low-k dielectric structures is disclosed. Low-k dielectric structures are fabricated while overcoming the otherwise existing problems associated with the use of low-k dielectric materials. In one embodiment, the physical properties of a low-k dielectric material is modified by exposing the low-k dielectric material to electron beams. The exposed portion of the low-k dielectric material becomes easier to etch and clean and exhibits greater mechanical strength and a reduction in absorption of moisture. In another embodiment, a number of incremental exposure and etch steps are performed to fabricate a desired structure. In yet another embodiment, the steps of exposure of a low-k dielectric material are combined with the etch steps. The exposure and the etching of the low-k dielectric material are performed concurrently in the same system. In still another embodiment, a single exposure and a single etch step are utilized to fabricate a desired structure.
    Type: Grant
    Filed: April 25, 2000
    Date of Patent: September 3, 2002
    Assignee: Newport Fab, LLC
    Inventors: Q. Z. Liu, Bin Zhao
  • Patent number: 6432317
    Abstract: This is a method for masking a structure 12 for patterning micron and submicron features, the method comprises: forming at least one monolayer 32 of adsorbed molecules on the structure; prenucleating portions 46,48 of the adsorbed layer by exposing the portions corresponding to a desired pattern 36 of an energy source 42; and selectively forming build-up layers 66,68 over the prenucleated portions to form a mask over the structure to be patterned. Other methods are also disclosed.
    Type: Grant
    Filed: August 4, 1994
    Date of Patent: August 13, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Monte A. Douglas, Richard A. Stoltz
  • Patent number: 6426015
    Abstract: A method is provided for reducing elevated boron concentrations (denoted as “boron spikes”) in an insulating layer containing silicon, boron and other elements where the layer interfaces with surfaces of a semiconductor device. The method includes the steps of: seasoning a reaction chamber by flowing into it a mixture of gasses containing silicon, boron, ozone and other elements in predetermined proportions under set conditions of time, pressure, temperature and flow rates to deposit on inner walls and surfaces of the chamber a thin seasoning coating, and placing a semiconductor device in the chamber and covering it with an insulating layer having a composition similar to the seasoning coating. Subsequent etching of selected portions of the insulating layer has been found not to expose conductive surfaces of the device.
    Type: Grant
    Filed: December 14, 1999
    Date of Patent: July 30, 2002
    Assignee: Applied Materials, Inc.
    Inventors: Li-Qun Xia, Francimar Campana, Ellie Yieh
  • Patent number: 6416938
    Abstract: A process for making a two-component plasma-deposited photo-oxidizable organosilicon film on a substrate from a silicon donor and an organic precursor. Subjecting selected areas of the film to photo-oxidation allows selective etching of the non-photo-oxidized or photo-oxidized areas of the film. The process is used as a resist for patterning substrates in the fabrication of solid-state devices. It is of particular use in patterning heat sensitive substrates and accomplishing microlithography in a closed chamber process at other than atmospheric pressure. The process allows photo-oxidation with ultraviolet light at wavelengths closer to visible light than that for conventional photoresists. The processed film exhibits selective wetting properties between the non-photo-oxidized and photo-oxidized areas of the film.
    Type: Grant
    Filed: November 6, 1999
    Date of Patent: July 9, 2002
    Inventor: Ronald M. Kubacki
  • Patent number: 6391219
    Abstract: A method for treating a film of material, which can be defined on a substrate, e.g., silicon. The method includes providing a substrate comprising a cleaved surface, which had a porous silicon layer thereon. The substrate may have a distribution of hydrogen bearing particles defined from the cleaved surface to a region underlying said cleaved surface. The method also includes increasing a temperature of the cleaved surface to greater than about 1,000 Degrees Celsius while maintaining the cleaved surface in a etchant bearing environment to reduce a surface roughness value by about fifty percent and greater. Preferably, the value can be reduced by about eighty or ninety percent and greater, depending upon the embodiment.
    Type: Grant
    Filed: July 30, 1999
    Date of Patent: May 21, 2002
    Assignee: Silicon Genesis Corporation
    Inventors: Sien G. Kang, Igor J. Malik
  • Patent number: 6383937
    Abstract: A method is disclosed for fabricating a semiconductor device structure which include a thin foot charge drain beneath the device on a silicon substrate. The structures retain high speed operation of SOI devices. In various embodiments, the invention includes forming a first diffusion-barrier layer on a semiconductor substrate, patterning the said first diffusion-barrier layer and the said silicon substrate to certain depth to form a trench, forming a second diffusion-barrier layer and patterning the said second diffusion-barrier layer to form a first spacer on the sidewall of the trench. Performing a directional etching to expose a portion of the sidewall of the trench. Introducing dopants into the said exposed sidewall to form a doped regions near the sidewall. Performing an isotropic etching using halogen gas plasma.
    Type: Grant
    Filed: November 17, 2000
    Date of Patent: May 7, 2002
    Assignee: Vanguard International Semiconductor Corp.
    Inventor: Horng-Huei Tseng
  • Patent number: 6379981
    Abstract: In one aspect, the invention includes a method of etching, comprising: a) forming a material over a substrate, the material comprising a lower portion near the substrate and an upper portion above the lower portion; b) providing a quantity of detectable atoms within the material, the detectable atoms being provided at a different concentration in the lower portion than in the upper portion; c) etching into the material and forming etching debris; and d) detecting the detectable atoms in the debris. In another aspect, the invention includes a method of etching, comprising: a) providing a semiconductor wafer substrate, the substrate having a center and an edge; b) forming a material over the substrate, the material comprising detectable atoms; c) etching into the material and forming etching debris; d) detecting the detectable atoms in the debris; and e) estimating a degree of center-to-edge uniformity of the etching from the detecting.
    Type: Grant
    Filed: March 27, 1998
    Date of Patent: April 30, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Terry Gilton
  • Patent number: 6368519
    Abstract: A magnetic gap is formed to be vertical to the film forming surface of a substrate with high accuracy by a simple method. The method comprises a non-magnetic film forming step of forming a non-magnetic film made of the non-magnetic material on the substrate, a high selectivity film forming step of forming a high selectivity film made of a material which has a higher selectivity ratio with respect to reactive ion etching than the non-magnetic material, on the non-magnetic film formed, a patterning step of patterning the high-selectivity film into a predetermined shape, and an etching step of etching the non-magnetic film by reactive ion etching, using the high selectivity film as a mask.
    Type: Grant
    Filed: December 9, 1999
    Date of Patent: April 9, 2002
    Assignee: Sony Corporation
    Inventors: Toru Katakura, Teiichi Miyauchi, Yuko Takanashi
  • Patent number: 6365525
    Abstract: The invention defines a method for fabricating a semiconductor insulation layer: A semiconductor substrate is first provided; an insulation layer is applied by way of region-by-region or whole-area application to the semiconductor substrate; impurity ions are selectively implanted into at least one predetermined zone of the insulation layer; then the insulation layer is selectively etched, and the insulation layer is thereby patterned in accordance with the zone or zones of the selectively implanted impurity ions.
    Type: Grant
    Filed: December 5, 2000
    Date of Patent: April 2, 2002
    Assignee: Siemens Aktiengesellschaft
    Inventor: Karlheinz Müller
  • Patent number: 6365235
    Abstract: A surface treatment method wherein one or more active particle streams are generated and aimed at a surface to be treated so that the particle stream interacts therewith. The active particle stream consists of activated particles forming chemically active sites on the surface, and modifying particles occupying said sites. The energy of the activated particles is greater than the energy at break of the inhibited surface bonds of the surface, and lower than the radiative flaw formation energy on the surface. The strength of the particle stream at the treated surface is greater than a quantity N/t where N is the surface density of the inhibited bonds to be broken and t is the duration of exposure of any point on the treated surface to the stream. A device for carrying out the method is also provided.
    Type: Grant
    Filed: May 13, 1998
    Date of Patent: April 2, 2002
    Assignee: TePla AG
    Inventors: Pavel Koulik, Evgenia Zorina
  • Patent number: 6344364
    Abstract: In one aspect, the invention includes a method of etching, comprising: a) forming a material over a substrate, the material comprising a lower portion near the substrate and an upper portion above the lower portion; b) providing a quantity of detectable atoms within the material, the detectable atoms being provided at a different concentration in the lower portion than in the upper portion; c) etching into the material and forming etching debris; and d) detecting the detectable atoms in the debris. In another aspect, the invention includes a method of etching, comprising: a) providing a semiconductor wafer substrate, the substrate having a center and an edge; b) forming a material over the substrate, the material comprising detectable atoms; c) etching into the material and forming etching debris; d) detecting the detectable atoms in the debris; and e) estimating a degree of center-to-edge uniformity of the etching from the detecting.
    Type: Grant
    Filed: August 23, 2000
    Date of Patent: February 5, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Terry Gilton
  • Patent number: 6344115
    Abstract: A pattern forming method using an improved charged particle beam process, and a charged particle beam processing system prevent effectively the corrosion of a workpiece by a reactive gas adsorbed by and adhering to the surface of the workpiece when the workpiece is taken out into the atmosphere after pattern formation. The charged particle beam processing system comprises, as principal components, an ion beam chamber provided with an ion beam optical system, a processing chamber provided with a gas nozzle through which a reactive gas is blown against a workpiece, a load-lock chamber connected through a gate valve to the processing chamber. The load-lock chamber is capable of producing a plasma of an inert gas for processing the surface of the workpiece by sputtering.
    Type: Grant
    Filed: October 13, 1999
    Date of Patent: February 5, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Junzou Azuma, Akira Shimase, Yuichi Hamamura, Hidemi Koike
  • Patent number: 6335290
    Abstract: In a method of etching an Al or Al alloy layer, an Al or Al alloy layer is formed on an underlying surface, the surface of the Al or Al alloy layer is processed with TMAH, a resist pattern is formed on the surface of the Al or Al alloy layer processed with TMAH, and by using the resist pattern as an etching mask, the Al or Al alloy layer is wet-etched.
    Type: Grant
    Filed: March 29, 1999
    Date of Patent: January 1, 2002
    Assignee: Fujitsu Limited
    Inventor: Yukimasa Ishida
  • Patent number: 6323046
    Abstract: A method and apparatus for endpointing a planarization process of a microelectronic substrate. In one embodiment, the apparatus may include a species analyzer that receives a slurry resulting from the planarization process and analyzes the slurry to determine the presence of an endpointing material implanted beneath the surface of the microelectronic substrate. The species analyzer may include a mass spectrometer or a spectrum analyzer. In another embodiment, the apparatus may include a radiation source that directs impinging radiation toward the microelectronic substrate, exciting atoms of the substrate, which in turn produce an emitted radiation. A radiation detector is positioned proximate to the substrate to receive the emitted radiation and determine the endpoint by determining the intensity of the radiation emitted by the endpointing material.
    Type: Grant
    Filed: August 25, 1998
    Date of Patent: November 27, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Vishnu K. Agarwal
  • Publication number: 20010037994
    Abstract: A method of manufacturing a compound layer, containing a nitrified metal as a major component thereof and having a predetermined microstructure pattern, includes: an ion implantation step for implanting hydrogen ions into a predetermined region of a compound layer formed on a substrate to form an implanted region; and an etching step for selectively etching the implanted region by using a gas containing at least oxygen, to remove the implanted region of the compound layer while maintaining the other region as a microstructure pattern. By introducing a halogen element like fluorine in addition to hydrogen, fabrication of the pattern can be executed more reliably and more easily. As a result, volatility of reaction products produced upon etching the compound layer is enhanced, and micro-loading effects are suppressed.
    Type: Application
    Filed: March 29, 2001
    Publication date: November 8, 2001
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Mizunori Ezaki
  • Patent number: 6313040
    Abstract: A process for etching a dielectric layer, including the steps of forming, over the dielectric layer, a layer of polysilicon, forming over the layer of polysilicon a photoresist mask layer, etching the layer of polysilicon using the photoresist mask layer as an etching mask for selectively removing the layer of polysilicon, removing the photoresist mask layer from over the layer of polysilicon, etching the dielectric layer using the layer of polysilicon as a mask. Subsequently, the layer of polysilicon is converted into a layer of a transition metal silicide, and the layer of transition metal silicide is etched for selectively removing the latter from over the dielectric layer.
    Type: Grant
    Filed: September 28, 1999
    Date of Patent: November 6, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Lorena Beghin, Francesca Canali, Francesco Cazzaniga, Luca Riva, Carmelo Romeo
  • Publication number: 20010023010
    Abstract: A substrate on which a plurality of thin films having a plurality of cross-sections corresponding to the cross-section of a micro-structure are formed is placed on a substrate holder. The substrate holder is elevated to bond a thin film formed on the substrate to the surface of a stage, and by lowering the substrate holder, the thin film is separated from the substrate and transferred to the stage side. The transfer process is repeated to laminate a plurality of thin films on the stage and to form the micro-structure. Accordingly, there are provided a micro-structure having high dimensional precision, especially high resolution in the lamination direction, which can be manufactured from a metal or an insulator such as ceramics and can be manufactured in the combined form of structural elements together, and a manufacturing method and an apparatus thereof.
    Type: Application
    Filed: February 26, 2001
    Publication date: September 20, 2001
    Applicant: Fuji Xerox Co. Ltd.
    Inventors: Takayuki Yamada, Mutsuya Takahashi, Masaki Nagata
  • Publication number: 20010010229
    Abstract: In one embodiment, the present invention relates to a method of processing a semiconductor structure, involving the steps of providing the semiconductor structure having a patterned resist thereon; stripping the patterned resist from the semiconductor structure, wherein an amount of carbon containing resist debris remain on the semiconductor structure; and contacting the semiconductor structure with ozone thereby reducing the amount of carbon containing resist debris thereon.
    Type: Application
    Filed: January 31, 2000
    Publication date: August 2, 2001
    Applicant: R. Subramanian
    Inventors: Ramkumar Subramanian, Khoi A. Phan, Bharath Rangarajan, Bhanwar Singh, Sanjay K. Yedur, Bryan K. Choo
  • Publication number: 20010006166
    Abstract: A method for removal of post reactive ion etch sidewall polymer rails on a Al/Cu metal line of a semiconductor or microelectronic composite structure comprising:
    Type: Application
    Filed: December 3, 1998
    Publication date: July 5, 2001
    Inventors: RAVIKUMAR RAMACHANDRAN, WESLEY NATZLE, MARTIN GUTSCHE, HIROYUKI AKATSU, CHIEN YU
  • Patent number: 6245249
    Abstract: A substrate on which a plurality of thin films having a plurality of cross-sections corresponding to the cross-section of a micro-structure are formed is placed on a substrate holder. The substrate holder is elevated to bond a thin film formed on the substrate to the surface of a stage, and by lowering the substrate holder, the thin film is separated from the substrate and transferred to the stage side. The transfer process is repeated to laminate a plurality of thin films on the stage and to form the micro-structure. Accordingly, there are provided a micro-structure having high dimensional precision, especially high resolution in the lamination direction, which can be manufactured from a metal or an insulator such as ceramics and can be manufactured in the combined form of structural elements together, and a manufacturing method and an apparatus thereof.
    Type: Grant
    Filed: April 22, 1998
    Date of Patent: June 12, 2001
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Takayuki Yamada, Mutsuya Takahashi, Masaki Nagata
  • Patent number: 6200903
    Abstract: A semiconductor device is manufactured by forming a thin layer over a semiconductor substrate, coating photoresist on the thin layer, forming a photoresist pattern over the semiconductor substrate, injecting ions into the photoresist pattern so as to harden the photoresist pattern, and etching the thin layer by using the hardened photoresist pattern as an etch mask. The hardened photoresist pattern has an increased etch selectivity with respect to an underlying layer, allowing the use of thinner photoresist layers and improved etching.
    Type: Grant
    Filed: September 20, 1999
    Date of Patent: March 13, 2001
    Assignee: Samsung Electronics, Co., Ltd.
    Inventors: Sang-kuen Oh, Sung-kyu Han, Yeon-sang Hwang, Dong-ha Lim, Jung-ki Kim
  • Patent number: 6197697
    Abstract: A method of patterning a brittle material, and particularly a semiconductor material, is provided comprising ion implantation induced selective area exfoliation. The method includes steps of masking the material, implanting unmasked regions of the material, with light ions of Hydrogen or Helium, and rapid thermal annealing at the temperature causing exfoliation of the material from the implanted regions. As a result, the material is patterned to a depth determined by the depth of ion implantation. The method allows patterning through crystalline or non-crystalline materials, or several layers of different materials at the same time. When the mask has straight sharp edges aligned parallel to natural cleavage planes of the semiconductor material, the exfoliation results in formation of high quality sidewall-facets of exfoliated material and of the remaining patterned material at the boundaries of exfoliated regions.
    Type: Grant
    Filed: August 19, 1999
    Date of Patent: March 6, 2001
    Assignee: Nortel Networks Limited
    Inventors: Todd William Simpson, Ian Vaughan Mitchell, Grantley Oliver Este, Frank Reginald Shepherd
  • Patent number: 6171966
    Abstract: An improved delineation pattern for epitaxial depositions is created by forming a mask on a single-crystal silicon substrate which leaves an area (10) of the substrate exposed, doping the area with a dopant to create a doped region defined by a periphery, anisotropically, vertically etching the doped region to create a delineation pattern corresponding to the periphery, and then forming an epitaxial layer over the substrate and doped region. The periphery of the delineation pattern has a squared-off delineation step including a first step wall generally perpendicular to the surface of the substrate and a second step wall generally parallel to the surface of the substrate. The squared-off delineation step helps prevent wash-out of the delineation pattern as one or more epitaxial layers are deposited on the substrate.
    Type: Grant
    Filed: August 15, 1996
    Date of Patent: January 9, 2001
    Assignee: Applied Materials, Inc.
    Inventors: Thomas E. Deacon, Norma B. Riley
  • Patent number: 6156668
    Abstract: A method for forming a fine pattern in a semiconductor device removes roughness from a pattern produced in a fine pattern fabrication process using a silylation process as being one kind of a TSI process, eliminates smoothly a photosensitive film residue caused by a residue silylation layer remained on a-non-pattern area, and increases a margin of a lithography process. To achieve the foregoing, the method performs an etching process with a fluorine/oxygen mixture gas so as to remove a thin oxide film being formed on the non-pattern area after a silylation process, enables an edge portion of a silylation region to be planarized so as to prevent the pattern from becoming rough, and forms a photosensitive film pattern by developing the photosensitive film with oxygen plasma. Thereafter, the photosensitive film residue is etched again with a mixture gas of fluorine/oxygen, thereby increasing a fabrication margin of the fine pattern.
    Type: Grant
    Filed: April 20, 1999
    Date of Patent: December 5, 2000
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Hyung Gi Kim, Myung Soo Kim, Cheol Kyu Bok, Ki Ho Baik, Dae Hoon Lee, Jin Woong Kim, Byung Jun Park
  • Patent number: 6136719
    Abstract: A method of fabricating a semiconductor wafer is disclosed.
    Type: Grant
    Filed: April 30, 1999
    Date of Patent: October 24, 2000
    Assignee: LSI Logic Corporation
    Inventors: Gayle W. Miller, Gail D. Shelton
  • Patent number: 6120875
    Abstract: The subject of the present invention is a solid material in the form of a microperforated sheet transparent to light of wavelengths in the visible and infrared, characterized in that the mean distance between two immediately neighbouring perforations is at least 5, and preferably 7 .mu.m, and is so over each face of the material. Preferably, the mean angle of inclination of the perforations through the thickness of the material is less than 10.degree., even 5.degree.. In a particular embodiment, the material is a membrane produced from a flexible polymer film with a thickness lying between 0.1 and 100 .mu.m, more generally between 5 and 50 .mu.m, and the perforation diameters lying between 0.01 and 15 .mu.m. The membranes obtained according to the invention are particularly useful as support membranes for viewing in an optical microscope or in infrared spectroscopy. They may also be used as filter membranes or, amongst other applications, as a support for cell culture.
    Type: Grant
    Filed: April 27, 1995
    Date of Patent: September 19, 2000
    Assignee: Cyclopore S.A.
    Inventors: Charles Haumont, Roger Legras
  • Patent number: 6120597
    Abstract: A method is provided for detaching a single-crystal film from an epilayer/substrate or bulk crystal structure. The method includes the steps of implanting ions into the crystal structure to form a damage layer within the crystal structure at an implantation depth below a top surface of the crystal structure, and chemically etching the damage layer to effect detachment the single-crystal film from the crystal structure. The method of the present invention is especially useful for detaching single-crystal metal oxide films from metal oxide crystal structures.
    Type: Grant
    Filed: February 17, 1998
    Date of Patent: September 19, 2000
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Miguel Levy, Richard M. Osgood, Jr.
  • Patent number: 6096459
    Abstract: A method of repairing quartz bump defects on an alternating phase shifting template such as a mask or reticle that includes the steps of locating a defect by either SEM scanning or low energy FIB scanning; directing a FIB at the bump defect, and irradiating the bump detect with high energy ions from the FIB. After the bump has been thoroughly stained with ions, the template is exposed to a strongly basic solution to remove the stained bump. Suitable bases include sodium hydroxide, potassium hydroxide, ammonium hydroxide, to tetramethyl ammonium hydroxide, and the like. According to this method, a quartz bump defect is removed with high precision and less damage to the substrate.
    Type: Grant
    Filed: December 28, 1998
    Date of Patent: August 1, 2000
    Assignee: Micron Technology, Inc.
    Inventor: Baorui Yang
  • Patent number: 6083771
    Abstract: A method and system for manufacturing theft-deterrent computer components is disclosed. Initially, computer components are grouped in a single batch. Each of the computer components are then provided with multiple indelible indicia during manufacturing. All of the indelible indicia on each component have a common value that is different than that assigned to any other computer component.
    Type: Grant
    Filed: February 17, 1998
    Date of Patent: July 4, 2000
    Assignee: International Business Machines Corporation
    Inventors: James Peter Ward, Richard Mark Flanagan, James Andrew McNee, Brian John Walsh
  • Patent number: 6074569
    Abstract: A method for stripping photoresist used as an etch mask in carbon based reactive ion etching includes flood exposing a patterned photoresist with a light and cyclically exposing the photoresist with an oxygen plasma in between the carbon based plasma. The step of cyclically exposing occurs after the step of flood exposing. The step of flood exposing includes the step of decomposing photosensitive compounds in the photoresist, while the step of cyclically exposing includes the step of cyclically removing layers of the photoresist.
    Type: Grant
    Filed: December 9, 1997
    Date of Patent: June 13, 2000
    Assignee: Hughes Electronics Corporation
    Inventors: Kursad Kiziloglu, Ming Hu
  • Patent number: 6066265
    Abstract: A microprobe having a mounting block and a silicon cantilever with an integral silicon tip is produced from a SOI wafer having a bottom layer of silicon substrate, a middle layer of insulating material, and a top layer of silicon substrate. The top layer is coated with a first layer of masking material. The bottom layer is masked and etched to form a bottom section of the mounting block. The middle layer provides an etch stop for precise control of the bottom layer etch. A tip mask is formed by partially etching the first layer of masking material. A front side mask is formed by further etching of the first layer. The front side mask defines a cantilever pattern and a top mounting block pattern. The cantilever pattern and the top mounting block pattern are transferred into the top layer by etching the top layer to a depth corresponding to a desired cantilever thickness. Further etching of the top layer forms a tip column and releases the cantilever and a top section of the mounting block from the top layer.
    Type: Grant
    Filed: June 19, 1996
    Date of Patent: May 23, 2000
    Assignee: Kionix, Inc.
    Inventors: Gregory J. Galvin, Timothy J. Davis
  • Patent number: 6045710
    Abstract: A manufacturing process for printing heads which operate using the coincident forces drop on demand printing principles. The print head integrates many nozzles into a single monolithic silicon structure. Semiconductor processing methods such as photolithography and chemical etching are used to simultaneously fabricate a multitude of nozzles into the monolithic head. The nozzles are etched through the silicon substrate, allowing two dimensional arrays of nozzles for color printing. The manufacturing process can be based on existing CMOS, nMOS and bipolar semiconductor manufacturing processes, allowing fabrication in existing semiconductor fabrication facilities. Drive transistors, shift registers, and fault tolerance circuitry can be fabricated on the same wafer as the nozzles. The manufacturing process uses anisotropic wet etching using KOH on a (110) wafer to form ink channels with vertical side-walls. Nozzle barrels are formed using the same etching process, using boron as an etch stop.
    Type: Grant
    Filed: December 4, 1996
    Date of Patent: April 4, 2000
    Inventor: Kia Silverbrook