Etching A Multiple Layered Substrate Where The Etching Condition Used Produces A Different Etching Rate Or Characteristic Between At Least Two Of The Layers Of The Substrate Patents (Class 216/72)
  • Patent number: 11756964
    Abstract: A method for etching an insulating layer includes: sequentially forming a first gate insulating layer, an amorphous silicon layer, a first interlayer insulating layer, and a second interlayer insulating layer on a substrate; applying a photoresist on the second interlayer insulating layer, and patterning the photoresist through a photo-process; first etching the second interlayer insulating layer and the first interlayer insulating layer until at least a portion of the amorphous silicon layer is exposed by using the patterned photoresist as a mask; second etching the second interlayer insulating layer and the first interlayer insulating layer; third etching the amorphous silicon layer; and fourth etching the first gate insulating layer, wherein an etching gas used in the second etching includes a material having a higher etching selection ratio of the first and second interlayer insulating layers to the amorphous silicon layer than an etching gas used in the first etching.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: September 12, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Dae Soo Kim, Yu-Gwang Jeong, Sung Won Cho
  • Patent number: 11631679
    Abstract: A method of forming a semiconductor device includes the following steps. First of all, a substrate is provided, and a dielectric layer is formed on the substrate. Then, at least one trench is formed in the dielectric layer, to partially expose a top surface of the substrate. The trench includes a discontinuous sidewall having a turning portion. Next, a first deposition process is performed, to deposit a first semiconductor layer to fill up the trench and to further cover on the top surface of the dielectric layer. Following these, the first semiconductor layer is laterally etched, to partially remove the first semiconductor layer till exposing the turning portion of the trench. Finally, a second deposition is performed, to deposit a second semiconductor layer to fill up the trench.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: April 18, 2023
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Luo-Hsin Lee, Ting-Pang Chung, Shih-Han Hung, Po-Han Wu, Shu-Yen Chan, Shih-Fang Tzou
  • Patent number: 10553438
    Abstract: A method for fabricating a semiconductor device includes stacking a semiconductor layer, a first sacrificial layer, and a second sacrificial layer, patterning the second sacrificial layer to form a second sacrificial pattern, forming a spacer pattern on both sides of the second sacrificial pattern, wherein a pitch of the spacer pattern is constant, and a width of the spacer pattern is constant, removing the second sacrificial pattern, forming a mask layer that covers the spacer pattern, forming a supporting pattern on the mask layer, wherein a width of the supporting pattern is greater than a width of the spacer pattern, and the supporting pattern is overlapped with the spacer pattern, transferring the supporting pattern and the spacer pattern onto the first sacrificial layer to form gate and supporting patterns, and transferring the gate and supporting patterns onto the semiconductor layer to form a gate and a supporting gate.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: February 4, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yun Kyeong Jang, Sang Jin Kim, Dong Woon Park, Joon Soo Park, Chang Jae Yang, Kwang Sub Yoon, Hye Kyoung Jue
  • Patent number: 10283368
    Abstract: There is provided a plasma etching method for etching a base film by a plasma using a photoresist as a mask. The method includes etching the base film by the plasma, under a first processing condition in which a selectivity of the photoresist to the base film is set to a first selectivity, while using as a mask the photoresist formed in a predetermined pattern by exposure and development and a scum remaining in the photoresist, without performing a process of removing the scum; and switching, during the etching of the base film, the first processing condition to a second processing condition in which the selectivity of the photoresist to the base film is set to a second selectivity lower than the first selectivity and further etching the base film by a plasma while using the photoresist as a mask under the second processing condition.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: May 7, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Shunichi Mikami
  • Patent number: 10155903
    Abstract: The present inventive concepts provide metal etchant compositions and methods of fabricating a semiconductor device using the same. The metal etchant composition includes an organic peroxide in a range of about 0.1 wt % to about 20 wt %, an organic acid in a range of about 0.1 wt % to about 70 wt %, and an alcohol-based solvent in a range of about 10 wt % to about 99.8 wt %. The metal etchant composition may be used in an anhydrous system.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: December 18, 2018
    Assignees: Samsung Electronics Co., Ltd., Cornell University
    Inventors: Hyosan Lee, Yongsun Ko, Kyoungseob Kim, Kuntack Lee, Jihoon Jeong, Chen Lin, Christopher K. Ober
  • Patent number: 10026614
    Abstract: A method for manufacturing a semiconductor device includes forming features of a first mold pattern on a substrate including a first region and a second region, and forming a first insulation layer covering the first mold pattern from the first region to the second region. The method further includes forming a photoresist pattern on the first insulation layer in the second region, forming a second insulation layer covering the first insulation layer in the first region and the photoresist pattern in the second region from the first region to the second region, etching the second insulation layer, removing the photoresist pattern, and forming a first double patterning technology pattern having a first width in the first region and a second DPT pattern having a second width in the second region, wherein the second width is different from the first width.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: July 17, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chan Sic Yoon, Ki Seok Lee, Dong Oh Kim
  • Patent number: 9818610
    Abstract: A method for treating a substrate is disclosed. The method includes forming a film stack on the substrate, the film stack comprising an underlying layer, a coating layer disposed above the underlying layer, and a patterning layer disposed above the coating layer. In the method, portions of the patterning layer are removed to form sidewalls of the patterning layer and expose portions of the coating layer, a carbon-containing layer is deposited on the exposed portions of the coating layer and non-sidewall portions of the patterning layer, and the carbon-containing layer and a portion of the coating layer are removed to expose other portions of the coating layer and the patterning layer. The method further includes repeating the deposition and removal of the carbon-coating layer at least until portions of the underlying layer are exposed.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: November 14, 2017
    Assignee: Tokyo Electron Limited
    Inventors: Hiroie Matsumoto, Andrew W. Metz, Yannick Feurprier, Katie Lutker-Lee
  • Patent number: 9735025
    Abstract: A method of etching a first region including a multilayered film, in which first dielectric films and second dielectric films serving as silicon nitride films are alternately stacked, and a second region including a single-layered silicon oxide film is provided. The etching method includes a first plasma process of generating plasma of a first processing gas containing a fluorocarbon gas and an oxygen gas within a processing vessel of a plasma processing apparatus; and a second plasma process of generating plasma of a second processing gas containing a hydrogen gas, nitrogen trifluoride gas and a carbon-containing gas within the processing vessel. A temperature of an electrostatic chuck is set to a first temperature in the first plasma process, and the temperature of the electrostatic chuck is set to a second temperature lower than the first temperature in the second plasma process.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: August 15, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Masayuki Sawataishi, Tomonori Miwa, Yuki Kaneko
  • Patent number: 9607834
    Abstract: A method for etching an antireflective coating on a substrate is disclosed. The substrate comprises an organic layer, an antireflective coating layer disposed above the organic layer, and a photoresist layer disposed above the antireflective coating layer. The method includes patterning the photoresist layer to expose a non-masked portion of the antireflective coating layer and selectively depositing a carbon-containing layer on the non-masked portions of the antireflective coating layer and on non-sidewall portions of the patterned photoresist layer. The method further includes etching the film stack to remove the carbon-containing layer and to remove a partial thickness of the non-masked portions of the antireflective coating layer without reducing a thickness of the photoresist layer.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: March 28, 2017
    Assignee: Tokyo Electron Limited
    Inventors: Hiroie Matsumoto, Andrew W. Metz, Yannick Feurprier, Katie Lutker-Lee
  • Patent number: 9039909
    Abstract: There is provided a plasma etching method for forming a hole in a silicon oxide film formed on an etching stopper layer. The plasma etching method includes a main etching process for etching the silicon oxide film; and an etching process that is performed when at least a part of the etching stopper layer is exposed after the main etching process. The etching process includes a first etching process using a gaseous mixture of a C4F6 gas, an Ar gas and an O2 gas as the processing gas; and a second etching process using a gaseous mixture of a C4F8 gas, an Ar gas and an O2 gas or a gaseous mixture of a C3F8 gas, an Ar gas and an O2 gas as the processing gas. The first etching process and the second etching process are alternately performed plural times.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: May 26, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Akira Nakagawa, Yuji Otsuka
  • Patent number: 9034770
    Abstract: A method of etching exposed silicon oxide on patterned heterogeneous structures is described and includes a gas phase etch created from a remote plasma etch. The remote plasma excites a fluorine-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents combine with water vapor. Reactants thereby produced etch the patterned heterogeneous structures to remove two separate regions of differing silicon oxide at different etch rates. The methods may be used to remove low density silicon oxide while removing less high density silicon oxide.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 19, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Seung H. Park, Yunyu Wang, Jingchun Zhang, Anchuan Wang, Nitin K. Ingle
  • Patent number: 9017571
    Abstract: A dry etching agent according to the present invention preferably contains: (A) 1,3,3,3-tetrafluoropropene; (B) at least one kind of additive gas selected from the group consisting of H2, O2, O3, CO, CO2, COCl2, COF2, CF3OF, NO2, F2, NF3, Cl2, Br2, I2, CH4, C2H2, C2H4, C2H6, C3H4, C3H6, C3H8, HF, HI, HBr, HCl, NO, NH3 and YFn (where Y represents Cl, Br or I; and n represents an integer satisfying 1?n?7); and (C) an inert gas. This dry etching agent has less effect on the global environment and can obtain a significant improvement in process window and address processing requirements such as low side etching ratio and high aspect ratio even without any special substrate excitation operation.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: April 28, 2015
    Assignee: Central Glass Company, Limited
    Inventors: Tomonori Umezaki, Yasuo Hibino, Isamu Mori, Satoru Okamoto, Akiou Kikuchi
  • Patent number: 8999856
    Abstract: A method of selectively etching silicon nitride from a substrate comprising a silicon nitride layer and a silicon oxide layer includes flowing a fluorine-containing gas into a plasma generation region of a substrate processing chamber and applying energy to the fluorine-containing gas to generate a plasma in the plasma generation region. The plasma comprises fluorine radicals and fluorine ions. The method also includes filtering the plasma to provide a reactive gas having a higher concentration of fluorine radicals than fluorine ions and flowing the reactive gas into a gas reaction region of the substrate processing chamber. The method also includes exposing the substrate to the reactive gas in the gas reaction region of the substrate processing chamber. The reactive gas etches the silicon nitride layer at a higher etch rate than the reactive gas etches the silicon oxide layer.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: April 7, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Jingchun Zhang, Anchuan Wang, Nitin Ingle
  • Patent number: 8992792
    Abstract: Methods of fabricating ultra low-k dielectric self-aligned vias are described. In an example, a method of forming a self-aligned via (SAV) in a low-k dielectric film includes forming a trench pattern in a metal nitride hardmask layer formed above a low-k dielectric film formed above a substrate. A via pattern is formed in a masking layer formed above the metal nitride hardmask layer. The via pattern is etched at least partially into the low-k dielectric film, the etching comprising using a plasma etch using a chemistry based on CF4, H2, and a diluent inert gas composition.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: March 31, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Chih-Yang Chang, Sean S. Kang, Chia-Ling Kao, Nikolaos Bekiaris
  • Patent number: 8987143
    Abstract: Methods and apparatus for processing using a remote plasma source are disclosed. The apparatus includes an outer chamber enclosing a substrate support, a remote plasma source, and a showerhead. A substrate heater can be mounted in the substrate support. A transport system moves the substrate support and is capable of positioning the substrate. The plasma system may be used to generate activated hydrogen species. The activated hydrogen species can be used to etch/clean semiconductor oxide surfaces such as silicon oxide or germanium oxide.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: March 24, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Ratsamee Limdulpaiboon, Chi-I Lang, Sandip Niyogi, J. Watanabe
  • Patent number: 8986493
    Abstract: When a substrate is etched by using a processing gas including a first gas containing halogen and carbon and having a carbon number of two or less per molecule, while supplying the processing gas toward the substrate independently from a central and a peripheral portion of a gas supply unit, which face the central and the periphery part of the substrate respectively, the processing gas is supplied such that a gas flow rate is greater in the central portion than in the peripheral portion. When the substrate is etched by using a processing gas including a second gas containing halogen and carbon and having a carbon number of three or more per molecule, the processing gas is supplied such that a gas flow rate is greater in the peripheral portion than in the central portion.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: March 24, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Shigeru Tahara, Masaru Nishino
  • Patent number: 8975190
    Abstract: A plasma processing method includes a surface improving step of improving a surface of the photoresist film by performing plasma processing using a hydrogen-containing gas as a processing gas and an etching step of etching the SiON film by performing plasma processing using a processing gas including a gas containing a CHF-based gas and a chlorine-containing gas while using as a mask the photoresist film having the improved surface.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: March 10, 2015
    Assignee: Tokyo Electron Limited
    Inventor: Ryoichi Yoshida
  • Publication number: 20150041434
    Abstract: The invention relates to a method for separating a metal part from a ceramic part, which are joined at a connecting face within a modular hybrid component, especially of a gas turbine. The method includes said component being subjected to a reducing atmosphere in a gaseous process at elevated temperatures to dissolve the connection between said metal part and said ceramic part, especially by dissolving the ceramic part itself.
    Type: Application
    Filed: September 24, 2014
    Publication date: February 12, 2015
    Inventors: Daniel BECKEL, Alexander Stankowski, Sophie Betty Claire Duval
  • Patent number: 8937021
    Abstract: In some embodiments, methods for forming a three dimensional NAND structure include providing to a process chamber a substrate having alternating nitride layers and oxide layers or alternating polycrystalline silicon consisting layers and oxide layers formed atop the substrate and a photoresist layer formed atop the alternating layers; etching the photoresist layer to expose at least a portion of the alternating layers; providing a process gas comprising sulfur hexafluoride and oxygen to the process chamber; providing RF power of about 4 kW to about 6 kW to a first inductive RF coil and a second inductive RF coil disposed proximate the process chamber to ignite the process gas to form a plasma, wherein a current flowing through the first inductive RF coil is out of phase with RF current flowing through the second inductive RF coil; and etching through a desired number of the alternating layers to form a feature.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: January 20, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Han Soo Cho, Sang Wook Kim, Joo Won Han, Kee Young Cho, Anisul H. Khan
  • Patent number: 8921232
    Abstract: A method of taper-etching a layer to be etched that is made of a dielectric material and has a top surface. The method includes the steps of: forming an etching mask with an opening on the top surface of the layer to be etched; and taper-etching a portion of the layer to be etched, the portion being exposed from the opening, by reactive ion etching so that a groove having two wall faces intersecting at a predetermined angle is formed in the layer to be etched. The step of taper-etching employs an etching gas containing a first gas contributing to the etching of the layer to be etched and a second gas contributing to the deposition of a sidewall protective film, and changes, during the step, the ratio of the flow rate of the second gas to the flow rate of the first gas so that the ratio increases.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: December 30, 2014
    Inventors: Hironori Araki, Yoshitaka Sasaki, Hiroyuki Ito, Shigeki Tanemura
  • Patent number: 8906810
    Abstract: An all-in-one trench-over-via etch wherein etching of a low-k material beneath a metal hard mask of titanium nitride containing material is carried out in alternating steps of (a) etching the low-k material while maintaining chuck temperature at about 45 to 80° C. and (b) metal hard mask rounding and Ti-based residues removal while maintaining chuck temperature at about 90 to 130° C.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: December 9, 2014
    Assignee: Lam Research Corporation
    Inventors: Ananth Indrakanti, Bhaskar Nagabhirava, Alan Jensen, Tom Choi
  • Patent number: 8900468
    Abstract: A method includes forming a hydrophilic guide layer, a DBARC layer and a photoresist film. A portion of the photoresist film and DBARC layer is exposed to form exposed and unexposed portions. The unexposed photoresist film is removed to form a photoresist pattern including the exposed photoresist film portion. A neutral layer is formed on the photoresist pattern. The photoresist pattern and the DBARC layer of the exposed portion are removed to form first opening portions exposing the guide layer. A block copolymer layer includes a block copolymer having first and second polymer blocks coated on the neutral layer while filling the first opening portions. The block copolymer layer is microphase separated to form a pattern layer including first and second patterns. A pattern including one polymer block is removed to form a pattern mask. The object layer is etched to form a pattern including second opening portions.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: December 2, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-Sung Kim, Jae-Woo Nam, Chul-Ho Shin, Shi-Yong Yi
  • Patent number: 8901005
    Abstract: Embodiments of the invention may include first providing a stack of layers including a semiconductor substrate, a buried oxide layer on the semiconductor substrate, a semiconductor-on-insulator layer on the buried-oxide layer, a nitride layer on the semiconductor-on-insulator layer, and a silicon oxide layer on the nitride layer. A first opening and second opening with a smaller cross-sectional area than the first opening are then formed in the silicon oxide layer, the nitride layer, the semiconductor-on-insulator layer, and the buried-oxide layer. The first opening and the second opening are then etched with a first etching gas. The first opening and the second opening are then etched with a second etching gas, which includes the first etching gas and a halogenated silicon compound, for example, silicon tetrafluoride or silicon tetrachloride. In one embodiment, the first etching gas includes hydrogen bromide, nitrogen trifluoride, and oxygen.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Habib Hichri, Xi Li, Richard Wise
  • Patent number: 8894871
    Abstract: The present invention relates to a lithography method using tilted evaporation, and includes: (1) coating a resist on top of a substrate; (2) patterning the resist using a lithography process; (3) tilt-evaporating a first thin film material on an upper layer of the patterned resist to form a modified pattern mask; (4) evaporating a second thin film material on the top of the substrate with the modified pattern mask; and (5) removing the resist coated on the top of the substrate.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: November 25, 2014
    Assignee: Korea Research Institute of Bioscience and Biotechnology
    Inventors: Yong Beom Shin, Seung Woo Lee
  • Patent number: 8889024
    Abstract: A plasma etching method that can improve an etching selection ratio of a film to be etched to a film different from the film to be etched compared with the related art is provided. The present invention provides a plasma etching method for selectively etching a film to be etched against a film different from the film to be etched, in which plasma etching of the film to be etched is performed using a gas that can cause to generate a deposited film containing similar components as components of the different film.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: November 18, 2014
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Tomoyuki Watanabe, Michikazu Morimoto, Mamoru Yakushiji, Tetsuo Ono
  • Patent number: 8877646
    Abstract: A method of manufacturing a plurality of spacers in a film stack includes forming at least one electrically-conductive element having sidewalls on a substrate, depositing a plurality of passivation layers proximate to the substrate, and performing etching on one of the plurality of passivation layers to form a plurality of spacers substantially across from the sidewalls of the at least one electrically-conductive element.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: November 4, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Valerie J Marty, Galen P. Cook
  • Patent number: 8845909
    Abstract: A process of fabricating a heat dissipation substrate is provided. A metal substrate having an upper surface, a lower surface, first recesses located on the upper surface and second recesses located on the lower surface is provided. The metal substrate is divided into carrier units and connecting units connecting the carrier units. A first and a second insulating materials are respectively filled into the first and the recesses. A first conductive layer is formed on the upper surface and the first insulating material. A second conductive layer is formed on the lower surface and the second insulating material. The first and the second conductive layers are patterned to form a first and a second patterned conductive layers. The first and the second insulating materials are taken as an etching mask to etch the connecting units of the metal substrate so as to form a plurality of individual heat dissipation substrates.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: September 30, 2014
    Assignee: Subtron Technology Co., Ltd.
    Inventor: Tzu-Shih Shen
  • Patent number: 8828248
    Abstract: Write heads may be formed by reactive ion etching (RIE) a dielectric mask and then reactive ion etching a polymeric underlayer. The first RIE affects the second RIE. The first portion of the first RIE process is performed with a ratio of CF4 to CHF3 between about 1.3 to 2, a gas flow ratio of CF4 to He between 2.2 and about 3, and a ratio of RF source power to RF bias power between about 10 and about 16. The second portion of the first RIE process is performed with a ratio of CF4 to CHF3 between about 0.3 to 0.8, a gas flow ratio of CF4 to He between about 1.2 and about 1.8, and a ratio of RF source power to RF bias between about 22 to 28. With the above parameters, the dielectric mask can be formed with minimized damage on the underlayer.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: September 9, 2014
    Assignee: HGST Netherlands B.V
    Inventors: Guomin Mao, Satyanarayana Myneni, Aron Pentek, Xiaoye Zhao
  • Patent number: 8795790
    Abstract: [Problem] An object is to provide a magnetic recording medium with improved HDI characteristics, such as impact resistance, and its manufacturing method. [Solution] A typical structure of a magnetic recording medium 100 according to the present invention includes, on a base, at least a magnetic recording layer 122, a protective layer 126, and a lubricating layer 128, wherein the magnetic recording layer 122 includes, in an in-plane direction, a magnetic recording part 136 configured of a magnetic material and a non-recording part 134 magnetically separating the magnetic recording part 136, and a surface corresponding to the non-recording part 134 protuberates more than a surface corresponding to the magnetic recording part 136.
    Type: Grant
    Filed: December 9, 2009
    Date of Patent: August 5, 2014
    Assignee: WD Media (Singapore) Pte. Ltd.
    Inventors: Yoshiaki Sonobe, Akira Shimada, Tsuyoshi Ozawa, Masanori Aniya
  • Patent number: 8778195
    Abstract: A method to fabricate an imprint mould in three dimensions including at least: a) forming at least one trench, of width W and depth h, in a substrate, thereby forming three surfaces including, a bottom of the at least one trench, sidewalls of the at least one trench, and a remaining surface of the substrate, called top of the substrate; b) forming alternate layers in the at least one trench, each having at least one portion perpendicular to the substrate, in a first material and in a second material which can be selectively etched relative to the first material; and c) selectively etching said portions of the layers perpendicular to the substrate.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: July 15, 2014
    Assignee: Commissariat a l' Energie Atomique
    Inventor: Stéfan Landis
  • Patent number: 8771536
    Abstract: A method of etching exposed silicon-and-carbon-containing material on patterned heterogeneous structures is described and includes a remote plasma etch formed from a fluorine-containing precursor and an oxygen-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the exposed regions of silicon-and-carbon-containing material. The plasmas effluents react with the patterned heterogeneous structures to selectively remove silicon-and-carbon-containing material from the exposed silicon-and-carbon-containing material regions while very slowly removing other exposed materials. The silicon-and-carbon-containing material selectivity results partly from the presence of an ion suppression element positioned between the remote plasma and the substrate processing region. The ion suppression element reduces or substantially eliminates the number of ionically-charged species that reach the substrate.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: July 8, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Jingchun Zhang, Anchuan Wang, Nitin K. Ingle, Yunyu Wang, Young Lee
  • Patent number: 8764952
    Abstract: In a method of irradiating a gas cluster ion beam on a solid surface and smoothing the solid surface, the angle formed between the solid surface and the gas cluster ion beam is chosen to be between 1° and an angle less than 30°. In case the solid surface is relatively rough, the processing efficiency is raised by first irradiating a beam at an irradiation angle ? chosen to be something like 90° as a first step, and subsequently at an irradiation angle ? chosen to be 1° to less than 30° as a second step. Alternatively, the set of the aforementioned first step and second step is repeated several times.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: July 1, 2014
    Assignee: Japan Aviation Electronics Industry Limited
    Inventors: Akinobu Sato, Akiko Suzuki, Emmanuel Bourelle, Jiro Matsuo, Toshio Seki, Takaaki Aoki
  • Patent number: 8759227
    Abstract: A method for processing a target object includes arranging a first electrode and a second electrode for supporting the target object in parallel to each other in a processing chamber and processing the target object supported by the second electrode by using a plasma of a processing gas supplied into the processing chamber, the plasma being generated between the first electrode and the second electrode by applying a high frequency power between the first electrode and the second electrode. The target object includes an organic film and a photoresist layer formed on the organic film. The processing gas contains H2 gas, and the organic film is etched by a plasma containing H2 by using the photoresist layer as a mask while applying a negative DC voltage to the first electrode.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: June 24, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Kazuki Narishige, Kazuo Shigeta
  • Patent number: 8741166
    Abstract: A plasma etching method that can improve an etching selection ratio of a film to be etched to a film different from the film to be etched compared with the related art is provided. The present invention provides a plasma etching method for selectively etching a film to be etched against a film different from the film to be etched, in which plasma etching of the film to be etched is performed using a gas that can cause to generate a deposited film containing similar components as components of the different film.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: June 3, 2014
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Tomoyuki Watanabe, Michikazu Morimoto, Mamoru Yakushiji, Tetsuo Ono
  • Patent number: 8735296
    Abstract: A method of forming multiple different width dimension features simultaneously. The method includes forming multiple sidewall spacers of different widths formed from different combinations of conformal layers on different mandrels, removing the mandrels, and simultaneously transferring the pattern of the different sidewall spacers into an underlying layer.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: May 27, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ryan O. Jung, Sivananda K. Kanakasabapathy
  • Patent number: 8722547
    Abstract: Wafers having a high K dielectric layer and an oxide or nitride containing layer are etched in an inductively coupled plasma processing chamber by applying a source power to generate an inductively coupled plasma, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be between 100° C. and 350° C., and etching the wafer with a selectivity of high K dielectric to oxide or nitride greater than 10:1. Wafers having an oxide layer and a nitride layer are etched in a reactive ion etch processing chamber by applying a bias power to the wafer, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be between 20° C. and 200° C., and etching the wafer with an oxide to nitride selectivity greater than 10:1.
    Type: Grant
    Filed: April 17, 2007
    Date of Patent: May 13, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Radhika Mani, Nicolas Gani, Wei Liu, Meihua Shen, Shashank C. Deshmukh
  • Patent number: 8715515
    Abstract: A sequence of process steps having balanced process times are implemented in sequence of etch chambers coupled linearly and isolated one from the other, resulting in the optimization of island to trench ratio for a patterned media. A biased chemical etching using active etching gas is used to descum and trim the resist patterns. An inert gas sputter etch is performed on the magnetic layers, resulting in the patterned magnetic layer on the disk. A final step of stripping is then performed to remove the residual capping resist and carbon hard mask on top of un-etched magnetic islands. The effective magnetic material remaining on the disk surface can be optimized by adjusting the conditions of chemical etch and sputter etch conditions. Relevant process conditions that may be adjusted include: pressure, bias, time, and the type of gas in each step.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: May 6, 2014
    Assignee: Intevac, Inc.
    Inventors: Houng T. Nguyen, Ren Xu, Michael S. Barnes
  • Patent number: 8703003
    Abstract: In a method of vapor etching, a sample that includes a first layer atop of and in contact with a second layer which is atop of and in contact with a third layer, wherein at least the first and second layers are comprised of different materials. The sample is etched by a vapor etchant under first process conditions that cause at least a part of the first layer to be fully removed while leaving the third layer and the second layer underlying the removed part of the first layer substantially unetched. The sample is then etched by the same or a different vapor etchant under second process conditions that cause at least the part of the second layer exposed by the removal of the at least part of the first layer to be fully removed while leaving the third layer underlying the removed part of the second layer substantially unetched.
    Type: Grant
    Filed: April 20, 2010
    Date of Patent: April 22, 2014
    Assignee: SPTS Technologies Limited
    Inventors: Kyle S. Lebouitz, David L. Springer, John J. Neumann, Jr.
  • Patent number: 8679358
    Abstract: A plasma etching method includes a preparation process for performing a plasma etching process using a processing gas including a first processing gas containing carbon (C) and fluorine (F), a ratio (C/F) of the first processing gas having a first value, and obtaining a residual amount of the mask layer corresponding to a variation point where a variation amount of the bowing CD is increased; a first plasma etching process using the processing gas including the first processing gas until a residual amount of the mask layer reaches the variation point; and a second plasma etching process performed after the first plasma etching process. The second plasma etching process is performed by using a processing gas including at least a second processing gas containing carbon (C) and fluorine (F), and a ratio (C/F) of the second processing gas is smaller than the first value.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: March 25, 2014
    Assignee: Tokyo Electron Limited
    Inventor: Akira Nakagawa
  • Patent number: 8679985
    Abstract: A dry etching method for a silicon nitride film capable of improving throughput is provided. A dry etching method for dry-etching a silicon nitride film 103 includes dry-etching the silicon nitride film 103 without generating plasma by using a processing gas containing at least a hydrogen fluoride gas (HF gas) and a fluorine gas (F2 gas), with respect to a processing target object 100 including the silicon nitride film 103.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: March 25, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Eiichi Nishimura, Yusuke Shimizu
  • Patent number: 8668837
    Abstract: A method for etching a substrate includes etching at least one first layer of the substrate with a non-uniform substrate temperature and etching at least one second layer of the substrate with uniform substrate temperatures.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: March 11, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Kenny Linh Doan, Jong Mun Kim
  • Patent number: 8652342
    Abstract: A semiconductor fabrication apparatus and a method of fabricating a semiconductor device using the same performs semiconductor etching and deposition processes at an edge of a semiconductor substrate after disposing the semiconductor substrate at a predetermined place in the semiconductor fabrication apparatus. The semiconductor fabrication apparatus has lower, middle and upper electrodes sequentially stacked. The semiconductor substrate is disposed on the middle electrode. Semiconductor etching and deposition processes are performed on the semiconductor substrate in the semiconductor fabrication apparatus. The semiconductor fabrication apparatus forms electrical fields along an edge of the middle electrode during performance of the semiconductor etching and deposition processes.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: February 18, 2014
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Kyung-Woo Lee, Jin-Sung Kim, Joo-Byoung Yoon, Yeong-Cheol Lee, Sang-Jun Park, Hee-Kyeong Jeon
  • Patent number: 8647981
    Abstract: Some embodiments include methods of forming a pattern. First lines are formed over a first material, and second lines are formed over the first lines. The first and second lines form a crosshatch pattern. The first openings are extended through the first material. Portions of the first lines that are not covered by the second lines are removed to pattern the first lines into segments. The second lines are removed to uncover the segments. Masking material is formed between the segments. The segments are removed to form second openings that extend through the masking material to the first material. The second openings are extended through the first material. The masking material is removed to leave a patterned mask comprising the first material having the first and second openings therein. In some embodiments, spacers may be formed along the first and second lines to narrow the openings in the crosshatch pattern.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: February 11, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Vishal Sipani
  • Patent number: 8632687
    Abstract: The invention relates to a method for electron beam induced etching of a layer contaminated with gallium, with the method steps of providing at least one first halogenated compound as an etching gas at the position at which an electron beam impacts on the layer, and providing at least one second halogenated compound as a precursor gas for removing of the gallium from this position.
    Type: Grant
    Filed: August 11, 2009
    Date of Patent: January 21, 2014
    Assignee: Carl Zeiss SMS GmbH
    Inventors: Nicole Auth, Petra Spies, Rainer Becker, Thorsten Hofmann, Klaus Edinger
  • Patent number: 8628677
    Abstract: Processes for making a profile-transferring substrate surface and membranes having curved features are disclosed. A profile-transferring substrate surface having a curved feature is created by isotropic plasma etching through a shadow mask. The shadow mask has a through hole which has a lower portion adjacent to the bottom surface of the shadow mask and an upper portion that is above and narrower than the lower portion. The isotropic plasma etching through the shadow mask can create a curved dent in a planar substrate in a central portion of an area enclosed by the bottom opening. After the shadow mask is removed. A uniform layer of material deposited over the exposed surface of the substrate will include a curved feature at the location of the curved dent in the substrate surface.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: January 14, 2014
    Assignee: FUJIFILM Corporation
    Inventors: Gregory De Brabander, Mark Nepomnishy
  • Patent number: 8617406
    Abstract: The invention relates to a device for the actively-controlled deposition of microdrops of biological solutions. The inventive device includes at least one flat silicon lever comprising a central body and an end area which forms a point, a slit or groove being disposed in said point. The invention is characterized in that it also comprises at least one metallic track which is disposed on one face of the central body and which runs alongside said slit or groove at least partially. The invention also relates to a method of producing the inventive device and a method for the active-controlled deposition and sampling of microdrops of biological solutions using said device.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: December 31, 2013
    Assignee: Centre National de la Recherche Scientifique
    Inventors: Christian Bergaud, Matthieu Guirardel, Pascal Belaubre, Benoit Belier, Jean-Bernard Pourciel
  • Patent number: 8598043
    Abstract: The invention includes methods of forming isolation regions for semiconductor constructions. A hard mask can be formed and patterned over a semiconductor substrate, with the patterned hard mask exposing a region of the substrate. Such exposed region can be etched to form a first opening having a first width. The first opening is narrowed with a conformal layer of carbon-containing material. The conformal layer is punched through to expose substrate along a bottom of the narrowed opening. The exposed substrate is removed to form a second opening which joins to the first opening, and which has a second width less than the first width. The carbon-containing material is then removed from within the first opening, and electrically insulative material is formed within the first and second openings. The electrically insulative material can substantially fill the first opening, and leave a void within the second opening.
    Type: Grant
    Filed: September 20, 2010
    Date of Patent: December 3, 2013
    Assignee: Micron Technology Inc.
    Inventors: Ramakanth Alapati, Ardavan Niroomand, Gurtej S. Sandhu, Luan C. Tran
  • Patent number: 8591755
    Abstract: A time-dependent substrate temperature to be applied during a plasma process is determined. The time-dependent substrate temperature at any given time is determined based on control of a sticking coefficient of a plasma constituent at the given time. A time-dependent temperature differential between an upper plasma boundary and a substrate to be applied during the plasma process is also determined. The time-dependent temperature differential at any given time is determined based on control of a flux of the plasma constituent directed toward the substrate at the given time. The time-dependent substrate temperature and time-dependent temperature differential are stored in a digital format suitable for use by a temperature control device defined and connected to direct temperature control of the upper plasma boundary and the substrate. A system is also provided for implementing upper plasma boundary and substrate temperature control during the plasma process.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: November 26, 2013
    Assignee: Lam Research Corporation
    Inventor: Rajinder Dhindsa
  • Patent number: 8580131
    Abstract: It is an object of the present invention to provide a plasma etching method that can improve a selection ratio of a film to be etched to a film different from the film to be etched than that in the related art. The present invention provides a plasma etching method for selectively etching a film to be etched with respect to another film different from the film to be etched, the plasma etching method including etching, using gas that can generate a deposited film containing components same as components of the another film different from the film to be etched, the film on which generation of the deposited film is suppressed.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: November 12, 2013
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Tomoyuki Watanabe, Mamoru Yakushiji, Michikazu Morimoto, Tetsuo Ono
  • Patent number: 8541313
    Abstract: A method of etching a sacrificial layer for a micro-machined structure, the sacrificial layer positioned between a layer of a first material and a layer of a second material, the etching being carried out by an etching agent. The method includes: providing at least one species having an affinity for the etching agent greater than that of the layers of first material and second material and less than or equal to that of the sacrificial layer; and then etching the sacrificial layer by the etching agent, the etching being carried out to eliminate at least partially the sacrificial layer and then to eliminate at least partially the species.
    Type: Grant
    Filed: October 25, 2006
    Date of Patent: September 24, 2013
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Stéphan Borel, Jeremy Bilde