Etching A Multiple Layered Substrate Where The Etching Condition Used Produces A Different Etching Rate Or Characteristic Between At Least Two Of The Layers Of The Substrate Patents (Class 216/72)
  • Patent number: 6824697
    Abstract: Three fundamental and three derived aspects of the present invention are disclosed. The three fundamental aspects each disclose a process sequence that may be integrated in a full process. The first aspect, designated as “latent masking”, defines a mask in a persistent material like silicon oxide that is held abeyant after definition while intervening processing operations are performed. The latent oxide pattern is then used to mask an etch. The second aspect, designated as “simultaneous multi-level etching (SMILE)”, provides a process sequence wherein a first pattern may be given an advanced start relative to a second pattern in etching into an underlying material, such that the first pattern may be etched deeper, shallower, or to the same depth as the second pattern. The third aspect, designated as “delayed LOCOS”, provides a means of defining a contact hole pattern at one stage of a process, then using the defined pattern at a later stage to open the contact holes.
    Type: Grant
    Filed: November 2, 2001
    Date of Patent: November 30, 2004
    Assignee: Kionix, Inc.
    Inventors: James E. Moon, Timothy J. Davis, Gregory J. Galvin, Kevin A. Shaw, Paul C. Waldrop, Sharlene A. Wilson
  • Patent number: 6818140
    Abstract: A high plasma density etch process for etching an oxygen-containing layer overlying a non-oxygen containing layer on a workpiece in a plasma reactor chamber, by providing a chamber ceiling overlying the workpiece and containing a semiconductor material, supplying into the chamber a process gas containing etchant precursor species, polymer precursor species and hydrogen, applying plasma source power into the chamber, and cooling the ceiling to a temperature range at or below about 150 degrees C. The etchant and polymer precursor species contain fluorine, and the chamber ceiling semiconductor material includes a fluorine scavenger precursor material. Preferably, the process gas includes at least one of CHF3 and CH2F2. Preferably, the process gas further includes a species including an inert gas, such as HeH2 or Ar. If the chamber is of the type including a heated fluorine scavenger precursor material, this material is heated to well above the polymer condensation temperature, while the ceiling is cooled.
    Type: Grant
    Filed: October 31, 2001
    Date of Patent: November 16, 2004
    Inventor: Jian Ding
  • Publication number: 20040224264
    Abstract: A method for etching a feature in a layer is provided. An underlayer of a polymer material is formed over the layer. A top image layer is formed over the underlayer. The top image layer is exposed to patterned radiation. A pattern is developed in the top image layer. The pattern is transferred from the top image layer to the underlayer with a reducing dry etch. The layer is etched through the underlayer, where the top image layer is completely removed and the underlayer is used as a pattern mask during the etching the layer to transfer the pattern from the underlayer to the layer.
    Type: Application
    Filed: May 9, 2003
    Publication date: November 11, 2004
    Applicant: Lam Research Corporation
    Inventors: Hanzhong Xiao, Helen H. Zhu, Kuo-Lung Tang, S.M. Reza Sadjadi
  • Patent number: 6810577
    Abstract: The present invention provides a method of efficiently manufacturing a dielectric waveguide with high reliability and precision. In the method, a resist material is formed on the outer surface of a green compact provided with a removal inhibiting layer, and predetermined portion of the green compact defined by the resist material is removed by the sand blasting method using the resist material as a mask, until the removal inhibiting layer is exposed to obtain a shaped green compact structure. The thus-obtained structure is fired to obtain a sintered body which comprises a dielectric strip and a wing.
    Type: Grant
    Filed: February 25, 2003
    Date of Patent: November 2, 2004
    Assignee: Murata Manufacturing Co. Ltd.
    Inventor: Toshikazu Takeda
  • Patent number: 6806035
    Abstract: A serialization process presents an efficient method of creating serial numbers on a ceramic-like semiconductor wafer by forming a non-rigid photomask that incorporates character specifications for the serial numbers. The non-rigid photomask is retained in a rigid, optically transparent photomask holder that enables the photomask to be handled as a rigid structure. Upon preparation of the wafer, the serial numbers are created onto wafer dies using a combined process involving photolithography, and a reactive ion etching process with a selective etch rate. The serialization process enables a rapid creation of serial numbers, with the selective RIE process substantially increasing the optical contrast of the characters without the need for deep trenches and without generation of excessive debris.
    Type: Grant
    Filed: June 25, 2002
    Date of Patent: October 19, 2004
    Assignee: Western Digital (Fremont), Inc.
    Inventors: Thanawatana Atireklapvarodom, Richard D. Anderson
  • Patent number: 6800213
    Abstract: An oxide etching recipe including a heavy hydrogen-free fluorocarbon having F/C ratios less than 2, preferably C4F6, an oxygen-containing gas such as O2 or CO, a lighter fluorocarbon or hydrofluorocarbon, and a noble diluent gas such as Ar or Xe. The amounts of the first three gases are chosen such that the ratio (F—H)/(C—O) is at least 1.5 and no more than 2. Alternatively, the gas mixture may include the heavy fluorocarbon, carbon tetrafluoride, and the diluent with the ratio of the first two chosen such the ratio F/C is between 1.5 and 2.
    Type: Grant
    Filed: June 7, 2002
    Date of Patent: October 5, 2004
    Inventors: Ji Ding, Hidehiro Kojiri, Yoshio Ishikawa, Keiji Horioka, Ruiping Wang, Robert W. Wu, Hoiman (Raymond) Hung
  • Patent number: 6797189
    Abstract: A plasma etching process, particularly useful for selectively etching oxide over a feature having a non-oxide composition, such as silicon nitride and especially when that feature has a corner that is prone to faceting during the oxide etch. A primary fluorine-containing gas, preferably hexafluorobutadiene (C4F6), is combined with a significantly larger amount of the diluent gas xenon (Xe) enhance nitride selectivity without the occurrence of etch stop. The chemistry is also useful for etching oxides in which holes and corners have already been formed, for which the use of xenon also reduces faceting of the oxide. For this use, the relative amount of xenon need not be so high. The invention may be used with related heavy fluorocarbons and other fluorine-based etching gases.
    Type: Grant
    Filed: March 25, 1999
    Date of Patent: September 28, 2004
    Inventors: Hoiman (Raymond) Hung, Joseph P. Caulfield, Hongqing Shan, Michael Rice, Kenneth S Collins, Chunshi Cui
  • Patent number: 6790788
    Abstract: A method is provided for processing a substrate including providing a processing gas comprising hydrogen gas and an organosilicon compound comprising a phenyl group to the processing chamber, and reacting the processing gas to deposit a low k silicon carbide barrier layer useful as a barrier layer in damascene or dual damascene applications with low k dielectric materials.
    Type: Grant
    Filed: January 13, 2003
    Date of Patent: September 14, 2004
    Assignee: Applied Materials Inc.
    Inventors: Lihua Li, Tzu-Fang Huang, Li-Qun Xia
  • Patent number: 6787054
    Abstract: A process for etching a substrate and removing etch residue deposited on the surfaces in the etching chamber has two stages. In the first stage, an energized first process gas is provided in the chamber, and in the second stage, an energized second process gas is provided in the chamber. The energized first process gas comprises SF6 and Ar, the volumetric flow ratio of SF6 to other components of the first process gas being from about 5:1 to about 1:10. The energized second process gas comprises CF4 and Ar, the volumetric flow ratio of CF4 to other components of the second process gas being from about 1:0 to about 1:10.
    Type: Grant
    Filed: February 3, 2003
    Date of Patent: September 7, 2004
    Inventors: Xikun Wang, Scott Williams, Shaoher X. Pan
  • Patent number: 6783874
    Abstract: First electrode layers are formed on second antiferromagnetic layers, and in a step separate from the above, second electrode layers are formed above internal end surfaces of the second antiferromagnetic layers and the first electrode layers and parts of the upper surface of the multilayer film with an additional film provided therebetween. Since the first and the second electrode layers are formed separately, it is not necessary to perform mask alignment twice, and hence an overlap structure can be precisely formed in which the thickness of the second electrode layer at the left side is equivalent to that at the right side.
    Type: Grant
    Filed: April 2, 2003
    Date of Patent: August 31, 2004
    Assignee: Alps Electric Co., Ltd.
    Inventors: Naoya Hasegawa, Eiji Umetsu, Naohiro Ishibashi, Masahiro Oshima
  • Patent number: 6780342
    Abstract: A processing gas constituted of CH2F2, O2 and Ar is introduced into a processing chamber 102 of a plasma processing apparatus 100. The flow rate ratio of the constituents of the processing gas is set at CH2F2/O2/Ar=20 sccm/10 sccm/100 sccm. The pressure inside the processing chamber 102 is set at 50 mTorr. 500 W high frequency power with its frequency set at 13.56 Mz is applied to a lower electrode 108 on which a wafer W is placed. The processing gas is raised to plasma and thus, an SiNx layer 206 formed on a Cu layer 204 is etched. The exposed Cu layer 204 is hardly oxidized and C and F are not injected into it.
    Type: Grant
    Filed: January 11, 2002
    Date of Patent: August 24, 2004
    Assignee: Tokyo Electron Limited
    Inventors: Masaaki Hagihara, Koichiro Inazawa, Wakako Naito
  • Patent number: 6780336
    Abstract: Three fundamental and three derived aspects of the present invention are disclosed. The three fundamental aspects each disclose a process sequence that may be integrated in a full process. The first aspect, designated as “latent masking”, defines a mask in a persistent material like silicon oxide that is held abeyant after definition while intervening processing operations are performed. The latent oxide pattern is then used to mask an etch. The second aspect, designated as “simultaneous multi-level etching (SMILE)”, provides a process sequence wherein a first pattern may be given an advanced start relative to a second pattern in etching into an underlying material, such that the first pattern may be etched deeper, shallower, or to the same depth as the second pattern. The third aspect, designated as “delayed LOCOS”, provides a means of defining a contact hole pattern at one stage of a process, then using the defined pattern at a later stage to open the contact holes.
    Type: Grant
    Filed: November 2, 2001
    Date of Patent: August 24, 2004
    Inventors: James E. Moon, Timothy J. Davis, Gregory J. Galvin, Kevin A. Shaw, Paul C. Waldrop, Sharlene A. Wilson
  • Publication number: 20040137372
    Abstract: The direct-write pulsed UV laser technique combined with the variable laser exposure fabrication method entails the precise variation of the laser irradiance during pattern formation in the photostructurable glass for variable laser exposing processing. The variable laser exposure patterning utilizes the dependence of the chemical etching rate on the controlled laser exposure dose for forming variable laser irradiated and crystallized regions of the exposed glass, that have variable etch rates that are dependent on the laser irradiance, resulting in the formation of high and low aspect ratio features in a common substrate that are realized during a single, maskless etch step.
    Type: Application
    Filed: January 15, 2003
    Publication date: July 15, 2004
    Inventors: Frank E. Livingston, Henry Helvajian
  • Patent number: 6756317
    Abstract: Various methods for forming surface micromachined microstructures are disclosed. One aspect relates to executing surface micromachining operation to structurally reinforce at least one structural layer in a microstructure. Another aspect relates to executing the surface micromachining operation to form a plurality of at least generally laterally extending etch release channels within a sacrificial material to facilitate the release of the corresponding microstructure.
    Type: Grant
    Filed: April 23, 2001
    Date of Patent: June 29, 2004
    Assignee: MEMX, Inc.
    Inventors: Jeffry J. Sniegowski, M. Steven Rodgers
  • Patent number: 6719915
    Abstract: A method of forming a relief image in a structure comprising a substrate and a transfer layer formed thereon comprises covering the transfer layer with a polymerizable fluid composition, and then contacting the polymerizable fluid composition with a mold having a relief structure formed therein such that the polymerizable fluid composition fills the relief structure in the mold. The polymerizable fluid composition is subjected to conditions to polymerize polymerizable fluid composition and form a solidified polymeric material therefrom on the transfer layer. The mold is then separated from the solid polymeric material such that a replica of the relief structure in the mold is formed in the solidified polymeric material; and the transfer layer and the solidified polymeric material are subjected to an environment to selectively etch the transfer layer relative to the solidified polymeric material such that a relief image is formed in the transfer layer.
    Type: Grant
    Filed: July 19, 2001
    Date of Patent: April 13, 2004
    Assignee: Board of Regents, The University of Texas System
    Inventors: Carlton Grant Willson, Matthew Earl Colburn
  • Patent number: 6716571
    Abstract: A process for forming sub-lithographic features in an integrated circuit is disclosed herein. The process includes modifying a photoresist layer after patterning and development but before it is utilized to pattern the underlying layers. The modified photoresist layer has different etch rates in the vertical and horizontal directions. The modified photoresist layer is trimmed with a plasma etch. A feature included in the trimmed photoresist layer has a sub-lithographic lateral dimension.
    Type: Grant
    Filed: March 28, 2001
    Date of Patent: April 6, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Calvin T. Gabriel, Harry J. Levinson, Uzodinma Okoroanyanwu
  • Patent number: 6712983
    Abstract: A method of etching a trench in a substrate using a dry plasma etch technique that allows precise control of lateral undercut. The method includes optionally forming at least one on-chip device or micro-machined structure in a surface of a silicon substrate, and covering the surface with a masking layer. A trench pattern is then imaged in or transferred to the masking layer for subsequent etching of the substrate. Upper portions of the trench are anisotropically etched in the substrate. The trench is then semi-anisotropically etched and isotropically etched in the substrate. By modifying isotropic etching time, a controlled lateral undercut can be achieved as the trench is etched vertically in the substrate.
    Type: Grant
    Filed: April 12, 2001
    Date of Patent: March 30, 2004
    Assignee: Memsic, Inc.
    Inventors: Yang Zhao, Yaping Hua
  • Patent number: 6689283
    Abstract: A dry etching is performed using a mask made of a titanium nitride under a reaction gas of a carbon monoxide with an additive of a nitrogen containing compound gas.
    Type: Grant
    Filed: March 26, 2001
    Date of Patent: February 10, 2004
    Assignee: TDK Corporation
    Inventors: Kazuhiro Hattori, Kenji Uchiyama
  • Patent number: 6686296
    Abstract: A method of etching an organic antireflective film layer underlying a patterned resist layer on a semiconductor substrate by contacting the exposed organic film with a fluorocarbon and nitrogen etchant in the presence of a plasma-generated energy and removing exposed areas of the organic film with the etchant. An oxide layer underlying the organic film layer is substantially undamaged after contact with the etchant. The plasma is a high density plasma and preferably contains argon, C4F8, and nitrogen.
    Type: Grant
    Filed: November 28, 2000
    Date of Patent: February 3, 2004
    Assignee: International Business Machines Corp.
    Inventors: Gregory Costrini, Peter D. Hoh, Richard S. Wise, Wendy Yan
  • Patent number: 6682657
    Abstract: A method of forming three-dimensional structures on a substrate by a single reactive ion each run whereby a mask is formed on said substrate before a series of iterations are carried out, each iteration including a mask etch and a substrate etch, so that successive iterations give life to reduction in the mask area and exposure of further areas of substrate.
    Type: Grant
    Filed: July 7, 1998
    Date of Patent: January 27, 2004
    Assignee: Qinetiq Limited
    Inventors: David T Dutton, Anthony B Dean
  • Patent number: 6669858
    Abstract: A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications. A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide. The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects.
    Type: Grant
    Filed: November 5, 2001
    Date of Patent: December 30, 2003
    Assignee: Applied Materials Inc.
    Inventors: Claes H. Bjorkman, Min Melissa Yu, Hongquing Shan, David W. Cheung, Wai-Fan Yau, Kuowei Liu, Nasreen Gazala Chapra, Gerald Yin, Farhad K. Moghadam, Judy H. Huang, Dennis Yost, Betty Tang, Yunsang Kim
  • Publication number: 20030230551
    Abstract: An etching system for subjecting a single film to be etched to etching comprised of a plurality of etching steps applying respective different recipes. The etching system comprises a recipe generating means which fixes the recipe to be applied to the final etching step affecting an underlying film making contact with the film to be etched, of the etching steps, to a preset recipe and which generates a recipe to be applied to the residual etching step on the basis of the results of processing, and etching processing is conducted according to the recipes generated by the recipe generating means.
    Type: Application
    Filed: August 21, 2002
    Publication date: December 18, 2003
    Inventors: Akira Kagoshima, Motohiko Yoshigai, Hideyuki Yamamoto, Daisuke Shiraishi, Junichi Tanaka, Kenji Tamaki, Natsuyo Morioka
  • Patent number: 6664026
    Abstract: An etch barrier to be used in a photolithograph process is disclosed. A silicon rich etch barrier is deposited on a substrate using a low energy deposition technique. A diamond like carbon layer is deposited on the silicon rich etch barrier. Photoresist is then placed on this etch barrier DLC combination. To form photolithographic features, successive steps of oxygen and flourine reactive ion etching is used.
    Type: Grant
    Filed: March 22, 2001
    Date of Patent: December 16, 2003
    Assignee: International Business Machines Corporation
    Inventors: Son Van Nguyen, Neil Leslie Robertson, Thomas Edward Dinan, Thao Duc Pham
  • Patent number: 6660647
    Abstract: A surface processing method of a sample having a mask layer that does not contain carbon as a major component formed on a substance to be processed, the substance being a metal, semiconductor and insulator deposited on a silicon substrate, includes the steps of installing the sample on a sample board in a vacuum container, generating a plasma that consists of a mixture of halogen gas and adhesive gas inside the vacuum container, applying a radio frequency bias voltage having a frequency ranging from 200 kHz to 20 MHz on the sample board, and controlling a periodic on-off of the radio frequency bias voltage with an on-off control frequency ranging from 100 Hz to 10 kHz.
    Type: Grant
    Filed: January 11, 2001
    Date of Patent: December 9, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Tetsuo Ono, Takafumi Tokunaga, Tadashi Umezawa, Motohiko Yoshigai, Tatsumi Mizutani, Tokuo Kure, Masayuki Kojima, Takashi Sato, Yasushi Goto
  • Publication number: 20030211753
    Abstract: Disclosed herein is a method of etching a trench in silicon overlying a dielectric material which reduces or substantially eliminates notching at the base of the trench, while reducing scalloping on the sidewalls of the trench. The method comprises etching a first portion of a trench by exposing a silicon substrate, through a patterned masking layer, to a plasma generated from a fluorine-containing gas. This etching is followed by a polymer deposition step comprising exposing the substrate to a plasma generated from a gas which is capable of forming a polymer on etched silicon surfaces. The etching and polymer deposition steps are repeated for a number of cycles, depending on the desired depth of the first portion of the trench. The final portion of the trench is etched by exposing the silicon to a plasma generated from a combination of a fluorine-containing gas and a polymer-forming gas.
    Type: Application
    Filed: May 9, 2002
    Publication date: November 13, 2003
    Inventors: Padmapani C. Nallan, Ajay Kumar, Anisul H. Khan, Chan-Syun David Yang
  • Publication number: 20030205556
    Abstract: A process to form a capillary that is well insulated from its environment is described. Said process has two stages. The first stage, which is the same for both of the invention's two embodiments, comprises forming a micro-channel in the surface of a sheet of glassy material. For the first embodiment, this sheet is bonded to a layer of oxide, that lies on the surface of a sheet of silicon, thereby sealing in the capillary. After all silicon has been selectively removed, a thin membrane of oxide remains. Using a low temperature bonding process, a second sheet of glassy material is then bonded to this membrane. In the second embodiment, the silicon is not fully removed. Instead, the oxide layer of the first embodiment is replaced by an oxide/nitride/oxide trilayer which provides improved electrical insulation between the capillary and the remaining silicon at a lower level of inter-layer stress.
    Type: Application
    Filed: May 2, 2002
    Publication date: November 6, 2003
    Applicant: Institute of Microelectronics
    Inventors: Yu Chen, Janak Singh
  • Patent number: 6638441
    Abstract: A method for pitch reduction is disclosed. The method can form a pattern with a pitch ⅓ the original pitch formed by available photolithography technologies by only using one photo mask or one pattern transfer process, self-aligned etching back processes, and conventional deposition processes. By choosing appropriate layers to be deposited and etched, the pattern can be an etching mask or it can be a device structure itself.
    Type: Grant
    Filed: January 7, 2002
    Date of Patent: October 28, 2003
    Assignee: Macronix International Co., Ltd.
    Inventors: Ching-Yu Chang, Wei-Ming Chung
  • Patent number: 6623652
    Abstract: A method of altering the topography of a trailing edge or ABS of a slider is disclosed, the slider having a substrate surface, at least one magnetic recording head on top of the alumina, and an overcoat of a material, preferably SiO2. The steps include first applying an SiO2 overcoat at the wafer level followed by slicing the wafer into rows, then lapping the rows. The rows are then placed on a bias electrode, exposing the trailing edge to a plasma generated from a controlled source in a reactive ion etching process. The plasma is generated using an chemical etchant such as CHF3 and other F-containing compounds, the plasma being generated with a combination of an inert gas such as Argon and the chemical etchant. In the plasma, the electrode is charged to accelerate the plasma ions towards the exposed surface. Reacted material is drawn from the surface of the slider. The SiO2 trailing edge reacts preferentially with the plasma, thus effectuating a change in the trailing edge topography.
    Type: Grant
    Filed: June 14, 2000
    Date of Patent: September 23, 2003
    Assignee: International Business Machines Corporation
    Inventors: Richard Hsiao, Cherngye Hwang, Hugo Alberto Emilio Santini
  • Patent number: 6623653
    Abstract: A method has been provided for etching adjoining layers of indium tin oxide (ITO) and silicon in a single, continuous dry etching process. A conventional dry etching gas, such as HI, is used to etch ITO using RF or plasma energy. When the silicon layer underlying the ITO layer is reached, oxygen or nitrogen is added to etching gas to improve the selectivity of ITO to silicon. In some aspects of the invention an etch-stop layer is formed in the silicon layer. A specific example of fabricating a bottom gate thin film transistor (TFT) is also provided where adjoining layers of source metal, ITO, and channel silicon are etched in the same dry etch step.
    Type: Grant
    Filed: June 12, 2001
    Date of Patent: September 23, 2003
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Gaku Furuta, Apostolos Voutsas
  • Publication number: 20030173333
    Abstract: A process for etching a substrate and removing etch residue deposited on the surfaces in the etching chamber has two stages. In the first stage, an energized first process gas is provided in the chamber, and in the second stage, an energized second process gas is provided in the chamber. The energized first process gas comprises SF6 and Ar, the volumetric flow ratio of SF6 to other components of the first process gas being from about 5:1 to about 1:10. The energized second process gas comprises CF4 and Ar, the volumetric flow ratio of CF4 to other components of the second process gas being from about 1:0 to about 1:10.
    Type: Application
    Filed: February 3, 2003
    Publication date: September 18, 2003
    Applicant: Applied Materials, Inc.
    Inventors: Xikun Wang, Scott Williams, Shaoher X. Pan
  • Patent number: 6613243
    Abstract: A method of producing surface features in a substrate includes steps of forming a film having a composition that varies in the direction of its thickness on the substrate, forming a mask on the heterogeneous film, etching the film to thereby pattern the film, and etching the structure that includes the patterned film to erode the film and correspondingly shape the substrate as the film is so being eroded. In this way, the pattern of the film is transferred to the substrate in a manner dependent on the selectivity of one or both of the etching processes as well as the thickness of the discrete mask layers, or in the case of a continuously graded film, the “slope” of the stoichiometric change with respect to position in the overall thickness of the film.
    Type: Grant
    Filed: July 25, 2001
    Date of Patent: September 2, 2003
    Assignee: Shipley Company, L.L.C.
    Inventor: Neal Ricks
  • Patent number: 6613691
    Abstract: An oxide etching process, particular useful for selectively etching oxide over a feature having a non-oxide composition, such as silicon nitride and especially when that feature has a corner that is prone to faceting during the oxide etch. The invention preferably uses the unsaturated 4-carbon fluorocarbons, specifically hexafluorobutadiene (C4F6), which has a below 10°C. and is commercially available. The hexafluorobutadiene together with argon is excited into a high-density plasma in a reactor which inductively couples plasma source power into the chamber and RF biases the pedestal electrode supporting the wafer. Preferably, a two-step etch is used process is used in which the above etching gas is used in the main step to provide a good vertical profile and a more strongly polymerizing fluorocarbon such as difluoromethane (CH2F2) is added in the over etch to protect the nitride corner.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: September 2, 2003
    Assignee: Applied Materials, Inc.
    Inventors: Raymond Hung, Joseph P. Caulfield, Hongching Shan, Ruiping Wang, Gerald Z. Yin
  • Patent number: 6613434
    Abstract: The invention concerns a method for treating a surface for the protection and functionalisation of polymers (4) by gas plasma deposit in a confined chamber (10) of one or several silicon alloy layers (43). The silicon alloy is selected among silicon and its oxides, nitrides, oxynitrides; the deposit is performed at a temperature less than the degradation temperature of the polymer, and a physico—chemical surface pre-treatment by plasma is performed in the same chamber before the silicon alloy is deposited; the pre-treatment consisting in a surface treatment comprising etching a surface zone of the polymer and step which consists in depositing a polymeric carbon compound.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: September 2, 2003
    Assignee: Centre National de la Recherche Scientifique
    Inventors: Bernard Drevillon, Pavel Bulkine, Alfred Franz Hofrichter
  • Patent number: 6607675
    Abstract: We have discovered a method for plasma etching a carbon-containing silicon oxide film which provides excellent etch profile control, a rapid etch rate of the carbon-containing silicon oxide film, and high selectivity for etching the carbon-containing silicon oxide film preferentially to an overlying photoresist masking material. When the method of the invention is used, a higher carbon content in the carbon-containing silicon oxide film results in a faster etch rate, at least up to a carbon content of 20 atomic percent. In particular, the carbon-containing silicon oxide film is plasma etched using a plasma generated from a source gas comprising NH3 and CxFy. It is necessary to achieve the proper balance between the relative amounts of NH3 and CxFy in the plasma source gas in order to provide a balance between etch by-product polymer deposition and removal on various surfaces of the substrate being etched.
    Type: Grant
    Filed: August 29, 2000
    Date of Patent: August 19, 2003
    Assignee: Applied Materials Inc.
    Inventors: Chang Lin Hsieh, Hui Chen, Jie Yuan, Yan Ye
  • Patent number: 6605226
    Abstract: A method is disclosed for speeding workpiece thoughput in low pressure, high temperature semiconductor processing reactor. The method includes loading a workpiece into a chamber at atmospheric pressure, bringing the chamber down to an intermediate pressure, and heating the wafer while under the intermediate pressure. The chamber is then pumped down to the operating pressure. The preferred embodiments involve single wafer plasma ashers, where a wafer is loaded onto lift pins at a position above a wafer chuck, the pressure is rapidly pumped down to about 40 Torr by rapidly opening and closing an isolation valve, and the wafer is simultaneously lowered to the heated chuck. Alternatively, the wafer can be pre-processed to remove an implanted photoresist crust at a first temperature and the chamber then backfilled to about 40 Torr for further heating to close to the chuck temperature. At 40 Torr, the heat transfer from the chuck to the wafer is relatively fast, but still slow enough to avoid thermal shock.
    Type: Grant
    Filed: June 10, 2002
    Date of Patent: August 12, 2003
    Assignee: Matrix Integrated Systems, Inc.
    Inventors: Albert Wang, Scott Baron, Prasad Padmanabhan, Gerald M. Cox
  • Patent number: 6605540
    Abstract: The invention describes a method for forming a dual damascene structure. An etch stop layer (150) is formed on a dielectric layer (140). A second dielectric layer (160) is formed on the etch stop layer (150) and an ARC layer (170) is formed the second dielectric layer. A first trench (185) and a second trench (195) are then simultaneously formed in the first and second dielectric layers (140) and (160) respectively.
    Type: Grant
    Filed: July 9, 2001
    Date of Patent: August 12, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Abbas Ali, Ming Yang
  • Patent number: 6602434
    Abstract: An oxide etching process, particularly useful for selectively etching oxide over a feature having a non-oxide composition, such as silicon nitride and especially when that feature has a corner that is prone to faceting during the oxide etch. One aspect of the invention uses one of four hydrogen-free fluorocarbons having a low F/C ratio, specifically hexafluorobutadiene (C4F6), octafluoropentadiene (C5F8), hexafluorocyclobutene (C4F6), and hexafluorobenzene (C6F6). At least hexafluorobutadiene has a boiling point below 10° C. and is commercially available. Another aspect of the invention, uses an unsaturated fluorocarbon such as pentafluoropropylene (C3HF5), and trifluoropropyne (C3HF3), both of which have boiling points below 10° C. and are commercially available.
    Type: Grant
    Filed: November 15, 1999
    Date of Patent: August 5, 2003
    Assignee: Applied Materials, Inc.
    Inventors: Hoiman (Raymond) Hung, Joseph P. Caulfield, Hongqing Shan, Ruiping Wang, Gerald Z. Yin
  • Patent number: 6599437
    Abstract: A two-step method of etching an organic coating layer, in particular, an organic antireflection coating (ARC) layer, is disclosed. During the main etch step, the organic coating layer is etched using a plasma generated from a first source gas which includes a fluorocarbon and a non-carbon-containing, halogen-comprising gas. Etching is performed using a first substrate bias power. During the overetch step, residual organic coating material remaining after the main etch step is removed by exposing the substrate to a plasma generated from a second source gas which includes a chlorine-containing gas and an oxygen-containing gas, and which does not include a polymer-forming gas. The overetch step is performed using a second substrate bias power which is less than the first substrate bias power.
    Type: Grant
    Filed: March 20, 2001
    Date of Patent: July 29, 2003
    Assignee: Applied Materials Inc.
    Inventors: Oranna Yauw, Meihua Shen, Nicolas Gani, Jeffrey D. Chinn
  • Publication number: 20030127422
    Abstract: A method for SAC etching is provided involving a) etching a Si wafer having a nitride present thereon with a first etching gas containing a first perfluorocarbon and carbon monoxide, and b) etching the resultant Si wafer having an initially etched nitride photoresist thereon with a second etching gas containing a second perfluorocarbon in the substantial absence of carbon monoxide, wherein the etching steps a) and b) are performed at high RF power and low pressure compared to conventional processes to provide higher selectivity etching and a larger process window for SAC etching, as well as the ability to perform SAC etching and island contact etching under the same conditions with high verticality of the island contact and SAC walls.
    Type: Application
    Filed: October 30, 2002
    Publication date: July 10, 2003
    Inventor: Kazuo Tsuchiya
  • Publication number: 20030127429
    Abstract: Disclosed is a method for forming fine grooves capable of forming stably a pattern in order of Å without requiring an expensive device and accomplishing high density of disc land & grooves.
    Type: Application
    Filed: December 17, 2002
    Publication date: July 10, 2003
    Inventor: Masaru Ohgaki
  • Patent number: 6589715
    Abstract: A process for etching a PPMS layer that increases the etch selectivity of PPMS relative to PPMSO from an initial low etch selectivity to a higher etch selectivity at a later stage of the etching process. In some embodiments, the etch selectivity used during a first etching step of the process is less than 4:1 and the etch selectivity used during a second etching step, subsequent to the first step, is greater than 5:1. In some other embodiments, the etch selectivity of the first step is between 2-3:1 and the etch selectivity of the second step is greater than 8:1. Optionally, in still other embodiments a third etching step, performed between the first and second etching steps may be employed where the etch selectivity is between 3-8:1.
    Type: Grant
    Filed: March 15, 2001
    Date of Patent: July 8, 2003
    Assignees: France Telecom, Applied Materials, Inc.
    Inventors: Olivier Joubert, Cedric Monget, Timothy Weidman, Dian Sugiarto, David Mui
  • Publication number: 20030121888
    Abstract: An etching method of the invention includes: an arranging step of arranging an object to be processed in a processing chamber, the object to be processed having a silicon oxide film and a silicon nitride film, the silicon oxide film being covered by the silicon nitride film; and an etching step of generating plasma of an etching gas in the processing chamber to etch the silicon nitride film of the object to be processed. A mixture gas including CH3F gas and O2 gas is used as the etching gas in the etching step. The essential feature of the invention is that a mixture ratio of the O2 gas with respect to the CH3F gas in the mixture gas (O2/CH3F) is set to be 4 to 9.
    Type: Application
    Filed: December 2, 2002
    Publication date: July 3, 2003
    Inventor: Kenji Adachi
  • Patent number: 6582617
    Abstract: Provided is a method of etching an etch layer using a polycarbonate layer as a mask. The method includes placing an etch structure in a reaction chamber, the etch structure including an etch layer underlying a polycarbonate layer, the polycarbonate layer having apertures. The etch layer is then etched using a low-pressure high density plasma generate at a pressure in the range of approximately 1 to 30 millitorr where the ionized particle concentration is at least 1011 ions/cm3 and where the ionized particle concentration is substantially equal throughout the volume of the reaction chamber. To increase the etch rate, the etch structure can be cooled or biased. To decrease the etch rate, an inert gas can be added to the process gas mixture used to form the plasma.
    Type: Grant
    Filed: April 29, 1999
    Date of Patent: June 24, 2003
    Assignee: Candescent Technologies Corporation
    Inventor: Chungdee Pong
  • Patent number: 6576152
    Abstract: In a dry etching method for etching a structure obtained by successively depositing, on a substrate, a gate insulating film, a silicon base film, a tungsten film or an alloy film containing tungsten, the dry etching includes a first process of dry-etching the tungsten film or the alloy film including tungsten, and a second process of dry-etching the silicon base film, and the first process employs, as an etching gas, a gas mixture obtained by mixing O2 gas into a gas including at least C and F, with the flow ratio of the O2 gas being 10˜50% by volume percentages. This dry etching method realizes highly-precise dry etching by which a vertical configuration of the poly-metal structure is obtained, and the selection ratio of W with respect to poly-Si can be controlled and, moreover, penetration through the underlying gate oxide film is prevented.
    Type: Grant
    Filed: July 6, 2001
    Date of Patent: June 10, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Tetsuya Matsutani
  • Patent number: 6572782
    Abstract: Recycling process for CdTe/CdS thin film-solar cell modules in which the modules are mechanically disintegrated into module fragments, the module fragments are exposed to an oxygen-containing atmosphere at a temperature of at least 300° C. causing a pyrolysis of adhesive material contained in the module fragments in form of a hydrocarbon based plastics material and the gaseous decomposition products that are generated during the pyrolysis are discharged, and, afterwards, the module fragments freed from the adhesive means are exposed to a chlorine-containing gas atmosphere at a temperature of more than 400° C. causing an etching process wherein the CdCl2 and TeCl4 that are generated in the etching process are made to condense and precipitate by cooling.
    Type: Grant
    Filed: August 24, 2001
    Date of Patent: June 3, 2003
    Assignee: ANTEC Solar GmbH
    Inventors: Manuel Diequez Campo, Dieter Bonnet, Rainer Gegenwart, Jutta Beier
  • Publication number: 20030098289
    Abstract: A method of forming an optical component is disclosed. The method includes obtaining an optical component precursor having a first medium positioned over a base and converting a portion of the first medium to a second medium. The method further includes removing a portion of the second medium so as to form a ridge in the second medium. The portion of the second medium is removed so as to expose a portion of the first medium.
    Type: Application
    Filed: November 29, 2001
    Publication date: May 29, 2003
    Inventors: Dawei Zheng, Yiqiong Wang, Dazeng Feng, Xiaoming Yin
  • Patent number: 6568067
    Abstract: The present invention provides a method of efficiently manufacturing a dielectric waveguide with high reliability and precision. In the method, a resist material is formed on the outer surface of a green compact provided with a removal inhibiting layer, and predetermined portion of the green compact defined by the resist material is removed by the sand blasting method using the resist material as a mask, until the removal inhibiting layer is exposed to obtain a shaped green compact structure. The thus-obtained structure is fired to obtain a sintered body which comprises a dielectric strip and a wing.
    Type: Grant
    Filed: February 9, 2001
    Date of Patent: May 27, 2003
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Toshikazu Takeda
  • Publication number: 20030092279
    Abstract: This invention relates to a method of forming a dual damascene via, in particular to a method of forming a dual damascene via by using a metal hard mask layer. The present invention uses a metal layer to be a hard mask layer to make the surface of the isolation layer become a level and smooth surface and not become a rounding convex and to prevent the via being connected with others vias to cause the leakage defects after forming the shape of the via.
    Type: Application
    Filed: November 13, 2001
    Publication date: May 15, 2003
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Teng-Chun Tsai, Chia-Lin Hsu
  • Patent number: 6558563
    Abstract: A thermal head fabricating method forms a lower protective layer made of ceramics for protecting a plurality of heat-generating resistors and electrodes, subjects the lower protective layer to etching processing by a plasma and forms a carbon protective layer on the thus subjected lower protective layer. The etching processing is performed using a mask which defines an area where the carbon protective layer is formed, a protective layer is formed on a surface of the mask, and the protective layer is made of a material which is etched at an extremely slow rate or substantially not etched compared with ceramics composing the lower protective layer and/or which does not impart an adverse effect to the carbon protective layer that is subsequently formed.
    Type: Grant
    Filed: April 2, 2001
    Date of Patent: May 6, 2003
    Assignee: Fuji Photo Film Co., Ltd.
    Inventors: Makoto Kashiwaya, Junji Nakada
  • Patent number: 6552256
    Abstract: A multi-stage cooler is formed from monolithically integrated thermionic and thermoelectric coolers, wherein the thermionic and thermoelectric coolers each have a separate electrical connection and a common ground, thereby forming a three terminal device. The thermionic cooler is comprised of a superlattice barrier surrounded by cathode and anode layers grown onto an appropriate substrate, one or more metal contacts with a finite surface area deposited on top of the cathode layer, and one or more mesas of different areas formed by etching around the contacts to the anode layer. The thermoelectric cooler is defined by metal contacts deposited on the anode layer or the substrate itself. A backside metal is deposited on the substrate for connecting to the common ground.
    Type: Grant
    Filed: March 6, 2001
    Date of Patent: April 22, 2003
    Assignee: The Regents of the University of California
    Inventors: Ali Shakouri, Christopher J. LaBounty, John E. Bowers