Etching A Multiple Layered Substrate Where The Etching Condition Used Produces A Different Etching Rate Or Characteristic Between At Least Two Of The Layers Of The Substrate Patents (Class 216/72)
  • Patent number: 7807579
    Abstract: An oxygen-free hydrogen plasma ashing process particularly useful for low-k dielectric materials based on hydrogenated silicon oxycarbide materials. The main ashing step includes exposing a previously etched dielectric layer to a plasma of hydrogen and optional nitrogen, a larger amount of water vapor, and a yet larger amount of argon or helium. Especially for porous low-k dielectrics, the main ashing plasma additionally contains a hydrocarbon gas such as methane. The main ashing may be preceded by a short surface treatment by a plasma of a hydrogen-containing reducing gas such as hydrogen and optional nitrogen.
    Type: Grant
    Filed: April 19, 2007
    Date of Patent: October 5, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Chan-Syun Yang, Changhun Lee
  • Patent number: 7767106
    Abstract: Provided is a dry etching method for an oxide semiconductor film containing at least In, Ga, and Zn, which includes etching an oxide semiconductor film in a gas atmosphere containing a halogen-based gas.
    Type: Grant
    Filed: July 10, 2007
    Date of Patent: August 3, 2010
    Assignee: Canon Kabushiki Kaisha
    Inventor: Chienliu Chang
  • Patent number: 7749915
    Abstract: A method of protecting a polymeric layer from contamination by a photoresist layer. The method includes: (a) forming a polymeric layer over a substrate; (b) forming a non-photoactive protection layer over the polymeric layer; (c) forming a photoresist layer over the protection layer; (d) exposing the photoresist layer to actinic radiation and developing the photoresist layer to form a patterned photoresist layer, thereby exposing regions of the protection layer; (e) etching through the protection layer and the polymeric layer where the protection layer is not protected by the patterned photoresist layer; (f) removing the patterned photoresist layer in a first removal process; and (g) removing the protection layer in a second removal process different from the first removal process.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: July 6, 2010
    Assignee: International Business Machines Corporation
    Inventors: Ute Drechsler, Urs T. Duerig, Jane Elizabeth Frommer, Bernd W. Gotsmann, James Lupton Hedrick, Armin W. Knoll, Tobias Kraus, Robert Dennis Miller
  • Patent number: 7749902
    Abstract: Provided is a method of manufacturing a semiconductor device using double patterning. The method includes: forming a first material layer pattern having recesses in a first direction on an object layer and a second material layer pattern formed on the first material layer pattern; selectively etching the second material layer pattern and the first material layer pattern in a direction perpendicular to the first direction to form an etching mask; and etching the object layer to form minute patterns.
    Type: Grant
    Filed: June 5, 2007
    Date of Patent: July 6, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-chul Kim, Sung-il Cho, Jae-seung Hwang, Jun Sen, Yong-hyun Kwon
  • Patent number: 7740903
    Abstract: A method for manufacturing magnetic recording media is provided, by which a magnetic recording medium that has a recording layer formed in a concavo-convex pattern, a sufficiently flat surface, and good recording/reproducing properties can be manufactured. The method includes the steps of: depositing a first filling material over a workpiece to cover recording elements formed as convex portions of the concavo-convex pattern, and to fill at least part of a concave portion; depositing a detection material over the first filling material; depositing a second filling material over the detection material; and irradiating a surface of the workpiece with a process gas to flatten the surface. In the flattening step, a component of the detection material removed from and flying off the workpiece is detected to stop the irradiation with the process gas based on a result of detecting the component of the detection material.
    Type: Grant
    Filed: February 21, 2007
    Date of Patent: June 22, 2010
    Assignee: TDK Corporation
    Inventors: Takahiro Suwa, Kazuhiro Hattori, Shuichi Okawa
  • Patent number: 7741222
    Abstract: An etch stop layer is formed over a first structure by depositing a metal oxide material over the first structure and annealing the deposited metal oxide material. A second structure is formed over the etch stop layer, and a formation is etched through the second structure using the etch stop layer as an etch stop.
    Type: Grant
    Filed: April 11, 2005
    Date of Patent: June 22, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Sub You, Jae-Young Park, Won-Shik Shin, Hyeon-Deok Lee, Ki-Vin Im, Seok-Woo Nam, Hun-Young Lim, Won-Jun Jang, Yong-Woo Hyung
  • Patent number: 7741229
    Abstract: A method for manufacturing a magnetic recording medium is provided, which can manufacture a magnetic recording medium that includes a recording layer having a concavo-convex pattern and has a sufficiently flat surface. The method includes the steps of: forming an object to be processed including a recording layer having a predetermined concavo-convex pattern formed over a substrate and a first mask layer (temporary underlying material) formed at least on recording elements (convex portions) of the recording layer; depositing a filling material on the object to be processed to fill concave portions; removing a part of the filling material by dry etching to expose at least side faces of the first mask layer; and removing the first mask layer by an etching method in which an etching rate of the first mask layer is higher than that of the filling material to flatten a surface.
    Type: Grant
    Filed: December 9, 2005
    Date of Patent: June 22, 2010
    Assignee: TDK Corporation
    Inventors: Takahiro Suwa, Shuichi Okawa, Kazuya Shimakawa
  • Patent number: 7704680
    Abstract: Ultrafine patterns with dimensions smaller than the chemical and optical limits of lithography are formed by superimposing two photoresist patterns using a double exposure technique. Embodiments include forming a first resist pattern over a target layer to be patterned, forming a protective cover layer over the first resist pattern, forming a second resist pattern on the cover layer superimposed over the first resist pattern while the cover layer protects the first resist pattern, selectively etching the cover layer with high selectivity with respect to the first and second resist patterns leaving an ultrafine target pattern defined by the first and second resist patterns, and etching the underlying target layer using the superimposed first and second resist patterns as a mask.
    Type: Grant
    Filed: June 8, 2006
    Date of Patent: April 27, 2010
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ryoung-Han Kim, Jong-wook Kye
  • Patent number: 7699996
    Abstract: A method for simultaneously forming multiple line-widths, one of which is less than that achievable employing conventional lithographic techniques. The method includes providing a structure which includes a memory layer and a sidewall image transfer (SIT) layer on top of the memory layer. Then, the SIT layer is patterned resulting in a SIT region. Then, the SIT region is used as a blocking mask during directional etching of the memory layer resulting in a first memory region. Then, a side wall of the SIT region is retreated a retreating distance D in a reference direction resulting in a SIT portion. Said patterning comprises a lithographic process. The retreating distance D is less than a critical dimension CD associated with the lithographic process. The SIT region includes a first dimension W2 and a second dimension W3 in the reference direction, wherein CD<W2<2D<W3.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: April 20, 2010
    Assignee: International Business Machines Corporation
    Inventors: Toshiharu Furukawa, John G. Gaudiello, Mark Charles Hakey, David Vaclav Horak, Charles William Koburger, III
  • Patent number: 7695897
    Abstract: The present invention relates to improved methods and structures for forming interconnect patterns in low-k or ultra low-k (i.e., having a dielectric constant ranging from about 1.5 to about 3.5) interlevel dielectric (ILD) materials. Specifically, reduced lithographic critical dimensions (CDs) (i.e., in comparison with target CDs) are initially used for forming a patterned resist layer with an increased thickness, which in turn allows use of a simple hard mask stack comprising a lower nitride mask layer and an upper oxide mask layer for subsequent pattern transfer. The hard mask stack is next patterned by a first reactive ion etching (RIE) process using an oxygen-containing chemistry to form hard mask openings with restored CDs that are substantially the same as the target CDs. The ILD materials are then patterned by a second RIE process using a nitrogen-containing chemistry to form the interconnect pattern with the target CDs.
    Type: Grant
    Filed: May 8, 2006
    Date of Patent: April 13, 2010
    Assignee: International Business Machines Corporation
    Inventors: James J. Bucchignano, Gerald W. Gibson, Mary B. Rothwell, Roy R. Yu
  • Patent number: 7692840
    Abstract: An apparatus for controlling propagation of incident electromagnetic radiation is described, comprising a composite material having electromagnetically reactive cells of small dimension relative to a wavelength of the incident electromagnetic radiation. At least one of a capacitive and inductive property of at least one of the electromagnetically reactive cells is temporally controllable to allow temporal control of an associated effective refractive index encountered by the incident electromagnetic radiation while propagating through the composite material.
    Type: Grant
    Filed: June 4, 2008
    Date of Patent: April 6, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Philip J Kuekes, Shih-Yuan Wang, Raymond G Beausoleil, Alexandre M. Bratkovski, Wei Wu, M. Saif Islam
  • Patent number: 7682986
    Abstract: A method for etching an ultra high aspect ratio feature in a dielectric layer through a carbon based mask is provided. The dielectric layer is selectively etched with respect to the carbon based mask, wherein the selective etching provides a net deposition of a fluorocarbon based polymer on the carbon based mask. The selective etch is stopped. The fluorocarbon polymer is selectively removed with respect to the carbon based mask, so that the carbon based mask remains, using a trimming. The selectively removing the fluorocarbon polymer is stopped. The dielectric layer is again selectively etched with respect to the carbon based mask, wherein the second selectively etching provides a net deposition of a fluorocarbon based polymer on the carbon based mask.
    Type: Grant
    Filed: February 5, 2007
    Date of Patent: March 23, 2010
    Assignee: Lam Research Corporation
    Inventors: Kyeong-Koo Chi, Erik A. Edelberg
  • Patent number: 7670496
    Abstract: A structural body comprising a substrate and a structural layer formed on the substrate through an air gap in which the structural layer functions as a micro movable element is produced by a process comprising a film-deposition step of successively forming a sacrificial layer made of a silicon oxide film and the structural layer on the substrate, an air gap-forming step of removing the sacrificial layer by etching with a treating fluid to form the air gap between the substrate and the structural layer, and a cleaning step. By using a supercritical carbon dioxide fluid containing a fluorine compound, a water-soluble organic solvent and water as the treating fluid, the sacrificial layer is removed in a short period of time with a small amount of the treating fluid without any damage to the structural body.
    Type: Grant
    Filed: December 15, 2004
    Date of Patent: March 2, 2010
    Assignees: SONY Corporation, Mitsubishiki Gas Chemical Company, Inc.
    Inventors: Koichiro Saga, Hiroya Watanabe, Tomoyuki Azuma
  • Patent number: 7648641
    Abstract: A method of the present invention is presented for deep etching of features on a surface. In one embodiment, the method includes providing a substrate having a surface selected to undergo a feature etching process and coating the substrate surface with a protective layer and an imprintable layer. The coated substrate is then subjected to a feature imprinting and etching process. Subsequent to the feature etching process, exposed portions of the protective layer are removed, exposing a well-defined, topographically patterned substrate. In addition, an apparatus for undergoing a feature etching process is disclosed. The apparatus comprises a substrate, an imprintable layer selected to undergo an imprinting process, and a protective layer positioned between the substrate and the imprintable layer.
    Type: Grant
    Filed: June 17, 2005
    Date of Patent: January 19, 2010
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Thomas Robert Albrecht, Henry Hung Yang
  • Patent number: 7641806
    Abstract: By steps of forming first masks 13, 14 each having a first pattern on a first surface of a substrate 11 on which a membrane is to be formed, etching the first surface of the substrate 11 by using the first masks 13, 14 to forming first support beams 15, positioning a second surface of the substrate 11 on the basis of the first pattern on the first surface, forming a second mask 17 having a second pattern on the second surface of the substrate 11 based on the alignment and etching the second surface of the substrate 11 in dry by using the second mask 17 to form the second support beams 20, a membrane member 22a where the first and second support beams 15, 20 are formed on both surfaces of the membrane 12 is manufactured. Consequently, it is possible to provide the membrane member that is sufficient in strength and is hard to be deformed by heat.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: January 5, 2010
    Assignees: Tokyo Electron Limited, OCTEC Inc.
    Inventors: Katsuya Okumura, Kazuya Nagaseki, Naoyuki Satoh, Koji Maruyama
  • Patent number: 7631412
    Abstract: The present invention is a method for adjusting the resonant frequency of a mechanical resonator whose frequency is dependent on the overall resonator thickness. Alternating selective etching is used to remove distinct adjustment layers from a top electrode. One of the electrodes is structured with a plurality of stacked adjustment layers, each of which has distinct etching properties from any adjacent adjustment layers. Also as part of the same invention is a resonator structure in which at least one electrode has a plurality of stacked layers of a material having different etching properties from any adjacent adjustment layers, and each layer has a thickness corresponding to a calculated frequency increment in the resonant frequency of the resonator.
    Type: Grant
    Filed: October 10, 2007
    Date of Patent: December 15, 2009
    Assignee: Agere Systems Inc.
    Inventors: Bradley Paul Barber, Yiu-Huen Wong
  • Patent number: 7628866
    Abstract: A method of cleaning a wafer after an etching process is provided. A substrate having an etching stop layer, a dielectric layer, a patterned metal hard mask sequentially formed thereon is provided. Using the patterned metal hard mask, an opening is defined in the dielectric layer. The opening exposes a portion of the etching stop layer. A dry etching process is performed in the environment of helium to remove the etching stop layer exposed by the opening. A dry cleaning process is performed on the wafer surface using a mixture of nitrogen and hydrogen as the reactive gases. A wet cleaning process is performed on the wafer surface using a cleaning solution containing a trace amount of hydrofluoric acid.
    Type: Grant
    Filed: November 23, 2006
    Date of Patent: December 8, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Miao-Chun Lin, Cheng-Ming Weng, Chun-Jen Huang
  • Patent number: 7625603
    Abstract: A silicon oxide layer is formed by oxidation or decomposition of a silicon precursor gas in an oxygen-rich environment followed by annealing. The silicon oxide layer may be formed with slightly compressive stress to yield, following annealing, an oxide layer having very low stress. The silicon oxide layer thus formed is readily etched without resulting residue using HF-vapor.
    Type: Grant
    Filed: November 14, 2003
    Date of Patent: December 1, 2009
    Assignee: Robert Bosch GmbH
    Inventors: Aaron Partridge, Markus Lutz, Silvia Kronmueller
  • Patent number: 7585424
    Abstract: This invention provides a pattern reversal process for self aligned imprint lithography (SAIL). The method includes providing a substrate and depositing at least one layer of material upon the substrate. A pattern is then established upon the layer of material, the pattern providing at least one exposed area and at least one covered area of the layer of material. The exposed areas are treated to toughen the material and reverse the pattern. Subsequent etching removes the un-toughened material. A thin-film transistor device provided by the pattern reversal process is also provided.
    Type: Grant
    Filed: January 18, 2005
    Date of Patent: September 8, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Ping Mei
  • Patent number: 7567027
    Abstract: A negative hole is formed by etching a dielectric layer that includes at least a lower dielectric sublayer and an upper dielectric sublayer. The lower dielectric sublayer and the upper dielectric sublayer have substantially the same permittivity, and the lower dielectric sublayer may have a higher etching rate lower than the upper dielectric sublayer. The negative hole formed in the upper and lower dielectric sublayers has an etched profile with a protruded portion protruding from at least the boundary between the lower dielectric sublayer and the upper dielectric sublayer. With various embodiments of the disclosed invention, resistance between the cathode and the gate may be secured to prevent arc generation and signal distortion.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: July 28, 2009
    Assignee: Samsung SDI Co., Ltd.
    Inventor: Sang Jin Lee
  • Patent number: 7547636
    Abstract: A method for selectively etching an ultra high aspect ratio feature dielectric layer through a carbon based mask in an etch chamber is provided. A flow of an etch gas is provided, comprising a fluorocarbon containing molecule and an oxygen containing molecule to the etch chamber. A pulsed bias RF signal is provided. An energizing RF signal is provided to transform the etch gas to a plasma.
    Type: Grant
    Filed: February 5, 2007
    Date of Patent: June 16, 2009
    Assignee: Lam Research Corporation
    Inventors: Kyeong-Koo Chi, Erik A. Edelberg
  • Patent number: 7537868
    Abstract: The present invention provides a method of manufacturing color filters using a first mixed gas and a second mixed gas. In the method, a stopper layer whose etching rate by the second mixed gas is low is formed on the support, a colored layer is formed on the stopper layer, a photo resist layer is formed on the colored layer, an image on the colored layer is formed by removing the photo resist layer according to a pattern, a part of the colored layer is removed by dry etching process using the first mixed gas to the extent that the stopper layer is not exposed removing so as to form a colored-layer removed portion according to the pattern, and the colored-layer removed portion is removed by dry etching process using the second mixed gas so as to form a stopper-layer exposed portion according to the pattern.
    Type: Grant
    Filed: March 20, 2008
    Date of Patent: May 26, 2009
    Assignee: Fujifilm Corporation
    Inventor: Hisashi Suzuki
  • Patent number: 7517550
    Abstract: A picture element for an electro-luminescent display comprises a substrate, a first intermediate structure disposed above a first area of the substrate, at least one first color type electro-luminescent device disposed above the first intermediate structure, a second intermediate structure disposed above a second area of the substrate, and at least one second color type electro-luminescent device disposed above the second intermediate structure. The second intermediate structure is different from the first intermediate structure.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: April 14, 2009
    Assignee: Au Optronics Corporation
    Inventors: Wei-Pang Huang, Yi-Fan Wang
  • Patent number: 7494598
    Abstract: Miniature optically transparent windows are disclosed that extend vertically from a plane, which may be used to transmit light traveling in a direction substantially parallel with the plane. In one illustrative embodiment, a method for forming such miniature optically transparent windows includes: providing a substrate having a first surface and an opposing second surface, the substrate having a first layer and an adjacent second layer; forming a recess in the first layer of the substrate, the recess extending to the second layer; providing an optically transparent material in the recess to form an optically transparent feature; and removing at least a portion of the first layer that extends adjacent the optically transparent feature so that light can pass through the optically transparent feature in a direction that is substantially parallel to the first surface of the substrate.
    Type: Grant
    Filed: November 22, 2005
    Date of Patent: February 24, 2009
    Assignee: Honeywell International Inc.
    Inventors: Daniel W. Youngner, Son T. Lu
  • Patent number: 7494599
    Abstract: A method for forming a fine pattern in a semiconductor device includes forming a first polymer layer over an etch target layer, the first polymer layer including a carbon-rich polymer layer, forming a second polymer layer over the first polymer layer, the second polymer layer including a silicon-rich polymer layer, patterning the second polymer layer, oxidizing surfaces of the patterned second polymer layer, etching the first polymer layer using the patterned second polymer layer comprising the oxidized surfaces, and etching the etch target layer using the patterned second polymer layer comprising the oxidized surfaces and the etched first polymer layer.
    Type: Grant
    Filed: April 30, 2007
    Date of Patent: February 24, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sung-Kwon Lee, Seung-Chan Moon, Won-Kyu Kim
  • Patent number: 7488685
    Abstract: Methods for patterning integrated circuit (IC) device arrays employing an additional mask process for improving center-to-edge CD uniformity are disclosed. In one embodiment, a repeating pattern of features is formed in a masking layer over a first region of a substrate. Then, a blocking mask is applied over the features in the masking layer. The blocking mask is configured to differentiate array regions of the first region from peripheral regions of the first region. Subsequently, the pattern of features in the array regions is transferred into the substrate. In the embodiment, an etchant can be uniformly introduced to the masking layer because there is no distinction of center/edge in the masking layer. Thus, CD uniformity can be achieved in arrays which are later defined.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: February 10, 2009
    Assignee: Micron Technology, Inc.
    Inventor: David Kewley
  • Patent number: 7476327
    Abstract: A method of manufacturing a microelectromechanical device includes forming at least two conductive layers on a substrate. An isolation layer is formed between the two conductive layers. The conductive layers are electrically coupled together and then the isolation layer is removed to form a gap between the conductive layers. The electrical coupling of the layers mitigates or eliminates the effects of electrostatic charge build up on the device during the removal process.
    Type: Grant
    Filed: May 4, 2004
    Date of Patent: January 13, 2009
    Assignee: IDC, LLC
    Inventors: Ming-Hau Tung, Brian James Gally, Manish Kothari, Clarence Chui, John Batey
  • Patent number: 7476329
    Abstract: A method for contacting an electrically conductive layer overlying a magnetoelectronics element includes forming a memory element layer overlying a dielectric region. A first electrically conductive layer is deposited overlying the memory element layer. A first dielectric layer is deposited overlying the first electrically conductive layer and is patterned and etched to form a first masking layer. Using the first masking layer, the first electrically conductive layer is etched. A second dielectric layer is deposited overlying the first masking layer and the dielectric region. A portion of the second dielectric layer is removed to expose the first masking layer. The second dielectric layer and the first masking layer are subjected to an etching chemistry such that the first masking layer is etched at a faster rate than the second dielectric layer. The etching exposes the first electrically conductive layer.
    Type: Grant
    Filed: February 2, 2005
    Date of Patent: January 13, 2009
    Assignee: EverSpin Technologies, Inc.
    Inventors: Gregory W. Grynkewich, Brian R. Butcher, Mark A. Durlam, Kelly Kyler, Charles A. Synder, Kenneth H. Smith, Clarence J. Tracy, Richard Williams
  • Patent number: 7473377
    Abstract: A plasma processing method includes a step of preparing a process subject having an organic layer on a surface thereof, and a step of irradiating the process subject with H2 plasma to improve plasma resistance of the organic layer.
    Type: Grant
    Filed: October 7, 2004
    Date of Patent: January 6, 2009
    Assignee: Tokyo Electron Limited
    Inventors: Tomoyo Yamaguchi, Takashi Fuse, Kiwamu Fujimoto, Masanobu Honda, Kazuya Nagaseki, Akiteru Koh, Takashi Enomoto, Hiroharu Ito, Akinori Kitamura
  • Publication number: 20080296257
    Abstract: Miniature optically transparent windows are disclosed that extend vertically from a plane, which may be used to transmit light traveling in a direction substantially parallel with the plane. In one illustrative embodiment, a method for forming such miniature optically transparent windows includes: providing a substrate having a first surface and an opposing second surface, the substrate having a first layer and an adjacent second layer; forming a recess in the first layer of the substrate, the recess extending to the second layer; providing an optically transparent material in the recess to form an optically transparent feature; and removing at least a portion of the first layer that extends adjacent the optically transparent feature so that light can pass through the optically transparent feature in a direction that is substantially parallel to the first surface of the substrate.
    Type: Application
    Filed: November 22, 2005
    Publication date: December 4, 2008
    Applicant: HONEYWELL INTERNATIONAL INC.
    Inventors: Daniel W. Youngner, Son T. Lu
  • Patent number: 7456110
    Abstract: A method for controlling an etch process comprises providing a wafer having at least a first layer and a second layer formed over the first layer. The thickness of the second layer is measured. An etch selectivity parameter is determined based on the measured thickness of the second layer. An operating recipe of an etch tool is modified based on the etch selectivity parameter. A processing line includes an etch tool, a first metrology tool, and a process controller. The etch tool is adapted to etch a plurality of wafers based on an operating recipe, each wafer having at least a first layer and a second layer formed over the first layer. The first metrology tool is adapted to measure a pre-etch thickness of the second layer. The process controller is adapted to determine an etch selectivity parameter based on the measured pre-etch thickness of the second layer and modify the operating recipe of the etch tool based on the etch selectivity parameter.
    Type: Grant
    Filed: November 23, 2004
    Date of Patent: November 25, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jeremy S. Lansford, Laura Faulk
  • Patent number: 7435074
    Abstract: The process of producing a dual damascene structure used for the interconnect architecture of semiconductor chips. More specifically the use of imprint lithography to fabricate dual damascene structures in a dielectric and the fabrication of dual damascene structured molds.
    Type: Grant
    Filed: March 13, 2004
    Date of Patent: October 14, 2008
    Assignee: International Business Machines Corporation
    Inventors: Matthew E. Colburn, Kenneth Raymond Carter, Gary M. McClelland, Dirk Pfeiffer
  • Patent number: 7425277
    Abstract: Broadly speaking, methods and an apparatus are provided for removing an inorganic material from a substrate. More specifically, the methods provide for removing the inorganic material from the substrate through exposure to a high density plasma generated using an inductively coupled etching apparatus. The high density plasma is set and controlled to isotropically contact particular regions of the inorganic material to allow for trimming and control of a critical dimension associated with the inorganic material.
    Type: Grant
    Filed: August 13, 2003
    Date of Patent: September 16, 2008
    Assignee: Lam Research Corporation
    Inventors: C. Robert Koemtzopoulos, Shibu Gangadharan, Chris G. N. Lee, Alan Miller
  • Patent number: 7405162
    Abstract: An etching method forms an opening with a substantially vertical profile extending to a stopper layer by performing an etching with a plasma of an etching gas acting on an object to be processed loaded in an evacuable processing vessel, wherein the object has a mask layer of a predetermined pattern, a silicon layer to be etched formed below the mask layer and the stopper layer formed below the silicon layer. The etching method includes a first etching process for forming an opening with a tapered wall surface in the silicon layer by using a first etching gas including a fluorine-containing gas and O2 but not HBr; and a second etching process for etching the opening by using a second etching gas including a fluorine-containing gas, O2 and HBr.
    Type: Grant
    Filed: September 22, 2005
    Date of Patent: July 29, 2008
    Assignee: Tokyo Electron Limited
    Inventors: Koji Maruyama, Yusuke Hirayama, Nozomi Hirai, Takanori Mimura
  • Patent number: 7402255
    Abstract: A micro-electro-mechanical system (MEMS) device includes a mirror having a top surface with trenches, a beam connected to the mirror, rotational comb teeth connected to the beam, and one or more springs connecting the beam to a bonding pad. The mirror can have a bottom surface for reflecting light. The mirror can include a top flange and a bottom flange joined by a web, wherein the top and the bottom flanges form the top and the bottom surfaces, respectively. The rotational comb teeth can have a tapered shape. Stationary comb teeth can be interdigitated with the rotational comb teeth either in-plane or out-of-plane. Steady or oscillating voltage difference between the rotational and the stationary comb teeth can be used to oscillate or tune the mirror.
    Type: Grant
    Filed: March 7, 2006
    Date of Patent: July 22, 2008
    Assignee: Advanced NuMicro Systems, Inc.
    Inventor: Yee-Chung Fu
  • Patent number: 7393795
    Abstract: Methods for post-etch deposition on a dielectric film are provided in the present invention. In one embodiment, the method includes providing a substrate having a low-k dielectric layer disposed thereon in a etch reactor, etching the low-k dielectric layer in the etch reactor, and forming a protection layer on the etched low-k dielectric layer. In another embodiment, the method includes providing a substrate having a low-k dielectric layer disposed thereon in an etch reactor, etching the low-k dielectric layer in the reactor, bonding the etched low-k dielectric layer with a polymer gas supplied into the reactor, forming a protection layer on the etched low-k dielectric layer, and removing the protection layer formed on the etched low-k dielectric layer.
    Type: Grant
    Filed: February 1, 2006
    Date of Patent: July 1, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Robin Cheung, Siyi Li
  • Patent number: 7384530
    Abstract: The invention includes methods of fabrication and apparatuses. In at least some embodiments of the applicants' invention, the methods include processes of: maskless selective deposition of non-layered structures, selective etching and/or deposition without use of a separate mask and/or lithography techniques, retaining selected portions of sacrificial material during removal (e.g. etching) of other portions of sacrificial material, depositing materials other than the structural and sacrificial materials, including more than one type of structural and/or sacrificial material, and fabrication of interlacing elements. Embodiments of the methods of the invention provide increased capabilities, properties, flexibility and in the fabrication of three-dimensional structures by electro-deposition or other techniques.
    Type: Grant
    Filed: May 7, 2004
    Date of Patent: June 10, 2008
    Assignee: Microfabrica Inc.
    Inventors: Adam L. Cohen, Dennis R. Smalley
  • Patent number: 7380320
    Abstract: A piezoelectric device includes a substrate, a buffer layer on the substrate, a lower electrode layer on the buffer layer, a piezoelectric layer on the lower electrode layer, and an upper electrode layer on the piezoelectric layer. The piezoelectric layer has a base portion extending outwardly at its lower portion of its periphery. The piezoelectric device provides enhanced bonding strength between the substrate and the stacked structure including the upper electrode layer, the lower electrode layer, and the piezoelectric layer.
    Type: Grant
    Filed: December 4, 2006
    Date of Patent: June 3, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Masaya Nakatani
  • Patent number: 7364665
    Abstract: A method of selectively etching a three-layer structure consisting of SiO2, In2O3, and titanium, includes etching the SiO2, stopping at the titanium layer, using C3F8 in a range of between about 10 sccm to 30 sccm; argon in a range of between about 20 sccm to 40 sccm, using an RF source in a range of between about 1000 watts to 3000 watts and an RF bias in a range of between about 400 watts to 800 watts at a pressure in a range of between about 2 mtorr to 6 mtorr; and etching the titanium, stopping at the In2O3 layer, using BCl in a range of between about 10 sccm to 50 sccm; chlorine in a range of between about 40 sccm to 80 sccm, a Tcp in a range of between about 200 watts to 500 watts at an RF bias in a range of between about 100 watts to 200 watts at a pressure in a range of between about 4 mtorr to 8 mtorr.
    Type: Grant
    Filed: October 21, 2004
    Date of Patent: April 29, 2008
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Tingkai Li, Bruce D. Ulrich, David R. Evans, Sheng Teng Hsu
  • Publication number: 20080087638
    Abstract: Calibration wafers and methods for calibrating a plasma process performed in a plasma processing apparatus, such as an ionized physical vapor deposition apparatus. The calibration wafer includes one or more selective-redeposition sources that may be used for calibrating a plasma process. The selective-redeposition sources are constructed to promote the redeposition of a controllable and/or measurable amount of material during the plasma process.
    Type: Application
    Filed: September 29, 2006
    Publication date: April 17, 2008
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Jozef Brcka, Rodney L. Robison, Takashi Horiuchi
  • Patent number: 7338907
    Abstract: A dry etch process is described for selectively etching silicon nitride from conductive oxide material for use in a semiconductor fabrication process. Adding an oxidant in the etch gas mixture could increase the etch rate for the silicon nitride while reducing the etch rate for the conductive oxide, resulting in improving etch selectivity. The disclosed selective etch process is well suited for ferroelectric memory device fabrication using conductive oxide/ferroelectric interface having silicon nitride as the encapsulated material for the ferroelectric.
    Type: Grant
    Filed: October 4, 2004
    Date of Patent: March 4, 2008
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Tingkai Li, Sheng Teng Hsu, Bruce D. Ulrich, Mark A. Burgholzer, Ray A. Hill
  • Patent number: 7328497
    Abstract: A method is provided for adjusting the resonant frequency of a mechanical resonator whose frequency is dependent on the overall resonator thickness. Alternating selective etching is used to remove distinct adjustment layers from a top electrode. One of the electrodes is structured with a plurality of stacked adjustment layers, each of which has distinct etching properties from any adjacent adjustment layers. Also as part of the same invention is a resonator structure in which at least one electrode has a plurality of stacked layers of a material having different etching properties from any adjacent adjustment layers, and each layer has a thickness corresponding to a calculated frequency increment in the resonant frequency of the resonator.
    Type: Grant
    Filed: June 6, 2005
    Date of Patent: February 12, 2008
    Assignee: Agere Systems Inc.
    Inventors: Bradley Paul Barber, Yiu-Huen Wong
  • Patent number: 7326358
    Abstract: A plasma processing method performs a plasma processing on a substrate mounted on a mounting table installed in an airtight processing chamber, the mounting table having a smaller size than the substrate. The substrate having a surface, on which a resist mark is formed, is mounted on the mounting table and then electrostatically adsorbed on the mounting table by applying a voltage to an electrostatic chuck. The surface of the substrate is etched by using a plasma of an etching gas while the substrate is cooled through a heat transfer between the substrate and the mounting table via a thermally conductive gas supplied between a top surface of the mounting table and a bottom surface of the substrate. The supply of the thermally conductive gas is stopped, and the resist mask on the substrate is ashed by using a plasma of an ashing gas containing O2.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: February 5, 2008
    Assignee: Tokyo Electron Limited
    Inventor: Masaru Sugimoto
  • Publication number: 20080023441
    Abstract: A method of deep etching is disclosed. Initially, a wafer is provided, and a patterned mask having at least an opening to expose a surface of the wafer is formed on the surface of the wafer. A deposition process is performed to form a polymer layer on the patterned mask and a part of the surface through the opening. And accordingly, a plasma etching process is performed to remove the polymer layer and to etch the surface through the opening to form a deep opening. An oxide layer is formed on a sidewall of the deep opening to protect the sidewall during the plasma etching process. The deposition process and the plasma etching process are repeated alternatively until the deep opening has a predetermined aspect ratio. The method of the invention etches the wafer anisotropically and forms a deep opening having a hydrophilic surface of the sidewall.
    Type: Application
    Filed: October 18, 2006
    Publication date: January 31, 2008
    Inventor: Te-Keng Tsai
  • Patent number: 7316785
    Abstract: In a plasma processing system, including a plasma processing chamber, a method of optimizing the etch resistance of a substrate material is described. The method includes flowing pre-coat gas mixture into the plasma processing chamber, wherein the pre-coat gas mixture has an affinity for a etchant gas flow mixture; striking a first plasma from the pre-coat gas mixture; and introducing a substrate comprising the substrate material. The method also includes flowing the etchant gas mixture into the plasma processing chamber; striking a second plasma from the etchant gas mixture; and etching the substrate with the second plasma. Wherein the first plasma creates a pre-coat residual on a set of exposed surfaces in the plasma processing chamber, and the etch resistance of the substrate material is maintained.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: January 8, 2008
    Assignee: Lam Research Corporation
    Inventors: Yoko Yamaguchi Adams, George Stojakovic, Alan Miller
  • Patent number: 7311852
    Abstract: A semiconductor manufacturing process wherein a low-k dielectric layer is plasma etched with selectivity to an overlying mask layer. The etchant gas can be oxygen-free and include a fluorocarbon reactant, a nitrogen reactant and an optional carrier gas, the fluorocarbon reactant and nitrogen reactant being supplied to a chamber of a plasma etch reactor at flow rates such that the fluorocarbon reactant flow rate is less than the nitrogen reactant flow rate. The etch rate of the low-k dielectric layer can be at least 5 times higher than that of a silicon dioxide, silicon nitride, silicon oxynitride or silicon carbide mask layer. The process is useful for etching 0.25 micron and smaller contact or via openings in forming structures such as damascene structures.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: December 25, 2007
    Assignee: Lam Research Corporation
    Inventors: Si Yi Li, Helen H. Zhu, S. M. Reza Sadjadi, James V. Tietz, Bryan A. Helmer
  • Patent number: 7311850
    Abstract: In a method of forming a patterned thin film, first, an etching stopper film and a film to be patterned are formed in this order on a base layer. Next, a patterned first film is formed on the film to be patterned. Next, a second film is formed over an entire surface on top of the film to be patterned and the first film. Then, by removing the first film, an etching mask is obtained from the second film formed on the film to be patterned. The film to be patterned is selectively etched through dry etching using the etching mask. A patterned thin film having a groove is thereby obtained.
    Type: Grant
    Filed: October 17, 2002
    Date of Patent: December 25, 2007
    Assignee: TDK Corporation
    Inventors: Akifumi Kamijima, Yoichi Ishida, Koichi Terunuma
  • Patent number: 7309448
    Abstract: A process of selectively etching a sacrificial light absorbing material (SLAM) over a dielectric material, such as carbon doped oxide, on a substrate using a plasma of a gas mixture in a plasma etch chamber. The gas mixture comprises a hydrofluorocarbon gas, an optional hydrogen-containing gas, an optional fluorine-rich fluorocarbon gas, a nitrogen gas, an oxygen gas, and an inert gas. The process could provide a SLAM to a dielectric material etching selectivity ratio greater than 10:1.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: December 18, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Hee Yeop Chae, Jeremiah T. P. Pender, Gerardo A. Delgadino, Xiaoye Zhao, Yan Ye
  • Patent number: 7306746
    Abstract: A method for controlling a critical dimension in an etched structure comprises the steps of: forming a hard mask above a substrate, measuring a critical dimension of the hard mask, and using the measured hard mask critical dimension to control a critical dimension trim operation performed on a circuit trace above the substrate.
    Type: Grant
    Filed: January 30, 2004
    Date of Patent: December 11, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Fang-Cheng Chen, Li Te Hsu, I Cheng Tseng, Hsu Chiung Wen, Tsung Chuan Chen, Pin Chia Su
  • Patent number: RE40951
    Abstract: A dry etching method in which a plasma of an etching gas is generated and a magnetic material is dry-etched using a mask material made of a non-organic material, wherein an alcohol having at least one hydroxyl group is used as the etching gas. The alcohol used as the etching gas has one hydroxyl group such as an alcohol selected from the group including methanol (CH3OH), ethanol (C2H5OH) and propanol (C3H7OH).
    Type: Grant
    Filed: June 12, 2008
    Date of Patent: November 10, 2009
    Assignee: Canon Anelva Corporation
    Inventors: Yoshimitsu Kodaira, Taichi Hiromi