Etching A Multiple Layered Substrate Where The Etching Condition Used Produces A Different Etching Rate Or Characteristic Between At Least Two Of The Layers Of The Substrate Patents (Class 216/72)
  • Patent number: 7307013
    Abstract: A method for etching to form a planarized surface is disclosed. Spaced-apart features are formed of a first material, the first material either conductive or insulating. A second material is deposited over and between the first material. The second material is either insulating or conductive, opposite the conductivity of the first material. The second material is preferably self-planarizing during deposition. An unpatterned etch is performed to etch the second material and expose the top of the buried features of the first material. The etch is preferably a two-stage etch: The first stage is selective to the second material. When the second material is exposed, the etch chemistry is changed such that the etch is nonselective, etching the first material and the second material at substantially the same rate until the buried features are exposed across the wafer, producing a substantially planar surface.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: December 11, 2007
    Assignee: Sandisk 3D LLC
    Inventors: Usha Raghuram, Michael W. Konevecki, Samuel V. Dunton
  • Patent number: 7300597
    Abstract: A process of selectively etching a sacrificial light absorbing material (SLAM) over a dielectric material, such as carbon doped oxide, on a substrate using a plasma of a gas mixture in a plasma etch chamber. The gas mixture comprises a hydrofluorocarbon gas, an optional hydrogen-containing gas, an optional fluorine-rich fluorocarbon gas, a nitrogen gas, an oxygen gas, and an inert gas. The process could provide a SLAM to a dielectric material etching selectivity ratio greater than 10:1.
    Type: Grant
    Filed: September 27, 2006
    Date of Patent: November 27, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Hee Yeop Chae, Jeremiah T. P. Pender, Gerardo A. Delgadino, Xiaoye Zhao, Yan Ye
  • Patent number: 7300595
    Abstract: A method for filling concave portions of a concavo-convex pattern by which the concave portions of the concavo-convex pattern can be filled to flatten the surface with reliability, and a method for manufacturing a magnetic recording medium by which a magnetic recording medium having a magnetic recording layer of concavo-convex pattern with a sufficiently flat surface can be manufactured efficiently. A filler for filling the concave portions is deposited over the surface of an object to be processed, the object being provided with a concavo-convex pattern. A cladding is further deposited over the filler. Then, an excess part of the filler and the cladding above the surface of the object are removed for flattening, by using a dry etching method having a lower etching rate to the cladding than to the filler.
    Type: Grant
    Filed: December 20, 2004
    Date of Patent: November 27, 2007
    Assignee: TDK Corporation
    Inventors: Takahiro Suwa, Kazuhiro Hattori, Shuichi Okawa, Mikiharu Hibi
  • Patent number: 7297286
    Abstract: A method for manufacturing an article having polymeric residue that is to be removed during the manufacture of the article is disclosed. The article is introduced into a controlled environment of a processing tool having one or more processing chambers. Free radicals are generated from one or more reactant gases and introduced into at least one of the one or more processing chambers where they react with the polymeric residue. A cryogenic cleaning medium is supplied into at least one of the one or more processing chambers where the cryogenic cleaning medium removes the polymeric residue present after the free radicals react with the polymeric residue. The reactant gases are selected to facilitate removal of the polymeric residue with the cryogenic cleaning medium. The cryogenic cleaning medium is supplied with a pulsating flow via a nozzle implement that sweeps across the article.
    Type: Grant
    Filed: January 28, 2005
    Date of Patent: November 20, 2007
    Assignee: Nanoclean Technologies, Inc.
    Inventors: Adel George Tannous, Khalid Makhamreh
  • Patent number: 7291559
    Abstract: In a method of manufacturing a semiconductor device, a dummy sample and an actual device are prepared. The dummy sample and the actual device have substantially an identical layer and an identical resist pattern formed on the layer. Then, a dummy discharge is carried out. The layer and the resist pattern of the dummy sample are etched in an etching device so that the layer and the resist pattern of the dummy device are simultaneously slimmed. Finally, the layer and the resist pattern of the actual device are etched in the etching device after the etching of the dummy sample so that the layer and the resist pattern of the actual device are simultaneously slimmed.
    Type: Grant
    Filed: December 15, 2004
    Date of Patent: November 6, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Akira Takahashi
  • Patent number: 7291563
    Abstract: The invention includes methods of etching substrates, methods of forming features on substrates, and methods of depositing a layer comprising silicon, carbon and fluorine onto a semiconductor substrate. In one implementation, a method of etching includes forming a masking feature projecting from a substrate. The feature has a top, opposing sidewalls, and a base. A layer comprising SixCyFz is deposited over the feature, where “x” is from 0 to 0.2, “y” is from 0.3 to 0.9, and “z” is from 0.1 to 0.6. The SixCyFz-comprising layer and upper portions of the feature opposing sidewalls are etched effective to laterally recess such upper portions proximate the feature top relative to lower portions of the feature opposing sidewalls proximate the feature base. After such etching of the SixCyFz-comprising layer and such etching of upper portions of the feature sidewalls, the substrate is etched using the masking feature as a mask.
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: November 6, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Mirzafer Abatchev, Krupakar M. Subramanian
  • Publication number: 20070221617
    Abstract: The method of manufacturing a nozzle plate which includes a nozzle having a tapered section and a linear section includes the steps of: forming an etching stopper layer for stopping dry etching of a silicon substrate, on a first surface of the silicon substrate; forming a mask layer on a second surface of the silicon substrate reverse to the first surface; performing a first patterning process with respect to the mask layer so that an opening section is formed in the mask layer; carrying out the dry etching of the silicon substrate through the opening section in the mask layer so that the tapered section of the nozzle is formed in the silicon substrate; carrying out dry etching of the etching stopper layer through the opening section in the mask layer so that at least a part of the linear section of the nozzle is formed in the etching stopper layer; and removing the mask layer.
    Type: Application
    Filed: March 22, 2007
    Publication date: September 27, 2007
    Inventor: Shuji Takahashi
  • Patent number: 7273563
    Abstract: A method for manufacturing a magnetic recording medium is provided, which can efficiently manufacture a magnetic recording medium that includes a recording layer formed in a concavo-convex pattern and has good recording and reproduction characteristics. The method includes: a non-magnetic material filling step of depositing a non-magnetic material over a recording layer formed in a predetermined concavo-convex pattern over a substrate so as to fill a concave portion of the concavo-convex pattern with the non-magnetic material; and a flattening step of removing the excess part of the non-magnetic material above the recording layer by dry etching so as to flatten the surfaces of the non-magnetic material and the recording layer. The flattening step includes a former flattening step and a latter flattening step for finishing.
    Type: Grant
    Filed: February 3, 2005
    Date of Patent: September 25, 2007
    Assignee: TDK Corporation
    Inventors: Kazuhiro Hattori, Shuichi Okawa, Takahiro Suwa, Mikiharu Hibi
  • Patent number: 7259104
    Abstract: A surface processing method of a sample having a mask layer that does not contain carbon as a major component formed on a substance to be processed, the substance being a metal, semiconductor and insulator deposited on a silicon substrate, includes the steps of installing the sample on a sample board in a vacuum container, generating a plasma that consists of a mixture of halogen gas and adhesive gas inside the vacuum container, applying a radio frequency bias voltage having a frequency ranging from 200 kHz to 20 MHz on the sample board, and controlling a periodic on-off of the radio frequency bias voltage with an on-off control frequency ranging from 100 Hz to 10 kHz.
    Type: Grant
    Filed: September 29, 2003
    Date of Patent: August 21, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Tetsuo Ono, Takafumi Tokunaga, Tadashi Umezawa, Motohiko Yoshigai, Tatsumi Mizutani, Tokuo Kure, Masayuki Kojima, Takashi Sato, Yasushi Goto
  • Patent number: 7256134
    Abstract: The present invention includes a process for selectively etching a low-k dielectric material formed on a substrate using a plasma of a gas mixture in a plasma etch chamber. The gas mixture comprises a fluorine-rich fluorocarbon or hydrofluorocarbon gas, a nitrogen-containing gas, and one or more additive gases, such as a hydrogen-rich hydrofluorocarbon gas, an inert gas and/or a carbon-oxygen gas. The process provides a low-k dielectric to a photoresist mask etching selectivity ratio greater than about 5:1, a low-k dielectric to a barrier/liner layer etching selectivity ratio greater about 10:1, and a low-k dielectric etch rate higher than about 4000 ?/min.
    Type: Grant
    Filed: August 1, 2003
    Date of Patent: August 14, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Yunsang Kim, Neungho Shin, Heeyeop Chae, Joey Chiu, Yan Ye, Fang Tian, Xiaoye Zhao
  • Patent number: 7247251
    Abstract: A method for manufacturing a magnetic recording medium is provided, which can efficiently manufacture a magnetic recording medium that includes a recording layer formed in a concavo-convex pattern, has a sufficiently flat surface, and provides good recording and reproduction precision. The method includes: a non-magnetic material filling step of depositing a non-magnetic material over a recording layer formed in a predetermined concavo-convex pattern over a substrate, thereby filling a concave portion of the concavo-convex pattern with the non-magnetic material; and a flattening step of removing the excess part of the non-magnetic material above the recording layer by ion beam etching to flatten the surfaces of the non-magnetic layer and the recording layer.
    Type: Grant
    Filed: February 7, 2005
    Date of Patent: July 24, 2007
    Assignee: TDK Corporation
    Inventors: Kazuhiro Hattori, Shuichi Okawa, Takahiro Suwa, Mikiharu Hibi
  • Patent number: 7247247
    Abstract: A selective etching method with lateral protection function is provided. The steps includes: (a) providing a substrate; (b) forming a plurality of tunnels; (c) forming a lateral strengthening structure at a peripheral wall of the tunnels; (d) removing a bottom portion of the lateral strengthening structure, and a part of the substrate by an etching process so as to form a lower structure and expose an unstrengthened structure; and (f) etching the unstrengthened structure laterally so as to form an upper structure.
    Type: Grant
    Filed: May 6, 2004
    Date of Patent: July 24, 2007
    Assignee: Walsin Lihwa Corporation
    Inventors: Jerwei Hsieh, Huai-Yuan Chu, Julius Ming-Lin Tsai, Weileun Fang
  • Patent number: 7247248
    Abstract: The invention relates to a method for forming silicon atomic force microscope tips. The method includes the steps of depositing a masking layer onto a first layer of doped silicon so that some square or rectangular areas of the first layer of doped silicon are not covered by the masking layer, etching pyramidal apertures in the first layer of doped silicon, removing the masking layer, depositing a second layer of doped silicon onto the first layer of doped silicon, the second layer of doped silicon being oppositely doped to the first layer of doped silicon and etching away the first layer of doped silicon. Further steps may be added to form the atomic force microscope tips at the end of cantilevers.
    Type: Grant
    Filed: May 20, 2003
    Date of Patent: July 24, 2007
    Assignee: Sensfab Pte Ltd
    Inventors: Lay Har Angeline Tee, Kim Pong Daniel Chir, Kitt-Wai Kok, Kathirgamasundaram Sooriakumar, Bryan Keith Patmon
  • Patent number: 7244368
    Abstract: A manufacturing method of a magnetic head includes a process for forming a lift-off mask pattern on a magnetoresistance effect element, such that the upper part of the lift-off mask pattern is larger in size than the lower part, a process for forming a couple of electrodes on the magnetoresistance effect element using the lift-off mask pattern as a mask, and a process for removing the lift-off mask pattern. The process for forming the lift-off mask pattern is performed according to a dry etching process.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: July 17, 2007
    Assignee: Fujitsu Limited
    Inventors: Shoichi Suda, Masayuki Takeda, Keiji Watanabe
  • Patent number: 7211197
    Abstract: A processing gas constituted of CH2F2, O2 and Ar is introduced into a processing chamber 102 of a plasma processing apparatus 100. The flow rate ratio of the constituents of the processing gas is set at CH2F2/O2/Ar=20 sccm/10 sccm/100 sccm. The pressure inside the processing chamber 102 is set at 50 mTorr. 500 W high frequency power with its frequency set at 13.56 MHz is applied to a lower electrode. 108 on which a wafer W is placed. The processing gas is raised to plasma and thus, an SiNx layer 206 formed on a Cu layer 204 is etched. The exposed Cu layer 204 is hardly oxidized and C and F are not injected into it.
    Type: Grant
    Filed: August 2, 2004
    Date of Patent: May 1, 2007
    Assignee: Tokyo Electron Limited
    Inventors: Masaaki Hagihara, Koichiro Inazawa, Wakako Naito
  • Patent number: 7182878
    Abstract: This relates to optical devices such as planar light-wave components/circuits which are designed to have a high waveguide pattern density effecting a higher etch selectivity and overall improved dimensional control of the functional waveguides on the optical device.
    Type: Grant
    Filed: February 6, 2004
    Date of Patent: February 27, 2007
    Assignee: Lightwave Microsystems Corporation
    Inventors: Jongik Won, Calvin Ka Kuen Ho, Fan Zhong, Liang Zhao
  • Patent number: 7179396
    Abstract: The present invention provides a method to pattern a substrate which features creating a multi-layered structure by forming, on the substrate, a patterned layer having protrusions and recessions. Formed upon the patterned layer is a conformal layer, with the multi-layered structure having a crown surface facing away from the substrate. Portions of the multi-layered structure are removed to expose regions of the substrate in superimposition with the protrusions, while forming a hard mask in areas of the crown surface in superimposition with the recessions.
    Type: Grant
    Filed: March 25, 2003
    Date of Patent: February 20, 2007
    Assignee: Molecular Imprints, Inc.
    Inventor: Sidlgata V. Sreenivasan
  • Patent number: 7169440
    Abstract: A method is provided for plasma ashing to remove photoresist remnants and etch residues that are formed during preceding plasma etching of dielectric layers. The ashing method uses a two-step plasma process involving an oxygen-containing gas, where low or zero bias is applied to the substrate in the first cleaning step to remove significant amount of photoresist remnants and etch residues from the substrate, in addition to etching and removing detrimental fluoro-carbon residues from the chamber surfaces. An increased bias is applied to the substrate in the second cleaning step to remove the remains of the photoresist and etch residues from the substrate. The two-step process reduces the memory effect commonly observed in conventional one-step ashing processes. A method of endpoint detection can be used to monitor the ashing process.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: January 30, 2007
    Assignee: Tokyo Electron Limited
    Inventors: Vaidyanathan Balasubramaniam, Masaaki Hagiwara, Eiichi Nishimura, Kouichiro Inazawa
  • Patent number: 7141508
    Abstract: A manufacturing method of an MR thin-film magnetic head with an MR film and lead conductors overlapping each other, includes a step of depositing a conductor layer on at least the magnetoresistive effect film, a step of forming a cap layer patterned on the deposited conductor layer, and a step of dry-etching the deposited conductor layer through a mask of the patterned cap layer using an Ar gas and an O2 gas, an O2 gas or a N2 gas so as to pattern the deposited conductor film to form the lead conductors.
    Type: Grant
    Filed: August 7, 2002
    Date of Patent: November 28, 2006
    Assignee: TDK Corporation
    Inventors: Katsuya Kanakubo, Yoshimitsu Wada, Kazuhiro Hattori
  • Patent number: 7118683
    Abstract: The invention encompasses a method of enhancing selectivity of etching silicon dioxide relative to one or more organic substances. A material comprising one or more elements selected from Group VIII of the periodic table is provided within a reaction chamber; and a substrate is provided within the reaction chamber. The substrate has both a silicon-oxide-containing composition and at least one organic substance thereover. The silicon-oxide-containing composition is plasma etched within the reaction chamber. The plasma etching of the silicon-oxide-containing composition has increased selectivity for the silicon oxide of the composition relative to the at least one organic substance than would plasma etching conducted without the material in the chamber. The invention also encompasses a plasma reaction chamber assembly. The assembly comprises at least one interior wall, and at least one liner along the at least one interior wall. The liner comprises one or more of Ru, Fe, Co, Ni, Rh, Pd, Os, W, Ir, Pt and Ti.
    Type: Grant
    Filed: September 20, 2002
    Date of Patent: October 10, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Max F. Hineman, Li Li
  • Patent number: 7112288
    Abstract: Methods are provided for delineating different layers and interfaces for inspection of a semiconductor wafer, wherein a sectioned portion of a wafer is subjected to a reactive ion etch process before inspection using a scanning electron microscope.
    Type: Grant
    Filed: August 13, 2002
    Date of Patent: September 26, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Fred Y. Clark, Andrew L. Vance, David G. Farber
  • Patent number: 7081415
    Abstract: A method of dry plasma etching a semiconductor structure (20), having at least one semiconductor material layer (21), on a semiconductor wafer (200), involving a dry plasma reaction gas mixture (30i) being chemically selected for, and having an etch rate corresponding to, each semiconductor material layer (21); dividing the semiconductor structure (20) into a masked portion (23a) and an unmasked portion (23b); and sequentially exposing the unmasked portion (23b) of the semiconductor structure (20) to the dry plasma reaction gas mixture (30i).
    Type: Grant
    Filed: February 18, 2004
    Date of Patent: July 25, 2006
    Assignee: Northrop Grumman Corporation
    Inventor: Jennifer Wang
  • Patent number: 7064078
    Abstract: A method of etching a substrate is provided. The method of etching a substrate includes transferring a pattern into the substrate using a double patterned amorphous carbon layer on the substrate as a hardmask. Optionally, a non-carbon based layer is deposited on the amorphous carbon layer as a capping layer before the pattern is transferred into the substrate.
    Type: Grant
    Filed: January 30, 2004
    Date of Patent: June 20, 2006
    Assignee: Applied Materials
    Inventors: Wei Liu, Jim Zhongyi He, Sang H. Ahn, Meihua Shen, Hichem M'Saad, Wendy H. Yeh, Chistopher D. Bencher
  • Patent number: 7060625
    Abstract: A method of fabricating an imprint stamp is disclosed. The imprint stamp includes a plurality of layers of material that are deposited in a deposition order. After deposition, each layer is patterned and then etched to form a portion of an application specific imprint pattern. The portion includes variations in a topography of the layer. The application specific imprint pattern comprises a plurality of features that are defined by the variations in the topographies of all of the layers of material that were deposited, patterned, and etched. The imprint stamp can be used in a soft-lithography process by pressing the application specific imprint pattern into a mask layer in which the application specific imprint pattern is replicated.
    Type: Grant
    Filed: January 27, 2004
    Date of Patent: June 13, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Heon Lee
  • Patent number: 7060194
    Abstract: A dry etching method in which a plasma of an etching gas is generated and a magnetic material is dry-etched using a mask material made of a non-organic material, wherein an alcohol having at least one hydroxyl group is used as the etching gas. The alcohol used as the etching gas has one hydroxyl group such as an alcohol selected from the group including methanol (CH3OH), ethanol (C2H5OH) and propanol (C3H7OH).
    Type: Grant
    Filed: July 23, 2004
    Date of Patent: June 13, 2006
    Assignee: ANELVA Corporation
    Inventors: Yoshimitsu Kodaira, Taichi Hiromi
  • Patent number: 7052617
    Abstract: A process for producing multiple undercut profiles in a single material. A resist pattern is applied over a work piece and a wet etch is performed to produce an undercut in the material. This first wet etch is followed by a polymerizing dry etch that produces a polymer film in the undercut created by the first wet etch. The polymer film prevents further etching of the undercut portion during a second wet etch. Thus, an undercut profile can be obtained having a larger undercut in an underlying portion of the work piece, utilizing only a single resist application step. The work piece may be a multi-layer work piece having different layers formed of the same material, or it may be a single layer of material.
    Type: Grant
    Filed: December 13, 2002
    Date of Patent: May 30, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Karen Huang, Christophe Pierrat
  • Patent number: 7053003
    Abstract: A method for etching a feature in an etch layer through a photoresist mask over a substrate is provided. A substrate with an etch layer disposed below a photoresist mask is placed in a process chamber. The photoresist mask is conditioned, wherein the conditioning comprises providing a conditioning gas comprising a hydrogen containing gas with a flow rate and at least one of a fluorocarbon and a hydrofluorocarbon with a flow rate to the process chamber; and energizing the conditioning gas to form the conditioning plasma. The conditioning plasma is stepped. An etch plasma is provided to the process chamber, wherein the etch plasma is different than the conditioning plasma. A feature is etched in the etch layer with the etch plasma.
    Type: Grant
    Filed: October 27, 2004
    Date of Patent: May 30, 2006
    Assignee: Lam Research Corporation
    Inventors: Karen Jacobs Kanarik, Aaron Eppler
  • Patent number: 7049052
    Abstract: A method for etching a feature in a layer is provided. An underlayer of a polymer material is formed over the layer. A top image layer is formed over the underlayer. The top image layer is exposed to patterned radiation. A pattern is developed in the top image layer. The pattern is transferred from the top image layer to the underlayer with a reducing dry etch. The layer is etched through the underlayer, where the top image layer is completely removed and the underlayer is used as a pattern mask during the etching the layer to transfer the pattern from the underlayer to the layer.
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: May 23, 2006
    Assignee: Lam Research Corporation
    Inventors: Hanzhong Xiao, Helen H. Zhu, Kuo-Lung Tang, S. M. Reza Sadjadi
  • Patent number: 7041224
    Abstract: The etching of a material in a vapor phase etchant is disclosed where a vapor phase etchant is provided to an etching chamber at a total gas pressure of 10 Torr or more, preferably 20 Torr or even 200 Torr or more. The vapor phase etchant can be gaseous acid etchant, a noble gas halide or an interhalogen. The sample/workpiece that is etched can be, for example, a semiconductor device or MEMS device, etc. The material that is etched/removed by the vapor phase etchant is preferably silicon and the vapor phase etchant is preferably provided along with one or more diluents. Another feature of the etching system includes the ability to accurately determine the end point of the etch step, such as by creating an impedance at the exit of the etching chamber (or downstream thereof) so that when the vapor phase etchant passes from the etching chamber, a gaseous product of the etching reaction is monitored, and the end point of the removal process can be determined.
    Type: Grant
    Filed: March 22, 2002
    Date of Patent: May 9, 2006
    Assignee: Reflectivity, Inc.
    Inventors: Satyadev R. Patel, Gregory P. Schaadt, Douglas B. MacDonald, Hongqin Shi, Andrew G. Huibers, Peter Heureux
  • Patent number: 7037848
    Abstract: In one aspect, the invention encompasses a method of etching insulative materials which comprise complexes of metal and oxygen. The insulative materials are exposed to physical etching conditions within a reaction chamber and in the presence of at least one oxygen-containing gas. In another aspect, the invention encompasses a method of forming a capacitor. An electrically conductive first layer is formed over a substrate, and a second layer is formed over the first layer. The second layer is a dielectric layer and comprises a complex of metal and oxygen. A conductive third layer is formed over the second layer. The first, second and third layers are patterned into a capacitor construction. The patterning of the second layer comprises exposing the second layer to at least one oxygen-containing gas while also exposing the second layer to physical etching conditions.
    Type: Grant
    Filed: June 17, 2004
    Date of Patent: May 2, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Daryl C. New
  • Patent number: 7018934
    Abstract: Method and apparatus for etching a metal layer disposed on a substrate, such as a photomask, are provided. In one aspect, a method is provided for processing a substrate including positioning the substrate in a processing chamber, introducing a processing gas comprising (i) hydrogen chloride, (ii) an oxygen containing gas, (iii) another chlorine containing gas, and optionally, (iv) an inert gas into the processing chamber, wherein the substrate is maintained at a reduced temperature, and the processing gas is excited into a plasma state at a reduced power level to etch exposed portions of the metal layer disposed on the substrate.
    Type: Grant
    Filed: September 4, 2002
    Date of Patent: March 28, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Melisa J. Buie, Brigitte C. Stoehr
  • Patent number: 7008547
    Abstract: Provided is a solid phase array of electrical sensors, each comprising a channel and electrical leads for attaching to a voltage, current or resistivity meter for measuring the voltage, current or resistivity through the pore, wherein the channels are formed of a single substrate.
    Type: Grant
    Filed: March 7, 2003
    Date of Patent: March 7, 2006
    Assignee: Sarnoff Corporation
    Inventors: Jia Ming Chen, Yongchi Tian, Zilan Shen, Pradyumna Swain
  • Patent number: 7005247
    Abstract: A method of fabricating an optical component includes forming a mask on an optical component precursor. The method also includes etching through at least a portion of the mask so as to etch an underlying medium concurrently with remaining mask and transfer a feature of an upper surface of the mask onto an upper surface of the underlying medium. The etch can be configured such that a ratio of the underlying medium etch rate to the mask etch rate is less than about 1.5:1. In some instances, the underlying medium is silicon and the mask is a photoresist.
    Type: Grant
    Filed: January 15, 2003
    Date of Patent: February 28, 2006
    Assignee: Kotusa, Inc.
    Inventors: Joan Fong, Wei Qian, Dawei Zheng, Zhian Shao, Lih-Jou Chung, Xiaoming Yin
  • Patent number: 6991944
    Abstract: This invention relates to a process for treatment of a multi-layer wafer with materials having differential thermal characteristics, the process comprising a high temperature heat treatment step that can generate secondary defects, characterised in that this process includes a wafer surface preparation step before the high temperature heat treatment step.
    Type: Grant
    Filed: August 10, 2004
    Date of Patent: January 31, 2006
    Assignees: S.O.I.Tec Silicon on Insulation Technologies S.A., Commissariat à l'Energie Atomique (CEA)
    Inventors: Olivier Rayssac, Beryl Blondeau, Hubert Moriceau, Christelle Lagahe-Blanchard, Franck Fournel
  • Patent number: 6984436
    Abstract: In homogeneous materials, etching characteristics depend on properties inherent in these materials regardless of whether they are isotropic or anisotropic, and there have been limitations in realizing various desired shapes. A subject for the invention is to provide a gradient material which eliminates these limitations. A gradient material is provided in which the rate of etching with a specific chemical substance changes continuously or by steps from the outermost surface to an inner part thereof. This gradient material is made of a main material which contains an additive capable of changing the etching rate of the main material so that the concentration of the additive changes continuously or by steps. Especially when a glass material containing SiO2 as the main component is used as the main material and fluorine is used as the additive, then a gradient material in which the rate of etching with an aqueous solution of hydrofluoric acid changes in the depth direction can be obtained.
    Type: Grant
    Filed: July 16, 2001
    Date of Patent: January 10, 2006
    Assignees: National Institute of Advanced Industrial Science and Technology, Nippon Sheet Glass Co., Ltd.
    Inventors: Junji Nishii, Tadashi Koyama, Jun Yamaguchi
  • Patent number: 6961995
    Abstract: An electronic package and method of making the electronic package is provided. A layer of dielectric material is positioned on a first surface of a substrate which includes a plurality of conductive contacts. At least one through hole is formed in the layer of dielectric material in alignment with at least one of the plurality of conductive contacts. A conductive material is positioned in the at least one through hole substantially filling the through hole. At least one conductive member is positioned on the conductive material in the through hole and in electrical contact with the conductive material. The electronic package improves field operating life of an assembly which includes a semiconductor chip attached to a second surface of the substrate and a printed wiring board attached to the conductive members.
    Type: Grant
    Filed: September 19, 2002
    Date of Patent: November 8, 2005
    Assignee: International Business Machines Corporation
    Inventors: Lisa J. Jimarez, Miguel A. Jimarez, Voya R. Markovich, Cynthia S. Milkovich, Charles H. Perry, Brenda L. Peterson
  • Patent number: 6962771
    Abstract: Key to the present invention is the subsequent use of two layers of different positive photoresists, possessing different exposure wavelength sensitivities. It is a general object of the present invention to provide a new and improved method of forming semiconductor integrated circuit devices, and more specifically, in the formation of self-aligned dual damascene interconnects and vias, which incorporates two positive photoresist systems, which have different wavelength sensitivities, to form trench/via openings with only a two-step etching process. In addition, the two layers of photoresist exhibit different etch resistant properties, for subsequent selective reactive ion etching steps. The use of a “high contrast” positive photoresist system has been developed wherein the resist system exposure sensitivity is optimized for wavelengths, deep-UV (248 nm) for the top layer of resist, the trench pattern, and I-line (365 nm) for the bottom layer of resist, the via pattern.
    Type: Grant
    Filed: October 13, 2000
    Date of Patent: November 8, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Shi Liu, Chih-Cheng Lin
  • Patent number: 6942811
    Abstract: The etching of a sacrificial silicon portion in a microstructure such as a microelectromechanical structure by the use of etchant gases that are noble gas fluorides or halogen fluorides is performed with greater selectivity toward the silicon portion relative to other portions of the microstructure by slowing the etch rate. The etch rate is preferably 30 um/hr or less, and can be 3 um/hr or even less. The selectivity is also improved by the addition of non-etchant gaseous additives to the etchant gas. Preferably the non-etchant gaseous additives that have a molar-averaged formula weight that is below that of molecular nitrogen offer significant advantages over gaseous additives of higher formula weights by causing completion of the etch in a shorter period of time while still achieving the same improvement in selectivity. The etch process is also enhanced by the ability to accurately determine the end point of the removal step.
    Type: Grant
    Filed: September 17, 2001
    Date of Patent: September 13, 2005
    Assignee: Reflectivity, Inc
    Inventors: Satyadev R. Patel, Gregory P. Schaadt, Douglas B. MacDonald, Hongqin Shi
  • Patent number: 6932916
    Abstract: A method for etching trenches having different depths on a semiconductor substrate includes providing a mask with first and second openings. The first and second openings are located where corresponding first and second trenches are to be etched. A slow-etch region, made of a slow-etch material, is provided above the substrate at a location corresponding to the second opening. When exposed to a selected etchant, the slow-etch material is etched at a rate less than the rate at which the semiconductor substrate is etched when exposed to the selected etchant.
    Type: Grant
    Filed: April 29, 2003
    Date of Patent: August 23, 2005
    Assignee: Infineon Technologies AG
    Inventors: Dirk Manger, Hans-Peter Moll, Till Schloesser
  • Patent number: 6913704
    Abstract: A magnetic head including a dual layer induction coil. Following the deposition of a first magnetic pole (P1) a first induction coil is fabricated. Following a chemical mechanical polishing (CMP) step a layer of etchable insulation material is deposited followed by the fabrication of a second induction coil etching mask. A reactive ion etch process is then conducted to etch the second induction coil trenches into the second etchable insulation material layer. The etching depth is controlled by the width of the trenches in an aspect ratio dependent etching process step. The second induction coil is next fabricated into the second induction coil trenches, preferably utilizing electrodeposition techniques. Thereafter, an insulation layer is deposited upon the second induction coil, followed by the fabrication of a second magnetic pole (P2) upon the insulation layer.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: July 5, 2005
    Assignee: Hitachi Global Storage Technologies Netherlands, B.V.
    Inventors: Richard Hsiao, Yiping Hsiao
  • Patent number: 6896821
    Abstract: A method of making an etched structure in the fabrication of a MEMS device involves depositing a bulk layer, typically of polysilicon, prone to surface roughness. At least one layer of photo-insensitive spin-on planarizing material, such as silicate-based spin-on glass, is formed on the bulk layer to reduce surface roughness. This is patterned with a photoresist layer. A deep etch is then performed through the photoresist layer into the bulk layer. This technique results in much more precise etch structures.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: May 24, 2005
    Assignee: DALSA Semiconductor Inc.
    Inventor: Luc Louellet
  • Patent number: 6893969
    Abstract: Method for etching organic low-k dielectric using ammonia, NH3, as an active etchant. Processes using ammonia results in at least double the etch rate of organic low-k dielectric materials than processes using N2/H2 chemistries, at similar process conditions. The difference is due to the much lower ionization potential of NH3 versus N2 in the process chemistry, which results in significantly higher plasma densities and etchant concentrations at similar process conditions.
    Type: Grant
    Filed: February 12, 2001
    Date of Patent: May 17, 2005
    Assignee: Lam Research Corporation
    Inventors: Chok W. Ho, Kuo-Lung Tang, Chung-Ju Lee
  • Patent number: 6881351
    Abstract: A method for contacting an electrically conductive layer overlying a magnetoelectronics element includes forming a memory element layer overlying a dielectric region. A first electrically conductive layer is deposited overlying the memory element layer. A first dielectric layer is deposited overlying the first electrically conductive layer and is patterned and etched to form a first masking layer. Using the first masking layer, the first electrically conductive layer is etched. A second dielectric layer is deposited overlying the first masking layer and the dielectric region. A portion of the second dielectric layer is removed to expose the first masking layer. The second dielectric layer and the first masking layer are subjected to an etching chemistry such that the first masking layer is etched at a faster rate than the second dielectric layer. The etching exposes the first electrically conductive layer.
    Type: Grant
    Filed: April 22, 2003
    Date of Patent: April 19, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Gregory W. Grynkewich, Brian R. Butcher, Mark A. Durlam, Kelly Kyler, Charles A. Synder, Kenneth H. Smith, Clarence J. Tracy, Richard Williams
  • Patent number: 6878300
    Abstract: In one embodiment, the invention includes a method of removing at least a portion of a material from a substrate. The method includes providing a substrate in a reaction chamber, the substrate having a material supported thereover, and first etching the material while the substrate is in the reaction chamber. The method also includes, after the first etching, cleaning a component from at least one sidewall of the reaction chamber while the substrate remains therein; the component comprising a species that is present in the material. The cleaning includes exposing the sidewall and substrate to conditions which substantially selectively remove the component from the sidewall while not removing the material from the substrate, and not etching any other materials supported by the substrate. After the cleaning, the method includes second etching the material while the substrate is in the reaction chamber.
    Type: Grant
    Filed: October 1, 2002
    Date of Patent: April 12, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Tuman Earl Allen, III
  • Patent number: 6869542
    Abstract: Form an opening in a dielectric layer formed on a substrate comprises depositing a hard mask composed of an etch resistant material over a dielectric layer, e.g. a silicon oxide. Use a photoresist mask to expose the hard mask. Use a fluorocarbon plasma to etch through the window to form an opening through the hard mask. Then etch through the hard mask opening to pattern the dielectric layer. The hard mask comprises an RCH/RCHX material with the structural formula R:C:H or R:C:H:X, where R is selected from Si, Ge, B, Sn, Fe, Ti and X is selected from O, N, S and F. The plasma etching process employs a) a gas mixture comprising N2; fluorocarbon (CHF3, C4F8, C4F6, CF4, CH2F2, CH3F); an oxidizer (O2, CO2), and a noble diluent (Ar, He); b) a high DC bias (500-3000 Volts bias on the wafer); 3) medium pressure (20-100 mT.; and d) moderate temperatures (?20 to 60°).
    Type: Grant
    Filed: March 12, 2003
    Date of Patent: March 22, 2005
    Assignee: International Business Machines Corporation
    Inventors: Sadanand V. Desphande, David Dobuzinsky, Arpan P. Mahorowala, Tina Wagner, Richard Wise
  • Patent number: 6858153
    Abstract: A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications. A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide. The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects.
    Type: Grant
    Filed: November 5, 2001
    Date of Patent: February 22, 2005
    Assignee: Applied Materials Inc.
    Inventors: Claes H. Bjorkman, Min Melissa Yu, Hongquing Shan, David W. Cheung, Wai-Fan Yau, Kuowei Liu, Nasreen Gazala Chapra, Gerald Yin, Farhad K. Moghadam, Judy H. Huang, Dennis Yost, Betty Tang, Yunsang Kim
  • Patent number: 6849191
    Abstract: According to the present invention, there is provided a sample surface treating apparatus for processing a fine pattern by plasma etching, including a stage provided in a chamber, on which a sample to be subjected to a surface treatment is placed; etching gas supply source for continuously supplying an etching gas for plasma generation into the chamber; a plasma generator for generating a high-density plasma in the chamber; a bias power supply for applying a bias voltage of 100 kHz or higher to the stage independently of the plasma generation; and a pulse modulator for modulating the bias power supply at a frequency of 100 Hz to 10 kHz, wherein a surface treatment in which the minimum feature size is 1 ?m or smaller is performed on the sample placed on the stage.
    Type: Grant
    Filed: February 12, 1999
    Date of Patent: February 1, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Tetsuo Ono, Tatsumi Mizutani, Ryouji Hamasaki, Tokuo Kure, Takafumi Tokunaga, Masayuki Kojima
  • Patent number: 6849193
    Abstract: An oxide etching process, particularly useful for selectively etching oxide over a feature having a non-oxide composition, such as silicon nitride and especially when that feature has a corner that is prone to faceting during the oxide etch. The invention uses a heavy perfluorocarbon, for example, hexafluorobutadiene (C4F6) or hexafluorobenzene (C6F6). The fluorocarbon together with a substantial amount of a noble gas such as argon is excited into a high-density plasma in a reactor which inductively couples plasma source power into the chamber and RF biases the pedestal electrode supporting the wafer. A more strongly polymerizing fluorocarbon such as difluoromethane (CH2F2) is added in the over etch to protect the nitride corner. Oxygen or nitrogen may be added to counteract the polymerization. The same chemistry can be used in a magnetically enhanced reactive ion etcher (MERIE) or with a remote plasma source.
    Type: Grant
    Filed: May 13, 2002
    Date of Patent: February 1, 2005
    Inventors: Hoiman Hung, Joseph P Caulfield, Hongqing Shan, Ruiping Wang, Gerald Zheyao Yin
  • Patent number: 6833079
    Abstract: The present disclosure pertains to our discovery of a method of etching a shaped cavity in a substrate, where the shaped cavity has a width that is at least as great as its depth. We have discovered that by varying the process chamber pressure during etching of the shaped cavity, we can control lateral etching of the shaped cavity, while allowing the removal of etch process byproducts from the shaped cavity during continued etching. The method of the invention can be used to etch shaped cavities having round or horizontal elliptical shapes. The method of the invention is particularly useful in the etching of buried cavities, where removal of etch byproducts from the cavity can be difficult.
    Type: Grant
    Filed: February 17, 2000
    Date of Patent: December 21, 2004
    Assignee: Applied Materials Inc.
    Inventor: Sara Giordani
  • Patent number: 6827868
    Abstract: A method of forming a fuse structure in which passivating material over the fuse has a controlled, substantially uniform thickness that is provided after C4 metallurgy formation. A laser fuse deletion process for the fuse formed by this method is also disclosed.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: December 7, 2004
    Assignee: International Business Machines Corporation
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, William T. Motsiff