Etching Silicon Containing Substrate Patents (Class 216/79)
  • Patent number: 8512586
    Abstract: A method and system for performing gas cluster ion beam (GCIB) etch processing of various materials is described. In particular, the GCIB etch processing includes setting one or more GCIB properties of a GCIB process condition for the GCIB to achieve one or more target etch process metrics.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: August 20, 2013
    Assignee: TEL Epion Inc.
    Inventors: Martin D. Tabat, Christopher K. Olsen, Yan Shao, Ruairidh MacCrimmon
  • Patent number: 8501630
    Abstract: A method for selectively etching a substrate is described. The method includes preparing a substrate comprising a silicon nitride layer overlying a silicon-containing contact region, and patterning the silicon nitride layer to expose the silicon-containing contact region using a plasma etching process in a plasma etching system. The plasma etching process uses a process composition having as incipient ingredients a process gas containing C, H and F, and a non-oxygen-containing additive gas, wherein the non-oxygen-containing additive gas includes H, or C, or both H and C, and excludes a halogen atom.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: August 6, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Andrew W. Metz, Hongyun Cottle
  • Patent number: 8501020
    Abstract: A method for making a three-dimensional nano-structure array includes following steps. First, a substrate is provided. Next, a mask is formed on the substrate. The mask is a monolayer nanosphere array or a film defining a number of holes arranged in an array. The mask is then tailored and simultaneously the substrate is etched by the mask. Lastly, the mask is removed.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: August 6, 2013
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Zhen-Dong Zhu, Qun-Qing Li, Shou-Shan Fan
  • Patent number: 8501604
    Abstract: A method of forming a doped region in a semiconductor layer of a substrate by alloying with doping elements is disclosed. In one aspect, the method includes screen printing a paste layer of doping element paste to the substrate and firing the screen printed paste layer of doping element paste, wherein a highly pure doping element layer is applied to the semiconductor layer after which the paste layer is screen printed to the doping element layer.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: August 6, 2013
    Assignee: IMEC
    Inventor: Sukhvinder Singh
  • Patent number: 8492280
    Abstract: Embodiments of the invention may include first providing a stack of layers including a semiconductor substrate, a buried oxide layer on the semiconductor substrate, a semiconductor-on-insulator layer on the buried-oxide layer, a nitride layer on the semiconductor-on-insulator layer, and a silicon oxide layer on the nitride layer. A first opening and second opening with a smaller cross-sectional area than the first opening are then formed in the silicon oxide layer, the nitride layer, the semiconductor-on-insulator layer, and the buried-oxide layer. The first opening and the second opening are then etched with a first etching gas. The first opening and the second opening are then etched with a second etching gas, which includes the first etching gas and a halogenated silicon compound, for example, silicon tetrafluoride or silicon tetrachloride. In one embodiment, the first etching gas includes hydrogen bromide, nitrogen trifluoride, and oxygen.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Habib Hichri, Xi Li, Richard S. Wise
  • Patent number: 8492285
    Abstract: A dry etching method for texturing a surface of a substrate is disclosed. The method includes performing a first dry etching onto the surface of the substrate thereby forming a surface texture with spikes and valleys, the first dry etching comprising etching the surface of the substrate in a plasma comprising fluorine (F) radicals and oxygen (O) radicals, wherein the plasma comprises an excess of oxygen (O) radicals. The method may further include performing a second dry etching onto the surface texture thereby smoothening the surface texture, the second dry etching comprising chemical isotropic etching the surface texture, obtained after the first dry etching, in a plasma comprising fluorine (F) radicals, wherein the spikes are etched substantially faster than the valleys.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: July 23, 2013
    Assignee: IMEC
    Inventor: Boon Teik Chan
  • Patent number: 8475666
    Abstract: A toughening agent composition for increasing the hydrophobicity of an organosilicate glass dielectric film when applied to said film. It includes a component capable of alkylating or arylating silanol moieties of the organosilicate glass dielectric film via silylation, and an activating agent selected from the group consisting of an amine, an onium compound and an alkali metal hydroxide.
    Type: Grant
    Filed: September 15, 2004
    Date of Patent: July 2, 2013
    Assignee: Honeywell International Inc.
    Inventors: Teresa A. Ramos, Robert R. Roth, Anil S. Bhanap, Paul G. Apen, Denis H. Endisch, Brian J. Daniels, Ananth Naman, Nancy Iwamoto, Roger Y. Leung
  • Publication number: 20130165365
    Abstract: There are provided a processing liquid for suppressing pattern collapse of a microstructure which includes at least one compound selected from the group consisting of an imidazolium halide containing an alkyl group having 12, 14 or 16 carbon atoms, a pyridinium halide containing an alkyl group having 14 or 16 carbon atoms and an ammonium halide containing an alkyl group having 16 or 18 carbon atoms, and water; and a method for producing a microstructure formed of silicon oxide using the processing liquid.
    Type: Application
    Filed: July 14, 2011
    Publication date: June 27, 2013
    Applicant: MITSUBISHI GAS CHEMICAL COMPANY, INC.
    Inventors: Hiroshi Matsunaga, Masaru Ohto
  • Patent number: 8470190
    Abstract: A method for processing at least one wall of an opening formed in a silicon substrate, successively including the steps of implanting fluorine atoms into an upper portion of the wall of the opening, performing an oxidization step, and applying a specific processing to at least a portion of the non-implanted portion of the opening.
    Type: Grant
    Filed: July 16, 2008
    Date of Patent: June 25, 2013
    Assignee: STMicroelectronics S.A.
    Inventors: Edgard Jeanne, Sylvain Nizou
  • Patent number: 8465660
    Abstract: A blazed grating is disclosed as well as mode hop-free tunable lasers and a process for fabricating gratings of this type. The grating lies in a general plane and includes a plurality of elongate beams carrying mutually parallel respective reflection surfaces spaced apart from one another with a predefined pitch, each of these reflection surfaces having a normal direction inclined at a grating angle ? to the normal direction of the general plane. The grating includes a plurality of resilient suspension arms connected to the beams and intended to be fastened to a grating support. A first pair of comb electrodes is provided for applying a mechanical force to this assembly, being placed on a first side of the grating, along an axis transverse to the beams, and designed so as to allow the pitch of the grating to be modified in response to the application of the mechanical force.
    Type: Grant
    Filed: January 22, 2007
    Date of Patent: June 18, 2013
    Assignee: CSEM Centre Suisse d'Electronique et de Microtechnique SA-Recherche et Developpement
    Inventors: Ross Stanley, Maurizio Tormen, Rino Kunz, Philippe Niedermann
  • Patent number: 8444867
    Abstract: A method for forming patterns on a wafer includes forming a fence having a sloped face in an edge portion of the wafer. The sloped face is direct to an inside of the wafer. A first photoresist layer is formed which extends to cover the fence on the wafer. First photoresist patterns are formed by performing a first exposure and development on the first photoresist layer. An etch process is performed using the first photoresist patterns and the fence as an etch mask. The fence is formed by selectively exposing a negative resist using a light shielding blade, and at this time, the first photoresist layer is formed including a positive resist.
    Type: Grant
    Filed: October 20, 2009
    Date of Patent: May 21, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hyun Jo Yang
  • Patent number: 8440574
    Abstract: A method for ashing hardened resist from a photoresist patterned chromium alloy post etch using a plasma ashing chemistry which contains no gaseous source of hydrogen and contains a gaseous source of oxygen and a gaseous source of nitrogen with an oxygen to nitrogen atomic ratio of at least 5.
    Type: Grant
    Filed: October 12, 2009
    Date of Patent: May 14, 2013
    Assignee: Texas Instruments Incorporated
    Inventor: Abbas Ali
  • Patent number: 8437585
    Abstract: A passive optical waveguide is solely built on a Si substrate while still maintaining high optical quality. Two side-by-side diamond shaped cavities may be etched into the Si wafer and oxide grown on the inner walls of the cavities until the oxide meets at opposing inner vertices of the diamond shaped cavities. An optical waveguide is formed by the inverted, generally triangular cross-sectional, portion of silicon remaining between the top surface of the wafer and the opposing inner vertices.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: May 7, 2013
    Assignee: Intel Corporation
    Inventor: Yun-Chung N. Na
  • Publication number: 20130095574
    Abstract: Silicon microcarriers suitable for fluorescent assays as a well as a method of producing such microcarriers are provided. The method includes the steps of providing a SOI wafer having a bottom layer of monocristalline silicone, an insulator layer and a bottom layer of monocristalline silicon, delineating microparticles, etching away the insulator layer and then depositing an oxide layer on the wafer still holding the microparticles before finally lifting-off the microparticles.
    Type: Application
    Filed: April 13, 2012
    Publication date: April 18, 2013
    Applicant: BIOCARTIS SA
    Inventors: Nicolas DEMIERRE, Stephan GAMPER
  • Patent number: 8420547
    Abstract: A plasma processing method performed in a plasma processing apparatus including a processing chamber accommodating a substrate in which a plasma is generated; a mounting table mounting the substrate, which is provided in the processing chamber and to which a plasma attraction high frequency voltage is applied; and a facing electrode provided to face the mounting table in the processing chamber, to which a negative DC voltage is applied, the method including: applying a plasma attraction high frequency voltage to the mounting table for a predetermined period of time; and stopping the application of the plasma attraction high frequency voltage to the mounting table. In the plasma processing method, the application of the plasma attraction high frequency voltage and stopping thereof are alternately repeated.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: April 16, 2013
    Assignee: Tokyo Electron Limited
    Inventor: Yoshinobu Ooya
  • Patent number: 8414787
    Abstract: Methods and devices for selective etching in a semiconductor process are shown. Chemical species generated in a reaction chamber provide both a selective etching function and concurrently form a protective coating on other regions. An electron beam provides activation to selective chemical species. In one example, reactive species are generated from a plasma source to provide an increased reactive species density. Addition of other gasses to the system can provide functions such as controlling a chemistry in a protective layer during a processing operation. In one example an electron beam array such as a carbon nanotube array is used to selectively expose a surface during a processing operation.
    Type: Grant
    Filed: May 14, 2010
    Date of Patent: April 9, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Neal R. Rueger, Mark J. Williamson, Gurtej S. Sandhu
  • Patent number: 8404595
    Abstract: A plasma processing method for processing a target substrate uses a plasma processing apparatus which includes a vacuum evacuable processing vessel for accommodating the target substrate therein, a first electrode disposed in the processing vessel and connected to a first RF power supply for plasma generation and a second electrode disposed to face the first electrode. The method includes exciting a processing gas containing fluorocarbon in the processing vessel to generate a plasma while applying a negative DC voltage having an absolute value ranging from about 100 V to 1500 V or an RF power of a frequency lower than about 4 MHz to the second electrode. The target layer is etched by the plasma, thus forming recesses on the etching target layer based on the pattern of the resist layer.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: March 26, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Masanobu Honda, Manabu Sato, Yoshiki Igarashi
  • Patent number: 8398867
    Abstract: Method for producing a probe for atomic force microscopy with a silicon nitride cantilever and an integrated single crystal silicon tetrahedral tip with high resonant frequencies and low spring constants intended for high speed AFM imaging.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: March 19, 2013
    Inventor: Chung Hoon Lee
  • Patent number: 8398870
    Abstract: There is provided a method for manufacturing a perpendicular magnetic recording medium that includes a step for forming a smooth substrate surface without generating abnormal protrusions or the like when forming a magnetic film or the like on the surface of the substrate, the method for manufacturing a perpendicular magnetic recording medium characterized by including a polishing step in which the surface of a non-magnetic substrate is smoothed before forming the laminated structure on top of the non-magnetic substrate, wherein a polishing liquid used in the polishing step contains diamond particles within a range from 0.001 to 0.05% by mass and also contains a polishing accelerator within a range from 10 to 100 times the amount of diamond particles, and the polishing accelerator is an organic polymer material containing a sulfonic group or a carboxylic group and having an average molecular weight of 4,000 to 10,000.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: March 19, 2013
    Assignee: Showa Denko K.K.
    Inventor: Ryuji Sakaguchi
  • Patent number: 8388854
    Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a first block on a nanodot material, forming a first spacer on the first block, removing the first block to form a free standing spacer, removing exposed portions of the nanodot material and then the free standing spacer to form nanowires, forming a second block at an angle to a length of the nanowires, forming a second spacer on the second block, forming a second free standing spacer on the nanowires by removing the second block, and removing exposed portions of the nanowires and then the second free standing spacer to form an ordered array of nanodots.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: March 5, 2013
    Assignee: Intel Corporation
    Inventors: Brian Doyle, Been-Yih Jin, Jack Kavalieros, Robert Chau
  • Publication number: 20130043213
    Abstract: The utilization of single crystal diamond in a nano- or micro-machine (N/MEMS) device is difficult, and there has been no report on such utilization. The reason for this resides in that it is difficult to grow single crystal diamond on an oxide which is a sacrifice layer. In a conventional technique, a cantilever or the like is produced by forming polycrystalline diamond or nanodiamond on an oxide as a sacrifice layer, but the mechanical performance, vibration characteristics, stability, and reproducibility of the produced cantilever or the like are unsatisfactory. In the present invention, utilizing the fact that the high concentration ion-implanted region in a diamond substrate 101 is modified into graphite, the layer 104 modified into graphite as a sacrifice layer is removed by electrochemical etching to obtain the diamond layer remaining on the resultant substrate as a movable structure. The produced cantilever 106 exhibited high frequency resonance.
    Type: Application
    Filed: February 18, 2011
    Publication date: February 21, 2013
    Inventors: Meiyong Liao, Yasuo Koide, Shunichi Hishida
  • Patent number: 8377323
    Abstract: A mold is for obtaining, on a substrate, an array of carbon nanotubes with a high control of their positioning. The mold includes a first layer of a first preset material having a surface having in relief at least one first plurality of projections having a free end portion with a substantially pointed profile.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: February 19, 2013
    Assignee: STMicroelectronics S.R.L.
    Inventors: Raffaele Vecchione, Luigi Occhipinti
  • Patent number: 8372756
    Abstract: A process for selectively etching a material comprising SiO2 over silicon, the method comprising the steps of: placing a silicon substrate comprising a layer of a material comprising SiO2 within a reactor chamber equipped with an energy source; creating a vacuum within the chamber; introducing into the reactor chamber a reactive gas mixture comprising a fluorine compound, a polymerizable fluorocarbon, and an inert gas, wherein the reactive gas mixture is substantially free of added oxygen; activating the energy source to form a plasma activated reactive etching gas mixture within the chamber; and selectively etching the material comprising SiO2 preferentially to the silicon substrate.
    Type: Grant
    Filed: July 16, 2009
    Date of Patent: February 12, 2013
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Glenn Michael Mitchell, Stephen Andrew Motika, Andrew David Johnson
  • Patent number: 8366949
    Abstract: A mold for producing microlenses or a microlens array is produced by sequentially carrying out an etching step of forming quadrangular pyramid concave parts on a single crystal silicon substrate by anisotropic etching and an ion etching step of forming molding concave parts with spherical or cylindrical surface parts from the quadrangular pyramid concave parts.
    Type: Grant
    Filed: August 17, 2006
    Date of Patent: February 5, 2013
    Inventor: Kiichi Takamoto
  • Patent number: 8367769
    Abstract: Embodiments of the invention provide silicon-based nanoparticle composites, where the silicon nanoparticles are highly luminescent. Preferred embodiments of the invention are Si—O solid composite networks, e.g., glass, having a homogenous distribution of luminescent hydrogen terminated silicon nanoparticles in a homogenous distribution throughout the solid. Embodiments of the invention also provide fabrication processes for silicon-based silicon nanoparticle composites. A preferred method for forming a silicon-based nanoparticle composite disperses hydrogen terminated silicon nanoparticles and an inorganic precursor of an organosilicon gel in an aprotic solvent to form a sol. A catalyst is mixed into the sol. The sol is then permitted to dry into a gel of the silicon-based nanoparticle composite.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: February 5, 2013
    Assignee: NanoSi Advanced Technologies, Inc.
    Inventors: Abdullah Saleh Aldwayyan, Mohamad Saleh AlSalhi, Abdurahman Mohammed Aldukhail, Mansour S. Alhoshan, Muhammad Naziruddin Khan, Ghassan K. Al-Chaar, Munir Nayfeh
  • Patent number: 8298959
    Abstract: Embodiments of the invention relate to a substrate etching method and apparatus. In one embodiment, a method for etching a substrate in a plasma etch reactor is provided that includes a) depositing a polymer on a substrate in an etch reactor, b) etching the substrate using a gas mixture including a fluorine-containing gas and oxygen in the etch reactor, c) etching a silicon-containing layer the substrate using a fluorine-containing gas without mixing oxygen in the etch reactor, and d) repeating a), b) and c) until an endpoint of a feature etched into the silicon-containing layer is reached.
    Type: Grant
    Filed: May 24, 2010
    Date of Patent: October 30, 2012
    Assignee: Applied Materials, Inc.
    Inventor: Alan Cheshire
  • Publication number: 20120261627
    Abstract: Some embodiments include methods of removing silicon dioxide in which the silicon dioxide is exposed to a mixture that includes activated hydrogen and at least one primary, secondary, tertiary or quaternary ammonium halide. The mixture may also include one or more of thallium, BX3 and PQ3, where X and Q are halides. Some embodiments include methods of selectively etching undoped silicon dioxide relative to doped silicon dioxide, in which thallium is incorporated into the doped silicon dioxide prior to the etching. Some embodiments include compositions of matter containing silicon dioxide doped with thallium to a concentration of from about 1 weight % to about 10 weight %.
    Type: Application
    Filed: June 22, 2012
    Publication date: October 18, 2012
    Applicant: Micron Technology, Inc.
    Inventor: Nishant Sinha
  • Patent number: 8273260
    Abstract: A method of etching a semiconductor wafer is provided. The method comprises the steps of: jetting a mixed gas including hydrogen fluoride and ozone onto a surface of a semiconductor wafer; monitoring the surface of the semiconductor wafer; analyzing the surface of the semiconductor wafer; and adjusting at least one of the hydrogen fluoride concentration and the ozone concentration in the mixed gas based on a result of the analysis.
    Type: Grant
    Filed: May 13, 2009
    Date of Patent: September 25, 2012
    Assignee: Sumco Techxiv Corporation
    Inventors: Kazuaki Kozasa, Tomonori Kawasaki
  • Patent number: 8262920
    Abstract: A method for forming features in a silicon layer is provided. A mask is formed with a plurality of mask openings over the silicon layer. A polymer layer is deposited over the mask by flowing a hydrogen free deposition gas comprising C4F8, forming a plasma from the deposition gas, depositing a polymer from the plasma for at least 20 seconds, and stopping the depositing the polymer after the at least 20 seconds. The deposited polymer layer is opened by flowing an opening gas, forming a plasma from the opening gas which selectively removes the deposited polymer on bottoms of the plurality of mask openings with respect to deposited polymer on sides of the plurality of mask openings, and stopping the opening when at least some of the plurality of mask features are opened. The silicon layer is etched through the mask and deposited polymer layer.
    Type: Grant
    Filed: June 18, 2007
    Date of Patent: September 11, 2012
    Assignee: Lam Research Corporation
    Inventors: Tamarak Pandhumsoporn, Patrick Chung, Jackie Seto, S. M. Reza Sadjadi
  • Patent number: 8252194
    Abstract: A method of removing at least a portion of a silicon oxide material is disclosed. The silicon oxide is removed by exposing a semiconductor structure comprising a substrate and the silicon oxide to an ammonium fluoride chemical treatment and a subsequent plasma treatment, both of which may be effected in the same vacuum chamber of a processing apparatus. The ammonium fluoride chemical treatment converts the silicon oxide to a solid reaction product in a self-limiting reaction, the solid reaction product then being volatilized by the plasma treatment. The plasma treatment includes a plasma having an ion bombardment energy of less than or equal to approximately 20 eV. An ammonium fluoride chemical treatment including an alkylated ammonia derivative and hydrogen fluoride is also disclosed.
    Type: Grant
    Filed: May 2, 2008
    Date of Patent: August 28, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Mark W. Kiehlbauch, J. Neil Greeley, Paul A. Morgan
  • Patent number: 8231795
    Abstract: An acoustic device includes a transducer formed on a first surface of a substrate and an acoustic horn formed in the substrate by a dry-etching process through an opposing second surface of the substrate. The acoustic horn is positioned to amplify sound waves from the transducer and defines a non-linear cross-sectional profile.
    Type: Grant
    Filed: May 1, 2009
    Date of Patent: July 31, 2012
    Assignee: Avago Technologies Wireless IP (Singapore) Pte. Ltd.
    Inventors: David Martin, Joel Philliber, John Choy
  • Patent number: 8226840
    Abstract: Some embodiments include methods of removing silicon dioxide in which the silicon dioxide is exposed to a mixture that includes activated hydrogen and at least one primary, secondary, tertiary or quaternary ammonium halide. The mixture may also include one or more of thallium, BX3 and PQ3, where X and Q are halides. Some embodiments include methods of selectively etching undoped silicon dioxide relative to doped silicon dioxide, in which thallium is incorporated into the doped silicon dioxide prior to the etching. Some embodiments include compositions of matter containing silicon dioxide doped with thallium to a concentration of from about 1 weight % to about 10 weight %.
    Type: Grant
    Filed: May 2, 2008
    Date of Patent: July 24, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Nishant Sinha
  • Patent number: 8206605
    Abstract: A substrate processing method capable of preventing a reduction in productivity of the fabrication of a semiconductor device from a substrate. An HF gas is supplied toward a wafer having a thermally-oxidized film, a BPSG film, and a deposit film, to thereby selectively etch the BPSG film and the deposit film using fluorinated acid. A residual matter of H2SiF6 produced at the time of etching is decomposed into HF and SiF4 by being heated.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: June 26, 2012
    Assignee: Tokyo Electron Limited
    Inventor: Daisuke Hayashi
  • Patent number: 8202435
    Abstract: A method for selectively etching areas of a substrate is described. The method includes providing in a process chamber a substrate containing a first material having a film deposition surface and a second material having an etch surface. The method further includes forming a gas cluster ion beam (GCIB) from a pressurized gas containing a deposition-etch gas, and exposing the substrate to the GCIB to remove at least a portion of the second material from the etch surface and deposit a thin film on the film deposition surface of the first material. According to some embodiments, the deposition-etch gas may contain silicon (Si) and carbon (C), and it may possess a Si—C bond.
    Type: Grant
    Filed: August 1, 2008
    Date of Patent: June 19, 2012
    Assignee: TEL Epion Inc.
    Inventor: Martin D. Tabat
  • Patent number: 8187486
    Abstract: Etching of nitride and oxide layers with reactant gases is modulated by etching in different process regimes. High etch selectivity to silicon nitride is achieved in an adsorption regime where the partial pressure of the etchant is lower than its vapor pressure. Low etch selectivity to silicon nitride is achieved in a condensation regime where the partial pressure of the etchant is higher than its vapor pressure. By controlling partial pressure of the etchant, very high etch selectivity to silicon nitride may be achieved.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: May 29, 2012
    Assignee: Novellus Systems, Inc.
    Inventors: Xinye Liu, Chiukin Steven Lai
  • Patent number: 8173549
    Abstract: A first mask layer pattern including a plurality of parallel line portions is formed on an etch target layer on a semiconductor substrate. A sacrificial layer is formed on the first mask layer pattern and portions of the etch target layer between the parallel line portions of the first mask layer pattern. A second mask layer pattern is formed on the sacrificial layer, the second mask layer pattern including respective parallel lines disposed between respective adjacent ones of the parallel line portions of the first mask layer pattern, wherein adjacent line portions of the first mask layer pattern and the second mask layer pattern are separated by the sacrificial layer. A third mask layer pattern is formed including first and second portions covering respective first and second ends of the line portions of the first mask layer pattern and the second mask layer pattern and having an opening at the line portions of the first and second mask layer patterns between the first and second ends.
    Type: Grant
    Filed: June 3, 2009
    Date of Patent: May 8, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-ho Lee, Jae-hwang Sim, Jae-kwan Park, Jong-min Lee, Mo-seok Kim, Hyon-woo Kim
  • Patent number: 8173030
    Abstract: A method for forming a self-aligned hole through a substrate to form a fluid feed passage is provided by initially forming an insulating layer on a first side of a substrate having two opposing sides; and forming a feature on the insulating layer. Next, etch an opening through the insulating layer, such that the opening is physically aligned with the feature on the insulating layer; and coat the feature with a layer of protective material. Patterning the layer of protective material will expose the opening through the insulating layer. Dry etching from the first side of the substrate forms a blind feed hole in the substrate corresponding to the location of the opening in the insulating layer, the blind feed hole including a bottom. Subsequently, grind a second side of the substrate and blanket etch it to form a hole through the entire substrate.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: May 8, 2012
    Assignee: Eastman Kodak Company
    Inventors: John Andrew Lebens, Weibin Zhang, Christopher Newell Delametter
  • Patent number: 8143175
    Abstract: The invention provides a dry etching method for performing a wiring process on a semiconductor substrate using a plasma etching apparatus, wherein the wiring process is performed without causing disconnection or deflection of the wiring. The invention provides a dry etching method for performing a wiring process on a semiconductor substrate using a plasma etching apparatus, wherein during a step for etching a material 12 to be etched using a mask pattern composed of a photoresist 15 and inorganic films 14 and 13 made of SiN, SiON, SiO and the like formed on the material 12 to be etched, a mixed gas formed of a halogen-based gas such as chlorine-containing gas or bromine-containing gas and at least one fluorine-containing gas selected from a group of fluorine-containing gases composed of CF4, CHF3, SF6 and NF3 is used to reduce the mask pattern and the processing dimension of the material to be etched substantially equally during processing of the material 12 to be etched.
    Type: Grant
    Filed: May 5, 2009
    Date of Patent: March 27, 2012
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Satoshi Une, Masamichi Sakaguchi, Kenichi Kuwabara, Tomoyoshi Ichimaru
  • Patent number: 8138096
    Abstract: In a plasma etching method, a substrate including an underlying film, an insulating film and a resist mask is plasma etched to thereby form a number of holes in the insulating film including a dense region and a sparse region by using a parallel plate plasma etching apparatus for applying a plasma-generating high frequency electric power to a space between an upper and a lower electrode and a biasing high frequency electric power to the lower electrode. The plasma etching method includes mounting the substrate on a mounting table; supplying a first process gas containing carbon and fluorine to form the holes in the insulating film to a depth close to the underlying film; and supplying a second process gas including an inert gas and another gas contain carbon and fluorine to have the holes reach the underlying film while applying a negative DC voltage to the upper electrode.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: March 20, 2012
    Assignee: Tokyo Electron Limited
    Inventor: Ryoichi Yoshida
  • Patent number: 8119019
    Abstract: A method of fabricating a printhead ejection nozzle is provided which includes depositing sacrificial material on a planar substrate form a scaffold of the sacrificial material on the substrate, defining openings in the sacrificial material to the plane of the substrate at positions for sidewalls of a nozzle chamber and a filter structure for the nozzle chamber, depositing roof material over, and into the openings of, the sacrificial material so as to form the sidewalls of the nozzle chamber on the substrate, a roof of the nozzle chamber bridging the sidewalls, and the filter structure, etching the roof material to the sacrificial material to form a nozzle aperture through the roof of the nozzle chamber, and removing the sacrificial material.
    Type: Grant
    Filed: November 27, 2008
    Date of Patent: February 21, 2012
    Assignee: Silverbrook Research Pty Ltd
    Inventor: Kia Silverbrook
  • Patent number: 8088297
    Abstract: The present invention relates firstly to HF/fluoride-free etching and doping media which are suitable both for the etching of silicon dioxide layers and also for the doping of underlying silicon layers. The present invention also relates secondly to a process in which these media are employed.
    Type: Grant
    Filed: June 13, 2006
    Date of Patent: January 3, 2012
    Assignee: Merck Patent GmbH
    Inventors: Armin Kuebelbeck, Werner Stockum
  • Patent number: 8088693
    Abstract: There is provided a substrate treatment method for performing treatment by feeding a chemical liquid to a surface of a substrate, in which, before feeding the chemical liquid to a predetermined area of the substrate, a liquid substance having a resistivity lower than that of the chemical liquid is fed to the surface of the substrate so that the liquid substance wets at least the predetermined area, and then, the chemical liquid is fed to the predetermined area so that the treatment is performed on the substrate with the chemical liquid fed to the surface of the substrate.
    Type: Grant
    Filed: October 4, 2006
    Date of Patent: January 3, 2012
    Assignee: Sony Corporation
    Inventors: Yoshimichi Shiki, Seiji Oda, Hayato Iwamoto, Yoshiya Hagimoto
  • Patent number: 8071413
    Abstract: The present invention discloses an MEMS sensor and a method for making the MEMS sensor. The MEMS sensor according to the present invention includes: a substrate including an opening; a suspended structure located above the opening; and an upper structure, a portion of which is at least partially separated from a portion of the suspended structure; wherein the suspended structure and the upper structure are separated from each other by a step including metal etch.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: December 6, 2011
    Assignee: PixArt Imaging Incorporation, R.O.C.
    Inventor: Chuan Wei Wang
  • Patent number: 8062535
    Abstract: Method for producing a probe for atomic force microscopy with a silicon nitride cantilever and an integrated single crystal silicon tetrahedral tip with high resonant frequencies and low spring constants intended for high speed AFM imaging.
    Type: Grant
    Filed: January 30, 2008
    Date of Patent: November 22, 2011
    Inventor: Chung Hoon Lee
  • Patent number: 8062536
    Abstract: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: November 22, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Chien Liu, Ta-Shan Tseng, Wen-Bin Shieh, Juan-Yuan Wu, Water Lur, Shih-Wei Sun
  • Patent number: 8043518
    Abstract: The method of manufacturing a nozzle plate which includes a nozzle having a tapered section and a linear section includes the steps of: forming an etching stopper layer for stopping dry etching of a silicon substrate, on a first surface of the silicon substrate; forming a mask layer on a second surface of the silicon substrate reverse to the first surface; performing a first patterning process with respect to the mask layer so that an opening section is formed in the mask layer; carrying out the dry etching of the silicon substrate through the opening section in the mask layer so that the tapered section of the nozzle is formed in the silicon substrate; carrying out dry etching of the etching stopper layer through the opening section in the mask layer so that at least a part of the linear section of the nozzle is formed in the etching stopper layer; and removing the mask layer.
    Type: Grant
    Filed: March 22, 2007
    Date of Patent: October 25, 2011
    Assignee: Fujifilm Corporation
    Inventor: Shuji Takahashi
  • Patent number: 8025776
    Abstract: Embodiments of the present invention may provide a microchip applicable to an electrophoresis employing UV detection and a method of manufacturing the same. The microchip of the present invention has a glass channel plate, which is formed on an upper surface thereof with a loading channel and a separation channel and is provided on the upper surface thereof with an optical slit layer made of silicon except the channel region, and a glass reservoir plate, which is formed with sample solution reservoirs and buffer solution reservoirs. The loading channel and the separation channel are formed on the channel plate by deep reactive ion etching. The sample solution reservoirs and the buffer solution reservoirs are formed in the reservoir plate by sand blasting. The channel plate and the reservoir plate are combined by anodic bonding the optical slit layer and the reservoir plate. Electrodes for sample and electrodes for buffer are deposited by sputtering Pt with a shadow mask after anodic bonding.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: September 27, 2011
    Assignee: Korea Institute of Science and Technology
    Inventors: Myung-Suk Chun, Tae Ha Kim
  • Patent number: 8012366
    Abstract: A method is provided for defining a pattern on a workpiece such as a transparent substrate or mask or a workpiece that is at least transparent within a range of optical wavelengths. The method includes defining a photoresist pattern on the top surface of the mask, the pattern including a periodic structure having a periodic spacing between elements of the structure. The method further includes placing the mask on a support pedestal in a plasma reactor chamber and generating a plasma in the chamber to etch the top surface of the mask through openings in the photoresist pattern. The method also includes transmitting light through the pedestal and through the bottom surface of the mask, while viewing through the support pedestal light reflected from the periodic structure and detecting an interference pattern in the reflected light. The method further includes determining from the interference pattern a depth to which periodic structure has been etched in the top surface.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: September 6, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Richard Lewington, Michael N. Grimbergen, Khiem K. Nguyen, Darin Bivens, Madhavi R. Chandrachood, Ajay Kumar
  • Patent number: 8012365
    Abstract: A method of anisotropic plasma etching of a silicon wafer, maintained at a temperature from ?40° C. to ?120° C., comprising alternated and repeated steps of: etching with injection of a fluorinated gas, into the plasma reactor, and passivation with injection of silicon tetrafluoride, SiF4, and of oxygen into the plasma reactor, the flow rate of the gases in the plasma reactor being on the order of from 10% to 25% of the gas flow rate during the etch step.
    Type: Grant
    Filed: April 3, 2008
    Date of Patent: September 6, 2011
    Assignee: STMicroelectronics, SA
    Inventors: Remi Dussart, Philippe Lefaucheux, Xavier Mellhaoui, Lawrence John Overzet, Pierre Ranson, Thomas Tillocher, Mohamed Boufnichel
  • Patent number: RE44356
    Abstract: A method of manufacturing a tunable wavelength optical filter. The method includes steps of forming a first sacrificial oxide film for floating a lower mirror on a semiconductor substrate; sequentially laminating conductive silicon films and oxide films for defining a mirror region on the first sacrificial oxide film in a multi-layer and laminating another conductive silicon film to form a lower mirror; sequentially laminating conductive silicon films and oxide films for defining the mirror region on a second sacrificial oxide film in a multi-layer and laminating another conductive silicon film to form an upper mirror and forming an optical tuning space between the lower mirror and the upper mirror and etching the first sacrificial oxide film and the second sacrificial oxide film such that the lower mirror is floated on the semiconductor substrate.
    Type: Grant
    Filed: July 1, 2010
    Date of Patent: July 9, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Chang Auck Choi, Myung Lae Lee, Chang Kyu Kim, Chi Hoon Jun, Youn Tae Kim