Etching Silicon Containing Substrate Patents (Class 216/79)
  • Patent number: 7368062
    Abstract: Undoped layers are introduced in the passive waveguide section of a butt-joined passive waveguide connected to an active structure. This reduces the parasitic capacitance of the structure.
    Type: Grant
    Filed: September 17, 2004
    Date of Patent: May 6, 2008
    Assignee: Avago Technologies Fiber IP Pte Ltd
    Inventors: Tirumala R. Ranganath, Jintian Zhu
  • Patent number: 7361285
    Abstract: A method for fabricating a cliché including: providing a transparent glass substrate; depositing a metal layer on the substrate; patterning the metal layer and thereby forming a first metal pattern; etching the glass substrate by using the first metal pattern as a mask and thereby forming a first convex pattern; patterning the first metal pattern and thereby forming a second metal pattern; and etching the first convex pattern by using the second metal pattern as a mask and thereby forming a second convex pattern.
    Type: Grant
    Filed: April 26, 2005
    Date of Patent: April 22, 2008
    Assignee: LG.Philips LCD Co., Ltd.
    Inventor: Chul-Ho Kim
  • Patent number: 7361287
    Abstract: A method is proposed for etching structures into an etching body, in particular, recesses which are laterally precisely defined by an etching mask, into a silicon body, using a plasma. In the process, a high-frequency pulsed, low-frequency modulated high-frequency power is coupled at least intermittently into the etching body using a high-frequency a.c. voltage and, in addition, the intensity of the plasma is modulated as a function of time.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: April 22, 2008
    Assignee: Robert Bosch GmbH
    Inventor: Franz Laermer
  • Patent number: 7361605
    Abstract: In processing an integrated circuit structure including a contact arrangement that is initially covered by a stop layer, a first plasma is used to etch to form openings through an overall insulation layer covered by a patterned layer of photoresist such that one contact opening is associated with each contact. Stripping of the patterned layer of photoresist and related residues is performed. After stripping, the stop layer is removed from the contacts. In one feature, the stop layer is removed from the contacts by etching the stop layer using a plasma that is generated from a plasma gas input that includes hydrogen and essentially no oxygen. In another feature, the photoresist is stripped after the stop layer is removed. Stripping the patterned layer of photoresist and the related residues is performed, in this case, using a plasma that is formed predominantly including hydrogen without oxygen.
    Type: Grant
    Filed: January 19, 2005
    Date of Patent: April 22, 2008
    Assignee: Mattson Technology, Inc.
    Inventors: Stephen E. Savas, Wolfgang Helle
  • Patent number: 7358192
    Abstract: Embodiments of a cluster tool, processing chamber and method for processing a film stack are provided. In one embodiment, a method for in-situ etching of silicon and metal layers of a film stack is provided that includes the steps of etching an upper metal layer of the film stack in a processing chamber to expose a portion of an underlying silicon layer, and etching a trench in the silicon layer without removing the substrate from the processing chamber. The invention is particularly useful for thin film transistor fabrication for flat panel displays.
    Type: Grant
    Filed: April 8, 2004
    Date of Patent: April 15, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Walter R. Merry, Quanyuan Shang, John M. White
  • Patent number: 7354695
    Abstract: A method is provided for preparing high surface-area texturing of a substrate using methods by which material from a substrate is subtracted from or added to the surface of the substrate. In one embodiment, the method is a subtractive lithographic method that involves exposing a laser-ablatable substrate, such as a polymeric or ceramic substrate, to laser light. A mask may be used to define the pattern of light incident on the substrate. High surface-area textured substrates, in particular, miniaturized planar analysis devices having high surface-area textured features, prepared by the methods disclosed herein, are also provided. A method by which the high surface-area textured substrate or the miniaturized planar analysis device is used as a master from which replicate copies thereof may be made is also provided.
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: April 8, 2008
    Assignee: Agilent Technologies, Inc.
    Inventors: Reid A. Brennen, Sally A. Swedberg
  • Patent number: 7351347
    Abstract: GaN crystal having few dislocations is grown by using together ELO-mask and defect-seeding-mask means. ELO masks make it so that GaN crystal does not grow directly, but grows laterally; defect-seeding masks make it so that closed defect-gathering regions in which defects are concentrated are grown. Any of the materials SiN, SiON or SiO2 is utilized for the ELO mask, while any of the materials Pt, Ni or Ti is utilized for the defect-seeding masks. With a sapphire, GaAs, spinel, Si, InP, SiC, etc. single-crystal substrate, or one in which a GaN buffer layer is coated onto a single-crystal substrate of these, as an under-substrate, the ELO mask and defect-seeding masks are provided complementarily and GaN is vapor-phase deposited.
    Type: Grant
    Filed: January 23, 2003
    Date of Patent: April 1, 2008
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Katsushi Akita, Takuji Okahisa
  • Patent number: 7344652
    Abstract: An etching method for forming a recess (220) having an opening dimension (R) of millimeter order in an object (212) to be etched such as a semiconductor wafer. A mask (214) having an opening corresponding to the recess (220) is formed on the object (212). The object (212) with the mask (214) is placed in a processing vessel for plasma etching and etched in it using a plasma. The material of the portion around the opening of the mask (214) is the same as the material, for example, silicon of the object (212). Hence, the recess (220) can be so formed as not to form a sub-trench shape (a shape formed by etching the periphery of which is deeper than the center) substantially in the bottom (222).
    Type: Grant
    Filed: July 17, 2006
    Date of Patent: March 18, 2008
    Assignee: Tokyo Electron Limited
    Inventors: Kazuya Nagaseki, Takanori Mimura, Hiroki Miyajima
  • Patent number: 7341952
    Abstract: A method for etching a deep trench in a substrate. A multi-layer hard mask structure is formed overlying the substrate, which includes a first hard mask layer and at least one second hard mask layer disposed thereon. The first hard mask layer is composed of a first boro-silicate glass (BSG) layer and an overlying first undoped silicon glass (USG) layer and the second is composed of a second BSG layer and an overlying second USG layer. A polysilicon layer is formed overlying the multi-layer hard mask structure and then etched to form an opening therein. The multi-layer hard mask structure and the underlying substrate under the opening are successively etched to simultaneously form the deep trench in the substrate and remove the polysilicon layer. The multi-layer hard mask structure is removed.
    Type: Grant
    Filed: February 7, 2006
    Date of Patent: March 11, 2008
    Assignee: Nanya Technology Corporation
    Inventors: Kaan-Lu Tzou, Tzu-Ching Tsai, Yi-Nan Chen
  • Patent number: 7341672
    Abstract: A method of fabricating a printhead is provided in which sacrificial material is deposited on a drive circuitry substrate and etched to define first zones, thermally expandable material is deposited on the first zones and etched with the substrate to define second zones, conductive material is deposited on the second zones and etched to define heating circuitry and connections between the heating and drive circuitry, thermally expandable material is deposited to embed the heating circuitry in the thermally expandable materials and etched to define thermally expandable actuator arms and closure members, chamber material is deposited and etched to form nozzle chambers having inkjet ports and associated actuator arms and closure members, the sacrificial material is etched so that each actuator arm has ends connected between the substrate and the associated closure member, and the substrate is etched to form ink supply channels for supply of ink under pulsed pressure.
    Type: Grant
    Filed: October 12, 2006
    Date of Patent: March 11, 2008
    Assignee: Silverbrook Research Pty Ltd
    Inventor: Kia Silverbrook
  • Patent number: 7338907
    Abstract: A dry etch process is described for selectively etching silicon nitride from conductive oxide material for use in a semiconductor fabrication process. Adding an oxidant in the etch gas mixture could increase the etch rate for the silicon nitride while reducing the etch rate for the conductive oxide, resulting in improving etch selectivity. The disclosed selective etch process is well suited for ferroelectric memory device fabrication using conductive oxide/ferroelectric interface having silicon nitride as the encapsulated material for the ferroelectric.
    Type: Grant
    Filed: October 4, 2004
    Date of Patent: March 4, 2008
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Tingkai Li, Sheng Teng Hsu, Bruce D. Ulrich, Mark A. Burgholzer, Ray A. Hill
  • Patent number: 7338610
    Abstract: A wafer having a dielectric layer and an electrode partially protruding from the top surface of the dielectric layer is provided. The dielectric layer is etched with a chemical solution such as LAL. Prior to etching, the protruding portion of the electrode is removed or reduced to prevent any bubbles included in the chemical solution from adhering to the electrode. Thus, the chemical solution can etch the dielectric layers without being blocked by any bubbles included in a chemical solution.
    Type: Grant
    Filed: January 23, 2004
    Date of Patent: March 4, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Jun Lee, Byoung-Moon Yoon, In-Seak Hwang, Yong-Sun Ko
  • Patent number: 7326358
    Abstract: A plasma processing method performs a plasma processing on a substrate mounted on a mounting table installed in an airtight processing chamber, the mounting table having a smaller size than the substrate. The substrate having a surface, on which a resist mark is formed, is mounted on the mounting table and then electrostatically adsorbed on the mounting table by applying a voltage to an electrostatic chuck. The surface of the substrate is etched by using a plasma of an etching gas while the substrate is cooled through a heat transfer between the substrate and the mounting table via a thermally conductive gas supplied between a top surface of the mounting table and a bottom surface of the substrate. The supply of the thermally conductive gas is stopped, and the resist mask on the substrate is ashed by using a plasma of an ashing gas containing O2.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: February 5, 2008
    Assignee: Tokyo Electron Limited
    Inventor: Masaru Sugimoto
  • Patent number: 7316785
    Abstract: In a plasma processing system, including a plasma processing chamber, a method of optimizing the etch resistance of a substrate material is described. The method includes flowing pre-coat gas mixture into the plasma processing chamber, wherein the pre-coat gas mixture has an affinity for a etchant gas flow mixture; striking a first plasma from the pre-coat gas mixture; and introducing a substrate comprising the substrate material. The method also includes flowing the etchant gas mixture into the plasma processing chamber; striking a second plasma from the etchant gas mixture; and etching the substrate with the second plasma. Wherein the first plasma creates a pre-coat residual on a set of exposed surfaces in the plasma processing chamber, and the etch resistance of the substrate material is maintained.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: January 8, 2008
    Assignee: Lam Research Corporation
    Inventors: Yoko Yamaguchi Adams, George Stojakovic, Alan Miller
  • Publication number: 20080000875
    Abstract: A porous dielectric layer is formed on a substrate. Aluminum is incorporated in the porous dielectric layer with a pattern process using an Aluminum gas precursor. The incorporated Aluminum improves the mechanical properties of the porous dielectric layer.
    Type: Application
    Filed: June 30, 2006
    Publication date: January 3, 2008
    Inventors: Vijayakumar Ramachandrarao, Grant Kloster
  • Patent number: 7314574
    Abstract: An etching apparatus comprises a workpiece holder (21) for holding a workpiece (X), a plasma generator (10, 20) for generating a plasma (30) in a vacuum chamber (3), an orifice electrode (4) disposed between the workpiece holder (21) and the plasma generator (10, 20), and a grid electrode (5) disposed upstream of the orifice electrode (4) in the vacuum chamber (3). The orifice electrode (4) has orifices (4a) defined therein. The etching apparatus further comprises a voltage applying unit (25, 26) for applying a voltage between the orifice electrode (4) and the grid electrode (5) to accelerate ions from the plasma (30) generated by the plasma generator (10, 20) and to pass the extracted ions through the orifices (4a) in the orifice electrode (4), for generating a collimated neutral particle beam having an energy ranging from 10 eV to 50 eV.
    Type: Grant
    Filed: September 24, 2002
    Date of Patent: January 1, 2008
    Assignee: Ebara Corporation
    Inventors: Katsunori Ichiki, Kazuo Yamauchi, Hirokuni Hiyama, Seiji Samukawa
  • Patent number: 7311850
    Abstract: In a method of forming a patterned thin film, first, an etching stopper film and a film to be patterned are formed in this order on a base layer. Next, a patterned first film is formed on the film to be patterned. Next, a second film is formed over an entire surface on top of the film to be patterned and the first film. Then, by removing the first film, an etching mask is obtained from the second film formed on the film to be patterned. The film to be patterned is selectively etched through dry etching using the etching mask. A patterned thin film having a groove is thereby obtained.
    Type: Grant
    Filed: October 17, 2002
    Date of Patent: December 25, 2007
    Assignee: TDK Corporation
    Inventors: Akifumi Kamijima, Yoichi Ishida, Koichi Terunuma
  • Patent number: 7309641
    Abstract: A method for rounding the bottom corners of a trench is described. In the method, an etching process is performed using a fluorocarbon compound with at least two carbon atoms, He and O2 as an etching gas to round the bottom corners of the trench.
    Type: Grant
    Filed: November 24, 2004
    Date of Patent: December 18, 2007
    Assignee: United Microelectronics Corp.
    Inventor: Kao-Su Huang
  • Patent number: 7306744
    Abstract: A method of manufacturing a nozzle plate 2 is disclosed. The nozzle plate 2 has a plurality of nozzle openings 22 through each of which a droplet is adapted to be ejected. The method includes the steps of: preparing a processing substrate (silicon substrate 10) constituted from silicon as a main material, the processing substrate having two major surfaces; providing a supporting substrate 50 for supporting the processing substrate onto one major surface of the processing substrate 50; and forming the plurality of nozzle openings 22 on the other major surface of the processing substrate by subjecting the other major surface of the processing substrate to an etching process while the processing substrate is supported by the supporting substrate 50.
    Type: Grant
    Filed: April 27, 2005
    Date of Patent: December 11, 2007
    Assignee: Seiko Epson Corporation
    Inventors: Yoshihide Matsuo, Katsuji Arakawa
  • Publication number: 20070278181
    Abstract: A manufacturing method of a silicon nozzle plate, having; a film forming process to provide the film representing an etching mask for etching the silicon substrate on a surface of the silicon substrate; a pattern film forming to form a pattern film by partially removing the film based on a nozzle hole forming patter and an outer shape forming pattern; a silicon substrate etching process to form nozzle holes based on the nozzle hole forming pattern representing the etching mask, and to form a half etching portion at least in a part of the silicon substrate based on the outer shape forming patter; and a silicon substrate separating process to separate the silicon substrate by splitting along the half etching portion.
    Type: Application
    Filed: May 25, 2007
    Publication date: December 6, 2007
    Inventors: Kazuhiko Tsuboi, Tohru Hirai
  • Patent number: 7297635
    Abstract: A processing method which, when an organic film layer such as a PR film layer 202 formed on the surface of a wafer W is to be removed from an SiO2 film layer 204 below it by generating plasma of a process gas in a chamber 1 comprises the step of using O2 gas as the process gas to remove the organic film layer at a first pressure, e.g., 20 mTorr, lower than in a conventional case, and the step of using the same O2 gas to remove the organic film layer at a second pressure, e.g., 200 mTorr, higher than the first pressure.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: November 20, 2007
    Assignee: Tokyo Electron Limited
    Inventors: Akihito Toda, Kazuto Ogawa
  • Patent number: 7291286
    Abstract: Methods for removing black silicon or black silicon carbide from a plasma-exposed surface of an upper electrode of a plasma processing chamber are provided. The methods include forming a plasma using a gas composition containing a fluorine-containing gas, and removing the black silicon or black silicon carbide from the surface with the plasma. The methods can also remove black silicon or black silicon carbide from surfaces of the components in the chamber in addition to the upper electrode.
    Type: Grant
    Filed: December 23, 2004
    Date of Patent: November 6, 2007
    Assignee: Lam Research Corporation
    Inventors: Enrico Magni, Michael Kelly, Robert Hefty, Michelle Lupan
  • Patent number: 7270760
    Abstract: A method and apparatus are provided for simulating a standard wafer in semiconductor manufacturing equipment. The apparatus includes a support layer suitable for being handled by the semiconductor manufacturing equipment. Applied to the support layer is a mixture including a process agent and a material. During use, the present invention simulates a standard production wafer including material similar to that in the mixture of the present invention.
    Type: Grant
    Filed: October 4, 2005
    Date of Patent: September 18, 2007
    Assignee: Lam Research Corporation
    Inventors: Gregory J. Goldspring, Robert J. O'Donnell
  • Patent number: 7259104
    Abstract: A surface processing method of a sample having a mask layer that does not contain carbon as a major component formed on a substance to be processed, the substance being a metal, semiconductor and insulator deposited on a silicon substrate, includes the steps of installing the sample on a sample board in a vacuum container, generating a plasma that consists of a mixture of halogen gas and adhesive gas inside the vacuum container, applying a radio frequency bias voltage having a frequency ranging from 200 kHz to 20 MHz on the sample board, and controlling a periodic on-off of the radio frequency bias voltage with an on-off control frequency ranging from 100 Hz to 10 kHz.
    Type: Grant
    Filed: September 29, 2003
    Date of Patent: August 21, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Tetsuo Ono, Takafumi Tokunaga, Tadashi Umezawa, Motohiko Yoshigai, Tatsumi Mizutani, Tokuo Kure, Masayuki Kojima, Takashi Sato, Yasushi Goto
  • Patent number: 7247248
    Abstract: The invention relates to a method for forming silicon atomic force microscope tips. The method includes the steps of depositing a masking layer onto a first layer of doped silicon so that some square or rectangular areas of the first layer of doped silicon are not covered by the masking layer, etching pyramidal apertures in the first layer of doped silicon, removing the masking layer, depositing a second layer of doped silicon onto the first layer of doped silicon, the second layer of doped silicon being oppositely doped to the first layer of doped silicon and etching away the first layer of doped silicon. Further steps may be added to form the atomic force microscope tips at the end of cantilevers.
    Type: Grant
    Filed: May 20, 2003
    Date of Patent: July 24, 2007
    Assignee: Sensfab Pte Ltd
    Inventors: Lay Har Angeline Tee, Kim Pong Daniel Chir, Kitt-Wai Kok, Kathirgamasundaram Sooriakumar, Bryan Keith Patmon
  • Patent number: 7247247
    Abstract: A selective etching method with lateral protection function is provided. The steps includes: (a) providing a substrate; (b) forming a plurality of tunnels; (c) forming a lateral strengthening structure at a peripheral wall of the tunnels; (d) removing a bottom portion of the lateral strengthening structure, and a part of the substrate by an etching process so as to form a lower structure and expose an unstrengthened structure; and (f) etching the unstrengthened structure laterally so as to form an upper structure.
    Type: Grant
    Filed: May 6, 2004
    Date of Patent: July 24, 2007
    Assignee: Walsin Lihwa Corporation
    Inventors: Jerwei Hsieh, Huai-Yuan Chu, Julius Ming-Lin Tsai, Weileun Fang
  • Patent number: 7247252
    Abstract: A method for avoiding plasma arcing during a reactive ion etching (RIE) process including providing a semiconductor wafer having a process surface for depositing a dielectric insulating layer; depositing at least a portion of a dielectric insulating layer to form a deposition layer according to plasma assisted chemical vapor deposition (CVD) process; treating the deposition layer portion with a hydrogen plasma treatment to reduce an electrical charge nonuniformity of the deposition layer including applying a biasing power to the semiconductor wafer; and, carrying out a subsequent reactive ion etching process.
    Type: Grant
    Filed: June 20, 2002
    Date of Patent: July 24, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shing-Chyang Pan, Yu-Chun Huang, Shwangming Jing
  • Patent number: 7244368
    Abstract: A manufacturing method of a magnetic head includes a process for forming a lift-off mask pattern on a magnetoresistance effect element, such that the upper part of the lift-off mask pattern is larger in size than the lower part, a process for forming a couple of electrodes on the magnetoresistance effect element using the lift-off mask pattern as a mask, and a process for removing the lift-off mask pattern. The process for forming the lift-off mask pattern is performed according to a dry etching process.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: July 17, 2007
    Assignee: Fujitsu Limited
    Inventors: Shoichi Suda, Masayuki Takeda, Keiji Watanabe
  • Patent number: 7238293
    Abstract: The described embodiments relate to a slotted substrate and methods of forming same. One exemplary method patterns a hardmask on a first substrate surface sufficient to expose a first area of the first surface and forms a slot portion in the substrate through less than an entirety of the first area of the first surface. The slot portion has a cross-sectional area at the first surface that is less than a cross-sectional area of the first area. After forming the slot portion, the method etches the substrate to remove material from within the first area to form a fluid-handling slot.
    Type: Grant
    Filed: June 20, 2003
    Date of Patent: July 3, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jeremy Donaldson, Martha A. Truninger, Jeffrey S. Obert
  • Patent number: 7217371
    Abstract: The present invention relates to interfacing new sensors to incumbent controls. In particular, it relates to optically interfacing a new sensor, such as a spectrometer with plasma generator, to an incumbent electro-optical sensor. Logic and resources to control activation of the incumbent electro-optical sensor may be included. Particular aspects of the present invention are described in the claims, specification and drawings.
    Type: Grant
    Filed: July 26, 2004
    Date of Patent: May 15, 2007
    Assignee: Lightwind Corporation
    Inventor: Herbert E. Litvak
  • Patent number: 7211197
    Abstract: A processing gas constituted of CH2F2, O2 and Ar is introduced into a processing chamber 102 of a plasma processing apparatus 100. The flow rate ratio of the constituents of the processing gas is set at CH2F2/O2/Ar=20 sccm/10 sccm/100 sccm. The pressure inside the processing chamber 102 is set at 50 mTorr. 500 W high frequency power with its frequency set at 13.56 MHz is applied to a lower electrode. 108 on which a wafer W is placed. The processing gas is raised to plasma and thus, an SiNx layer 206 formed on a Cu layer 204 is etched. The exposed Cu layer 204 is hardly oxidized and C and F are not injected into it.
    Type: Grant
    Filed: August 2, 2004
    Date of Patent: May 1, 2007
    Assignee: Tokyo Electron Limited
    Inventors: Masaaki Hagihara, Koichiro Inazawa, Wakako Naito
  • Patent number: 7205240
    Abstract: A gapfill process is provided using cycling of HDP-CVD deposition, etching, and deposition step. The fluent gas during the first deposition step includes an inert gas such as He, but includes H2 during the remainder deposition step. The higher average molecular weight of the fluent gas during the first deposition step provides some cusping over structures that define the gap to protect them during the etching step. The lower average molecular weight of the fluent gas during the remainder deposition step has reduced sputtering characteristics and is effective at filling the remainder of the gap.
    Type: Grant
    Filed: June 4, 2003
    Date of Patent: April 17, 2007
    Assignee: Applied Materials, Inc.
    Inventors: M. Ziaul Karim, Bikram Kapoor, Anchuan Wang, Dong Qing Li, Katsunari Ozeki, Manoj Vellaikal, Zhuang Li
  • Patent number: 7201852
    Abstract: A method for eliminating eruptions, impurities, and/or damage in a crystal lattice by selectively etching silicon elements of surface-plated and sawn-out parts of a silicon wafer. At least areas of the silicon elements are brought into contact with a gaseous etching medium that etches silicon selectively in a chemical reaction, and gaseous reaction products are produced during etching. An interhalogen or fluorine-noble gas compound that is in a gaseous state or was converted to the gaseous phase may be used as the etching medium. The method is believed to be suitable for producing power diodes sawn from a wafer or for overetching fully mounted individual diodes.
    Type: Grant
    Filed: April 26, 2000
    Date of Patent: April 10, 2007
    Assignee: Robert Bosch GmbH
    Inventors: Richard Spitz, Helga Uebbing, Doerte Eimers-Klose, Franz Laermer, Andrea Schilp
  • Patent number: 7198727
    Abstract: The present invention provides an optical microbench having intersecting structures etched into a substrate. In particular, microbenches in accordance with the present invention include structures having a planar surfaces formed along selected crystallographic planes of a single crystal substrate. Two of the structures provided are an etch-stop pit and an anisotropically etched feature disposed adjacent the etch-stop pit. At the point of intersection between the etch-stop pit and the anisotropically etched feature the orientation of the crystallographic planes is maintained. The present invention also provides a method for micromachining a substrate to form an optical microbench. The method comprises the steps of forming an etch-stop pit and forming an anisotropically etched feature adjacent the etch-stop pit. The method may also comprise coating the surfaces of the etch-stop pit with an etch-stop layer.
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: April 3, 2007
    Assignee: Shipley Company, L.L.C.
    Inventors: Dan A. Steinberg, Larry J. Rasnake
  • Patent number: 7192875
    Abstract: Processes for treating a morphologically-modified surface of a silicon upper electrode of a plasma processing chamber include exposing the surface to a gas composition containing at least one gas-phase halogen fluoride. The gas composition is effective to remove silicon from the morphologically-modified surface and restore the surface state.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: March 20, 2007
    Assignee: Lam Research Corporation
    Inventor: Joel M. Cook
  • Patent number: 7189334
    Abstract: A method of fabricating a plurality of nozzle arrangements for an inkjet printhead chip includes fabricating drive circuitry layers on a substrate with a CMOS fabrication process; depositing a first sacrificial layer on the substrate; depositing a heater layer for forming one or more heating circuits on the first sacrificial layer and etching the heater layer to form the heating circuits; depositing a resiliently flexible layer of dielectric material on the substrate to cover the heater layer and etching the dielectric layer to form one or more actuators and one or more ink ejection members; depositing a second sacrificial layer on the substrate to cover the actuators and the ink ejection members and etching the sacrificial layer to define deposition zones for one or more nozzle chamber walls and one or more roof walls; depositing a layer of a structural material on the second sacrificial layer to form the nozzle chamber walls and the roof walls; and etching away the sacrificial layers.
    Type: Grant
    Filed: June 24, 2005
    Date of Patent: March 13, 2007
    Assignee: Silverbrook Research Pty Ltd
    Inventor: Kia Silverbrook
  • Patent number: 7189332
    Abstract: Processes for the removal of a layer or region from a workpiece material by contact with a process gas in the manufacture of a microstructure are enhanced by the ability to accurately determine the endpoint of the removal step. A vapor phase etchant is used to remove a material that has been deposited on a substrate, with or without other deposited structure thereon. By creating an impedance at the exit of an etching chamber (or downstream thereof), as the vapor phase etchant passes from the etching chamber, a gaseous product of the etching reaction is monitored, and the endpoint of the removal process can be determined. The vapor phase etching process can be flow through, a combination of flow through and pulse, or recirculated back to the etching chamber.
    Type: Grant
    Filed: October 11, 2002
    Date of Patent: March 13, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Satyadev R. Patel, Gregory P. Schaadt, Douglas B. MacDonald, Niles K. MacDonald, Hongqin Shi
  • Patent number: 7186349
    Abstract: A fluid ejection device includes a first substrate having a first crystal orientation, a second substrate having a second crystal orientation, bound to the first substrate, a manifold through the first and second substrates, a chamber formed in the second substrate, connected with the manifold, and a plurality of nozzles connecting to the chamber, wherein the first crystal orientation is different from the second crystal orientation. A method of fabricating the same is also disclosed.
    Type: Grant
    Filed: November 4, 2004
    Date of Patent: March 6, 2007
    Assignee: Benq Corporation
    Inventors: Hung-Sheng Hu, Wei-Lin Chen
  • Patent number: 7182878
    Abstract: This relates to optical devices such as planar light-wave components/circuits which are designed to have a high waveguide pattern density effecting a higher etch selectivity and overall improved dimensional control of the functional waveguides on the optical device.
    Type: Grant
    Filed: February 6, 2004
    Date of Patent: February 27, 2007
    Assignee: Lightwave Microsystems Corporation
    Inventors: Jongik Won, Calvin Ka Kuen Ho, Fan Zhong, Liang Zhao
  • Patent number: 7182876
    Abstract: In the present invention, disclosed are a cantilever microstructure and a fabrication thereof comprising a base plate; a cantilever beam extended from one surface of the base plate to outside so that a part thereof can be suspended, and formed of a silicon nitride material, and a probing tip formed at a front end of one surface of the cantilever beam, whereby the thickness of the cantilever beam becomes uniform and the mechanical and electrical characteristic thereof are improved.
    Type: Grant
    Filed: September 8, 2004
    Date of Patent: February 27, 2007
    Assignee: LG Electronics Inc.
    Inventor: Hyo-Jin Nam
  • Patent number: 7179396
    Abstract: The present invention provides a method to pattern a substrate which features creating a multi-layered structure by forming, on the substrate, a patterned layer having protrusions and recessions. Formed upon the patterned layer is a conformal layer, with the multi-layered structure having a crown surface facing away from the substrate. Portions of the multi-layered structure are removed to expose regions of the substrate in superimposition with the protrusions, while forming a hard mask in areas of the crown surface in superimposition with the recessions.
    Type: Grant
    Filed: March 25, 2003
    Date of Patent: February 20, 2007
    Assignee: Molecular Imprints, Inc.
    Inventor: Sidlgata V. Sreenivasan
  • Patent number: 7163641
    Abstract: A plasma etch process for etching BPSG employing two primary etchants at low flows and pressures, and a relatively low temperature environment within the etch chamber, which includes a fluorine scavenger in the form of silicon. The two primary etchant gases are CHF3 and CH2F2, delivered at flow rates on the order of between about 10 and 40 sccm for CHF3 and between about 10 and 40 sccm for CH2F2. Small quantities, on the order of 10 sccm or less, of other gases such as C2HF5 and CF4 may be added.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: January 16, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Kevin G. Donohoe, David S. Becker
  • Patent number: 7153443
    Abstract: A microstructure and the method for making the same are disclosed herein. The microstructure has structural members, at least one of which comprises an intermetallic compound. In making such a microstructure, a sacrificial material is employed. After completion of forming the structural layers, the sacrificial material is removed by a spontaneous vapor phase chemical etchant.
    Type: Grant
    Filed: March 18, 2004
    Date of Patent: December 26, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Jonathan Doan, Satyadev Patel
  • Patent number: 7147791
    Abstract: A method of fabricating an ink jet printhead includes the step of depositing a layer of a sacrificial material on a substrate that incorporates drive circuitry layers positioned on a wafer substrate. The layer of sacrificial material is etched to define deposition zones for actuators. A first layer of a thermally expandable actuator material is deposited on the deposition zones. The first layer of actuator material and the drive circuitry layers are etched to define deposition zones for a conductive material of the actuators and for vias for heating circuits of the actuators. A layer of a conductive material is deposited on the first layer of actuator material. The layer of conductive material is etched to define a heating circuit for each actuator. A second layer of actuator material is deposited on the layer of conductive material so that the heating circuits are embedded in the actuator material. The actuator material is etched to define the actuators and the closure members.
    Type: Grant
    Filed: October 28, 2003
    Date of Patent: December 12, 2006
    Assignee: Silverbrook Research Pty Ltd
    Inventor: Kia Silverbrook
  • Patent number: 7144820
    Abstract: A method of manufacturing a layer sequence having a first and a second laterally confined structure comprises the steps of providing a first layer on a first surface portion of a substrate, which first layer is doped with dopant of a first type of conductivity, providing a second layer on a second surface portion of the substrate, which second layer is free of dopant of the first type of conductivity, forming a third layer on the first layer, which third layer is free of dopant of the first type of conductivity, and forming a fourth layer on the second layer, which forth layer is doped with dopant of the first type of conductivity. The first layer and the third layer are etched, thereby patterning the first and third layer to form the first laterally confined structure. The second layer and the forth layer are etched, thereby patterning the second and fourth layer to form the second laterally confined structure.
    Type: Grant
    Filed: January 2, 2004
    Date of Patent: December 5, 2006
    Assignee: Infineon Technologies AG
    Inventor: Kwon O. Sung
  • Patent number: 7140374
    Abstract: A method for cleaning a processing chamber that includes heating an inner surface of the processing chamber to a first temperature. The first temperature can be sufficient to cause a first species to become volatile. The first species can be one of several species deposited on the inner surface. A cleaning chemistry is injected into the processing chamber. The cleaning chemistry can be reactive with a second one of the species to convert the second species to the first species. The volatilized first species can also be output from the processing chamber. A system for cleaning the process chamber is also described.
    Type: Grant
    Filed: March 16, 2004
    Date of Patent: November 28, 2006
    Assignee: Lam Research Corporation
    Inventors: Andrew D. Bailey, III, Shrikant P. Lohokare, Arthur M. Howald, Yunsang Kim
  • Patent number: 7135120
    Abstract: The UV, deep UV and/or far UV (ultraviolet) filter transmission spectrum of an MPSi spectral filter is optimized by introducing at least one layer of substantially transparent dielectric material on the pore walls. Such a layer will modify strongly the spectral dependences of the leaky waveguide loss coefficients through constructive and/or destructive interference of the leaky waveguide mode inside the layer. Increased blocking of unwanted wavelengths is obtained by applying a metal layer to one or both of the principal surfaces of the filter normal to the pore directions. The resulting filters are stable, do not degrade over time and exposure to UV irradiation, and offer superior transmittance for use as bandpass filters. Such filters are useful for a wide variety of applications including but not limited to spectroscopy and biomedical analysis systems.
    Type: Grant
    Filed: June 4, 2003
    Date of Patent: November 14, 2006
    Assignee: Lake Shore Cryotronics, Inc.
    Inventors: Vladimir Kochergin, Philip Swinehart
  • Patent number: 7128975
    Abstract: A surface of a multicrystalline silicon substrate is etched with an alkaline aqueous solution in a condition so that a surface area-to-planar surface area ratio R is smaller than 1.1. A multiplicity of fine textures are formed over the irregularities by dry etching. This allows fine textures to be formed uniformly, and a solar cell with high efficiency can thus be produced.
    Type: Grant
    Filed: January 22, 2004
    Date of Patent: October 31, 2006
    Assignee: Kyocera Corporation
    Inventor: Yosuke Inomata
  • Patent number: 7129176
    Abstract: An optical device includes a semiconductor substrate and an optical part having a plurality of columnar members disposed on the substrate. Each columnar member is disposed in a standing manner and adhered each other so that the optical part is provided. The optical part is integrated with the substrate. This optical part has high design freedom.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: October 31, 2006
    Assignee: Denso Corporation
    Inventors: Junji Oohara, Kazuhiko Kano, Yoshitaka Noda, Yukihiro Takeuchi, Toshiyuki Morishita
  • Patent number: 7125496
    Abstract: A method of etching is disclosed using a photoresist etch barrier formed by an exposure with a light source of which wavelength is in the range of 157 nm to 193 nm, such as an argon fluoride(ArF) laser or fluorine laser(F2 laser), the method includes the steps of coating a photoresist layer on a etch target layer; forming photoresist pattern by developing the photoresist layer after exposing the photoresist layer with a light source of which wavelength is in the range of 157 nm to 193 nm; forming a polymer layer and etching a portion of the etch target layer simultaneously with a mixture of fluorine-based gas, an Ar gas and an O2 gas, wherein the fluorine-based gas is CxFy or CaHbFc, and wherein x, y, a, b and c range from 1 to 10, respectively; and etching the etch target layer using the polymer layer and the photoresist pattern as the etch mask.
    Type: Grant
    Filed: June 10, 2002
    Date of Patent: October 24, 2006
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sung-Kwon Lee