Abstract: The present disclosure provides for a heatshield that can be actively cooled during a rework process. The heatshield may include a backer plate, a metal plate, and/or a package pedestal. The backer plate may include one or more air inlet ports configured to be connected to an air compressor. Air inlet ducts may extend from the air inlet ports through at least a portion of the backer plate. A plurality of vents may extend from the air inlet ducts to a top surface of the backer plate such that the plurality of vents directs cooling gas forced into the heatshield towards the metal plate and a first BGA. The cooling gas may maintain the solder joint temperature of the first BGA package below the reflow temperature and below the solidus temperature of the solder joints to prevent reflow-related solder joint defects from occurring in the first BGA package during rework of a second BGA package.

Abstract: A method for manufacturing electrical connector assemblies is disclosed. The electrical connector assemblies include an electrical interposer and a first electrical receptacle. The method includes positioning a fixture coupled to or including an array of the first electrical receptacles such that each of the first electrical receptacles aligns with one of the electrical interposers on an assembly with an array of the electrical interposers. The method further includes reflowing solder to mechanically and electrically couple the array of the first electrical receptacles to the array of the electrical interposers.

Abstract: The present disclosure is related to thermoelectric panels and their use in cooling and heating systems. The cooling/heating systems may include a plurality of thermoelectric panels. The panels may include thermoelectric devices embedded between a housing formed by heat conductive layers and edge structures for preserve a low thermal conductivity volume.

Abstract: The present invention has: a heater; and a bonding tool having a lower surface on which a memory chip is adsorbed; and an upper surface attached to the heater, and is provided with a bonding tool which presses the peripheral edge of the memory chip to a solder ball in a first peripheral area of the lower surface and which presses the center of the memory chip (60) to a DAF having a heat resistance temperature lower than that of the solder ball in a first center area. The amount of heat transmitted from the first center area to the center of the memory chip is smaller than that transmitted from the first peripheral area (A) to the peripheral edge of the memory chip. Thus, the bonding apparatus in which the center of a bonding member can be heated to a temperature lower than that at the peripheral edge can be provided.

Abstract: A semiconductor device is disclosed including a semiconductor die mounted on a substrate. The substrate includes a pattern of solder balls which is complementary and aligned to a pattern of solder bumps on the semiconductor die. These complementary and aligned patterns of solder balls and solder bumps minimize the lengths of current paths between the solder balls and solder bumps, and provide current paths between the solder balls and solder bumps of relatively uniform lengths.

Abstract: An electronic device (100) includes a substrate (110) and an integrated circuit (120) provided on the substrate (110) having a surface facing away from the substrate (110). An insulating layer (150) extends over the substrate (110) and around the integrated circuit (120) to define an interface (154) between the insulating layer (150) and the integrated circuit (120). An electrically conductive via (130) is provided on the surface of the integrated circuit (120). An insulating material (140) extends over the via (130) and includes an opening (142) exposing a portion of the via (130). A repassivation member (162) extends over the insulating layer (150) and has a surface (164) aligned with the interface (154). An electrically conductive redistribution member (181) is electrically connected to the via (130) and extends over the repassivation member (162) into contact with the insulating layer (150).

Abstract: A method for producing an electronic sensor module includes applying first soldering material onto electrical soldering pads of a printed circuit board element and/or electrical soldering pads of a printed circuit board element contact side of a sensor carrier, arranging the sensor carrier with the electrical soldering pads of the printed circuit board element contact side on the electrical soldering pads of the printed circuit board element to produce electrical connections between connecting lines and the printed circuit board element, applying second soldering material onto electrical connecting elements of a sensor element and/or soldering pads of the sensor receptacle, arranging the sensor element in the sensor receptacle such that the second soldering material produces electrical connections between the electrical connecting elements of the sensor element and the soldering pads of the sensor receptacle, and reflow-soldering the first soldering material and the second soldering material in a joint reflow

Abstract: The present invention provides a chip carrier structure including: a non-circuit substrate, a plurality of micro heaters, and an adhesive layer. The micro heaters are disposed on the non-circuit substrate. The adhesive layer is disposed on the micro heaters, and a plurality of chips are disposed on the adhesive layer. Thereby, the present invention improves the solder yield of the process by a wafer carrying structure and a wafer carrying device.

Abstract: The present invention relates to a reel-to-reel layer reflow method, which emits a uniformized laser beam, which can easily adjust the emission area, and which is for the purpose of improving productivity. An embodiment of the present invention provides a reel-to-reel layer reflow method comprising the steps of: a) transferring a substrate, which has been wound in a roll type, to one side while unwinding the same; b) forming a solder portion on the substrate; c) seating an emission target element on the solder portion and seating a non-emission target element on the substrate; d) surface-emitting a laser beam to the solder portion, on which the emission target element is seated, such that the emission target element is attached to the substrate; e) inspecting the substrate structure manufactured through said step d); and f) winding the substrate structure in a roll type.

Abstract: A flip-chip on leadframe package includes a leadframe having a plurality of leads with each lead including an inner leadfinger portion, wherein at least a landing region of all of the inner leadfinger portions are in a single common level (or plane) and include etched areas providing bump pads having concave landing sites (landing sites). A semiconductor die (die) having an active top side surface with functional circuitry including bond pads has bumps or pillars thereon. An area of the landing sites is greater than an area of the bumps or pillars. A distal end of the bumps or pillars is within and electrically coupling to the landing sites. A mold material encapsulates the die and at least a portion of the inner leadfinger portions. The package can be a leaded package or a leadless package.

Abstract: A face-up fan-out electronic package including at least one passive component located on a support. The electronic package can include a die. The die can include a plurality of conductive pillars having a proximal end communicatively coupled to the first side of the die and a distal end opposite the proximal end. A mold can at least partially surround the die. The mold can include a first surface that is coplanar with the distal end of the conductive pillars and a second surface opposing the first surface. In an example, the passive component can include a body and a lead. The passive component can be located within the mold. The lead can be coplanar with the first surface, and the body can be located at a distance from the second surface. The support can be located between the body and the second surface.

Abstract: A method of mounting a component includes an approaching step of causing the pair of clamping members to approach each other with the first body of the first component disposed between the paired clamping members, a clamping step of clamping the first component, and a mounting step of moving the pair of clamping members clamping the first component to the substrate and pressing out the first component clamped by the pair of clamping members with the pusher for mounting on the substrate, when the clamping members mount the first component on the substrate.

Abstract: The present invention provides a method for manufacturing an electronic device including a base material that has an exposed metal portion on a surface of the base material and an electronic component that is provided on the base material. The method includes a flux treatment step of treating the exposed metal portion with a flux by bringing the exposed metal portion into contact with the flux and an introduction step of introducing a resin composition such that the resin composition comes into contact with a surface of the exposed metal portion treated with the flux. The flux contains a rosin, an activator, and a solvent. The content of the rosin is equal to or greater than 1 part by mass and equal to or smaller than 18 parts by mass with respect to 100 parts by mass of the flux. The percent change in mass of the flux before and after a heating treatment is equal to or lower than 21% by mass. The resin composition contains an epoxy resin and a phenolic resin curing agent.

Abstract: The present disclosure provides an integrated circuit with an interconnect structure and a method for forming the integrated circuit. In one embodiment, a method of the present disclosure includes receiving a workpiece that includes a first recess in a dielectric layer over the workpiece, depositing a contact fill in the first recess and over the dielectric layer to form a contact feature, planarizing a top surface of the workpiece to remove the contact fill over the dielectric layer, depositing an interlayer dielectric layer over the planarized top surface of the workpiece, forming a second recess in the interlayer dielectric layer to expose the contact fill in the dielectric layer, recessing the contact fill by soaking the workpiece in a room temperature ionic liquid, and depositing a conductive layer over the recessed contact fill. The material forming the contact fill is soluble in the room temperature ionic liquid.

Abstract: A solder bonding method that bonds, using a solder joint, an electrode of a circuit board to an electrode of an electronic component includes: depositing, on the electrode of the circuit board, an Sn—Bi-based solder alloy with a lower melting point than a solder alloy deposited on the electrode of the electronic component; mounting the electronic component on the circuit board such that the Sn—Bi-based solder alloy contacts the solder alloy on the electrode of the electronic component; heating the circuit board to a peak temperature of heating of 150° C. to 180° C.; holding the peak temperature of heating at a holding time of greater than 60 seconds and less than or equal to 150 seconds; and cooling, after the heating and to form the solder joint, the circuit board at a cooling rate greater than or equal to 3° C./sec.

Abstract: A circuit assembly may include a substrate and a pattern of contact points formed from deformable conductive material supported by the substrate. The assembly may further include an electric component supported by the substrate and having terminals arranged in a pattern corresponding to the pattern of contacts points. The one or more of the terminals of the electric component may contact one or more of the corresponding contact points to form one or more electrical connections between the electric component and the contact points.

Abstract: An electronic component mounting method is performed by an electronic component mounting system including a component mounting line formed by interconnecting component mounting units which concurrently performs component mounting work on two kinds of boards different in mounting workload. The component mounting units includes: first and second board conveyance mechanisms; a component mounting unit; a board distribution unit which receives the board from the upstream-side apparatus and distributes the received board to either the first board conveyance mechanism or the second board conveyance mechanism; and a distribution control unit which controls the first board conveyance mechanism, the second board conveyance mechanism and the board distribution unit.

Abstract: The invention relates to a process to connect, by soldering, at least one electronic component (104, 204, 304, 404, 504) with a mounting plate (100, 200, 300, 400, 500), the mounting plate having at least one mounting plate contact surface (102, 202, 302, 402, 502) and the at least one electronic component having at least one component contact surface (105) corresponding to it, the at least one mounting plate contact surface being surrounded by a solder resist layer (101, 201, 301, 401, 501) that borders the at least one mounting plate contact surface, the process having the following steps: a) Applying solder paste (106, 206, 306, 406, 506) onto at least areas of the solder resist layer (101, 201, 301, 401, 501), minimally overlapping with the mounting plate contact surface (102, 202, 302, 402, 502) adjacent to the solder resist layer, b) Equipping the mounting plate with the at least one electronic component (104, 204, 304, 404, 504), the at least one component contact surface (105) at least partly covering

Abstract: One embodiment facilitates a shared memory. During operation, the system receives, by a memory expansion device, an I/O request via a first interface which is distinct from a memory bus, wherein the memory expansion device includes a first set of memory modules, and wherein the memory expansion device is attached to a computer system via the first interface. The system processes, by a controller of the memory expansion device, the I/O request. The system transmits, by the controller via a second interface, the I/O request to a selected memory module. The system executes, by the selected memory module, the I/O request, thereby allowing the computer system to expand memory capacity beyond memory slots available on the memory bus.

Abstract: In a method of manufacturing a semiconductor device, a semiconductor chip has first and second pads, a passivation film formed such that respective parts of the first and second pads are exposed, a first surface-metal-layer provided on the part of the first pad and a part of the passivation film, and a second surface-metal-layer provided on the part of the second pad and another part of the passivation film. Respective wires are electrically connected to the first and second surface-metal-layers. The semiconductor chip and the respective wires are then sealed with a resin.

Abstract: Various embodiments may provide an electrical connection structure. The electrical connection structure may include a first substrate having a first surface defining a cavity, and an inner wall defining a via extending from the cavity. The electrical connection structure may also include an interconnect structure provided in the via so that at least a portion of the interconnect structure protrudes into the cavity. The electrical connection structure may further include a second substrate having a second surface facing the first surface. The electrical connection structure may additionally include a connection element on the second surface. At least a portion of the connection element may be received in the cavity so that the connection element is in electrical connection with the interconnect structure.

Abstract: A circuit board includes a substrate and at least two through holes defined in the substrate. The substrate includes a first conductive circuit layer and a second conductive circuit layer. The first conductive circuit layer and the second conductive circuit layer are respectively formed on opposite surfaces of the substrate. A number of conductive strips are formed on an inner wall of each of the at least two through holes. The number of conductive strips on the inner wall of a first one of the at least two through holes faces the number of conductive strips on the inner wall of a second one of the at least one through hole.

Abstract: A method of measuring misalignment of chips, a method of fabricating a fan-out panel level package using the same, and a fan-out panel level package fabricated thereby are provided. The measuring method may include obtaining images by scanning chips on a substrate, obtaining absolute offsets of reference chips with respect to the substrate in the images, obtaining relative offsets of subordinate chips with respect to the reference chips in the images, and calculating misalignments of the chips based on the absolute offsets and the relative offsets.

Abstract: Herein provided are: a ceramic board; a semiconductor element for electric power, on one surface of which an electrode is formed, and the other surface of which is bonded to the ceramic board; a lead terminal, one end side of which is bonded to the electrode, and the other end side of which is to be electrically connected to an outside thereof; and a sealing member by which the semiconductor element for electric power is sealed together with a part, in the lead terminal, bonded to the electrode; wherein, near an end in said one end side of the lead terminal, an inclined surface is formed which becomes farther from the circuit board as it becomes closer to the end.

Abstract: The present disclosure relates to a computer-implemented method for electronic circuit design awareness. Embodiments may include providing, using a processor, an electronic design having a package layout and a die layout associated therewith. Embodiments may also include displaying at a graphical user interface, the package layout and allowing, at the graphical user interface, a user to edit the package layout. Embodiments may further include determining, using the processor, an impact of the edit on the die layout and in response to the edit, mirroring the edit at the die layout.

Abstract: Described herein are methods of manufacturing dual-sided packaged electronic modules to control the distribution of an under-fill material between one or more components and a packaging substrate. The disclosed technologies include forming a trench in a packaging substrate that is configured to prevent or limit the flow of a capillary under-fill material. This can prevent or limit the capillary under-fill material from flowing onto or contacting other components or elements on the packaging substrate, such as solder balls of a ball-grid array. Accordingly, the disclosed technologies control under-fill for dual-sided ball grid array packages using a trench in a packaging substrate.

Abstract: A method of manufacturing a solar cell module includes: placing a light reflection member across a gap between adjacent two solar cells set on a work table; and attaching the light reflection member to respective ends of the adjacent two solar cells, by thermocompression-bonding respective overlap regions of the light reflection member with the adjacent two solar cells using a compression bonding head that includes: a first thermocompression bonding portion and a second thermocompression bonding portion each having a contact surface that comes into contact with the light reflection member; and a non-thermocompression bonding portion interposed between the first thermocompression bonding portion and the second thermocompression bonding portion and not thermocompression-bonding the light reflection member.

Abstract: A face-up fan-out electronic package including at least one passive component located on a support. The electronic package can include a die. The die can include a plurality of conductive pillars having a proximal end communicatively coupled to the first side of the die and a distal end opposite the proximal end. A mold can at least partially surround the die. The mold can include a first surface that is coplanar with the distal end of the conductive pillars and a second surface opposing the first surface. In an example, the passive component can include a body and a lead. The passive component can be located within the mold. The lead can be coplanar with the first surface, and the body can be located at a distance from the second surface. The support can be located between the body and the second surface.

Abstract: Disclosed herein are methods of fabricating a packaged radio-frequency (RF) device. The disclosed methods use an encapsulant on solder balls to control the distribution of an under-fill material between one or more components and a packaging substrate. The encapsulant can be used in the ball attach process. The fluxing agent leaves behind a material that encapsulates the base of each solder ball. The encapsulant forms an obtuse angle with the substrate surface and with the ball surface. This reduces the tendency of the under-fill material to wick around the solder balls by capillary action which can prevent or limit the capillary under-fill material from flowing onto or contacting other components. Accordingly, the disclosed technologies control under-fill for dual-sided ball grid array packages using an encapsulant on the solder balls.

Abstract: A QFP has a die pad on which a semiconductor chip is mounted, a plurality of inner parts disposed around the die pad, a plurality of outer parts respectively connected with the plurality of inner parts, a plurality of wires electrically connect the bonding pads of the semiconductor chip and the plurality of inner parts, and a sealing body that seals the semiconductor chip. Moreover, the thickness of the semiconductor chip is larger than a thickness from a lower surface of the die pad to a lower surface of the sealing body, and a distance from the lower surface of the sealing body to a tip portion of each of the plurality of outer parts is larger than a thickness of the sealing body from a main surface of the semiconductor chip to an upper surface of the sealing body.

Abstract: A display apparatus and a fabricating method for a display apparatus are provided. The fabricating method for the display apparatus includes the following steps. An array substrate having a first electrode and a second electrode is provided. A first light emitting diode is heated to soften a first bump between the first electrode and the first light emitting diode, the first light emitting diode is bonded onto the first electrode by the first bump. The first light emitting diode and a second light emitting diode are heated to soften the first bump and a second bump between the second electrode and the second light emitting diode, the second light emitting diode is bonded onto the second electrode by the second bump, and the first light emitting diode and the second light emitting diode are pressed.

Abstract: In one example, a flexible circuit board includes a signal line disposed between a first ground and a second ground; a dielectric disposed between the first ground and the signal line and between the second ground and the signal line; a cover layer disposed below the first ground and having openings formed therein such that the first ground is exposed at certain intervals; and a position alignment portion formed across the opening and configured to bisect an area of the opening.

Abstract: Various circuit boards and methods of manufacturing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a solder mask on a circuit board with a first opening that has a sidewall. A solder interconnect pad is formed in the first opening. The sidewall sets the lateral extent of the solder interconnect pad.

Abstract: The present disclosure provides a conductor connecting structure that connects a cable to a substrate, where the substrate includes at least one connection pad, the cable includes at least one core wire, the core wire is connected to an upper surface of the connection pad through soldering, and the connection pad includes a solder storing part that is present further frontward than a front end of the core wire.

Abstract: An apparatus includes a frame to hold a wafer tape having a first side and a second side. A plurality of semiconductor device dies are disposed on the first side of the wafer tape. A support member supports a product substrate having a circuit trace thereon. The support member is configured to hold the product substrate such that the circuit trace is disposed facing the plurality of semiconductor device dies on the wafer tape. A plurality of needles are disposed adjacent the second side of the wafer tape. A needle actuator is connected to the plurality of needles and is configured to move at least one needle of the plurality of needles to a die transfer position at which the at least one needle presses on the second side of the wafer tape to press a semiconductor device die into contact with the circuit trace.

Abstract: A via structure for electric connection is disclosed. The via structure includes a substrate that has a first surface and a via hole opened to the first surface. The via structure includes also a stress buffer layer disposed on the first surface of the substrate, which has an opening aligned to the via hole of the substrate. The via structure further includes a conductive body formed in the via hole of the substrate at least up to the level of the first surface of the substrate. In the via structure, the stress buffer layer receives the conductive body extending into the opening over the level of the first surface of the substrate and/or covers, at least in part, the edge of the first surface around the via hole of the substrate.

Abstract: A method of forming a 3D package. The method may include joining an interposer to a laminate chip carrier with the solid state diffusion of a first plurality of solder bumps by applying a first selective non-uniform heat and first uniform pressure; joining a top chip to the interposer with the solid state diffusion of a second plurality of solder bumps by applying a second selective non-uniform heat and second uniform pressure; heating the 3D package, the first and second pluralities of solder bumps to a temperature greater than the reflow temperature of the first and second pluralities of solder bumps, where the second plurality of solder bumps achieves the reflow temperature before the first plurality of solder bumps, where the first and second selective non-uniform heats being less that the reflow temperature of the first and second pluralities of solder bumps, respectively.

Abstract: An apparatus, for attaching a semiconductor device die to a circuit substrate, includes an elongated rod to press a holding substrate carrying the semiconductor device die into a position at which the semiconductor device die attaches to the circuit substrate; and a support including a base portion having a hole via which the elongated rod passes when actuated to press the holding substrate.

Abstract: The present disclosure relates to an IC chip extractor for removing an IC chip from a panel. The IC chip extractor includes a base plate and a heating head arranged on the base plate. The heating head includes a protrusion protruded from an end of the heating head and a hook arranged at an end of the protrusion, the hook is capable of being in contact with a bottom of a portion the IC chip adjacent to a center of the panel.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations to control movement and position of surface mounted electrical devices. In one embodiment, an electrical contact includes a leg portion configured to extend in a first direction, a foot portion coupled with the leg portion, the foot portion having a surface that extends in a second direction that is substantially perpendicular to the first direction, the surface being configured to directly couple with solderable material to form a solder joint, a heel portion adjoining the leg portion and the foot portion, the heel portion having a profile shape, and a toe portion extending from the foot portion and disposed opposite to the heel portion, the toe portion having a profile shape that is symmetric with the profile shape of the heel portion. Other embodiments may be described and/or claimed.

Abstract: A manufacturing apparatus of a semiconductor device includes a stage, a head unit configured to face the stage, a driving unit configured to move the head unit towards and away from the stage, a heating unit configured to heat the head unit, and a control unit configured to control the driving unit to move the head unit away from the stage when the heating unit heats the head unit.

Abstract: A method of bonding two different substances includes the steps of: applying a bonding material containing a flux component that includes an organic material having at least two carboxyl groups to a bonding surface of a bonding object, disposing an object to be bonded on the bonding material, performing preliminary firing at a preset temperature in a state in which the object to be bonded is disposed, and performing a main firing by heating at a temperature higher than the temperature of the preliminary firing.

Abstract: Method and apparatus for establishing an electrical interconnection between an electrical lead and a printed circuit board (PCB), such as a PCB used in a data storage device. In some embodiments, the PCB includes a multi-layer substrate having at least one conductive layer and at least one electrically insulative layer. An electrically conductive pad is provided on a facing surface of the substrate in electrical communication with the at least one conductive layer. A flux reservoir is placed adjacent the pad which extends from the facing surface into the substrate. A solder mask layer is provided on the facing surface of the base structure which surrounds the pad and extends into the reservoir. The solder mask layer and reservoir collect liquid flux from a soldering operation used to form a solder joint between the pad and a conductive lead of an electronic component.

Abstract: An embedded component substrate includes: a core layer; a first electrode provided on a top surface of the core layer with a first insulating layer therebetween; and a second electrode provided on a bottom surface of the core layer with a second insulating layer therebetween, wherein a cavity is formed in the embedded component substrate from a top surface thereof to expose the second insulating layer at a bottom of the cavity, wherein a placement region is defined on the bottom of the cavity, for accommodating an electronic component; and wherein the embedded component substrate further includes a pad electrode on a portion of the second insulating layer, exposed by the cavity, surrounding the placement region located on the bottom of the cavity, the pad electrode vertically protruding from a top surface of the exposed second insulating layer upwardly and being configured to electrically connect to the electronic component.

Abstract: A QFP has a die pad on which a semiconductor chip is mounted, a plurality of inner parts disposed around the die pad, a plurality of outer parts respectively connected with the plurality of inner parts, a plurality of wires electrically connect the bonding pads of the semiconductor chip and the plurality of inner parts, and a sealing body that seals the semiconductor chip. Moreover, the thickness of the semiconductor chip is larger than a thickness from a lower surface of the die pad to a lower surface of the sealing body, and a distance from the lower surface of the sealing body to a tip portion of each of the plurality of outer parts is larger than a thickness of the sealing body from a main surface of the semiconductor chip to an upper surface of the sealing body.

Abstract: A lead bonding structure includes: a plurality of leads extending outward from a package; and a plurality of electrode pads formed on a circuit board. The plurality of leads are soldered to the electrode pads, respectively. Each of the leads includes a lower wide portion having a width dimension greater than a width dimension of each of the electrode pads. The lower wide portion of each of the leads is soldered to the corresponding electrode pad.

Abstract: The present invention relates to a circuit board assembly, comprising a circuit board which has a first and a second solder region, which is galvanically separated from the first, and which furthermore has a separator arranged between the solder regions and rising out from the solder regions, having a power semiconductor component which has a housing having an output connection side, from which at least one control connection and a plurality of output connections protrude, which are arranged substantially adjacent to each other on the output connection side, wherein the control connection is electrically and mechanically connected to the first solder region and the output connections are electrically and mechanically connected to the second solder region and the control connection is separated from the output connections via the raised separator.

Abstract: One or more embodiments disclosed herein are directed to a chip scale package camera module that includes a glass interposer between a lens and an image sensor. In some embodiments, the glass interposer is made from one or more layers of optical quality glass and includes an infrared filter coating. The glass interposer also includes electrically conductive paths to connect the image sensor, mounted on one side of the glass interposer, with other components such as capacitors, which may be mounted on a different side of the glass interposer, and the rest of the camera system. The conductive layers include traces and vias that are formed in the glass interposer in areas away from the path of light in the camera module, such that the traces and vias do not block the light between the lens and the image sensor.

Abstract: An apparatus includes a substrate and a circuit trace having a predetermined pattern disposed on the substrate. A plurality of LEDs are connected to the substrate via the circuit trace. The predetermined pattern is arranged as an array of lines along a surface of the substrate, and the plurality of LEDs are distributed along the lines of the array.

Abstract: An electronic packaging assembly having a semiconductor integrated circuit and a plurality of interconnect components is provided. The plurality of interconnect components is operatively coupled to the semiconductor integrated circuit. Further, one or more interconnect components include one or more support elements having a first surface and a second surface, and one or more spring elements having a first end and a second end, and wherein first ends of the one or more spring elements are coupled to the first surface or the second surface of a respective support element.