Lead-less (or "bumped") Device Patents (Class 228/180.22)
  • Patent number: 10729023
    Abstract: A method for producing an electronic assembly includes providing a printed circuit board with a first face, a second face facing away from the first face, and a first component arranged on the first face. The method further includes arranging the circuit board such that the second face lies on a reference surface, and applying a sealing material which is substantially not flowable prior to being cured onto the first face. The sealing material surrounds a sub-region of the first face of the circuit board. The method further includes arranging a second component at least partly on the reference surface such that the second component is pressed into the sealing material, electrically connecting the second component to the circuit board via an electric connection line, and applying a covering material onto the circuit board first face sub-region surrounded by the sealing material and onto the first component.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: July 28, 2020
    Assignee: Robert Bosch GmbH
    Inventors: Peter Zweigle, Helmut Deringer, Jens Hoffmann
  • Patent number: 10714448
    Abstract: A chip module includes a body, a bump, and a first bonding layer. The bump is disposed on the body. The first bonding layer is disposed on the bump. The first bonding layers and the bump are made of the same conductive material and the first bonding layer is porous.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: July 14, 2020
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Chin-Sheng Wang, Ra-Min Tain
  • Patent number: 10700045
    Abstract: Package structures and methods of forming them are described. In an embodiment, a package structure includes an integrated circuit die embedded in an encapsulant and a redistribution structure on the encapsulant. The redistribution structure includes a metallization layer distal from the encapsulant and the integrated circuit die, and a dielectric layer distal from the encapsulant and the integrated circuit die and on the metallization layer. The package structure also includes a first under metallization structure on the dielectric layer and a Surface Mount Device and/or Integrated Passive Device (“SMD/IPD”) attached to the first under metallization structure. The first under metallization structure includes first through fourth extending portions extending through first through fourth openings of the dielectric layer to first through fourth patterns of the metallization layer, respectively.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Hsieh, Hsien-Wei Chen, Chi-Hsi Wu, Chen-Hua Yu, Der-Chyang Yeh, Wei-Cheng Wu
  • Patent number: 10692835
    Abstract: A method for forming a ball bond for an integrated circuit formed on a semiconductor die includes forming a ball at a first send of a conductive wire inserted in a capillary tool and lowering the capillary tool toward a pad on the semiconductor die positioned on a support surface. The method further includes moving, using a motor, the support surface relative to the capillary tool to thereby bond the ball, without using ultrasound, to the pad and then raising the capillary tool.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: June 23, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Han Zhong, Zi Qi Wang, Chen Xiong, Yong Qiang Tang, Xi Lin Li, Xiao Lin Kang
  • Patent number: 10679966
    Abstract: A method for removing an electrical component from a substrate where the component is coupled to the substrate by connection elements. The method includes disposing liquid gallium (Ga) at or near an edge of the component and dispersing the liquid Ga between the substrate and the component such that the liquid Ga contacts one or more of the connection elements. The method also includes maintaining the liquid Ga between the substrate, component and one or more of the connection elements for a prescribed time period and removing the component from the substrate by applying a mechanical force to the component.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: June 9, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David Danovitch, Yolande Elodie Nguena Dongmo, Richard Langlois
  • Patent number: 10661394
    Abstract: Disclosed is a metal core solder ball having improved heat conductivity, including a metal core having a diameter of 40˜600 ?m, a first plating layer formed on the outer surface of the metal core, and a second plating layer formed on the outer surface of the first plating layer.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: May 26, 2020
    Assignee: DUKSAN HI-METAL CO., LTD.
    Inventors: Yong Cheol Chu, Hyun Kyu Lee, Jung Ug Kwak, Seung Jin Lee, Sang Ho Jeon, Yong Sik Choi
  • Patent number: 10643965
    Abstract: A method of manufacturing a semiconductor device structure includes forming a bond or joint between a first device and a second device. The first device comprises an integrated passive device (IPD) and a first contact pad disposed over the IPD. The second device comprises a second contact pad. The first contact pad has a first surface with first lateral extents. The second contact pad has a second surface with second lateral extents. The width of the second lateral extents is less than the width of the first lateral extents. The joint structure includes the first contact pad, the second contact pad, and a solder layer interposed therebetween. The solder layer has tapered sidewalls extending in a direction away from the first surface of the first contact pad to the second surface of the second contact pad. At least one of the first surface or the second surface is substantially planar.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: May 5, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Ju Chen, An-Jhih Su, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu
  • Patent number: 10607906
    Abstract: To provide a semiconductor package including a protruding part at the bottom surface of a package main body. A semiconductor package including a semiconductor chip is provided, the semiconductor package including: a package main body; a plurality of electrodes exposed at a bottom surface of the package main body; and a protruding part projecting from the bottom surface of the package main body and above the plurality of electrodes, wherein the protruding part is arranged not to overlap two least separated electrodes, among the plurality of electrodes, in a second direction different from a first direction in which the two electrodes are arrayed.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: March 31, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Takayuki Shimatou
  • Patent number: 10593645
    Abstract: A semiconductor device, includes: a first semiconductor chip including: a first substrate; a first via; a first rear surface-side pad connected to the first via; a first wiring layer; a first front surface-side pad formed on the first wiring layer; and an input circuit formed in the first substrate, an input signal wire connecting the first via, the first front surface-side pad, and an input terminal of the input circuit; and a second semiconductor chip including: a second substrate; a second wiring layer; a second front surface-side pad; and an output circuit formed in the second substrate, an output signal wire connecting the second front surface-side pad to an output terminal of the output circuit. The second semiconductor chip is stacked on a rear surface side of the first semiconductor chip, and the first rear surface-side pad and the second front surface-side pad are connected.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: March 17, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Takahiro Shikibu, Yusuke Hamada, Osamu Moriyama
  • Patent number: 10573616
    Abstract: The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: February 25, 2020
    Assignee: MediaTek Inc.
    Inventors: Tzu-Hung Lin, Wen-Sung Hsu, Ta-Jen Yu, Andrew C. Chang
  • Patent number: 10568245
    Abstract: Provided is a flip chip mounting apparatus for mounting chips (400) to a substrate (200), and the apparatus includes at least one sectionalized mounting stage (45) divided into a heating section (452) and a non-heating section (456), the heating section being for heating a substrate (200) fixed to a front surface of the heating section, the non-heating section not heating the substrate (200) suctioned to a front surface of the non-heating section. With this, it is possible to provide an electronic-component mounting apparatus that is simple and capable of efficiently mounting a large number of electronic components.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: February 18, 2020
    Assignee: SHINKAWA LTD.
    Inventor: Kohei Seyama
  • Patent number: 10559549
    Abstract: A method for removing an electrical component from a substrate where the component is coupled to the substrate by connection elements. The method includes disposing liquid gallium (Ga) at or near an edge of the component and dispersing the liquid Ga between the substrate and the component such that the liquid Ga contacts one or more of the connection elements. The method also includes maintaining the liquid Ga between the substrate, component and one or more of the connection elements for a prescribed time period and removing the component from the substrate by applying a mechanical force to the component.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: February 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David Danovitch, Yolande Elodie Nguena Dongmo, Richard Langlois
  • Patent number: 10551578
    Abstract: A system may include a substrate and a lens component. The substrate may include pads and solder protuberances. Each solder protuberance may be located on a pad. The lens component may define grooves sized to receive at least a portion of the solder protuberances. The lens component may be positioned relative to the substrate such that at least a portion of each solder protuberance is positioned within the grooves.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: February 4, 2020
    Assignee: Finisar Corporation
    Inventors: Darin James Douma, Frank J. Flens
  • Patent number: 10535593
    Abstract: A package structure including a circuit substrate, a semiconductor die, a redistribution layer, a plurality of conductive balls and a circuit substrate is provided. The redistribution layer is disposed on the semiconductor die, and being electrically connected to the semiconductor die. The plurality of conductive balls is disposed between the redistribution layer and the circuit substrate. The semiconductor die is electrically connected to the circuit substrate through the conductive balls. Each of the conductive balls has a ball foot with a first width D1, a ball head with a third width D3 and a ball waist with a second width D2 located between the ball foot and the ball head. The ball foot is connected to the redistribution layer, the ball head is connected to the circuit substrate, and the ball waist is the narrowest portion of each of the conductive balls.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pi-Lan Chang, Chen-Shien Chen, Chin-Yu Ku, Hsu-Hsien Chen, Wei-Chih Huang, Chun-Ying Lin, Li-Chieh Chou
  • Patent number: 10490971
    Abstract: A method of forming a laser including device is provided that in one embodiment includes providing a laser chip including at least one ridge structure that provides an alignment features. The method further includes bonding a type IV photonics chip to the laser chip, wherein a vertical alignment feature from the type IV photonics chip is inserted in a recess relative to the at least one ridge structure that provides the alignment features of the laser structure.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: November 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tymon Barwicz, Yves C. Martin, Jason S. Orcutt
  • Patent number: 10477698
    Abstract: An improved solder column, having a solder core comprising a solder core material, an exoskeleton sleeve structure surrounding at least a majority of an outside surface of the solder core and comprising a plurality of wires woven together to form a mesh, and a plurality of spaces formed in the exoskeleton between the plurality of wires. The exoskeleton sleeve can be configured such that the exoskeleton sleeve will support the solder core so as to prevent a collapse of the solder core at temperatures exceeding a liquidus temperature of the solder core. Optionally, each of the plurality of spaces can have a width and a height that is at least as large as a width of the wire adjacent to the space, and the spaces can be configured to provide additional flexibility to the solder column.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: November 12, 2019
    Assignee: TOPLINE CORPORATION
    Inventor: Martin B. Hart
  • Patent number: 10453813
    Abstract: A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: October 22, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chang-Chia Huang, Tsung-Shu Lin, Cheng-Chieh Hsieh, Wei-Cheng Wu
  • Patent number: 10451672
    Abstract: A probing apparatus for detection of an electric signal generated by a device-under-test. The probing apparatus includes a rigid support structure having a contact surface for sliding contact with the device-under-test, and a probing instrument to contact the connector for tapping the electric signal. Magnets on the support structure apply attracting force on a mating metal element on the device-under-test such that the probing instrument is aligned to contact the connector, wherein a gap is formed between each magnet and mating metal element when the contact surface touches the device-under-test.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: October 22, 2019
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Vignesh Narasaraju, Karl-gösta Helgesson
  • Patent number: 10418316
    Abstract: A semiconductor substrate includes a first dielectric structure and a first circuit layer. The first circuit layer is embedded in the first dielectric structure. The first circuit layer does not protrude from a first surface of the first dielectric structure. The first circuit layer includes at least one conductive segment. The conductive segment includes a first portion adjacent to the first surface of the first dielectric structure and a second portion opposite to the first portion. A width of the first portion of the conductive segment is different from a width of the second portion of the conductive segment.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: September 17, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 10388622
    Abstract: In some embodiments, the present disclosure relates to a method of integrated chip bonding. The method is performed by forming a metal layer on a substrate, and forming a solder layer on the metal layer. The solder layer is reflowed. The metal layer and the solder layer have sidewalls defining a recess that is at least partially filled by the solder layer during reflowing of the solder layer.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: August 20, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Horng Chang, Tin-Hao Kuo, Chen-Shien Chen, Yen-Liang Lin
  • Patent number: 10373897
    Abstract: A device may include a carrier, a semiconductor chip arranged over a first surface of the carrier, and an encapsulation body comprising six side surfaces and encapsulating the semiconductor chip. A second surface of the carrier opposite to the first surface of the carrier is exposed from the encapsulation body. The device may further include electrical contact elements electrically coupled to the semiconductor chip and protruding out of the encapsulation body exclusively through two opposing side surfaces of the encapsulation body which have the smallest surface areas of all the side surfaces of the encapsulation body, and an electrically insulating layer arranged over the exposed second surface of the carrier.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: August 6, 2019
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Ralf Otremba, Felix Grawert, Amirul Afiq Hud, Uwe Kirchner, Teck Sim Lee, Guenther Lohmann, Hwee Yin Low, Edward Fuergut, Bernd Schmoelzer, Fabian Schnoy, Franz Stueckler
  • Patent number: 10354973
    Abstract: A method for producing a semiconductor chip is a method for producing a semiconductor chip that includes a substrate, a conductive portion formed on the substrate, and a microbump formed on the conductive portion, which includes a smooth surface formation process of forming a smooth surface on the microbump, and the smooth surface formation process includes a heating process of causing a reducing gas to flow in an inert atmosphere into a space where the semiconductor chips are arranged and heated at or higher than a temperature of a melting point of the microbump, and in the heating process, a pressure application member is mounted on the microbump and among principal surfaces of the pressure application member, a principal surface that contacts the microbump is a flat surface.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: July 16, 2019
    Assignee: TDK CORPORATION
    Inventors: Makoto Orikasa, Hideyuki Seike, Yuhei Horikawa, Hisayuki Abe
  • Patent number: 10342126
    Abstract: A method of making an electronic device includes forming a circuit layer on a liquid crystal polymer (LCP) substrate and having at least one solder pad. The method also includes forming an LCP solder mask having at least one aperture therein alignable with the at least one solder pad. The method further includes aligning and laminating the LCP solder mask and the LCP substrate together, then positioning solder paste in the at least one aperture. At least one circuit component may then be attached to the at least one solder pad using the solder paste.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: July 2, 2019
    Assignee: HARRIS CORPORATION
    Inventors: Louis Joseph Rendek, Jr., Travis L. Kerby, Casey Philip Rodriguez
  • Patent number: 10340248
    Abstract: A bonding system includes a substrate transfer device configured to transfer a first substrate and a second substrate in a normal pressure atmosphere, a surface modifying apparatus configured to modify surfaces of the first substrate and the second substrate to be bonded with each other in a depressurized atmosphere, a load lock chamber in which the first substrate and the second substrate are delivered between the substrate transfer device and the surface modifying apparatus and in which an internal atmosphere of the load lock chamber is switchable between an atmospheric pressure atmosphere and the depressurized atmosphere, a surface hydrophilizing apparatus configured to hydrophilize the modified surfaces of the first substrate and the second substrate, and a bonding apparatus configured to bond the hydrophilized surfaces of the first substrate and the second substrate by an intermolecular force.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: July 2, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Masataka Matsunaga, Takashi Koga, Takeshi Tamura, Takahiro Masunaga, Yuji Mimura, Masaru Honda, Toshifumi Inamasu, Satoshi Nishimura
  • Patent number: 10327325
    Abstract: A printed circuit board (1) comprising an insulating layer (2) and a conducting layer (3) arranged on the insulating layer (2) and structured into a contact surface (4) for an electronic component (11) which is to be populated on the printed circuit board (1) has, in the area of the contact surface (4), at least one channel (8) that passes through the contact surface (4) and the insulating layer (2) and that is filled with a thermally conductive material.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: June 18, 2019
    Assignee: ZK W Group GmbH
    Inventors: Erik Edlinger, Dietmar Kieslinger
  • Patent number: 10319606
    Abstract: An integrated circuit interconnects are described herein that are suitable for forming integrated circuit chip packages. In one example, an integrated circuit interconnect is provided that includes a package substrate having a plurality of solder balls coupled to a plurality of contact pads. The package substrate includes a solder mask having a plurality of stepped openings, a plurality of contact pads, and circuitry disposed in the package substrate and coupled to the plurality of contact pads. The solder mask defines a top side of the package substrate. The stepped openings expose the contact pads through solder mask.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: June 11, 2019
    Assignee: XILINX, INC.
    Inventors: Jaspreet Singh Gandhi, Tien-Yu Lee, Henley Liu, Ivor G. Barber, Suresh Ramalingam
  • Patent number: 10290788
    Abstract: Light-emitting devices and particularly light-emitting device assemblies that include light-emitting diodes (LEDs) as light sources are described. The methods and systems of at least some of the embodiments described herein increase the removal of thermal energy generated by the light-emitting devices.
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: May 14, 2019
    Assignee: Luminus Devices, Inc.
    Inventors: Jay Guoxu Liu, Paul Panaccione
  • Patent number: 10283549
    Abstract: Some embodiments of the present disclosure relate to a method of forming an integrated chip. The method includes forming a first interconnect wire within a first inter-level dielectric (ILD) layer over a substrate. One or more vias are formed on the first interconnect wire and within a second ILD layer separated from the substrate by the first ILD layer. One or more additional vias are formed within the second ILD layer. Respective ones of the one or more vias have a larger size than respective ones of the one or more additional vias. A thickness of the substrate is reduced, and the substrate is etched to form a bond pad opening extending through the substrate to the first interconnect wire. A bond pad is formed within the bond pad opening and directly over the one or more vias.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: May 7, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sin-Yao Huang, Ching-Chun Wang, Dun-Nian Yaung, Feng-Chi Hung
  • Patent number: 10276481
    Abstract: A package structure including a circuit substrate, a semiconductor die, a redistribution layer, a plurality of conductive balls and a circuit substrate is provided. The redistribution layer is disposed on the semiconductor die, and being electrically connected to the semiconductor die. The plurality of conductive balls is disposed between the redistribution layer and the circuit substrate. The semiconductor die is electrically connected to the circuit substrate through the conductive balls. Each of the conductive balls has a ball foot with a first width D1, a ball head with a third width D3 and a ball waist with a second width D2 located between the ball foot and the ball head. The ball foot is connected to the redistribution layer, the ball head is connected to the circuit substrate, and the ball waist is the narrowest portion of each of the conductive balls.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pi-Lan Chang, Chen-Shien Chen, Chin-Yu Ku, Hsu-Hsien Chen, Wei-Chih Huang, Chun-Ying Lin, Li-Chieh Chou
  • Patent number: 10269749
    Abstract: A method for manufacturing semiconductor devices is provided. A protection layer is conformally deposited over a passivation layer such that the protection layer has a protrusion pattern that protrudes from a top surface of the protection layer. Further, a post-passivation interconnect structure (PPI) is conformally formed on the protection layer such that the PPI structure includes a landing pad region, a protrusion pattern conformal to the protrusion pattern of the protection layer, and a connection line electrically connected to the conductive pad. A solder bump is then placed on the landing pad region in contact with the protrusion pattern of PPI structure. A semiconductor device with bump stop structure is also provided. The protrusion pattern of the PPI structure serves as a bump stop that constrains a ball shift in the placement of the solder bump over the landing pad.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Jie Chen, Hsien-Wei Chen
  • Patent number: 10270532
    Abstract: An optical transmission module includes: a main substrate having a front surface and a back surface; an optical connector having a connector substrate; a first transparent substrate disposed between the connector substrate and the main substrate; a heat source element disposed between the connector substrate and the back surface of the main substrate, and electrically connected to the main substrate; one or a plurality of wirings electrically connecting the heat source element to the main substrate, and each configured to transfer heat generated from the heat source element and the first transparent substrate, to the main substrate; a first special region preventing the heat generated from the heat source element and the first transparent substrate, from being transferred to the connector substrate; and a second special region providing a function of transferring the heat generated from the heat source element and the first transparent substrate.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: April 23, 2019
    Assignee: Sony Corporation
    Inventor: Hiizu Ootorii
  • Patent number: 10256113
    Abstract: A transfer substrate for transferring a metal wiring material to a transfer target including a substrate, at least one metal wiring material formed on the substrate, at least one coating layer formed on a surface of the metal wiring material, and an underlying metal film formed between the substrate and the metal wiring material, in which the metal wiring material is a compact formed by sintering metal powder such as gold powder having a purity of 99.9 wt % or more and an average particle size of 0.01 ?m to 1.0 ?m, and the coating layer is a predetermined metal such as gold or an alloy having a different composition from that of the metal wiring material and has a total thickness of 1 ?m or less, and the metal underlying film is made of a predetermined metal such as gold or an alloy. The transfer substrate can lower heating temperature on the transfer target side.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: April 9, 2019
    Assignee: TANAKA KIKINZOKU KOGYO K.K.
    Inventors: Toshinori Ogashiwa, Masaaki Kurita, Takashi Nishimori, Yukio Kanehira
  • Patent number: 10244631
    Abstract: A microwave device can include a printed circuit board substrate having a first microwave device subcircuit and a microdevice substrate having a second microwave device subcircuit. The first microwave device subcircuit may be formed at a low resolution and a low tolerance, while the second microwave device subcircuit may be formed at a high resolution and a high tolerance. The first microwave device subcircuit and the second microwave device subcircuit may be electrically coupled using a conductor.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: March 26, 2019
    Assignee: THE BOEING COMPANY
    Inventors: Tai Anh Lam, Jean Ann Nielsen, Minas H. Tanielian
  • Patent number: 10244632
    Abstract: A microelectronic structure may be formed comprising a microelectronic package having a plurality of interconnects and a microelectronic substrate including an upper metallization layer and a solder resist structure, wherein the solder resist structure includes a first structure which forms an electrical connection between a first interconnect of the plurality of interconnects of the microelectronic package and the upper metallization layer of the microelectronic substrate, and wherein solder resist structure includes a second structure which prevents second interconnect of the plurality of interconnects of the microelectronic package from making electrical contact with the upper metallization layer.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: March 26, 2019
    Assignee: Intel Corporation
    Inventors: Li-Sheng Weng, Chi-Te Chen, Wei-Lun Jen, Olivia Chen, Yun Ling
  • Patent number: 10225930
    Abstract: A method of producing a suspension board with circuit includes the steps of preparing a metal supporting layer, forming a curable insulating layer on the metal supporting layer using a photosensitive curable insulating composition such that an opening is formed in the curable insulating layer, curing the curable insulating layer to form an insulating layer, subjecting the metal supporting layer exposed from the opening to microwave plasma treatment, and forming a metal conducting portion on the metal supporting layer exposed from the opening.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: March 5, 2019
    Assignee: NITTO DENKO CORPORATION
    Inventors: Daisuke Yamauchi, Takatoshi Sakakura
  • Patent number: 10220619
    Abstract: Provided are an MEMS device, a head, and a liquid jet device in which substrates are inhibited from warping, so that a primary electrode and a secondary electrode can be reliably connected to each other. Included are a primary substrate 30 provided with a bump 32 including a primary electrode 34, and a secondary substrate 10 provided with a secondary electrode 91 on a bottom surface of a recessed portion 36 formed by an adhesive layer 35. The primary substrate 10 and the secondary substrate 30 are joined together with the adhesive layer 35, the primary electrode 34 is electrically connected to the secondary electrode 91 with the bump 32 inserted into the recessed portion 36, and part of the bump 32 and the adhesive layer 35 forming the recessed portion 36 overlap each other in a direction in which the bump 32 is inserted into the recessed portion 36.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: March 5, 2019
    Assignee: Seiko Epson Corporation
    Inventor: Shuichi Tanaka
  • Patent number: 10217712
    Abstract: A semiconductor package includes a substrate, a dielectric layer, at least one conductive pillar and an electrical device. The dielectric layer is disposed on the substrate and defines at least one through hole corresponding to the respective first pad of the substrate. The conductive pillar is disposed in the respective through hole. The conductive pillar includes a body portion and a cap portion. The body portion is physically connected to the cap portion, and the cap portion is electrically connected to the first pad. A maximum width of the cap portion is greater than a maximum width of the body portion. The electrical device is disposed on the dielectric layer and electrically connected to the body portion of the conductive pillar.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: February 26, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 10189706
    Abstract: A method of attaching a MEMS die to a surface includes centering and rotationally aligning a solder perform on a solder surface of a body, centering and rotationally aligning a MEMS die on the solder preform, and heating the solder perform in a reflow process until the solder is molten and surface tension of the molten solder moves the MEMS die to a position where the surface tensions balance, and the MEMS die is centered on, and rotationally aligned with, the solder surface of the body.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: January 29, 2019
    Assignee: DunAn Microstaq, Inc.
    Inventors: Wayne C. Long, Joe A. Ojeda, Gengxun K. Gurley, Joseph L. Nguyen
  • Patent number: 10178755
    Abstract: A circuit board includes a first dielectric layer, a first circuit layer, a second circuit layer, a plurality of conductive vias, a second dielectric layer, a patterned seed layer, and a plurality of bonding layers. The first circuit layer is disposed in the first dielectric layer. The second circuit layer is disposed on the first dielectric layer. The conductive vias are disposed in the first dielectric layer and connect the first circuit layer to the second circuit layer. The second dielectric layer is disposed on the first dielectric layer and the second circuit layer and has a plurality of openings to expose a plurality of parts of the second circuit layer. The patterned seed layer is disposed on the exposed parts of second circuit layer and sidewalls of the openings. The bonding layers are respectively disposed on the patterned seed layer and made of porous copper.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: January 8, 2019
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Ra-Min Tain, Kai-Ming Yang, Chien-Tsai Li
  • Patent number: 10173287
    Abstract: Provided is a solder material which enables a growth of an oxide film to be inhibited. A solder ball which is a solder material is composed of a solder layer and a covering layer covering the solder layer. The solder layer is spherical and is composed of a metal material containing an alloy including Sn content of 40% and more. Otherwise the solder layer is composed of a metal material including Sn content of 100%. In the covering layer, a SnO film is formed outside the solder layer, and a SnO2 film is formed outside the SnO film. A thickness of the covering layer is preferably more than 0 nm and equal to or less than 4.5 nm. Additionally, a yellow chromaticity of the solder ball is preferably equal to or less than 5.7.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: January 8, 2019
    Assignee: Senju Metal Industry Co., Ltd.
    Inventors: Hiroyoshi Kawasaki, Takahiro Roppongi, Daisuke Soma, Isamu Sato, Yuji Kawamata
  • Patent number: 10177108
    Abstract: A method of manufacturing an electronic component module and the electronic component module manufactured by the manufacturing method includes bumps, each including a thicker portion having a relatively large thickness and a thinner portion having a relatively small thickness and formed on one surface of the substrate. When looking at the electronic component in a mounted state in a plan view, the thicker portion is positioned on a side of a corresponding outer terminal closer to a center of the electronic component and the thinner portion is positioned on the opposite side of the corresponding outer terminal. In the plan view, joining portions joining the outer terminals respectively to the bumps are formed such that a height of each joining portion on the opposite side is lower than a height of the joining portion on the side closer to the center of the electronic component.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: January 8, 2019
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shinya Kiyono, Yoshiaki Satake
  • Patent number: 10147693
    Abstract: An apparatus includes a spool configured to supply a wire, a cutting device configured to form a notch in the wire, and a capillary configured to bond the wire and to form a stud bump. The apparatus is further configured to pull the wire to break at the notch, with a tail region attached to the stud bump.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: December 4, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien Ling Hwang, Yeong-Jyh Lin, Yi-Li Hsiao, Ming-Da Cheng, Tsai-Tsung Tsai, Chung-Shi Liu, Mirng-Ji Lii, Chen-Hua Yu
  • Patent number: 10141288
    Abstract: Package structures and methods of forming them are described. In an embodiment, a package structure includes an integrated circuit die embedded in an encapsulant and a redistribution structure on the encapsulant. The redistribution structure includes a metallization layer distal from the encapsulant and the integrated circuit die, and a dielectric layer distal from the encapsulant and the integrated circuit die and on the metallization layer. The package structure also includes a first under metallization structure on the dielectric layer and a Surface Mount Device and/or Integrated Passive Device (“SMD/IPD”) attached to the first under metallization structure. The first under metallization structure includes first through fourth extending portions extending through first through fourth openings of the dielectric layer to first through fourth patterns of the metallization layer, respectively.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: November 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Hsieh, Hsien-Wei Chen, Chi-Hsi Wu, Chen-Hua Yu, Der-Chyang Yeh, Wei-Cheng Wu
  • Patent number: 10118240
    Abstract: A method for forming solder deposits on elevated contact metallizations of terminal faces of a substrate formed in particular as a semiconductor component includes bringing wetting surfaces of the contact metallizations into physical contact with a solder material layer. The solder material is arranged on a solder material carrier. At least for the duration of the physical contact, a heating of the substrate and a tempering of the solder material layer takes place. Subsequently a separation of the physical contact between the contact metallizations wetted with solder material and the solder material layer takes place.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: November 6, 2018
    Assignee: PAC TECH—PACKAGING TECHNOLOGIES GMBH
    Inventor: Ghassem Azdasht
  • Patent number: 10117332
    Abstract: A printed circuit board (PCB) is disclosed on which various kinds of electronic components having diverse specifications may be mounted. The PCB includes a substrate base and a pad group formed on a surface of the substrate base. The pad group includes at least two pads. Each of the at least two pads includes a first sub-pad portion and a second sub-pad portion. The first sub-pad portion partially surrounds the second sub-pad portion. The second sub-pad portion of one of the at least two pads protrudes from an end portion of the first sub-pad portion toward another pad of the at least two pads.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: October 30, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ji-won Park
  • Patent number: 10109608
    Abstract: The invention provides a semiconductor package. The semiconductor package includes a semiconductor die having a central area and a peripheral area surrounding the central area. A first conductive bump is disposed on the semiconductor die in the central area. A second conductive bump is disposed on the semiconductor die in the peripheral area. An area ratio of the first conductive bump to the second conductive bump from a top view is larger than 1, and less than or equal to 3.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: October 23, 2018
    Assignee: MediaTek Inc.
    Inventors: Tzu-Hung Lin, Wen-Sung Hsu, Tai-Yu Chen
  • Patent number: 10096540
    Abstract: A semiconductor device has a semiconductor die with an insulation layer formed over an active surface of the semiconductor die. A conductive layer is formed over the first insulating layer electrically connected to the active surface. A plurality of conductive pillars is formed over the conductive layer. A plurality of dummy pillars is formed over the first insulating layer electrically isolated from the conductive layer and conductive pillars. The semiconductor die is mounted to a substrate. A height of the dummy pillars is greater than a height of the conductive pillars to maintain the standoff distance between the semiconductor die and substrate. The dummy pillars can be formed over the substrate. The dummy pillars are disposed at corners of the semiconductor die and a central region of the semiconductor die. A mold underfill material is deposited between the semiconductor die and substrate.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: October 9, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: KyungHoon Lee, SeongWon Park, KiYoun Jang, JaeHyun Lee
  • Patent number: 10085353
    Abstract: A board for mechanically supporting and electrically connecting electronic components includes a non-conductive substrate, a plurality of electrically conductive traces and pads disposed on the non-conductive substrate, and a solder mask applied to the non-conductive substrate and covering the traces. Metal lines are disposed on the non-conductive substrate under the solder mask and along at least two sides of the pads disposed in corners of the non-conductive substrate, so that a metal line is interposed between the pads in the corners of the non-conductive substrate and each adjacent pad. The metal lines form a raised region in the solder mask along the metal lines which prevents solder bridging in the corners of the non-conductive substrate during solder reflow. A corresponding semiconductor package and semiconductor assembly with such solder bridging prevention structures are also provided.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: September 25, 2018
    Assignee: Infineon Technologies AG
    Inventors: Carlo Baterna Marbella, Fabian Schnoy
  • Patent number: RE47600
    Abstract: A semiconductor device has a semiconductor die with a plurality of tapered bumps formed over a surface of the semiconductor die. The tapered bumps can have a non-collapsible portion and collapsible portion. A plurality of conductive traces is formed over a substrate with interconnect sites. A masking layer is formed over the substrate with openings over the conductive traces. The tapered bumps are bonded to the interconnect sites so that the tapered bumps contact the mask layer and conductive traces to form a void within the opening of the mask layer over the substrate. The substrate can be non-wettable to aid with forming the void in the opening of the masking layer. The void provides thermally induced stress relief. Alternatively, the masking layer is sufficiently thin to avoid the tapered interconnect structures contacting the mask layer. An encapsulant or underfill material is deposited between the semiconductor die and substrate.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: September 10, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventor: Rajendra D. Pendse
  • Patent number: RE48129
    Abstract: An elastic wave device includes resonators having a piezoelectric substrate, a resonation unit formed on the piezoelectric substrate, and reflectors formed on respective sides of the resonation unit on the piezoelectric substrate, and bumps formed on the piezoelectric substrate. The resonators are configured such that two or more split resonators are connected in parallel, and a bump is formed in a region sandwiched between reflectors of the split resonators.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: July 28, 2020
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Takashi Matsuda, Kazunori Inoue, Michio Miura