Abstract: A carrier film for performing a semiconductor package process on a mother substrate including a multi-layer circuit, a mother substrate, and a method of manufacturing a semiconductor package, the carrier film including a base material layer having a predetermined stiffness; and an adhesive layer configured to attach the base material layer onto the mother substrate, the adhesive layer including a water soluble material, wherein the carrier film includes a plurality of openings passing therethrough from a top surface to a bottom surface thereof.

Abstract: A device may include a first package and a second package where the first package has a warped shape. First connectors attached to a redistribution structure of the first package include a spacer embedded therein. Second connectors attached to the redistribution structure are fee from the spacer, the spacer of the first connectors keeping a minimum distance between the first package and the second package during attaching the first package to the second package.

Abstract: A semiconductor die includes a substrate and an integrated circuit provided on the substrate and having contacts. An electrically conductive layer is provided on the integrated circuit and defines electrically conductive elements electrically connected to the contacts. Electrically conductive interconnects coupled with respective electrically conductive elements. The electrically conductive interconnects have at least one of different sizes or shapes from one another.

Abstract: A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound.

Abstract: A method for forming thermally conductive composition on electronic components comprises three steps, (I) preparing a silicone composition comprising (A) a polyorganosiloxane, (B) a thermally conductive filler and (C) a catalyst, (II) applying the silicone composition on an electronic component of electronic devices, the electronic component generates heat when the electronic devices are working and (III) curing the silicone composition by heat generated by the electronic component.

Abstract: A method includes applying a first flux onto an electrode provided on a substrate and placing a solder material on the electrode, heating the substrate to form a solder bump on the electrode, deforming the solder bump to provide a flat surface or a depressed portion on the solder bump, applying a second flux to the solder bump; placing a core material on the solder bump, the core material including a core portion and a solder layer that covers a surface of the core portion, and heating the substrate to join the core material to the electrode by the solder bump and the solder layer.

Abstract: A semiconductor device includes a conductive frame comprising a die attach surface that is substantially planar, a semiconductor die comprising a first load on a rear surface and a second terminal disposed on a main surface, a first conductive contact structure disposed on the die attach surface, and a second conductive contact structure on the main surface. The first conductive contact structure vertically extends past a plane of the main surface of the semiconductor die. The first conductive contact structure is electrically isolated from the main surface of the semiconductor die by an electrical isolation structure. An upper surface of the electrical isolation structure is below the main surface of the semiconductor die.

Abstract: According to one embodiment, the electrode pads are provided at a surface of the substrate. The metal pad is provided at the surface of the substrate. The electronic component is mounted to the surface of the substrate. The electronic component includes a plurality of opposing electrodes. The opposing electrodes oppose the electrode pads in a direction toward the surface direction and are electrically connected to the electrode pads. The positioning component is fixed to the metal pad. A gap between the positioning component and the electronic component in an in-plane direction of the surface of the substrate is shorter than a minimum distance of the electrode pads.

Abstract: A solder preform is provided, at least one surface of the solder preform (C) is provided with a plurality of protruding portions and/or recessing portions provided at a certain interval.

Abstract: Embodiments may relate to an assembly that includes a first package substrate with a first electromagnetic cavity. The assembly may further include a second package substrate with a second electromagnetic cavity that is adjacent to the first electromagnetic cavity. The first and second electromagnetic cavities may form a millimeter wave (mmWave) resonant cavity of a mmWave filter. Other embodiments may be described or claimed.

Abstract: A surface mounting semiconductor component includes a semiconductor device, a circuit board, a number of first solder bumps, and a number of second solder bumps. The semiconductor device included a number of die pads. The circuit board includes a number of contact pads. The first solder bumps are configured to bond the semiconductor device and the circuit board. Each of the first solder bumps connects at least two die pads with a corresponding contact pad. Each of the second solder bumps connects a die pad with a corresponding contact pad.

Abstract: A bonding structure is a bonding structure which bonds a light emitting element and a substrate and includes a first electrode formed on the light emitting element, a second electrode formed on the substrate, and a bonding layer which bonds the first electrode and the second electrode, and the bonding layer contains a first bonding metal component and a second bonding metal component different from the first bonding metal component.

Abstract: A method of forming a semiconductor device is provided. A first substrate is provided with a conductive feature therein, a metal bump over the conductive feature and a passivation stack aside the metal bump. A first insulating layer is formed over the metal bump and the passivation stack. First and second patterning processes are performed to form first and second opening patterns in the first insulating layer. The metal bump is exposed by the second patterning process. A second substrate is provided with a second insulating layer thereon. The second substrate is bonded to the first substrate with the second insulating layer and the first insulating layer facing each other, so that the second insulating layer fills in the first and second opening patterns of the first insulating layer. The first insulating layer and a portion of the passivation stack are removed.

Abstract: Implementations of semiconductor packages may include: a wafer having a first side and a second side, a solder pad coupled to the first side of the wafer, a through silicon via (TSV) extending from the second side of the wafer to the solder pad a metal layer around the walls of the TSV, and a low melting temperature solder in the TSV. The low melting temperature solder may also be coupled to the metal layer. The low melting temperature solder may couple to the solder pad through an opening in a base layer metal of the solder pad.

Abstract: An antenna structure, a manufacturing method thereof and a communication device are provided. The antenna structure includes a first base substrate, a second base substrate, a dielectric layer provided between the first base substrate and the second base substrate, an isolation layer, first coplanar electrodes provided on one side of the isolation layer facing the first base substrate, and second coplanar electrodes provided on another side of the isolation layer facing the second base substrate. In the direction perpendicular to the first base substrate, the dielectric layer includes a first dielectric layer and a second dielectric layer, and the isolation layer is provided between the first dielectric layer and the second dielectric layer. The first coplanar electrodes include first electrodes and second electrodes alternately arranged. The second coplanar electrodes include third electrodes and fourth electrodes alternately arranged.

Abstract: A flexible circuit package. The circuit package includes a termination point on a flexible base substrate. The termination point is connected with an interface by conductive material on the base substrate. The conductive material extends across the surface area of the base substrate in multiple individual connections, which are in communication with each other and separated by voids in the conductive material for mitigating communication failure between the termination point and the interface during or following flexion, stretching, compression or other deformation of the base substrate and the circuit package. The termination point may include an input module such as a sensor, switch or other input. The termination point may include an output module such as a light, vibrator or other output. The interface may include an output interface for receiving data or an input interface for sending a command or other signal.

Abstract: A method of manufacturing a package-on-package device includes a bonding step carried out by a bonding apparatus including a pressing member and a light source that produces a laser beam. A bottom package including a lower substrate, lower solder balls alongside an edge of the lower substrate, and a lower chip on a center of the lower substrate is provided, the bottom package is bonded to an interposer substrate having upper solder balls aligned with the lower solder balls, and a top package having an upper substrate and an upper chip on the upper substrate is bonded to the interposer substrate. While the interposer substrate is disposed on the bottom package, the pressing member presses the interposer substrate against the bottom package, and the laser beam adheres the lower solder balls to the upper solder balls.

Abstract: In a general aspect, a semiconductor device assembly can include a semiconductor die having a first surface including active circuitry, a second surface opposite the first surface, and a plurality of side surfaces. Each of the plurality of side surfaces can extend between the first surface of the semiconductor die and the second surface of the semiconductor die. The semiconductor device assembly can also include a conductive spacer having a cavity defined therein. The semiconductor die can be electrically and thermally coupled with the conductive spacer, the semiconductor die being at least partially embedded in the cavity.

Abstract: A dual bond pad structure for a wafer with laser die attachment and methods of manufacture are disclosed. The method includes forming a bonding layer on a surface of a substrate. The method further includes forming solder bumps on the bonding layer. The method further includes patterning the bonding layer to form bonding pads some of which comprise the solder bumps thereon. The method further includes attaching a laser diode to selected bonding pads using solder connections formed on the laser diode. The method further includes attaching an interposer substrate to the solder bumps formed on the bonding pads.

Abstract: A printed wiring board includes a substrate, a contact member arranged in contact with the substrate, and a wear resistant member fixed at least in an area on the substrate that comes in contact with the contact member, the wear resistant member having a wear resistance higher than that of the substrate.

Abstract: A semiconductor device includes a first carrier including a first pad, a second carrier including a second pad disposed opposite to the first pad, a joint coupled with and standing on the first pad, a joint encapsulating the post and bonding the first pad with the second pad, a first entire contact interface between the first pad and the joint, a second entire contact interface between the first pad and the post, and a third entire contact interface between the joint and the second pad. The first entire contact interface, the second entire contact interface and the third entire contact interface are flat surfaces. A distance between the first entire contact interface and the third entire contact interface is equal to a distance between the second entire contact interface and the third entire contact interface. The second entire contact interface is a continuous surface.

Abstract: Embodiments are provided for package semiconductor devices, each device including: a low stress pad structure comprising: a dielectric layer, a seed layer having: a center section, and a ring section formed around the center section and over a top surface of the dielectric layer, wherein the ring section of the seed layer includes a set of elongated openings through which a portion of the top surface of the dielectric layer is exposed, and a metal layer having: an inner section formed over a top surface of the center section of the seed layer, and an outer section formed over a top surface of the ring section of the seed layer, wherein a bottom surface of the outer section of the metal layer directly contacts the portion of the top surface of the dielectric layer exposed through the set of elongated openings.

Abstract: A system for flux residue detection is provided. The system includes a flux heater, where the flux heater controls a temperature of a flux spray applied to a printed circuit board, and an infrared camera, wherein the infrared camera provides a thermal image of the flux on the printed circuit board. A method, a computer system, and a computer program product for flux residue detection is provided, including setting flux application parameters, applying flux to a printed circuit board, and capturing an infrared image of the flux applied to the printed circuit board. A method, a computer system, and a computer program product for flux residue detection is provided, including setting flux application parameters, applying flux to a printed circuit board, capturing an infrared image of the flux applied to the printed circuit board, and determining there is excess flux residue on the printed circuit board.

Abstract: An electronic device is disclosed. In one example, the electronic device includes a solder ball, a dielectric layer comprising an opening, and a redistribution layer (RDL) comprising an RDL pad connected with the solder ball. The RDL pad including at least one void, the void being disposed at least in partial in an area of the RDL pad laterally outside of the opening of the dielectric layer.

Abstract: Provided among other things is a method of affixing a small, single chip to a plastic item, the chip having a top surface having length and width dimensions, and having a height, the method comprising: (1) vacuum adhering a top-oriented surface of the chip to a probe of outer dimensions comparable to or smaller than those of the length and width; (2) conveying heat to the chip via the probe such that a bottom-oriented surface of the chip is sufficiently hot to melt the plastic; (3) applying via the probe the chip to the plastic such that the chip embeds in the plastic; and (4) releasing the chip from the probe, wherein the largest of the length and width is about 500 microns or less, and height is no more than about the smallest of length and width.

Abstract: A printed circuit board according to an embodiment includes: an insulating layer; a first pad disposed on a first surface of the insulating layer; a first conductive layer disposed on the first pad and including gold (Au); a second pad disposed on a second surface of the insulating layer; and a second conductive layer disposed on the second pad and including gold (Au), wherein the first conductive layer is a conductive layer connected to a wire, the second conductive layer is a conductive layer connected to a solder, and the first conductive layer is thicker than the second conductive layer.

Abstract: Methods and system for flip chip alignment for substrate and leadframe applications are disclosed and may include placing a semiconductor die on bond fingers of a metal leadframe, wherein at least two of the bond fingers comprise one or more recessed self-alignment features. A reflow process may be performed on the semiconductor die and leadframe, thereby melting solder bumps on the semiconductor die such that a solder bump may be pulled into each of the recessed self-alignment features and aligning the solder bumps on the semiconductor die to the bond fingers. The recessed self-alignment features may be formed utilizing a chemical etch process or a stamping process. A surface of the recessed self-alignment features or the bond fingers of the metal leadframe may be roughened. A solder paste may be formed in the recessed self-alignment features prior to placing the semiconductor die on the bond fingers of the metal leadframe.

Abstract: The array substrate taught by the present invention have dummy ITO lines on the fanout lines configured as multiple segments separated at intervals so that, when two neighboring dummy ITO lines are short-circuited, the place of short circuit is limited to a segment of the neighboring dummy ITO lines. Coupling capacitance is limited to that between the segments and fanout lines. Compared to prior arts where coupling capacitance occurs between neighboring dummy ITO lines and fanout lines, the present invention has much smaller coupling capacitance, thereby reducing the impact of coupling capacitance to signal transmission on the fanout lines, avoiding the occurrence of light lines on the display panel, and enhancing the display effect of the display panel.

Abstract: The present invention relates to a method for producing a soldered product by which soldering can be accomplished without using a jig.

Abstract: A semiconductor device manufacturing method includes: (A) orienting an upper surface of a semiconductor element which has the upper surface and a suction surface of a collet which has a suction hole so that the upper surface of the semiconductor device and the suction surface of the collet face each other, the upper surface including a first region and a second region, the second region lying higher than the first region; (B) bringing the suction surface of the collet into contact with a part of the second region of the semiconductor element; and (C) picking up the semiconductor element using the collet while the collet sucks in air between the first region and the suction surface via the suction hole, wherein in (B), an entirety of an uppermost surface of the second region is in contact with a region of the suction surface exclusive of the suction hole.

Abstract: A method for electrically coupling a pad and a front face of a pillar, including shaping the front face pillar, the front face having at least partially a convex surface, applying a suspension to the front face or to the pad, wherein the suspension includes a carrier fluid, electrically conducting microparticles and electrically conducting nanoparticles, arranging the front face of the pillar opposite to the pad at a distance such that the carrier fluid bridges at least partially a gap between the front face of the pillar and the pad, evaporating the carrier fluid thereby confining the microparticles and the nanoparticles, and thereby arranging the nanoparticles and the microparticles as percolation paths between the front face of the pillar and the pad, and sintering the arranged nanoparticles for forming metallic bonds at least between the nanoparticles and/or between the nanoparticles and the front face of the pillar or the pad.

Abstract: A semiconductor die includes a substrate and an integrated circuit provided on the substrate and having contacts. An electrically conductive layer is provided on the integrated circuit and defines electrically conductive elements electrically connected to the contacts. Electrically conductive interconnects coupled with respective electrically conductive elements. The electrically conductive interconnects have at least one of different sizes or shapes from one another.

Abstract: Provided are a Cu column, a Cu core column, a solder joint, and a through-silicon via, which have the low Vickers hardness and the small arithmetic mean roughness. For the Cu column 1 according to the present invention, its purity is equal to or higher than 99.9% and equal to or lower than 99.995%, its arithmetic mean roughness is equal to or less than 0.3 ?m, and its Vickers hardness is equal to or higher than 20 HV and equal to or less than 60 HV. Since the Cu column 1 is not melted at a melting temperature in the soldering and a definite stand-off height (a space between the substrates) can be maintained, it is preferably applied to the three dimensional mounting or the pitch narrowing mounting.

Abstract: A printed circuit board includes an insulating layer, a circuit pattern on the insulating layer, and a surface treatment layer on the circuit pattern. The surface treatment layer includes a bottom surface having a width wider than a width of a top surface of the circuit pattern.

Abstract: An embodiment of an integrated device, including a chip of semiconductor material wherein an integrated circuit is integrated, is proposed; the integrated device includes a set of contact terminals for contacting the integrated circuit. At least one contact terminal of said set of contact terminals includes a contact layer of metal material being suitable to be directly coupled mechanically to an element external to the chip, and a coupling element for improving an electrical and/or mechanical coupling between the contact layer and the chip. The coupling element includes a coupling layer being formed by a combination between the metal material of the contact layer and the semiconductor material of the chip, with the coupling layer that is directly coupled to the chip and to the contact layer.

Abstract: An integrated electronic device includes a semiconductor body and a passivation structure including a frontal dielectric layer bounded by a frontal surface. A conductive region forms a via region, extending into a hole through the frontal dielectric layer. An overlaid redistribution region extends over the frontal surface. A barrier structure includes at least a first barrier region extending into the hole and surrounding the via region. The first barrier region extends over the frontal surface. A first coating layer covers the top and the sides of the redistribution region and a second coating layer covers the first coating layer. A cavity extends between the redistribution region and the frontal surface and is bounded on one side by the first coating layer and on the other by the barrier structure.

Abstract: The present invention relates to an electronic module. In particular, to an electronic module which includes one or more components embedded in an installation base. The electronic module can be a module like a circuit board, which includes several components, which are connected to each other electrically, through conducting structures manufactured in the module. The components can be passive components, microcircuits, semiconductor components, or other similar components. Components that are typically connected to a circuit board form one group of components. Another important group of components are components that are typically packaged for connection to a circuit board. The electronic modules to which the invention relates can, of course, also include other types of components.

Abstract: A method of making a semiconductor device includes patterning a photoresist on a substrate to form a plurality of openings in the photoresist. A first opening is near a center of the substrate and has a first width. A second opening is near an edge of the substrate and has a second width smaller than the first width. A third opening is between the first opening and the second opening and has a third width greater than the second width and smaller than the first width. The method further includes plating a conductive material into each opening. Plating the conductive material includes plating the first conductive material in the first opening at a first current density; plating the first conductive material in the second opening at a second current density greater than the first current density; and plating the conductive material in the third opening at a third current density.

Abstract: A method for producing an electronic assembly includes providing a printed circuit board with a first face, a second face facing away from the first face, and a first component arranged on the first face. The method further includes arranging the circuit board such that the second face lies on a reference surface, and applying a sealing material which is substantially not flowable prior to being cured onto the first face. The sealing material surrounds a sub-region of the first face of the circuit board. The method further includes arranging a second component at least partly on the reference surface such that the second component is pressed into the sealing material, electrically connecting the second component to the circuit board via an electric connection line, and applying a covering material onto the circuit board first face sub-region surrounded by the sealing material and onto the first component.

Abstract: A chip module includes a body, a bump, and a first bonding layer. The bump is disposed on the body. The first bonding layer is disposed on the bump. The first bonding layers and the bump are made of the same conductive material and the first bonding layer is porous.

Abstract: Package structures and methods of forming them are described. In an embodiment, a package structure includes an integrated circuit die embedded in an encapsulant and a redistribution structure on the encapsulant. The redistribution structure includes a metallization layer distal from the encapsulant and the integrated circuit die, and a dielectric layer distal from the encapsulant and the integrated circuit die and on the metallization layer. The package structure also includes a first under metallization structure on the dielectric layer and a Surface Mount Device and/or Integrated Passive Device (“SMD/IPD”) attached to the first under metallization structure. The first under metallization structure includes first through fourth extending portions extending through first through fourth openings of the dielectric layer to first through fourth patterns of the metallization layer, respectively.

Abstract: A method for forming a ball bond for an integrated circuit formed on a semiconductor die includes forming a ball at a first send of a conductive wire inserted in a capillary tool and lowering the capillary tool toward a pad on the semiconductor die positioned on a support surface. The method further includes moving, using a motor, the support surface relative to the capillary tool to thereby bond the ball, without using ultrasound, to the pad and then raising the capillary tool.

Abstract: A method for removing an electrical component from a substrate where the component is coupled to the substrate by connection elements. The method includes disposing liquid gallium (Ga) at or near an edge of the component and dispersing the liquid Ga between the substrate and the component such that the liquid Ga contacts one or more of the connection elements. The method also includes maintaining the liquid Ga between the substrate, component and one or more of the connection elements for a prescribed time period and removing the component from the substrate by applying a mechanical force to the component.

Abstract: Disclosed is a metal core solder ball having improved heat conductivity, including a metal core having a diameter of 40˜600 ?m, a first plating layer formed on the outer surface of the metal core, and a second plating layer formed on the outer surface of the first plating layer.

Abstract: A method of manufacturing a semiconductor device structure includes forming a bond or joint between a first device and a second device. The first device comprises an integrated passive device (IPD) and a first contact pad disposed over the IPD. The second device comprises a second contact pad. The first contact pad has a first surface with first lateral extents. The second contact pad has a second surface with second lateral extents. The width of the second lateral extents is less than the width of the first lateral extents. The joint structure includes the first contact pad, the second contact pad, and a solder layer interposed therebetween. The solder layer has tapered sidewalls extending in a direction away from the first surface of the first contact pad to the second surface of the second contact pad. At least one of the first surface or the second surface is substantially planar.

Abstract: To provide a semiconductor package including a protruding part at the bottom surface of a package main body. A semiconductor package including a semiconductor chip is provided, the semiconductor package including: a package main body; a plurality of electrodes exposed at a bottom surface of the package main body; and a protruding part projecting from the bottom surface of the package main body and above the plurality of electrodes, wherein the protruding part is arranged not to overlap two least separated electrodes, among the plurality of electrodes, in a second direction different from a first direction in which the two electrodes are arrayed.

Abstract: A semiconductor device, includes: a first semiconductor chip including: a first substrate; a first via; a first rear surface-side pad connected to the first via; a first wiring layer; a first front surface-side pad formed on the first wiring layer; and an input circuit formed in the first substrate, an input signal wire connecting the first via, the first front surface-side pad, and an input terminal of the input circuit; and a second semiconductor chip including: a second substrate; a second wiring layer; a second front surface-side pad; and an output circuit formed in the second substrate, an output signal wire connecting the second front surface-side pad to an output terminal of the output circuit. The second semiconductor chip is stacked on a rear surface side of the first semiconductor chip, and the first rear surface-side pad and the second front surface-side pad are connected.

Abstract: The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure.

Abstract: Provided is a flip chip mounting apparatus for mounting chips (400) to a substrate (200), and the apparatus includes at least one sectionalized mounting stage (45) divided into a heating section (452) and a non-heating section (456), the heating section being for heating a substrate (200) fixed to a front surface of the heating section, the non-heating section not heating the substrate (200) suctioned to a front surface of the non-heating section. With this, it is possible to provide an electronic-component mounting apparatus that is simple and capable of efficiently mounting a large number of electronic components.

Abstract: An elastic wave device includes resonators having a piezoelectric substrate, a resonation unit formed on the piezoelectric substrate, and reflectors formed on respective sides of the resonation unit on the piezoelectric substrate, and bumps formed on the piezoelectric substrate. The resonators are configured such that two or more split resonators are connected in parallel, and a bump is formed in a region sandwiched between reflectors of the split resonators.