Component Terminal To Substrate Surface (i.e., Nonpenetrating Terminal) Patents (Class 228/180.21)
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Publication number: 20100252311Abstract: An intercoupling component is provided which permits reliable, non-permanent electrical connection between a first substrate and a second substrate. The intercoupling component includes an electrically conductive terminal including a first end and a second end opposed to the first end. The first and second ends are configured to receive a solder ball. An axial hole extends inward from the first end of the terminal, and an electrically conductive core member is disposed within the hole. The core member is sized and shaped to obstruct the hole. In addition, at least an outer surface of the core member includes a first material and at least an outer surface of the body includes a second material, the first material having greater solderability than the second material.Type: ApplicationFiled: April 1, 2009Publication date: October 7, 2010Applicant: Advanced Interconnections Corp.Inventor: James V. Murphy
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Patent number: 7805834Abstract: The present invention includes methods for making liquid crystalline polymer (LCP) interconnect structures using a high temperature and low temperature single sided LCP, where both the high and low temperature LCP are provided with a z-axis connection. The single sided conductive layer is a bus layer to form z-axis conductive stud within the high and low temperature LCP. High and low temperature LCP layers are etched or built up to form circuit patterns and subsequently bonded together to form final multilayer circuit pattern where the low temperature LCP melts to form both dielectric to dielectric bond to high temperature LCP circuit layer, and dielectric to conductive bond.Type: GrantFiled: August 3, 2007Date of Patent: October 5, 2010Assignee: Georgia Tech Research CorporationInventors: George E. White, Madhavan Swaminathan, Venkatesh Sundaram, Sidharth Dalmia
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Patent number: 7797820Abstract: In component mounting process for a plurality of components to be mounted onto a board, a plurality of bump electrode portions formed on mounting-side surfaces of the components to be mounted onto the board are brought into contact with a bonding-assistant agent so that the bonding-assistant agent is supplied thereto to allow the bonding-assistant agent-supplied components to be mounted onto the board, the component mounting process includes, supplying the bonding-assistant agent to a first component among the plurality of components, and starting the supply of the bonding-assistant agent to a second component among the plurality of components before completion of the mounting of the bonding-assistant agent-supplied first component onto the board.Type: GrantFiled: March 6, 2008Date of Patent: September 21, 2010Assignee: Panasonic CorporationInventors: Satoshi Shida, Shinji Kanayama, Shunji Onobori, Shuichi Hirata, Mamoru Nakao, Kunio Oe, Akira Kugihara, Shoriki Narita, Yoshitaka Etoh, Hiroshi Haji
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Patent number: 7797069Abstract: A production line is provided for forming a layered product. The production line includes a conveyor configured to convey a substrate. A plurality of elongate printheads extend transverse to the conveyance direction and is configured to print voxels upon the conveyed substrate to form the layered product. The printheads are arranged to form a plurality of sets which are equidistantly spaced apart.Type: GrantFiled: November 23, 2008Date of Patent: September 14, 2010Assignee: Silverbrook Research Pty LtdInventor: Kia Silverbrook
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Patent number: 7784670Abstract: A practical bonding technique is provided for solid-phase room-temperature bonding which does not require a profile irregularity of the order of several nanometers, in which a high-vacuum energy wave treatment and continuous high-vacuum bonding are not required. Since an adhering substance layer is thin immediately after a surface activating treatment using an energy wave, a bonding interface is spread by crushing the adhering substance layer to perform bonding, so that a new surface appears on a bonding surface, and objects to be bonded are bonded together. In order to crush the adhering substance layer more easily, a bonding metal of a bonding portion of the object to be bonded needs to have a low hardness. According to the results of various experiments conducted by the present inventors, it was found that the hardness of the bonding portion which is a Vickers hardness of 200 Hv or less is particularly effective for room-temperature bonding.Type: GrantFiled: January 21, 2005Date of Patent: August 31, 2010Assignees: Bondtech Inc.Inventors: Tadatomo Suga, Masuaki Okada
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Patent number: 7757930Abstract: Productivity is to be improved in assembling a semiconductor integrated circuit device. A matrix substrate is provided and semiconductor chips are disposed on a first heating stage, then the matrix substrate is disposed above the semiconductor chips on the first heating stage, subsequently the semiconductor chips and the matrix substrate are bonded to each other temporarily by thermocompression bonding while heating the chips directly by the first heating stage, thereafter the temporarily bonded matrix substrate is disposed on a second heating stage adjacent to the first heating stage, and then on the second heating stage the semiconductor chips are thermocompression-bonded to the matrix substrate while being heated directly by the second heating stage.Type: GrantFiled: August 10, 2007Date of Patent: July 20, 2010Assignees: Renesas Technology Corp., Renesas Eastern Japan Semiconductor, Inc.Inventors: Hiroshi Maki, Yukio Tani
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Patent number: 7757929Abstract: Methods of manufacturing optical transceiver modules using lead frame connectors that connect optical sub-assemblies to printed circuit boards are disclosed. The lead frame connector includes an electrically insulating case having a first part separated from a second part, and a plurality of conductors that are electrically isolated one from another by the electrically insulating case. Each of the plurality of conductors can form an electrical contact restrained in a fixed position with respect to the first part and a contact point extending from the second part. The electrical contact is aligned with and soldered to the leads that protrude from the back end of an optical sub-assembly. The contact points can then be connected to electrical pads on a PCB.Type: GrantFiled: June 23, 2006Date of Patent: July 20, 2010Assignee: Finisar CorporationInventors: Donald A. Ice, Darin James Douma
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Patent number: 7754343Abstract: Techniques and structures have been developed for providing lead-free column grid array interconnect structures. An exemplary interconnect has a body, a first joint, and a second joint, all having compositions off the eutectic composition in a ternary alloy system, the first joint having a ternary composition distinct from the body composition, and the second joint having a ternary composition distinct from the body composition and the first joint composition. The interconnect may be formed by solidifying a solder, having a Sn-poor ternary composition in the Sn—Ag—Cu alloy system, in contact with a column, having a Ag-rich Cu-deficient composition in the same system, and a bonding pad or bare substrate. A second solder, having a Sn-rich ternary composition, may be solidified in contact with the column and a second bonding pad or bare substrate. In some embodiments joints may be severed and reformed by remelting and resolidifying the lower-liquidus solder.Type: GrantFiled: December 21, 2005Date of Patent: July 13, 2010Assignee: Oracle America, Inc.Inventors: David Love, Bidyut Sen
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Patent number: 7735715Abstract: A method for mounting a semiconductor chip onto a substrate comprises the steps of positioning a solder dispenser over the substrate and passing a length of solder wire through the solder dispenser to the substrate. The feeding of the wire to the substrate in a feeding direction is controlled with a wire feeder. The solder dispenser is moved relative to the substrate with a positioning device along at least one of two orthogonal axes that are substantially perpendicular to the feeding direction contemporaneously with feeding the solder wire to the surface of the substrate to dispense a line of molten solder onto the substrate. The semiconductor chip is then mounted onto the molten solder that has been dispensed onto the substrate.Type: GrantFiled: December 7, 2007Date of Patent: June 15, 2010Assignee: ASM Assembly Automation LtdInventors: Kui Kam Lam, Chun Hung Samuel Ip
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Patent number: 7739077Abstract: A method determines a mounting condition of a mounter mounting a component onto a board, which includes the steps of: obtaining an operational sate parameter; and determining, in the case where a value of the obtained operational state parameter is not within a predetermined range, a mounting condition so that the value of the operational state parameter falls within the predetermined range.Type: GrantFiled: June 26, 2006Date of Patent: June 15, 2010Assignee: Panasonic CorporationInventor: Yasuhiro Maenishi
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Patent number: 7731076Abstract: A semiconductor device manufacturing apparatus includes a substrate holding section that holds a semiconductor wafer substrate, a discharge mechanism that discharges liquid drops of metal paste from a discharge nozzle toward a surface of the semiconductor wafer substrate, and a driving mechanism that moves at least one of the substrate holding section and the discharge nozzle. A control section is provided to control the discharge and driving mechanisms so as to adhere the metal paste to the surface. The semiconductor wafer substrate includes a terminal unit formed from two or more electrically separated terminals connected to a device circuit and an insulation layer having an opening in a formation position of the terminal unit. Further, the control section controls the discharge and driving mechanisms to selectively coat the opening of the semiconductor wafer substrate with the metal paste overlying the terminal unit to be electrically connected.Type: GrantFiled: June 18, 2008Date of Patent: June 8, 2010Assignee: Ricoh Company, Ltd.Inventor: Kazunari Kimino
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Patent number: 7712652Abstract: First components and second components in which bumps are formed on the lower surface thereof and laminate structures are formed by mounting them to stack with each other on a circuit board 13 are picked up from a component supply unit 1 using a placement head 16, and by lifting and lowering the placement head 16 holding the first components and the second components relative to a paste transfer device 5 supplying a flux 10 in the manner such as coating films having two types of different thicknesses, the flux 10 is supplied to the bumps of the plurality of components in a bundle using a transfer coating method. With such a configuration, it is possible to efficiently perform a component mounting with a satisfactory adhesiveness by ensuring an optimal amount of application quantity of a paste.Type: GrantFiled: May 3, 2007Date of Patent: May 11, 2010Assignee: Panasonic CorporationInventors: Takeshi Morita, Masanori Hiyoshi
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Patent number: 7703662Abstract: In a conductive ball mounting apparatus for mounting one conductive ball on each of a plurality of pads which are provided on a substrate and on which an adhesive is formed, the conductive ball mounting apparatus includes: a conductive ball container for containing a plurality of conductive balls therein and having an opening to pass through the plurality of conductive balls; a substrate holder disposed over the conductive ball container to face the opening, and holding the substrate in such a manner that the plurality of conductive balls and the plurality of pads face each other and the substrate is disposed over the conductive ball container with a space therebetween; and a conductive ball supplying unit for supplying the plurality of conductive balls to the plurality of pads via the opening by moving up the plurality of conductive balls.Type: GrantFiled: March 5, 2008Date of Patent: April 27, 2010Assignee: Shinko Electric Industries Co., Ltd.Inventors: Kiyoaki Iida, Kazuo Tanaka, Norio Kondo, Hideaki Sakaguchi, Mitsutoshi Higashi
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Patent number: 7699210Abstract: In some example embodiments, a method includes engaging a first contact on a motherboard with a second contact on an electronic package. A portion of one of the first and second contacts is covered with an interlayer that has a lower melting temperature than both of the first and second contacts. The method further includes bonding the first contact to the second contact by melting the interlayer to diffuse the interlayer into the first and second contacts. The bonded first and second contacts have a higher melting temperature than the interlayer before melting. In other example embodiments, an electronic assembly includes a motherboard having a first contact that is bonded to a second contact on an electronic package. An interlayer is diffused within the first and second contacts such that they have a higher melting temperature than the interlayer before the interlayer is diffused into the first and second contacts.Type: GrantFiled: February 5, 2008Date of Patent: April 20, 2010Assignee: Intel CorporationInventor: Daewoong Suh
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Patent number: 7692119Abstract: In the first buffering area provided between the inlet of the furnace and the heating chamber, the ambient gas is blown to the printed circuit board from the lower side of the carrier device, while the ambient gas is sucked in the upper side of the carrier device, thus the outside air is prevented from infiltrating and the ambient gas is prevented from flowing out. Furthermore, the flux is prevented from being attached to the printed circuit board, by installing the flux dropping prevention mechanism in the suction port of the ambient gas.Type: GrantFiled: June 29, 2006Date of Patent: April 6, 2010Assignee: Tamura FA System CorporationInventors: Motomu Shibamura, Kouichi Miyazaki, Motohiro Yamane
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Patent number: 7669752Abstract: A flux contains resin having film forming ability, activator, solvent and at least one complex selected from silver complex and copper complex. The flux is used when soldering is performed onto a circuit having electroless nickel plating or further having gold plating on the electroless nickel plating. Allowing a barrier layer of silver or copper to deposit on the surfaces of lands suppresses the diffusion of nickel into the melted solder alloy during soldering, and also prevents phosphorous concentration. This improves the bonding strength of soldering and suppresses the reduction deposition of silver and/or copper to portions other than circuit patterns.Type: GrantFiled: June 22, 2007Date of Patent: March 2, 2010Assignee: Harima Chemicals, Inc.Inventors: Kazuki Ikeda, Shunsuke Ishikawa, Takaaki Anada, Keigo Obata, Takao Takeuchi, Naoya Inoue
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Patent number: 7650688Abstract: A vacuum bonding tool for pick-and-place and bonding semiconductor chips onto a substrate or onto a previously mounted die to form a die stack includes a shank and a suction part. The shank has a vacuum conduit extending from a first end to a second end of the shank. The shank is adapted for cooperative engagement with the suction part at the second end, and the shank has a plate at the second end to support the suction part. The suction part has a surface for contacting a semiconductor chip during pick-and place operation. According to the invention, the suction part is made of an elastically deformable conductive or non-conductive material. In various embodiments, the chip contacting surface of the elastically deformable suction part flat overall, or is concave, of has a flat central region and concave regions.Type: GrantFiled: October 29, 2004Date of Patent: January 26, 2010Assignee: ChipPAC, Inc.Inventors: Hee-Bong Lee, Hyun-Joon Oh
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Patent number: 7603769Abstract: Methods of coupling a surface mount device with a substrate such as a printed circuit, for example, are disclosed. A method, according to one aspect, may include coupling a holder with a substrate such that terminals of the substrate are included in an opening of the holder, mounting an electronic device over the terminals with a conductive bonding material disposed there between, heating the conductive bonding material to its melting point, and cooling the conductive bonding material.Type: GrantFiled: September 14, 2007Date of Patent: October 20, 2009Assignee: Intel CorporationInventor: My Jang
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Patent number: 7591293Abstract: A device and method for bonding objects to be bonded each having a metal bonding portion on a substrate, comprising cleaning means for exposing the metal bonding portions to a plasma having an energy enough to etch the surfaces of the metal bonding portions at a depth of 1.6 nm or more over the entire surfaces of the metal bonding portions under a reduced pressure and bonding means for bonding the metal bonding portions of the objects taken out of the cleaning means in an atmospheric air. By using a specific scheme, metal bonding portions after the plasma cleaning can be bonded in the atmospheric air, thereby significantly simplifying the bonding process and the whole device and lowering the cost.Type: GrantFiled: September 22, 2003Date of Patent: September 22, 2009Assignees: Toray Engineering Co., Ltd., Oki Electric Industry Co., Ltd., Sanyo Electric Industry Co., Ltd., Sharp Kabushiki Kaisha, Sony Corporation, Kabushiki Kaisha Toshiba, Fujitsu Limited, Matsushita Electric Industrial Co., Ltd., Rohm Co., Ltd., Renesas Technology Corp.Inventors: Tadatomo Suga, Toshihiro Ito, Akira Yamauchi
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Patent number: 7581668Abstract: According to one aspect of the invention it is possible to rapidly heat a soldering item by reducing an initially larger volume flow at a constant or increasing temperature, effectively preventing small components from overheating. By using the volume flow of a convection heater to control effective heat transmission occurring on said soldering item, it is also possible to adapt the soldering process in an extremely flexible manner to special process requirements by virtue of the fact that adjustment of a modified volume flow can be controlled in a very quick and precise manner.Type: GrantFiled: October 29, 2004Date of Patent: September 1, 2009Assignee: Rehm Thermal Systems GmbHInventor: Hans Bell
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Patent number: 7578053Abstract: An interposer bonding device 3 is intended for bonding an interposer 10 having an interposer-side terminal to a base circuit sheet 20 provided with a base-side terminal. The interposer bonding device 3 has a press anvil 31 that holds the base circuit sheet 20 on which the interposer 10 is laminated and a bonding head 32 that moves relatively with respect to the press anvil 31. The bonding head 32 has a pressing surface 320 that presses the rear surface of the interposer by abutting against this surface. The pressing surface 320 scans the rear surface of the interposer 10 by the relative movement of the bonding head 32 with respect to the press anvil 31 and presses the whole surface of the interposer-side terminal 12 toward the base circuit sheet 20.Type: GrantFiled: December 3, 2005Date of Patent: August 25, 2009Assignee: Hallys CorporationInventors: Ryoichi Nishigawa, Hiroshi Aoyama
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Patent number: 7578057Abstract: A method of fabricating a large area, multi-element contactor. A segmented contactor is provided for testing semiconductor devices on a wafer that comprises a plurality of contactor units mounted to a substrate. The contactor units are formed, tested, and assembled to a backing substrate. The contactor units may include leads extending laterally for connection to an external instrument such as a burn-in board. The contactor units include conductive areas such as pads that are placed into contact with conductive terminals on devices under test.Type: GrantFiled: June 27, 2006Date of Patent: August 25, 2009Assignee: FormFactor, Inc.Inventors: Mohammad Eslamy, David V. Pedersen, Harry D. Cobb
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Patent number: 7568610Abstract: A method of soldering electronic component (6) having solder bumps (7) formed thereon to substrate (12), wherein bumps (7) are pressed against a flux transferring stage on which a thin film is formed of flux (10) containing metal powder (16) of good wettability to solder so as to cause metal powder (16) to penetrate oxide films (7a) and embed in the surfaces on the bottom parts of bumps (7), and bumps (7) in this state are positioned and mounted to electrodes (12a) on substrate (12). Substrate (12) is then heated to melt bumps (7) and allow the melted solder to flow and spread along the surfaces of metal powder (16) toward electrodes (12a). The method can thus provide solder bonding portions of high quality without any soldering defect and deterioration of the insulating property.Type: GrantFiled: June 22, 2005Date of Patent: August 4, 2009Assignee: Panasonic CorporationInventors: Tadahiko Sakai, Tadashi Maeda
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Patent number: 7562428Abstract: A manufacturing method that includes the steps of forming an actuator unit, disposing a metallic bond and a thermosetting resin; pressing the land and the terminal; and heating the metallic bond and the thermosetting resin so that the land and the terminal are electrically connected to each other with the metallic bond being disposed in at least one of a region between the land and the terminal and a region extending over the land and the terminal along the peripheries of the land and the terminal, and a protrusion made of the thermosetting resin is formed at least in the connecting portion between the main electrode portion and the land.Type: GrantFiled: September 23, 2003Date of Patent: July 21, 2009Assignee: Brother Kogyo Kabushiki KaishaInventor: Yuji Shinkai
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Patent number: 7556190Abstract: A mounting method and a mounting device are provided, which can mount an electric component with high reliability by using an adhesive. The mounting method includes thermocompression bonding an IC chip onto a wiring board by using an anisotropic conductive adhesive film. During the thermocompression bonding, a top region of the IC chip is pressed against the wiring board with a predetermined pressure, and a side region of the IC chip is pressed with a pressure smaller than the pressure applied to the top region of the IC chip. An elastomer having rubber hardness of 40 or more and 80 or less is used for a compression bonding portion of a thermocompression bonding head. The anisotropic conductive adhesive film contains a binding resin having melting viscosity of 1.0×102 mPa·s or more and 1.0×105 mPa·s or less.Type: GrantFiled: January 6, 2006Date of Patent: July 7, 2009Assignees: Sony Corporation, Sony Chemical & Information Device CorporationInventors: Takashi Matsumura, Hisashi Ando, Shiyuki Kanisawa, Yasuhiro Suga, Noriaki Kudo
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Publication number: 20090134205Abstract: A soldering method for soldering an electronic component to a circuit board is disclosed. The soldering method includes placing the electronic component on the bonding portion of the circuit board with solder arranged between the electronic component and the bonding portion, placing a weight on the electronic component, and heating and melting the solder while pressing the electronic component toward the circuit board with the weight. The weight is spaced from the electronic component while the temperature of the solder is still high after the melted solder wets the bonding portion and the bonding surface of the electronic component and spreads out therebetween.Type: ApplicationFiled: December 27, 2006Publication date: May 28, 2009Inventor: Masahiko Kimbara
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Patent number: 7501337Abstract: A method for forming a stud bumped semiconductor die is disclosed. The method includes forming a ball at the tip of a coated wire passing through a hole in a capillary, where the coated wire has a core and an oxidation-resistant coating. The formed ball is pressed to the conductive region on the semiconductor die. The coated wire is cut, thereby leaving a conductive stud bump on the conductive region, where the conductive stud bump includes an inner conductive portion and an outer oxidation-resistant layer.Type: GrantFiled: April 14, 2006Date of Patent: March 10, 2009Assignee: Fairchild Semiconductor CorporationInventors: Rajeev Joshi, Consuelo Tangpuz, Margie T. Rios, Erwin Victor R. Cruz
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Patent number: 7490402Abstract: The present invention provides a number of techniques for laminating and interconnecting multiple substrates to form a multilayer package or other circuit component. A solder bump may be formed on the conductive pad of at least one of two or more substrates. The solder bump preferably is formed from an application of solder paste to the conductive pad(s). Adhesive films may be positioned between the surfaces of the substrates having the conductive pads, where the adhesive films include apertures located substantially over the conductive pads such that the conductive pads and/or solder bumps confront each other through the aperture. The two or more substrates then may be pressed together to mechanically bond the two or more substrates via the adhesive films. The solder bump(s) may be reflowed during or after the lamination to create a solder segment that provides an electrical connection between the conductive pads through the aperture in the adhesive films.Type: GrantFiled: September 25, 2007Date of Patent: February 17, 2009Assignee: General Dynamics Advanced Information Systems, Inc.Inventors: Deepak K. Pai, Ronald R. Denny
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Patent number: 7490403Abstract: In a soldering method for soldering an electronic component including a palladium or palladium alloy layer formed on a surface of the electronic component and also including a soldering lead terminal onto a printed wiring board including a soldering land and plated through hole, a solder layer containing tin and zinc as main components is formed on the surfaces of the land through hole by a HAL treatment. The lead terminal is inserted and mounted in the through hole. The printed wiring board is brought into contact with jet flows of a solder containing tin and zinc as the main components to thereby supply a solder to the land and through hole.Type: GrantFiled: December 5, 2006Date of Patent: February 17, 2009Assignees: NEC Infrontia Corporation, NEC Toppan Circuit Solutions Toyoma, Inc., Soldercoat Co., Ltd., Maruya Seisakusbo Co., Ltd., Nihon Den-netsu Keiki Co., Ltd.Inventors: Kazuhiko Tanabe, Hiroaki Terada, Masahiro Sugiura, Tetsuharu Mizutani, Keiichiro Imamura, Takashi Tanaka
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Patent number: 7476564Abstract: A flip-chip packaging process is disclosed. The present invention is featured in forming a copper pillar on a wafer, forming a solder on a substrate; and enabling the solder to substantially cover the entire externally-exposed surface of the copper pillar, thereby connecting the copper pillar to the substrate. The copper pillar of the present invention can be such as a prism or a cylinder.Type: GrantFiled: December 30, 2005Date of Patent: January 13, 2009Assignee: Advanced Semiconductor Engineering Inc.Inventors: Chien-Fan Chen, Yi-Hsin Chen
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Patent number: 7472473Abstract: This invention provides a solder ball loading apparatus which enables fine solder balls to be loaded on pads while void is blocked from being caught into bump upon reflow. Inactive gas is supplied and the inactive gas is sucked from a loading cylinder located above a ball arrangement mask so as to gather solder balls. The gathered solder balls are rolled on the ball arrangement mask by moving the loading cylinder horizontally and the solder balls are dropped onto connecting pads on a multilayer printed wiring board through openings in the ball arrangement mask. Oxidation of the solder balls and mixture of voids upon reflow are prevented by loading the solder balls in the atmosphere of inactive gas.Type: GrantFiled: April 26, 2006Date of Patent: January 6, 2009Assignee: Ibiden Co., Ltd.Inventors: Yoichiro Kawamura, Katsuhiko Tanno
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Patent number: 7467742Abstract: Electrically conducting adhesives having a broader selectable range of properties are provided by having random sizes of micrometer diameter range particles coated with a low melting temperature metal. The coated particles are suspended in a vehicle of a mixture of thermosetting resins together with a flux resin selected for viscosity and low shrinkage, for screen printability, for electrical and for mechanical properties over a broad range of specification conditions. The vehicle or resin system includes thermosetting cyclo-aliphatic epoxy, thermosetting phenoxy polymer and thermosetting mono-functional limonene oxide. The low temperature melting coating system for the particles includes In, Sn, and alloys such as In—Sn, Sn—Pb, Bi—Sn—In and InAg. The micrometer diameter range particles includes Cu, Ni, Co, Ag, Pd, Pt, polymer and ceramic.Type: GrantFiled: February 24, 2000Date of Patent: December 23, 2008Assignee: International Business Machines CorporationInventors: Jeffrey Donald Gelorme, Sung Kwon Kang, Konstantinos Papathomas, Sampath Purushothaman
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Patent number: 7456438Abstract: A nitride-based semiconductor LED which is flip-chip bonded on a lead pattern of a sub-mount through a bump ball comprises a substrate; a light-emitting structure formed on the substrate; an electrode formed on the light-emitting structure; a protective film formed on the resulting structure having the electrode formed therein, the protective film exposing the electrode surface corresponding to a portion which is connected to the lead pattern of the sub-mount through a bump ball; and a grid-shape buffer film formed on the electrode surface exposed through the protective film.Type: GrantFiled: October 17, 2006Date of Patent: November 25, 2008Assignee: Samsung Electro-Mechanics Co., ltd.Inventors: Hyuk Min Lee, Hyoun Soo Shin, Chang Wan Kim, Yong Chun Kim
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Publication number: 20080277151Abstract: The present invention provides an electronic assembly 400 and a method for its manufacture 800, 900, 1000 1200, 1400, 1500, 1700. The assembly 400 uses no solder. Components 406, or component packages 402, 802, 804, 806 with I/O leads 412 are placed 800 onto a planar substrate 808. The assembly is encapsulated 900 with electrically insulating material 908 with vias 420, 1002 formed or drilled 1000 through the substrate 808 to the components' leads 412. Then the assembly is plated 1200 and the encapsulation and drilling process 1500 repeated to build up desired layers 422, 1502, 1702.Type: ApplicationFiled: May 12, 2008Publication date: November 13, 2008Applicant: OCCAM PORTFOLIO LLCInventor: Joseph C. Fjelstad
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Publication number: 20080261350Abstract: A method for assembling, and the resultant electronic module, includes attaching a chip to a substrate using a first solder interconnection array, and attaching a board to the substrate using a second solder interconnection array, which may be a single-melt or a dual-melt solder array. The second solder interconnection array resides entirely within a space defined between the board and substrate. A creep resistant structure is provided within this space for maintaining the defined space and optimizing integrity of the second solder interconnection array. The creep resistant structure may include an underfill material, balls, brackets, frames, collars or combinations thereof. Wherein the creep resistant structure is an underfill material, it is crucial that the substrate be attached to the board before either entirely encapsulating the second interconnection array with underfill material, or partially encapsulating the second solder interconnection array at discrete locations with underfill material.Type: ApplicationFiled: June 26, 2008Publication date: October 23, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Glenn G. Daves, David L. Edwards, Mukta G. Farooq, Frank L. Pompeo
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Publication number: 20080244900Abstract: There is provided a flux for soldering and a soldering process which form better solder connection without the occurrence of the poor connection nor the insulation degradation. Such flux which is placed between a solder portion formed on a first electrode and a second electrode when the first electrode is soldered to the second electrode contains: a liquid base material made of a resin component which is dissolved in a solvent, an active component which removes an oxide film, and a metal powder made of a metal of which melting point is higher than that of a solder material which forms the solder portion, and the flux contains the metal powder in an amount in the range between 1% and 9% by volume based on a volume of the flux.Type: ApplicationFiled: January 27, 2005Publication date: October 9, 2008Inventors: Tadashi Maeda, Tadahiko Sakai
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Publication number: 20080217384Abstract: An arrangement for the equipping of electronic packages with elliptical C4 connects possessing optimal orientation for enhanced reliability. Furthermore, disclosed is a method providing elliptical C4 connects which possesses optimal orientation for enhanced reliability, as implemented in connection with their installation in electronic packages. Employed are essentially elliptical solder pads or elliptical C4 pad configurations at various preferably corner locations on a semiconductor chip.Type: ApplicationFiled: March 5, 2007Publication date: September 11, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sri M. Jayantha, Lorenzo Valdevit
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Patent number: 7419084Abstract: A method for surface mount solder of a comparatively large component is provided wherein a first intermediate component is soldered to a printed wring board and a larger second component is positioned and soldered to the printed wiring board using the intermediate component. An electrical contact made this way is covered as well as its use in an electrostatographic printer.Type: GrantFiled: November 24, 2004Date of Patent: September 2, 2008Assignee: Xerox CorporationInventor: Hendrikus A. A. Verheijen
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Patent number: 7416106Abstract: A technique for processing a circuit board involves placing a mask layer on the circuit board, where the mask layer defines a set of pad profiles for a component mounting location. Each pad profile has a set of rounded corners. The technique further involves forming, for each pad profile, a soldering pad having a set of radii corresponding to the set of rounded corners of that pad profile to create a set of soldering pads for the component mounting location. Each soldering pad is configured for a high bond strength solder joint. The technique further involves removing the mask layer from the circuit board and soldering a component to the component mounting location. This technique is well-suited for robustly mounting the component to the circuit board at solder joints with relatively high solder joint bond strengths.Type: GrantFiled: September 29, 2003Date of Patent: August 26, 2008Assignee: EMC CorporationInventors: Stuart D. Downes, Jin Liang, Larry Norris
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Patent number: 7407084Abstract: A method for mounting a semiconductor chip onto a substrate the side of which facing towards the substrate is coated with an adhesive layer is characterised by the following steps: (1) Lowering the semiconductor chip until the semiconductor chip touches the substrate, (2) Waiting a predetermined period of time during which a force exerted on the semiconductor chip disappears or is at least comparatively small, and (3) Applying a bond force.Type: GrantFiled: December 5, 2005Date of Patent: August 5, 2008Assignee: Unaxis Trading LtdInventor: Matthias Urben
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Patent number: 7383977Abstract: A method for providing a PCB (printed circuit board) with a shield can (1) comprising a metal shell with a free rim (5). The method prescribes that the rim (5) of the shield can (1) is provided with an extra amount of solder (8) before the shield can (1) is placed on the PCB. A shield can (1) is also described.Type: GrantFiled: March 31, 2003Date of Patent: June 10, 2008Assignee: Sony Ericsson Mobile Communications ABInventors: Gustav Fagrenius, Fredrik Palmqvist
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Patent number: 7378297Abstract: A device and a method for bonding elements are described. A first solder ball is produced on a main surface of a first element. A second solder ball is produced on a main surface of a second element. Contact is provided between the first solder ball and the second solder ball. The first and second elements are bonded by applying a reflow act whereby the solder balls melt and form a joined solder ball structure. Prior to the bonding, the first solder ball is laterally embedded in a first layer of non-conductive material and the second solder ball is laterally embedded in a second layer of non-conductive material, such that the upper part of the first solder ball and upper part of the second solder ball are not covered by the non-conductive material. A third solder volume is applied on one or both of the embedded first or second solder balls, prior to the bonding.Type: GrantFiled: May 26, 2006Date of Patent: May 27, 2008Assignee: Interuniversitair Microelektronica Centrum (IMEC)Inventor: Eric Beyne
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Patent number: 7357293Abstract: In some example embodiments, a method includes engaging a first contact on a motherboard with a second contact on an electronic package. A portion of one of the first and second contacts is covered with an interlayer that has a lower melting temperature than both of the first and second contacts. The method further includes bonding the first contact to the second contact by melting the interlayer to diffuse the interlayer into the first and second contacts. The bonded first and second contacts have a higher melting temperature than the interlayer before melting. In other example embodiments, an electronic assembly includes a motherboard having a first contact that is bonded to a second contact on an electronic package. An interlayer is diffused within the first and second contacts such that they have a higher melting temperature than the interlayer before the interlayer is diffused into the first and second contacts.Type: GrantFiled: March 24, 2004Date of Patent: April 15, 2008Assignee: Intel CorporationInventor: Daewoong Suh
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Patent number: 7357294Abstract: A method for mounting a semiconductor package onto PCB includes a semiconductor package comprising a plurality of outer terminals exposed out of an encapsulant. A PCB having a surface with a plurality of contact pads is provided. Each contact pad has a first exposed side, a second exposed side and a center between the exposed sides. A plurality of first pre-solders and second pre-solders are formed on the surface to cover the first and second exposed sides of the contact pads respectively, the centers of the contact pads between the first and second pre-solders being exposed. Then the first and second pre-solders are reflowed and the semiconductor package is mounted on the PCB. When the outer terminals are connected to the contact pads, each first pre-solder and second pre-solder are flowed toward the centers of the contact pad to prevent the fine pitch contact pads from bridging.Type: GrantFiled: September 17, 2004Date of Patent: April 15, 2008Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Pai-Chou Liu, Hsin-Fu Chuang
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Patent number: 7351072Abstract: A memory extension memory module, a memory module system, and a memory module is disclosed. The memory module including at least one memory device and a connector for connecting the memory module to a computer system, wherein the memory module additionally includes a surface-mounted connector for connecting a memory extension memory module to the memory module. Furthermore, a method for manufacturing a memory module is disclosed. The memory module including at least one memory device and at least one connector for connecting a memory extension memory module to the memory module, wherein the at least one memory device and the at least one connector are connected to the memory module in a single manufacturing process.Type: GrantFiled: July 6, 2006Date of Patent: April 1, 2008Assignee: Qimonda AGInventors: Simon Muff, Siva Raghuram
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Patent number: 7344060Abstract: A device for orienting an integrated lead suspension tail during a head gimbal assembly soldering operation of a head stack assembly process is disclosed. The device includes a body portion and at least one pin extending from the body portion. The pin(s) is configured to position the integrated lead suspension tail proximate to a main flex cable such that electrical coupling between the integrated lead suspension tail and the main flex cable is established upon completion of said head gimbal assembly soldering operation. The pin(s) has sufficient length to extend past a terminal end of the main flex cable.Type: GrantFiled: September 27, 2004Date of Patent: March 18, 2008Assignee: Hitachi Global Storage Technologies Netherlands, B.V.Inventor: Choon Kuay Koh
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Patent number: 7337534Abstract: The apparatus is for securely fetching and positioning an SMD chip on a printed circuit board and soldering the same to the board. Two spring plates form the clasping fingers which are wedged apart to a width larger than the width of the SMD chip by an expander formed on an elongated rod slidably mounted within a vertical tubular housing. An SMD chip may be safely fetched by pressing the rod on the top of the SMD with a continuous depressing motion until the fingers clasp the SMD chip safely therebetween. A soldering unit with a bifurcate soldering head located juxtaposed to the fingers is operative to solder the SMD chip to the printed circuit board while the SMD chip is safely held in place.Type: GrantFiled: April 7, 2005Date of Patent: March 4, 2008Inventors: Chi Ming Wong, Woon-Wai Chan
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Patent number: 7331500Abstract: Method of forming solder bumps of an integrated circuit package is described. A solder paste is formed from a material having a characteristic that the deposited instances thereof substantially retain their geometric shape upon exposure to electromagnetic radiation.Type: GrantFiled: June 25, 2004Date of Patent: February 19, 2008Assignee: Intel CorporationInventors: Edward L. Martin, Paul A. Koning
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Patent number: 7328830Abstract: An integrated circuit structure and a method for fabricating the structure. The method comprises forming a copper bond pad for attaching the integrated circuit to a package. Copper oxide is removed from the pad by reduction in a hydrogen ion atmosphere. For attaching the integrated circuit to a bump-bonding package an under-bump metallization layer is formed over the reduced copper pad and a solder bump formed thereover. The process can also be employed in a wire bonding process by forming an aluminum layer overlying the cleaned copper pad. The structure of the present invention comprises a copper pad formed in a substrate. A passivation layer defining an opening therein overlies the copper pad. A under-bump metallization layer is disposed in the opening and a solder bump overlies the metallization layer. Alternatively, the structure further comprises an aluminum pad disposed overlying the reduced copper pad.Type: GrantFiled: December 19, 2003Date of Patent: February 12, 2008Assignee: Agere Systems Inc.Inventors: Mark Adam Bachman, Daniel Patrick Chesire, Sailesh Mansinh Merchant
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Patent number: 7322511Abstract: A method and device for printing liquid material such as liquid solder is provided. C4 structures as small as 10 microns in diameter can be produced using devices and methods described above. Further, devices and methods provided are able to operate at temperatures much higher than other print head designs such as piezoelectric actuated print heads. Additionally, due to the use of a gas flow restricting device and a recharging gas supply, ejection devices as described above can be used for a substantially extended lifetime, thus making devices and methods described above more economically desirable.Type: GrantFiled: September 21, 2005Date of Patent: January 29, 2008Assignee: Micron Technology, Inc.Inventors: Paul A. Farrar, Jerome M. Eldridge