Combined With A Heterojunction Involving A Iii-v Compound Patents (Class 257/11)
  • Patent number: 10692683
    Abstract: A novel photocathode employing a conduction band barrier is described. Incorporation of a barrier optimizes a trade-off between photoelectron transport efficiency and photoelectron escape probability. The barrier energy is designed to achieve a net increase in photocathode sensitivity over a specific operational temperature range.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: June 23, 2020
    Assignee: INTEVAC, INC.
    Inventors: Kenneth A. Costello, Verle W. Aebi, Michael Jurkovic, Xi Zeng
  • Patent number: 10651341
    Abstract: An optoelectronic device including first and second active regions suitable for emitting or detecting electromagnetic radiation and containing a first semiconductor material that predominantly contains a first compound selected from Compounds III-V, Compounds II-VI, and mixtures of same. The first active regions have a first polarity, and the second active regions have a second polarity different from the first polarity.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: May 12, 2020
    Assignees: Aledia, Centre National de la Recherche Scientifique
    Inventors: Benoît Amstatt, Sylvia Scaringella, Jesus Zuniga-Perez
  • Patent number: 10580871
    Abstract: Nucleation layers for growth of III-nitride structures, and methods for growing the nucleation layers, are described herein. A semiconductor can include a silicon substrate and a nucleation layer over the silicon substrate. The nucleation layer can include silicon and deep-level dopants. The semiconductor can include a III-nitride layer formed over the nucleation layer. At least one of the silicon substrate and the nucleation layer can include ionized contaminants. In addition, a concentration of the deep-level dopants is at least as high as a concentration of the ionized contaminants.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: March 3, 2020
    Assignee: IQE plc
    Inventors: Oleg Laboutin, Chen-Kai Kao, Chien-Fong Lo, Wayne Johnson, Hugues Marchand
  • Patent number: 10573677
    Abstract: A semiconductor device includes an elongated plate having at least a pair of grooves or protrusions, which are spaced from each other in a width direction and extend without interruption in a longitudinal direction, on a surface of the elongated plate, a semiconductor chip mounted on the surface of the elongated plate and including an element region which extends in the longitudinal direction, a resin over the semiconductor chip, the resin forming a slit that extends in the longitudinal direction of the elongated plate, leaving the element region exposed, and a transparent plate that extends in the longitudinal direction of the elongated plate and is disposed on the slit to allow light transmission.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: February 25, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Takao Egami
  • Patent number: 10483384
    Abstract: A transistor device includes a first emitter region of a first doping type, a second emitter region of a second doping type, a body of the second doping type, a drift region of the first doping type, a field-stop region of the first doping type, at least one boost structure, and a gate electrode. The boost structure is arranged between the field-stop region and the second emitter region. The at least one boost structure includes a base region of the first doping type and at least one auxiliary emitter region of the second doping type separated from the second emitter region by the base region. An overall dopant dose in the drift region and the field-stop region in a current flow direction of the transistor device is higher than a breakthrough charge of a semiconductor material of the drift region and the field-stop region.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: November 19, 2019
    Assignee: Infineon Technologies AG
    Inventors: Riteshkumar Bhojani, Franz-Josef Niedernostheide, Hans-Joachim Schulze, Josef Lutz, Roman Baburske
  • Patent number: 10424692
    Abstract: An optoelectronic device including first, and second active regions suitable for emitting or detecting electromagnetic radiation and containing a first semiconductor material that predominantly contains a first compound selected from Compounds III-V, Compounds II-VI, and mixtures of same. The first active regions have a first polarity, and the second active regions have a second polarity different from the first polarity.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: September 24, 2019
    Assignees: Aledia, Centre National de la Recherche Scientifique
    Inventors: Benoît Amstatt, Sylvia Scaringella, Jesus Zuniga-Perez
  • Patent number: 10403718
    Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes a channel, a first dielectric layer disposed over the semiconductor substrate, and a regrown contact formed through a first opening in the first dielectric layer. The regrown contact includes a regrown region formed over the semiconductor substrate, an overhang region coupled to the regrown region and formed over the first dielectric layer, adjacent the first opening, and a conductive cap formed over the regrown region and the overhang region. A method for fabricating the semiconductor device includes forming the first dielectric layer over the semiconductor substrate, forming the first opening in the first dielectric layer, forming a regrown semiconductor layer within the first opening and over the first dielectric layer, forming a conductive cap over the regrown semiconductor layer, and etching the regrown semiconductor layer outside the conductive cap.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: September 3, 2019
    Assignee: NXP USA, Inc.
    Inventors: Jenn Hwa Huang, Yuanzheng Yue
  • Patent number: 10374102
    Abstract: A semiconductor device includes first to fourth semiconductor regions, and first and second electrodes. The second semiconductor region is selectively disposed in a surface layer of one main surface of the first semiconductor region. The first electrode is in contact with a contact region of the second semiconductor region. The third semiconductor region is disposed in a surface layer on another main surface of the first semiconductor region, and having an impurity concentration higher than that of the first semiconductor region. The second electrode is in contact with the third semiconductor region. The fourth semiconductor region of the second conductivity type is disposed in the first semiconductor region, and disposed closer to the one main surface than the third semiconductor region. The fourth semiconductor region is disposed at least within the contact region in a plan view.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: August 6, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yuichi Onozawa, Takashi Yoshimura, Hiroshi Takishita
  • Patent number: 10297736
    Abstract: A Flip-chip LED chip includes: a substrate; a first semiconductor layer; a second semiconductor layer; a local defect region over part of the second semiconductor layer, which extends downward to the first semiconductor layer; a first metal layer over part of the first semiconductor layer; a second metal layer over part of the second semiconductor layer; an insulating layer covering the first metal layer, the second metal layer, the second semiconductor layer and the first semiconductor layer in the local defect region, with opening structures over the first metal layer and the second metal layer respectively; an eutectic electrode structure over the insulating layer, including a first eutectic layer and a second eutectic layer at vertical direction, and a first-type electrode region and a second-type electrode region at horizontal direction. Poor packaging caused by high eutectic void content during eutectic bonding process can therefore be reduced.
    Type: Grant
    Filed: December 24, 2017
    Date of Patent: May 21, 2019
    Assignee: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Anhe He, Suhui Lin, Jiansen Zheng, Kangwei Peng, Xiaoxiong Lin, Chenke Hsu
  • Patent number: 10276705
    Abstract: A semiconductor structure having a buffer layer, a pseudomorphic, impurity doped, back-barrier layer disposed on the buffer layer, a channel layer disposed on the back-barrier layer, the channel layer lattice matched to the buffer layer, and a top barrier layer disposed on the channel layer. A Group III-Nitride transition layer is disposed between the buffer layer and the pseudomorphic back-barrier layer. The buffer layer and the pseudomorphic back-barrier layer are both Group III-Nitride materials. The Group III-Nitride material of the buffer layer is different from the Group III-Nitride material in the back-barrier layer. The back-barrier layer has a wider bandgap of than the buffer layer bandgap. The composition of the Group III-Nitride material in the transition layer varies from the composition of the Group III-Nitride material in the buffer layer to the composition of the Group III-Nitride material in the pseudomorphic back-barrier layer as a function of distance from the buffer layer.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: April 30, 2019
    Assignee: Raytheon Company
    Inventors: Brian D. Schultz, Eduardo M. Chumbes
  • Patent number: 10147661
    Abstract: A semiconductor device includes: a semiconductor substrate having a main plane; a semiconductor element provided on the main plane of the semiconductor substrate; an electrode pad provided on the main plane of the semiconductor substrate and connected to the semiconductor element; a guard ring surrounding the semiconductor element and the electrode pad, and provided on the main plane of the semiconductor substrate; and an insulating film covering all region of a semiconductor of the main plane of the semiconductor substrate exposed inside the guard ring, wherein the insulating film is made of a water impermeable material.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: December 4, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yoichi Nogami
  • Patent number: 10074619
    Abstract: An optoelectronic component device includes first and second electrodes; a first optoelectronic component electrically coupled to the first and second electrodes; and a first electrically conductive section electrically coupled to the first electrode, and a second electrically conductive section electrically coupled to the second electrode; wherein the first and second electrically conductive sections are arranged electrically in parallel with the first optoelectronic component; wherein the first and second electrically conductive sections are arranged and configured relative to one another such that, beyond a response voltage applied over the first and second conductive sections, a discharge path is formed between the first and second conductive sections; and wherein the response voltage has as its value a value formed greater than the threshold voltage value of the first optoelectronic component and less than or equal to the value of the breakdown voltage of the first optoelectronic component.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: September 11, 2018
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Torsten Baade, Jörg Erich Sorg
  • Patent number: 9960262
    Abstract: A semiconductor structure having a buffer layer, a pseudomorphic, impurity doped, back-barrier layer disposed on the buffer layer, a channel layer disposed on the back-barrier layer, the channel layer lattice matched to the buffer layer, and a top barrier layer disposed on the channel layer. A Group III-Nitride transition layer is disposed between the buffer layer and the pseudomorphic back-barrier layer. The buffer layer and the pseudomorphic back-barrier layer are both Group III-Nitride materials. The Group III-Nitride material of the buffer layer is different from the Group III-Nitride material in the back-barrier layer. The back-barrier layer has a wider bandgap of than the buffer layer bandgap. The composition of the Group III-Nitride material in the transition layer varies from the composition of the Group III-Nitride material in the buffer layer to the composition of the Group III-Nitride material in the pseudomorphic back-barrier layer as a function of distance from the buffer layer.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: May 1, 2018
    Assignee: Raytheon Company
    Inventors: Brian D. Schultz, Eduardo M. Chumbes
  • Patent number: 9929107
    Abstract: In an embodiment, a method includes forming an opening in a front surface of a substrate including at least one Group III nitride-based transistor on the first surface, inserting conductive material into the opening, and coupling a source electrode of the Group III nitride-based transistor to a rear surface of the substrate with the conductive material.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: March 27, 2018
    Assignee: Infineon Technologies AG
    Inventors: Albert Birner, Helmut Brech
  • Patent number: 9786744
    Abstract: An epitaxial group-ill-nitride buffer-layer structure is provided on a heterosubstrate, wherein the buffer-layer structure has at least one stress-management layer sequence including an interlayer structure arranged between and adjacent to a first and a second group-ill-nitride layer, wherein the interlayer structure comprises a group-ill-nitride interlayer material having a larger band gap than the materials of the first and second group-ill-nitride layers, and wherein a p-type-dopant-concentration profile drops, starting from at least 1×1018 cm-3, by at least a factor of two in transition from the interlayer structure to the first and second group-ill-nitride layers.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: October 10, 2017
    Assignee: AZURSPACE Solar Power GmbH
    Inventors: Stephan Lutgen, Saad Murad, Ashay Chitnis
  • Patent number: 9779906
    Abstract: An electron emission device includes a substrate and an electron emission layer. The electron emission layer is provided above the substrate, and is provided with an opening. The electron emission layer has an edge defining the opening and is configured to emit electrons from the edge when the edge is irradiated with light.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: October 3, 2017
    Assignee: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO
    Inventors: Tsuyoshi Ishikawa, Takashi Katsuno, Narumasa Soejima
  • Patent number: 9716367
    Abstract: The present disclosure relates to nitride based optoelectronic and electronic devices with Si CMOS. The disclosure provides a semiconductor device, comprising a sapphire substrate, and a laser region and a detector region deposed on the sapphire substrate. The laser is formed onto the substrate from layers of GaN, InGaN and optionally the AlGaN. The detector can be an InGaN detector. A waveguide may be interposed between the laser and detector regions coupling these regions. The semiconductor device allows integration of nitride base optoelectronic and electronic devices with Si CMOS. The disclosure also provides a method for making the semiconductor devices.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: July 25, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tymon Barwicz, Effendi Leobandung, Ning Li, Jean-Olivier Plouchart, Devendra K. Sadana
  • Patent number: 9520211
    Abstract: Provided are a method of forming an upper electrode of a nanowire array and a nanowire array having an upper electrode formed thereon. The method includes a step of placing a polymeric thin film layer, a step of pressing, a step of treating a mixed solution, a step of etching, and a step of depositing an electrode material, such that the upper electrode is reliably formed in a state in which the polymeric thin film layer is formed on a portion of the nanowire, thereby making it possible to implement various nano-devices based on the nanowire array aligned on a substrate having a large area.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: December 13, 2016
    Assignee: KOREA RESEARCH INSTITUTE OF STANDARDS AND SCIENCE
    Inventors: Woo Lee, Hee Han
  • Patent number: 9368684
    Abstract: Provided are a light emitting device and a method for manufacturing the same. The light emitting device comprises a first conductive type semiconductor layer, an active layer, a second conductive type semiconductor layer, and a light extraction layer. The active layer is formed on the first conductive type semiconductor layer. The second conductive type semiconductor layer is formed on the active layer. The light extraction layer is formed on the second conductive type semiconductor layer. The light extraction layer has a refractive index smaller than or equal to a refractive index of the second conductive type semiconductor layer.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: June 14, 2016
    Assignee: LG Innotek Co., Ltd.
    Inventor: Dae Sung Kang
  • Patent number: 9324908
    Abstract: Provided is a nitride semiconductor light-emitting element including in order a first n-type nitride semiconductor layer, a second n-type nitride semiconductor layer, an n-type electron-injection layer, a light-emitting layer, and a p-type nitride semiconductor layer, wherein the average n-type dopant concentration of the second n-type nitride semiconductor layer is 0.53 times or less as high as the average n-type dopant concentration of the first n-type nitride semiconductor layer, and the average n-type dopant concentration of the n-type electron-injection layer is 1.5 times or more as high as the average n-type dopant concentration of the second n-type nitride semiconductor layer.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: April 26, 2016
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Masanori Watanabe, Satoshi Komada, Tomoya Inoue, Kosuke Kawabata
  • Patent number: 9312433
    Abstract: Embodiments of the present invention include a light emitting element, a method for manufacturing the light-emitting element according to one embodiment of the present invention, comprises: a first conductive semiconductor layer 112; a GaN-based superlattice layer 124 on the first conductive semiconductor layer 112; an active layer 114 on the GaN-based superlattice layer 124; and a second conductive semiconductor layer 116 on the active layer 114, wherein the GaN-based superlattice layer 124 has a bandgap energy level that varies in a direction from the first conductive semiconductor layer 112 to the active layer 114.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: April 12, 2016
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Dae Seob Han, Yong Tae Moon, A Ra Cho, Kwang Sun Baek
  • Patent number: 9312377
    Abstract: Semiconductor devices including a substrate (e.g., silicon substrate), a multi-layer structure disposed on a portion of the substrate, and at least one electrode disposed on the multi-layer structure and methods of manufacturing the same are provided. The multi-layer structure may include an active layer containing a Group III-V material and a current blocking layer disposed between the substrate and the active layer. The semiconductor device may further include a buffer layer disposed between the substrate and the active layer. In a case that the substrate is a p-type, the buffer layer may be an n-type material layer and the current blocking layer may be a p-type material layer. The current blocking layer may contain a Group III-V material. A mask layer having an opening may be disposed on the substrate so that the multi-layer structure may be disposed on the portion of the substrate exposed by the opening.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: April 12, 2016
    Assignee: Samsung Electronics Co. LTD
    Inventors: Sang-moon Lee, Young-jin Cho
  • Patent number: 9130141
    Abstract: Disclosed is a light-emitting diode element including a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, an active layer. A first electrode is provided on a surface of the second semiconductor layer. A second electrode is provided in a second region of the principal surface of the first semiconductor layer. A conductive layer is arranged such that the conductive layer covers a third region, a fourth region, and a fifth region in the rear surface of the first semiconductor layer. In the rear surface of the first semiconductor layer, the first semiconductor layer includes a sixth region which is not covered with the conductive layer and which overlaps another part of the first electrode. The first semiconductor layer is not provided with a through electrode.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: September 8, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Junko Iwanaga, Akira Inoue, Toshiya Yokogawa, Shigeo Hayashi
  • Patent number: 8981338
    Abstract: A semiconductor photocathode includes an AlXGa1-XN layer (0?X<1) bonded to a glass substrate via an SiO2 layer and an alkali-metal-containing layer formed on the AlXGa1-XN layer. The AlXGa1-XN layer includes a first region, a second region, an intermediate region between the first and second regions. The second region has a semiconductor superlattice structure formed by laminating a barrier layer and a well layer alternately, the intermediate region has a semiconductor superlattice structure formed by laminating a barrier layer and a well layer alternately. When a pair of adjacent barrier and well layers is defined as a unit section, an average value of a composition ratio X of Al in a unit section decreases monotonously with distance from an interface position between the second region and the SiO2 layer at least in the intermediate region.
    Type: Grant
    Filed: March 22, 2013
    Date of Patent: March 17, 2015
    Assignees: Sanken Electric Co., Ltd., Hamamatsu Photonics K.K.
    Inventors: Shunro Fuke, Tetsuji Matsuo, Yoshihiro Ishigami, Tokuaki Nihashi
  • Patent number: 8952419
    Abstract: A semiconductor device includes a substrate, a buffer layer on the substrate, and a plurality of nitride semiconductor layers on the buffer layer. The semiconductor device further includes at least one masking layer and at least one inter layer between the plurality of nitride semiconductor layers. The at least one inter layer is on the at least one masking layer.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: February 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-jo Tak, Jae-won Lee, Young-soo Park, Jun-youn Kim
  • Patent number: 8946674
    Abstract: A layered group III-nitride article includes a single crystal silicon substrate, and a highly textured group III-nitride layer, such as GaN, disposed on the silicon substrate. The highly textured group III-nitride layer is crack free and has a thickness of at least 10 ?m. A method for forming highly textured group III-nitride layers includes the steps of providing a single crystal silicon comprising substrate, depositing a nanostructured InxGa1-xN (1?x?0) interlayer on the silicon substrate, and depositing a highly textured group III-nitride layer on the interlayer. The interlayer has a nano indentation hardness that is less than both the silicon substrate and the highly textured group III-nitride layer.
    Type: Grant
    Filed: August 29, 2006
    Date of Patent: February 3, 2015
    Assignee: University of Florida Research Foundation, Inc.
    Inventors: Olga Kryliouk, Hyun Jong Park, Timothy J. Anderson
  • Patent number: 8940622
    Abstract: A method for manufacturing a compound semiconductor device, the method includes: forming a compound semiconductor laminated structure; removing a part of the compound semiconductor laminated structure, so as to form a concave portion; and cleaning the inside of the concave portion by using a detergent, wherein the detergent contains a base resin compatible with residues present in the concave portion and a solvent.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: January 27, 2015
    Assignee: Fujitsu Limited
    Inventor: Junichi Kon
  • Patent number: 8901533
    Abstract: Semiconductor devices including a substrate (e.g., silicon substrate), a multi-layer structure disposed on a portion of the substrate, and at least one electrode disposed on the multi-layer structure and methods of manufacturing the same are provided. The multi-layer structure may include an active layer containing a Group III-V material and a current blocking layer disposed between the substrate and the active layer. The semiconductor device may further include a buffer layer disposed between the substrate and the active layer. In a case that the substrate is a p-type, the buffer layer may be an n-type material layer and the current blocking layer may be a p-type material layer. The current blocking layer may contain a Group III-V material. A mask layer having an opening may be disposed on the substrate so that the multi-layer structure may be disposed on the portion of the substrate exposed by the opening.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: December 2, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-moon Lee, Young-jin Cho
  • Patent number: 8900985
    Abstract: A compound semiconductor device is manufactured by forming an III-nitride compound semiconductor device structure on a silicon-containing semiconductor substrate, the III-nitride compound semiconductor device structure including a GaN alloy on GaN and a channel region arising near an interface between the GaN alloy and the GaN. One or more silicon-containing insulating layers are formed on a surface of the III-nitride compound semiconductor device structure adjacent the GaN alloy, and a contact opening is formed which extends through the one or more silicon-containing insulating layers to at least the GaN alloy. A region of GaN is regrown in the contact opening, and the regrown region of GaN is doped exclusively with Si out-diffused from the one or more silicon-containing insulating layers to form an ohmic contact which is doped only with the Si out-diffused from the one or more silicon-containing insulating layers.
    Type: Grant
    Filed: October 15, 2012
    Date of Patent: December 2, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Gilberto Curatola, Gianmauro Pozzovivo, Simone Lavanga
  • Patent number: 8901612
    Abstract: Embodiments of a thin-film heterostructure thermoelectric material and methods of fabrication thereof are disclosed. In general, the thermoelectric material is formed in a Group IIa and IV-VI materials system. The thermoelectric material includes an epitaxial heterostructure and exhibits high heat pumping and figure-of-merit performance in terms of Seebeck coefficient, electrical conductivity, and thermal conductivity over broad temperature ranges through appropriate engineering and judicious optimization of the epitaxial heterostructure.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: December 2, 2014
    Assignees: Phononic Devices, Inc., The Board of Regents of the University of Oklahoma
    Inventors: Allen L. Gray, Robert Joseph Therrien, Patrick John McCann
  • Patent number: 8884265
    Abstract: An InGaAs n-channel quantum well heterostructure for use in a complementary transistor having a Sb-based p-channel. The heterostructure includes a buffer layer having a lattice constant intermediate that of the n- and p-channel materials and which is configured to accommodate the strain produced by a lattice-constant mismatch between the n-channel and p-channel materials.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: November 11, 2014
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Brian R. Bennett, John Bradley Boos, Theresa F. Chick, James G. Champlain
  • Publication number: 20140326943
    Abstract: A semiconductor device for electron emission in a vacuum comprises a stack of two or more semi-conductor layers of N and P type according to sequence N/(P)/N forming a juxtaposition of two head-to-tail NP junctions, in materials belonging to the III-N family, two adjacent layers forming an interface. The semiconductor materials of the layers of the stack close to the vacuum, where the electrons reach a high energy, have a band gap Eg>c/2, where c is the electron affinity of the semiconductor material, the P-type semiconductor layer being obtained partially or completely, by doping impurities of acceptor type or by piezoelectric effect to exhibit a negative fixed charge in any interface between the layers, a positive bias potential applied to the stack supplying, to a fraction of electrons circulating in the stack, the energy needed for emission in the vacuum by an emissive zone of an output layer.
    Type: Application
    Filed: July 20, 2012
    Publication date: November 6, 2014
    Applicant: THALES
    Inventors: Jean-Claude Jacquet, Raphaël Aubry, Marie-Antoinette Poisson, Sylvain Delage
  • Patent number: 8872308
    Abstract: III-N material grown on a silicon substrate includes a single crystal rare earth oxide layer positioned on a silicon substrate. The rare earth oxide is substantially crystal lattice matched to the surface of the silicon substrate. A first layer of III-N material is positioned on the surface of the rare earth oxide layer. An inter-layer of aluminum nitride (AlN) is positioned on the surface of the first layer of III-N material and an additional layer of III-N material is positioned on the surface of the inter-layer of aluminum nitride. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer. A cap layer of AlN is grown on the final III-N layer and a III-N layer of material with one of an LED structure and an HEMT structure is grown on the AlN cap layer.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: October 28, 2014
    Assignee: Translucent, Inc.
    Inventors: Erdem Arkun, Michael Lebby, Andrew Clark, Rytis Dargis
  • Patent number: 8835998
    Abstract: A compositionally graded semiconductor device and a method of making same are disclosed that provides an efficient p-type doping for wide bandgap semiconductors by exploiting electronic polarization within the crystalline lattice. The compositional graded semiconductor graded device includes a graded heterojunction interface that exhibits a 3D bound polarization-induced sheet charge that spreads in accordance with ??(z)=??·P(z), where ??(z) is a volume charge density in a polar (z) direction, and ? is a divergence operator, wherein the graded heterojunction interface is configured to exhibit substantially equivalent conductivities along both lateral and vertical directions relative to the graded heterojunction interface.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: September 16, 2014
    Assignee: University of Notre Dame du Lac
    Inventors: John Simon, Debdeep Jena, Huili Xing
  • Patent number: 8816321
    Abstract: A nitride semiconductor light-emitting device includes an n-type nitride semiconductor layer, a V pit generation layer, an intermediate layer, a multiple quantum well light-emitting layer, and a p-type nitride semiconductor layer provided in this order. The multiple quantum well light-emitting layer is a layer formed by alternately stacking a barrier layer and a well layer having a bandgap energy smaller than that of the barrier layer. A V pit is partly formed in the multiple quantum well light-emitting layer, and an average position of starting point of the V pit is located in the intermediate layer.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: August 26, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tadashi Takeoka, Yoshihiko Tani, Kazuya Araki, Yoshihiro Ueta
  • Patent number: 8809867
    Abstract: Lateral epitaxial overgrowth of non-polar III-nitride seed layers reduces threading dislocations in the non-polar III-nitride thin films. First, a thin patterned dielectric mask is applied to the seed layer. Second, a selective epitaxial regrowth is performed to achieve a lateral overgrowth based on the patterned mask. Upon regrowth, the non-polar III-nitride films initially grow vertically through openings in the dielectric mask before laterally overgrowing the mask in directions perpendicular to the vertical growth direction. Threading dislocations are reduced in the overgrown regions by (1) the mask blocking the propagation of dislocations vertically into the growing film and (2) the bending of dislocations through the transition from vertical to lateral growth.
    Type: Grant
    Filed: September 10, 2007
    Date of Patent: August 19, 2014
    Assignee: The Regents of the University of California
    Inventors: Michael D. Craven, Steven P. Denbaars, James S. Speck, Shuji Nakamura
  • Patent number: 8748861
    Abstract: An AlGaN/GaN-HEMT has a structure including: compound semiconductor layers formed on a substrate; a gate electrode, a gate pad that has a current path formed between the gate electrode and itself, and a semiconductor layer that is spontaneously polarized and piezoelectrically polarized, which are formed on the compound semiconductor layer; and a gate electrode connection layer formed on the semiconductor layer, wherein the gate electrode connection layer and the gate electrode are electrically connected with each other. This structure which is relatively simple allows the AlGaN/GaN-HEMT to realize an intended normally-off operation without causing such inconveniences as increase in a sheet resistance, increase in an on-resistance, and increase in a leakage current.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: June 10, 2014
    Assignee: Fujitsu Limited
    Inventor: Atsushi Yamada
  • Patent number: 8633569
    Abstract: III-N material grown on a silicon substrate includes a single crystal rare earth oxide layer positioned on a silicon substrate. The rare earth oxide is substantially crystal lattice matched to the surface of the silicon substrate. A first layer of III-N material is positioned on the surface of the rare earth oxide layer. An inter-layer of aluminum nitride (AlN) is positioned on the surface of the first layer of III-N material and an additional layer of III-N material is positioned on the surface of the inter-layer of aluminum nitride. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: January 21, 2014
    Assignee: Translucent, Inc.
    Inventors: Erdem Arkun, Michael Lebby, Andrew Clark, Rytis Dargis
  • Publication number: 20130320295
    Abstract: A vacuum encapsulated, hermetically sealed cathode capsule for generating an electron beam of secondary electrons, which generally includes a cathode element having a primary emission surface adapted to emit primary electrons, an annular insulating spacer, a diamond window element comprising a diamond material and having a secondary emission surface adapted to emit secondary electrons in response to primary electrons impinging on the diamond window element, a first high-temperature solder weld disposed between the diamond window element and the annular insulating spacer and a second high-temperature solder weld disposed between the annular insulating spacer and the cathode element.
    Type: Application
    Filed: May 17, 2013
    Publication date: December 5, 2013
    Applicant: Brookhaven Science Associates, LLC
    Inventors: Triveni Rao, John Walsh, Elizabeth Gangone
  • Publication number: 20130248815
    Abstract: A semiconductor photocathode includes an AlXGa1-XN layer (0?X<1) bonded to a glass substrate via an SiO2 layer and an alkali-metal-containing layer formed on the AlXGa1-XN layer. The AlXGa1-XN layer includes a first region, a second region, an intermediate region between the first and second regions. The second region has a semiconductor superlattice structure formed by laminating a barrier layer and a well layer alternately, the intermediate region has a semiconductor superlattice structure formed by laminating a barrier layer and a well layer alternately. When a pair of adjacent barrier and well layers is defined as a unit section, an average value of a composition ratio X of Al in a unit section decreases monotonously with distance from an interface position between the second region and the SiO2 layer at least in the intermediate region.
    Type: Application
    Filed: March 22, 2013
    Publication date: September 26, 2013
    Applicants: HAMAMATSU PHOTONICS K.K., SANKEN ELECTRIC CO., LTD.
    Inventors: Shunro FUKE, Tetsuji MATSUO, Yoshihiro ISHIGAMI, Tokuaki NIHASHI
  • Patent number: 8507921
    Abstract: A compound semiconductor substrate includes a first substrate and a second substrate made of single crystal silicon carbide. In each of the first substrate and the second substrate, one surface is a (000-1) C-face and an opposite surface is a (0001) Si-face. The first substrate and the second substrate are bonded to each other in a state where the (0001) Si-face of the first substrate and the (0001) Si-face of the second substrate face each other, and the (000-1) C-face of the first substrate and the (000-1) C-face of the second substrate are exposed.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: August 13, 2013
    Assignee: DENSO CORPORATION
    Inventors: Hiroaki Fujibayashi, Masami Naito, Nobuyuki Ooya
  • Patent number: 8476639
    Abstract: There is provided a surface treatment method of a group III nitride semiconductor including: providing a group III nitride semiconductor including a first surface having a group III polarity and a second surface opposing the first surface and having a nitrogen polarity; and irradiating a laser beam onto the second surface to change the nitrogen polarity of the second surface to the group III polarity.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: July 2, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong In Yang, Sang Bum Lee, Sang Yeob Song, Si Hyuk Lee, Tae Hyung Kim
  • Patent number: 8450192
    Abstract: Growth methods for planar, non-polar, Group-III nitride films are described. The resulting films are suitable for subsequent device regrowth by a variety of growth techniques.
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: May 28, 2013
    Assignees: The Regents of the University of California, Japan Science and Technology Center
    Inventors: Benjamin A. Haskell, Paul T. Fini, Shigemasa Matsuda, Michael D. Craven, Steven P. DenBaars, James S. Speck, Shuji Nakamura
  • Patent number: 8421054
    Abstract: A light-emitting diode element includes: an n-type conductive layer 2 being made of a gallium nitride-based compound, a principal surface being an m-plane; a semiconductor multilayer structure 21 provided on a first region 2a of the principal surface of the n-type conductive layer 2, the semiconductor multilayer structure 21 including a p-type conductive layer 4 and an active layer 3; a p-electrode 5 provided on the p-type conductive layer 4; a conductor portion 9 provided on a second region 2b of the principal surface of the n-type conductive layer 2, the conductor portion 9 being in contact with an inner wall of a through hole 8; and an n-type front surface electrode 6 provided on the second region 2b of the principal surface of the n-type conductive layer 2, the n-type front surface electrode 6 being in contact with the conductor portion 9.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: April 16, 2013
    Assignee: Panasonic Corporation
    Inventors: Junko Iwanaga, Toshiya Yokogawa, Atsushi Yamada
  • Patent number: 8405128
    Abstract: A method for enhancing growth of device-quality planar semipolar nitride semiconductor thin films via metalorganic chemical vapor deposition (MOCVD) by using an (Al, In, Ga)N nucleation layer containing at least some indium. Specifically, the method comprises loading a substrate into a reactor, heating the substrate under a flow of nitrogen and/or hydrogen and/or ammonia, depositing an InxGa1-xN nucleation layer on the heated substrate, depositing a semipolar nitride semiconductor thin film on the InxGa1-xN nucleation layer, and cooling the substrate under a nitrogen overpressure.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: March 26, 2013
    Assignee: The Regents of the University of California
    Inventors: Hitoshi Sato, John F. Kaeding, Michael Iza, Benjamin A. Haskell, Troy J. Baker, Steven P. DenBaars, Shuji Nakamura
  • Patent number: 8344354
    Abstract: A spin-polarized electron generating device includes a substrate, a buffer layer, a strained superlattice layer formed on the buffer layer, and an intermediate layer formed of a crystal having a lattice constant greater than a lattice constant of a crystal of the buffer layer, the intermediate layer intervening between the substrate and the buffer layer. The buffer layer includes cracks formed in a direction perpendicular to the substrate by tensile strain.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: January 1, 2013
    Assignee: National University Corporation Nagoya University
    Inventors: Toru Ujihara, Xiuguang Jin, Yoshikazu Takeda, Tsutomu Nakanishi, Naoto Yamamoto, Takashi Saka, Toshihiro Kato
  • Patent number: 8258497
    Abstract: A method for manufacturing an electronic-photonic device. Epitaxially depositing an n-doped III-V composite semiconductor alloy buffer layer on a crystalline surface of a substrate at a first temperature. Forming an active layer on the n-doped III-V epitaxial composite semiconductor alloy buffer layer at a second temperature, the active layer including a plurality of spheroid-shaped quantum dots. Depositing a p-doped III-V composite semiconductor alloy capping layer on the active layer at a third temperature. The second temperature is less than the first temperature and the third temperature. The active layer has a photoluminescence intensity emission peak in the telecommunication C-band.
    Type: Grant
    Filed: October 18, 2010
    Date of Patent: September 4, 2012
    Assignee: Alcatel Lucent
    Inventors: Nick Sauer, Nils Weimann, Liming Zhang
  • Patent number: 8242480
    Abstract: A light emitting device is provided that includes at least one first semiconductor material layers and at least one second semiconductor material layers. At least one near-direct band gap material layers are positioned between the at least one first semiconductor layers and the at least one second semiconductor material layers. The at least one first semiconductor layers and the at least one second material layers have a larger band gap than the at least one near-direct band gap material layers. The at least one near-direct band gap material layers have an energy difference between the direct and indirect band gaps of less than 0.5 eV.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: August 14, 2012
    Assignee: Massachusetts Institute of Technology
    Inventors: Lionel C. Kimerling, Jifeng Liu, Jurgen Michel
  • Patent number: 8222745
    Abstract: An electronic device includes a heat dissipating component located over a substrate. An isolation trench is formed in the substrate adjacent the component. A contact region of the substrate is bounded by the trench. An electrically isolated contact is located over and in contact with the contact region. The electrically isolated contact and the contact region provide a thermally conductive path to the substrate.
    Type: Grant
    Filed: January 19, 2010
    Date of Patent: July 17, 2012
    Assignee: LSI Corporation
    Inventors: Sangjune Park, Carl Iwashita
  • Patent number: 8222057
    Abstract: Disclosed herein is an article comprising a substrate; an interlayer comprising aluminum nitride, gallium nitride, boron nitride, indium nitride or a solid solution of aluminum nitride, gallium nitride, boron nitride and/or indium nitride; the interlayer being directly disposed upon the substrate and in contact with the substrate; where the interlayer comprises a columnar film and/or nanorods and/or nanotubes; and a group-III nitride layer disposed upon the interlayer; where the group-III nitride layer completely covers a surface of the interlayer that is opposed to a surface in contact with the substrate; the group-III nitride layer being free from cracks.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: July 17, 2012
    Assignee: University of Florida Research Foundation, Inc.
    Inventors: Olga Kryliouk, Timothy J. Anderson