Abstract: A method for emitting electrons includes the steps of applying a voltage to an electron source to cause hot electrons to be generated with the source, and applying an electric field to cause at least a portion of the hot electrons to be emitted from the electron source.

Abstract: Ultraviolet light incident from the side of a surface layer 5 passes through the surface layer 5 to reach an optical absorption layer 4. Light which reaches the optical absorption layer 4 is absorbed within the optical absorption layer 4, and photoelectrons are generated within the optical absorption layer 4. Photoelectrons diffuse within the optical absorption layer 4, and reach the interface between the optical absorption layer 4 and the surface layer 5. Because the energy band is curved in the vicinity of the interface between the optical absorption layer 4 and surface layer 5, the energy of the photoelectrons is larger than the electron affinity in the surface layer 5, and so photoelectrons are easily ejected to the outside. Here, the optical absorption layer 4 is formed from an Al0.3Ga0.

Abstract: A photocathode includes a first layer having a first energy band gap for providing absorption of light of wavelengths shorter than or equal to a first wavelength, a second layer having a second energy band gap for providing transmission of light of wavelengths longer than the first wavelength, and a third layer having a third energy band gap for providing absorption of light of wavelengths between the first wavelength and a second wavelength. The first wavelength is shorter than the second wavelength. The first, second and third layers are positioned in sequence between input and output sides of the photocathode.

Abstract: A boron phosphide-based semiconductor device includes a single crystal substrate having formed thereon a boron-phosphide (BP)-based semiconductor layer containing boron and phosphorus as constituent elements, where phosphorus (P) occupying the vacant lattice point (vacancy) of boron (B) and boron occupying the vacant lattice point (vacancy) of phosphorus are present in the boron-phosphide (BP)-based semiconductor layer. The boron phosphide-based semiconductor device includes a p-type boron phosphide-based semiconductor layer in which boron occupying the vacancy of phosphorus is contained in a higher atomic concentration than phosphorus occupying the vacancy of boron and a p-type impurity of Group II element or Group IV element is added.

Abstract: A gallium nitride-based multilayered reflective membrane with an excellent crystallinity while keeping a high reflectivity and a gallium nitride-based light emitting element using such a multilayered reflective are provided. The multilayered reflective membrane includes an AlaGa1−aN layer (0<a<1) having a thickness of (&agr;1·&lgr;)/(4n1) (&lgr;: incident light wavelength, n1: a reflectivity) and a GaN layer having a thickness of (&agr;2·&lgr;)/(4n2) (n2: a reflectivity) which are deposited alternately and satisfy the relationship of 0<&agr;1<1 and &agr;1+&agr;2=2.

Abstract: A method and structure for controlling the surface properties in the dielectric layers in a thin film component can be provided for improving the trimming process of thin film element. A metal fill is configured with a uniform fill pattern beneath an array of thin film resistors, and can comprise a plurality of smaller features or peaks providing a finer fill pattern that improves the control of the topology of the dielectric layers. The fill pattern can be configured in various manners, such as fill patterns parallel to the thin film resistor, fill patterns perpendicular to the thin film resistor, or fill patterns comprising a checkerboard-like configuration.

Abstract: A Group III-V compound semiconductor epitaxial layer has a tilt angle of at most 100 seconds and/or a tilt angle of at most 100 seconds. The layer is epitaxially grown by use of a mask, wherein the mask satisfies the equation (1): h≧(w/2)tan &thgr;  (1) where “&thgr;” is a base angle of a facet structure of the Group III-V compound semiconductor layer on the epitaxial growth; “h” is a thickness of the mask; and “w” is an opening width of the mask at its lower level, and the opening width is defined in a direction included in a plane which is vertical to both the surface of the base layer and the side face of the facet structure.

Abstract: A field emission display that is simple to manufacture in a large screen size and that provides improved display characteristics, includes first and second substrates provided opposing one another with a predetermined gap therebetween; a plurality of gate electrodes formed on a surface of the first substrate opposing the second substrate, the gate electrodes being formed in a striped pattern; an insulation layer formed on the first substrate covering the gate electrodes; a plurality of cathode electrodes formed on the insulation layer in a striped pattern to perpendicularly intersect the gate electrodes; a plurality of surface electron sources formed along one long edge of the cathode electrodes; focusing units provided on the cathode electrodes for controlling the emission of electron beams from the surface electron sources; an anode electrode formed on a surface of the second substrate opposing the first substrate; and a plurality of phosphor layers formed on the anode electrode.

Abstract: A GaAsP-base light emitting element capable of sustaining an excellent light emission property for a long period, and a method for manufacturing thereof are provided. The light emitting element 1 has a p-n junction interface responsible for light emission formed between a p-type GaAs1-aPa layer 9 and an n-type GaAs1-aPa layer 8, and has a nitrogen-doped zone 8c formed in a portion including the p-n junction interface between such p-type GaAs1-aPa layer 9 and n-type GaAs1-aPa layer 8. Such element can be manufactured by fabricating a plurality of light emitting elements by varying nitrogen concentration Y of the nitrogen-doped zone 8c while keeping a mixed crystal ratio a of the p-type GaAs1- aPa layer 9 and n-type GaAs1-aPa layer 8 constant; finding an emission luminance/nitrogen concentration relationship by measuring emission luminance of the individual light emitting elements; and adjusting the nitrogen concentration of the nitrogen-doped zone 8c so as to fall within a range from 1.05Yp to 1.

Abstract: An emitter has an electron supply layer and a tunneling layer formed on the electron supply layer. Optionally, an insulator layer is formed on the electron supply layer and has openings defined within which the tunneling layer is formed. A cathode layer is formed on the tunneling layer to provide a surface for energy emissions of electrons and/or photons. Preferably, the emitter is subjected to an annealing process thereby increasing the supply of electrons tunneled from the electron supply layer to the cathode layer.

Abstract: A lateral current blocking light emitting diode (LED) and a method of making the same are disclosed. The present invention features in that a trench is formed between the two electrodes via the technique of such as etching, wherein the depth of the trench reaches to at least the active layer, thereby blocking the lateral current between the two electrodes. With the use of the present invention, the possibility of the current passing through the active layer can be increased, thereby improving the brightness of the LED; and the chance of the photons emitted from the lateral of the trench can be raised wherein the photons are generated from the active layer, thereby increasing the output efficiency of the photons generated from the active layer.

Abstract: A light-emitting device includes a silicon substrate, a ZnOSSe layer provided on the silicon substrate that is lattice-matched to the silicon substrate, and a separate confinement heterostructure light-emitting layer that is provided on the ZnOSSe layer and includes an active layer and upper and lower clad layers.

Abstract: A field emission device, a field emission display for displaying images with good quality adopting the same, and a manufacturing method thereof are provided. The field emission device allows a mesh grid to closely contact the surface of a field emission array on a substrate and for this purpose, applies a tensile force to the mesh grid using a predetermined tension member.

Abstract: A semiconductor light-emitting device has a semiconductor layer containing Al between a substrate and an active layer containing nitrogen, wherein Al and oxygen are removed from a growth chamber before growing said active layer and a concentration of oxygen incorporated into said active layer together with Al is set to a level such that said semiconductor light-emitting device can perform a continuous laser oscillation at room temperature.

Abstract: A semiconductor light emitting device with improved luminous efficiency is provided. An underlying n-type GaN layer is grown on a sapphire substrate, and a growth mask made from SiO2 film or the like is formed on the underlying n-type GaN layer. An n-type GaN layer having a hexagonal pyramid shape is selectively grown on a portion, exposed from an opening of the growth mask, of the underlying n-type GaN layer. The growth mask is removed by etching, and then an active layer and a p-type GaN layer are sequentially grown on the entire substrate so as to cover the hexagonal pyramid shaped n-type GaN layer, to form a light emitting device. An n-side electrode and a p-side electrode are then formed.

Abstract: An emitter has an electron supply layer and a silicon-based dielectric layer formed on the electron supply layer. The silicon-based dielectric layer is preferably less than about 500 Angstroms. Optionally, an insulator layer is formed on the electron supply layer and has openings defined within which the silicon-based dielectric layer is formed. A cathode layer is formed on the silicon-based dielectric layer to provide a surface for energy emissions of electrons and/or photons. Preferably, the emitter is subjected to an annealing process thereby increasing the supply of electrons tunneled from the electron supply layer to the cathode layer.

Abstract: There is provided a field emitter device formed over a semiconductor substrate. The field emitter device includes at least one field emitter tip disposed over the substrate, and a conducting gate electrode layer disposed over the substrate. The field emitter device also includes a protective electronic component disposed over and integral to the substrate and electrically connecting the conducting gate electrode layer to the substrate such that if the conducting gate electrode layer experiences a voltage greater than a breakdown voltage of the field emitter device, the protective electronic component conducts current between the conducting gate electrode layer and the substrate.

Abstract: The group III-V semiconductor device comprises a quantum well layer, barrier layers sandwiching the quantum well layer and a region of a third semiconductor material formed by spatially-selective intermixing of atoms on the group V sublattice between the first semiconductor material of the quantum well layer and the second semiconductor material of the barrier layer. The quantum well layer is a layer of a first semiconductor material that has a band gap energy and a refractive index. The barrier layers are layers of a second semiconductor material that has a higher band gap energy and a lower refractive index than the first semiconductor material. The third semiconductor material has a band gap energy and a refractive index intermediate between the band gap energy and the refractive index, respectively, of the first semiconductor material and the second semiconductor material.

Abstract: There is provided a MQB layer as a multi-quantum barrier portion composed of well layers and barrier layers that are formed of extremely thin films having different compositions and alternately stacked. This enhances an effective barrier height by using the phenomenon that holes likely to flow from a SiGe base layer to a Si emitter layer are reflected by the MQB layer and thereby suppresses the reverse injection of the holes from the SiGe base layer into the Si emitter layer. As a result, the reverse injection of carriers is suppressed by the MQB layer even when the base doping concentration is increased, which provides a satisfactory current amplification factor and increases a maximum oscillation frequency. What results is a bipolar transistor having excellent RF characteristics such as current amplification factor, current gain cutoff frequency, and maximum oscillation frequency in a microwave band or the like.

Abstract: A lateral current blocking light emitting diode (LED) and a method of making the same are disclosed. The present invention features in that a trench is formed between the two electrodes via the technique of such as etching, wherein the depth of the trench reaches to at least the active layer, thereby blocking the lateral current between the two electrodes. With the use of the present invention, the possibility of the current passing through the active layer can be increased, thereby improving the brightness of the LED; and the chance of the photons emitted from the lateral of the trench can be raised wherein the photons are generated from the active layer, thereby increasing the output efficiency of the photons generated from the active layer.

Abstract: A semiconductor photocathode comprises a p+-type semiconductor substrate of GaSb, and a p−-type light absorbing layer of InAsSb. A p+-type hole blocking layer is formed between the substrate and the light absorbing layer having wider energy band gap than that of the light absorbing layer, the blocking layer being made of AlGaSb.

Abstract: A semiconductor device (100) has, as its well layer, a III-V compound semiconductor layer (106) containing, as V-group components, nitrogen, antimony, and one or more V-group elements other than nitrogen and antimony to improve emission characteristics. Such a III-V compound semiconductor layer is formed by repeating a cycle including a process of simultaneously supplying a plurality of sources containing at lest indium, and a process of simultaneously supplying a plurality of sources not containing indium but containing antimony.

Abstract: An improved MISFET is disclosed which is particularly suited as a replacement for conventional pull-up and load elements such as NDR diodes, passive resistors, and conventional FETs. The MISFET includes a charge trapping layer formed at or extremely near to an interface between a substrate (which can be silicon or SOI) and a gate insulation layer. In this fashion, charge traps can be optimized for extremely rapid trapping and de-trapping of charge because they are extremely close to a channel of hot carriers. The MISFET channel can be shut off during static operations to further reduce power dissipation, and can also be adapted to operate with negative differential resistance.

Abstract: In accordance with the invention, there is provided a device having a first portion with at least one quantum well, where the first portion emits light, a spacer layer, and a second portion with an amplifying region with at least one quantum well, where the device is configured so that the spacer layer transmits the light beam emitted by the first portion and the amplifying region increases the intensity of the light beam. In accordance with another aspect of the invention, there is provided a method of manufacturing a vertical cavity surface emitting laser having the steps of, forming a first portion, having at least one quantum well, that emits light, forming a spacer layer made of a material that is transmissive of light emitted from the first portion, forming a second portion having at least one quantum well, where the second portion is positioned over the spacer layer and the spacer layer is positioned over the first portion.

Abstract: The present invention provides a varactor diode for frequency multipliers at submillimeter wave frequencies and above. Functionally the new diode replaces the conventional heterostructure barrier varactor diode. Two important features of the antimony-based quantum well heterostructure barrier varactor are; first: an aluminum antimnide/aluminum-arsenic-antimnide heterostructure barrier and second: a bandgap-engineered, triangular quantum well cathode and anode.

Abstract: The monolithically integrated Enhancement/Depletion mode HEMT (high-electron-mobility transistor) of the present invention comprises: a buffer layer, a channel layer, a spacer layer, a first barrier layer, a second barrier layer, a third barrier layer, and an ohmic layer consecutively formed on a semiconductor substrate from bottom to top; the first exposed region (a gate region for a Depletion-mode HEMT) formed by selective etching of the ohmic layer to expose the third barrier layer; a second exposed region (a gate region for an Enhancement-mode HEMT) formed by selective etchings of the ohmic layer and the third barrier layer to expose the second barrier layer; and gate electrodes formed on the first and second exposed gate regions. According to the present invention, a monolithically integrated Enhancement/Depletion mode HEMT having a uniform threshold voltage can easily be fabricated.

Abstract: A group III nitride film is formed on an epitaxial substrate having an underlayer film containing Al. According to the present invention, the change of the properties of the II nitride film may be reduced The properties of the semiconductor device may be thus reduced and the production yield may be improved. An underlayer 2 made of a group III nitride containing at least Al is formed on a substrate 1 made of a single crystal. An oxide film 3 is formed on the underlayer film 2 to produce an epitaxial substrate 10. The oxygen content of the oxide film 3 at the surface is not lower than 3 atomic percent and the thickness is not larger than 50 angstrom.

Abstract: A field emission display device (1) includes a cathode plate (20), a resistive buffer (30) in contact with the cathode plate, a plurality of electron emitters (40) formed on the buffer, and an anode plate (50) spaced from the electron emitters. Each electron emitter includes a rod-shaped first part (401) and a conical second part (402). The buffer and first parts are made from silicon oxide. The combined buffer and first parts has a gradient distribution of electrical resistivity such that highest electrical resistivity is nearest the cathode plate and lowest electrical resistivity is nearest the anode plate. The second parts are made from niobium. When emitting voltage is applied between the cathode and anode plates, electrons emitted from the electron emitters traverse an interspace region and are received by the anode plate. Because of the gradient distribution of electrical resistivity, only a very low emitting voltage is needed.

Abstract: A semiconductor structure for providing an epitaxial zinc oxide layer having p-type conduction for semiconductor device manufacture and methods of depositing the p-type zinc oxide layer. A zinc oxide layer is deposited epitaxially by molecular beam epitaxy on a crystalline zinc oxide substrate. The zinc oxide layer incorporates a p-type dopant, such as nitrogen, in an atomic concentration adequate to provide p-type conduction. The p-type zinc oxide layer may further incorporate an atomic concentration of a compensating species, such as lithium, sufficient to electronically occupy excess donors therein so that the efficiency of the p-type dopant may be increased.

Abstract: The method for producing a semiconductor of the present invention grows a compound semiconductor on a substrate held by a susceptor provided, in a reaction chamber in accordance with a metalorganic vapor phase epitaxy technique. The method includes the steps of: supplying a Group III source gas containing indium and a Group V source gas containing nitrogen into the reaction chamber; and mixing the Group III and Group V source gases, supplied into the reaction chamber, with each other, and supplying a rare gas as a carrier gas into the reaction chamber so as to carry the mixed source gas onto the upper surface of the substrate.

Abstract: The method for fabricating a nitride semiconductor of the present invention includes the steps of: (1) growing a first semiconductor layer made of a first group III nitride over a substrate by supplying a first group III source and a group V source containing nitrogen; and (2) growing a second semiconductor layer made of a second group III nitride on the first semiconductor layer by supplying a second group III source and a group V source containing nitrogen. At least one of the steps (1) and (2) includes the step of supplying a p-type dopant over the substrate, and an area near the interface between the first semiconductor layer and the second semiconductor layer is grown so that the density of the p-type dopant locally increases.

Abstract: A cold electron emitter may include a heavily n+ doped wide band gap (WBG) substrate, a p-doped WBG region, and a low work function metallic layer (n+-p-M structure). A modification of this structure includes heavily p+ doped region between p region and M metallic layer (n+-p-p+-M structure). These structures make it possible to combine high current emission with stable (durable) operation. The high current density is possible because the p-doped (or p+ heavily doped) WBG region acts as a negative electron affinity material when in contact with low work function metals. The injection emitters with the n+-p-M and n+-p-p+-M structures are stable since the emitters make use of relatively low extracting electric field and are not affected by contamination and/or absorption from accelerated ions. In addition, the structures may be fabricated with current state-of-the-art technology.

Abstract: The invention concerns a light emitting and guiding device comprising at least one active region (22) in silicon and the means for creating photons in the said active region. In accordance with the invention, the means for creating the photons comprise a diode (22c, 22d) formed in the active region. In addition, the device includes the means for confining the carriers injected by the diode, and the silicon in the active region is mono-crystalline.

Abstract: An improved negative differential resistance field effect transistor (NDR-FET) is disclosed. The NDR FET includes a charge trapping layer formed at or extremely near to an interface between a substrate (which can be silicon or SOI) and a gate insulation layer. In this fashion, charge traps can be optimized for extremely rapid trapping and de-trapping of charge because they are extremely close to a channel of hot carriers. The NDR-FET is also useable as a replacement for conventional NDR diode and similar devices in memory cells, and enables an entire family of logic circuits that only require a single channel technology (i.e., instead of CMOS) and yet which provide low power.

Abstract: An emitter has an electron supply layer and a tunneling layer formed on the electron supply layer. Optionally, an insulator layer is formed on the electron supply layer and has openings defined within in which the tunneling layer is formed. A cathode layer is formed on the tunneling layer. A conductive layer is partially disposed on the cathode layer and partially on the insulator layer if present. The conductive layer defines an opening to provide a surface for energy emissions of electrons and/or photons. Preferably but optionally, the emitter is subjected to an annealing process thereby increasing the supply of electrons tunneled from the electron supply layer to the cathode layer.

Abstract: There are provided a semiconductor laser, a semiconductor light emitting device, and methods of manufacturing the same wherein a threshold current density in a short wavelength semiconductor laser using a nitride compound semiconductor can be reduced. An active layer is composed of a single gain layer having a thickness of more than 3 nm, and optical guiding layers are provided between the active layer and cladding layers respectively.

Abstract: Selenium (or tellurium or sulfur) is doped as an n-type dopant by homogeneous doping or planar doping in a compound semiconductor epitaxial wafer to form a selenium-doped layer. Thus, an epitaxial wafer having high carrier density can be prepared. The use of this epitaxial wafer can lower parasitic resistance and can provide HEMT having high gm. Further, the lowered resistance can significantly increase the freedom of device design.

Abstract: A semiconductor optical component is disclosed which includes a semiconductor material confinement layer containing acceptor dopants such that the doping is p-type doping. The confinement layer is deposited on another semiconductor layer and defines a plane parallel to the other semiconductor layer. Furthermore, the p-type doping concentration of the confinement layer has at least one gradient significantly different from zero in one direction in the plane. A method of fabricating the component is also disclosed.

Abstract: Field emission transistors where either N type or P type devices are made with an insulated gate isolated from both the emitter and the collector. Such devices have input voltage levels that match the output levels, and as such are fully cascadable and integrable. Emitter and collector functions are combined in combinations to make complimentary pairs, NAND gates and NOR gates.

Abstract: An electronic device includes a FET that is capable of operating in a negative differential resistance mode as well as in a conventional FET mode. The selection of the mode can be accomplished by providing a control signal to a body terminal of the FET as needed for a particular application. By providing two different operating modes a multi-function logic gate is effectuated that can perform two or more different logical functions on an input signal. Furthermore the device can be used as an element of a new logic family and synthesized into suitable configurations so that more sophisticated and complex functions are achieved with increased density, lower power, etc. over conventional semiconductor FETs.

Abstract: The performance of nitride based diodes is currently limited by the resistivity of the ohmic contacts to the p-type GaN. The large value of the contact resistance contributes to a large voltage for device operation. This in turn causes device heating, making cw operation difficult and limiting the device lifetime. A layer of GaP or GaNP alloy between the GaN and the metal contact layer serves to bridge the energetic barrier between the GaN valence band and the metal Fermi level, thus enhancing the hole injection and reducing the contact resistance.

Abstract: A light emitting diode is disclosed. The diode includes a silicon carbide substrate having a first conductivity type, a first gallium nitride layer above the SiC substrate having the same conductivity type as the substrate, a superlattice on the GaN layer formed of a plurality of repeating sets of alternating layers selected from among GaN, InGaN, and AlInGaN, a second GaN layer on the superlattice having the same conductivity type as the first GaN layer, a multiple quantum well on the second GaN layer, a third GaN layer on the multiple quantum well, a contact structure on the third GaN layer having the opposite conductivity type from the substrate and the first GaN layer, an ohmic contact to the SiC substrate, and an ohmic contact to the contact structure.

Abstract: A compound semiconductor device comprising: an semi-insulated InP substrate; a plurality of interconnections formed on the semi-insulated InP substrate; and an insulating film formed between the interconnections, the insulating film being a silicon oxide.

Abstract: A semiconductor optical device and a method for fabricating the same. The semiconductor optical device comprises a substrate, a semiconductor electrode layer of a first conductive type formed on the substrate and having a groove formed to a desired depth therein, a semiconductor layer of the first conductive type formed from side walls of the groove up to a part of the semiconductor electrode layer of the first conductive type on the periphery of the groove, a cladding layer of the first conductive type, an active layer of the first conductive type, a cladding layer of a second condcutive type and a semiconductor electrode layer of the second conductive type sequentially formed on the semiconductor layer of the first conductive type, and electrodes of the first and second conductive types formed respectively on the semiconductor electrode layers of the first and second conductive types.

Abstract: An insulating-gate semiconductor device has a first nitride semiconductor layer formed over a substrate and an insulating oxidation layer obtained by oxidizing a second nitride semiconductor layer formed on the first nitride semiconductor layer. A gate electrode is formed on the insulating oxidation layer.

Abstract: A quantic effect device which functions using a Coulomb blockade phenomenon. The device includes two electron reservoirs, two sets of islands that are separated by a dielectric layer, a protective insulating layer and a control electrode.

Abstract: An object of the present invention is to improve, in a group III nitride semiconductor device, the productivity, heat radiation characteristic and performance in the element high speed operation; upon a sapphire substrate in which an A plane (an (11-20) plane) is set to be the basal plane, an epitaxial growth layer of a group III nitride semiconductor is formed and, thereon, a gate electrode 16, a source electrode 15 and a drain electrode 17 are formed; these electrodes are disposed in such a way that a direction along which they are laid makes an angle within 20° with respect to a C axis of sapphire.

Abstract: A semiconductor device has a dielectric strength for a gate oxide film at a trench bottom that is higher than that of side walls used for channels. An n+ type substrate 1 having substrate plane orientation of (110) is prepared, and the side walls of a trench where channels are formed are in (100) planes. The other, non-channel forming, side walls of the trench are in (110) planes. Thus, the growth rate of the gate oxide film 7 in the non-channel forming side walls and the trench bottom is faster than that in the channel forming side walls. As a result, the film thickness at the non-channel-forming side walls and the trench bottom is greater than that of the channel-forming side walls. Accordingly, the device has high mobility, and there is no drop of dielectric strength due to partial reduction of the thickness of the gate oxide film 7. This achieves both a reduction of the ON resistance and an increase in the dielectric strength of the semiconductor device.

Abstract: A semiconductor device comprises a substrate having a first thermal expansion coefficient T1, a strain reducing layer formed on the substrate and having a second thermal expansion coefficient T2, and a semiconductor layer formed on the strain reducing layer, having a third thermal expansion coefficient T3, and made of a nitride compound represented by AlyGa1−y−zInzN (0≦y≦1, 0≦z ≦1). The second thermal expansion coefficient T2 is lower than the first thermal expansion coefficient T1. The third thermal expansion coefficient T3 is lower than the first thermal expansion coefficient T1 and higher than the second thermal expansion coefficient T2.

Abstract: A carrier transit layer made of group III-V compound semiconductor is formed on a semiconductor substrate. A carrier supply layer is formed on the carrier transit layer. The carrier supply layer supplies carriers for generating two-dimensional carrier gas in an interface between the carrier supply layer and carrier transit layer. The carrier supply layer is made of group III-V compound semiconductor which contains In as group III element. A gate electrode is disposed above a partial area of the carrier supply layer. An intermediate layer is disposed between the gate electrode and carrier supply layer. The intermediate layer is made of group III-V compound semiconductor not containing In as group III element. An ohmic electrode is disposed on both sides of the gate electrode.