Combined With A Heterojunction Involving A Iii-v Compound Patents (Class 257/11)
  • Patent number: 8421054
    Abstract: A light-emitting diode element includes: an n-type conductive layer 2 being made of a gallium nitride-based compound, a principal surface being an m-plane; a semiconductor multilayer structure 21 provided on a first region 2a of the principal surface of the n-type conductive layer 2, the semiconductor multilayer structure 21 including a p-type conductive layer 4 and an active layer 3; a p-electrode 5 provided on the p-type conductive layer 4; a conductor portion 9 provided on a second region 2b of the principal surface of the n-type conductive layer 2, the conductor portion 9 being in contact with an inner wall of a through hole 8; and an n-type front surface electrode 6 provided on the second region 2b of the principal surface of the n-type conductive layer 2, the n-type front surface electrode 6 being in contact with the conductor portion 9.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: April 16, 2013
    Assignee: Panasonic Corporation
    Inventors: Junko Iwanaga, Toshiya Yokogawa, Atsushi Yamada
  • Patent number: 8405128
    Abstract: A method for enhancing growth of device-quality planar semipolar nitride semiconductor thin films via metalorganic chemical vapor deposition (MOCVD) by using an (Al, In, Ga)N nucleation layer containing at least some indium. Specifically, the method comprises loading a substrate into a reactor, heating the substrate under a flow of nitrogen and/or hydrogen and/or ammonia, depositing an InxGa1-xN nucleation layer on the heated substrate, depositing a semipolar nitride semiconductor thin film on the InxGa1-xN nucleation layer, and cooling the substrate under a nitrogen overpressure.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: March 26, 2013
    Assignee: The Regents of the University of California
    Inventors: Hitoshi Sato, John F. Kaeding, Michael Iza, Benjamin A. Haskell, Troy J. Baker, Steven P. DenBaars, Shuji Nakamura
  • Patent number: 8344354
    Abstract: A spin-polarized electron generating device includes a substrate, a buffer layer, a strained superlattice layer formed on the buffer layer, and an intermediate layer formed of a crystal having a lattice constant greater than a lattice constant of a crystal of the buffer layer, the intermediate layer intervening between the substrate and the buffer layer. The buffer layer includes cracks formed in a direction perpendicular to the substrate by tensile strain.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: January 1, 2013
    Assignee: National University Corporation Nagoya University
    Inventors: Toru Ujihara, Xiuguang Jin, Yoshikazu Takeda, Tsutomu Nakanishi, Naoto Yamamoto, Takashi Saka, Toshihiro Kato
  • Patent number: 8258497
    Abstract: A method for manufacturing an electronic-photonic device. Epitaxially depositing an n-doped III-V composite semiconductor alloy buffer layer on a crystalline surface of a substrate at a first temperature. Forming an active layer on the n-doped III-V epitaxial composite semiconductor alloy buffer layer at a second temperature, the active layer including a plurality of spheroid-shaped quantum dots. Depositing a p-doped III-V composite semiconductor alloy capping layer on the active layer at a third temperature. The second temperature is less than the first temperature and the third temperature. The active layer has a photoluminescence intensity emission peak in the telecommunication C-band.
    Type: Grant
    Filed: October 18, 2010
    Date of Patent: September 4, 2012
    Assignee: Alcatel Lucent
    Inventors: Nick Sauer, Nils Weimann, Liming Zhang
  • Patent number: 8242480
    Abstract: A light emitting device is provided that includes at least one first semiconductor material layers and at least one second semiconductor material layers. At least one near-direct band gap material layers are positioned between the at least one first semiconductor layers and the at least one second semiconductor material layers. The at least one first semiconductor layers and the at least one second material layers have a larger band gap than the at least one near-direct band gap material layers. The at least one near-direct band gap material layers have an energy difference between the direct and indirect band gaps of less than 0.5 eV.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: August 14, 2012
    Assignee: Massachusetts Institute of Technology
    Inventors: Lionel C. Kimerling, Jifeng Liu, Jurgen Michel
  • Patent number: 8222057
    Abstract: Disclosed herein is an article comprising a substrate; an interlayer comprising aluminum nitride, gallium nitride, boron nitride, indium nitride or a solid solution of aluminum nitride, gallium nitride, boron nitride and/or indium nitride; the interlayer being directly disposed upon the substrate and in contact with the substrate; where the interlayer comprises a columnar film and/or nanorods and/or nanotubes; and a group-III nitride layer disposed upon the interlayer; where the group-III nitride layer completely covers a surface of the interlayer that is opposed to a surface in contact with the substrate; the group-III nitride layer being free from cracks.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: July 17, 2012
    Assignee: University of Florida Research Foundation, Inc.
    Inventors: Olga Kryliouk, Timothy J. Anderson
  • Patent number: 8222745
    Abstract: An electronic device includes a heat dissipating component located over a substrate. An isolation trench is formed in the substrate adjacent the component. A contact region of the substrate is bounded by the trench. An electrically isolated contact is located over and in contact with the contact region. The electrically isolated contact and the contact region provide a thermally conductive path to the substrate.
    Type: Grant
    Filed: January 19, 2010
    Date of Patent: July 17, 2012
    Assignee: LSI Corporation
    Inventors: Sangjune Park, Carl Iwashita
  • Patent number: 8213475
    Abstract: Provided is a group-III nitride semiconductor laser device with a laser cavity enabling a low threshold current, on a semipolar surface of a support base the c-axis of a hexagonal group-III nitride of which tilts toward the m-axis. In a laser structure 13, a first surface 13a is a surface opposite to a second surface 13b and first and second fractured faces 27, 29 extend each from an edge 13c of the first surface 13a to an edge 13d of the second surface 13b. A scribed mark SM1 extending from the edge 13c to the edge 13d is made, for example, at one end of the first fractured face 27, and the scribed mark SM1 or the like has a depressed shape extending from the edge 13c to the edge 13d. The fractured faces 27, 29 are not formed by dry etching and thus are different from the conventional cleaved facets such as c-planes, m-planes, or a-planes. It is feasible to use emission of a band transition enabling a low threshold current.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: July 3, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shimpei Takagi, Yusuke Yoshizumi, Koji Katayama, Masaki Ueno, Takatoshi Ikegami
  • Patent number: 8207556
    Abstract: A group III nitride semiconductor device having a gallium nitride based semiconductor film with an excellent surface morphology is provided. A group III nitride optical semiconductor device includes a group III nitride semiconductor supporting base, a GaN based semiconductor region, an active layer, and a GaN semiconductor region. The primary surface of the group III nitride semiconductor supporting base is not any polar plane, and forms a finite angle with a reference plane that is orthogonal to a reference axis extending in the direction of a c-axis of the group III nitride semiconductor. The GaN based semiconductor region, grown on the semipolar primary surface, includes a semiconductor layer of, for example, an n-type GaN based semiconductor doped with silicon. A GaN based semiconductor layer of an oxygen concentration of 5×1016 cm?3 or more provides an active layer, grown on the primary surface, with an excellent crystal quality.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: June 26, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takashi Kyono, Yusuke Yoshizumi, Yohei Enya, Katsushi Akita, Masaki Ueno, Takamichi Sumitomo, Takao Nakamura
  • Patent number: 8188456
    Abstract: A thermionic electron emitter/collector includes a substrate and a doped diamond electron emitter/collector layer on the substrate. The doped diamond electron emitter/collector layer has at least a first and a second doping concentration as a function of depth such that the first doping concentration is different from the second doping concentration.
    Type: Grant
    Filed: February 12, 2008
    Date of Patent: May 29, 2012
    Assignee: North Carolina State University
    Inventors: Robert J. Nemanich, Franz A. M. Koeck
  • Patent number: 8188458
    Abstract: A method for forming non-polar (Al,B,In,Ga)N quantum well and heterostructure materials and devices. Non-polar (11 20) a-plane GaN layers are grown on an r-plane (1 102) sapphire substrate using MOCVD. These non-polar (11 20) a-plane GaN layers comprise templates for producing non-polar (Al,B,In,Ga)N quantum well and heterostructure materials and devices.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: May 29, 2012
    Assignee: The Regents of the University of California
    Inventors: Michael D. Craven, Stacia Keller, Steven P. DenBaars, Tal Margalith, James S. Speck, Shuji Nakamura, Umesh K. Mishra
  • Patent number: 8168965
    Abstract: A semiconductor device includes at least one semiconductor layer, a metal layer in electrical contact with the semiconductor layer, and a carbon nanotube contact layer interposed between the metal layer and the semiconductor layer. The contact layer electrically couples the metal layer to the semiconductor layer and provides a semiconductor contact having low specific contact resistance. The contact layer can be substantially optically transparent layer in at least a portion of the visible light range.
    Type: Grant
    Filed: February 22, 2005
    Date of Patent: May 1, 2012
    Assignee: University of Florida Research Foundation, Inc.
    Inventors: Andrew Gabriel Rinzler, Stephen J. Pearton
  • Patent number: 8129710
    Abstract: A nanowire light emitting diode (LED) and method of emitting light employ a plasmonic mode. The nanowire LED includes a nanowire having a semiconductor junction, a shell layer coaxially surrounding the nanowire, and an insulating layer, which is plasmonically thin, isolating the shell layer from the nanowire. The shell layer supports a surface plasmon that couples to the semiconductor junction by an evanescent field. Light is generated in a vicinity of the semiconductor junction and the surface plasmon is coupled to the semiconductor junction during light generation. The coupling enhances one or both of an efficiency of light emission and a light emission rate of the LED. A method of making the nanowire LED includes forming the nanowire, providing the insulating layer on the surface of the nanowire, and forming the shell layer on the insulating layer in the vicinity of the semiconductor junction.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: March 6, 2012
    Inventors: Hans Cho, David Fattal, Nathaniel Quitoriano
  • Patent number: 8120139
    Abstract: Isolation of III-nitride devices may be performed with a dopant selective etch that provides a smooth profile with little crystal damage in comparison to previously used isolation techniques. The dopant selective etch may be an electro-chemical or photo-electro-chemical etch. The desired isolation area may be identified by changing the conductivity type of the semiconductor material to be etched. The etch process can remove a conductive layer to isolate a device atop the conductive layer. The etch process can be self stopping, where the process automatically terminates when the selectively doped semiconductor material is removed.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: February 21, 2012
    Assignee: International Rectifier Corporation
    Inventor: Paul Bridger
  • Patent number: 8084764
    Abstract: The present invention is a semiconductor light emitting device including an n-type semiconductor layer, an active layer, a first p-type semiconductor layer between the n-type semiconductor layer and the active layer, and a second p-type semiconductor layer on the opposite side of the first p-type semiconductor layer from the active layer. Further, the present invention is a nitride semiconductor light emitting device including an n-type nitride semiconductor layer, a nitride semiconductor active layer, a first p-type nitride semiconductor layer between the n-type nitride semiconductor layer and the nitride semiconductor active layer, and a second p-type nitride semiconductor layer on the opposite side of the first p-type nitride semiconductor layer from the nitride semiconductor active layer.
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: December 27, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Satoshi Komada
  • Patent number: 8030638
    Abstract: A compound semiconductor device is manufactured by using a polycrystalline SiC substrate, the compound semiconductor device having a buffer layer being formed on the substrate and having a high thermal conductivity of SiC and aligned orientations of crystal axes. The method for manufacturing the compound semiconductor device includes: forming a mask pattern on a polycrystalline SiC substrate, the mask pattern having an opening of a stripe shape defined by opposing parallel sides or a hexagonal shape having an apex angle of 120 degrees and exposing the surface of the polycrystalline SiC substrate in the opening; growing a nitride semiconductor buffer layer, starting growing on the polycrystalline SiC substrate exposed in the opening of the mask pattern, burying the mask pattern, and having a flat surface; and growing a GaN series compound semiconductor layer on the nitride semiconductor buffer layer.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: October 4, 2011
    Assignee: Fujitsu Limited
    Inventor: Toshihide Kikkawa
  • Patent number: 8017176
    Abstract: A method by which photocathodes(201), single crystal, amorphous, or otherwise ordered, can be surface modified to a robust state of lowered and in best cases negative, electron affinity has been discovered. Conventional methods employ the use of Cs(203) and an oxidizing agent(207), typically carried by diatomic oxygen or by more complex molecules, for example nitrogen trifluoride, to achieve a lowered electron affinity(404). In the improved activation method, a second alkali, other than Cs(205), is introduced onto the surface during the activation process, either by co-deposition, yo-yo, or sporadic or intermittent application. Best effect for GaAs photocathodes has been found through the use of Li(402) as the second alkali, though nearly the same effect can be found by employing Na(406).
    Type: Grant
    Filed: January 26, 2009
    Date of Patent: September 13, 2011
    Inventors: Gregory A. Mulhollan, John C. Bierman
  • Patent number: 7982208
    Abstract: A method for forming non-polar (Al,B,In,Ga)N quantum well and heterostructure materials and devices. Non-polar (11 20) a-plane GaN layers are grown on an r-plane (1 102) sapphire substrate using MOCVD. These non-polar (11 20) a-plane GaN layers comprise templates for producing non-polar (Al, B, In, Ga)N quantum well and heterostructure materials and devices.
    Type: Grant
    Filed: June 21, 2006
    Date of Patent: July 19, 2011
    Assignee: The Regents of the University of California
    Inventors: Michael D. Craven, Stacia Keller, Steven P. Denbaars, Tal Margalith, James Stephen Speck, Shuji Nakamura, Umesh K. Mishra
  • Patent number: 7973325
    Abstract: Provided are a reflective electrode and a compound semiconductor light emitting device having the reflective electrode, such as LED or LD is provided. The reflective electrode formed on a p-type compound semiconductor layer of a compound semiconductor light emitting device, comprising a first electrode layer formed one of a Ag and Ag-alloy and forms an ohmic contact with the p-type compound semiconductor layer, a third electrode layer formed of a material selected from the group consisting of Ni, Ni-alloy, Zn, Zn-alloy, Cu, Cu-alloy, Ru, Ir, and Rh on the first electrode layer, and a fourth electrode layer formed of a light reflective material on the third electrode layer.
    Type: Grant
    Filed: June 22, 2005
    Date of Patent: July 5, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mi-yang Kim, Joon-seop Kwak
  • Patent number: 7973303
    Abstract: A nitride semiconductor device includes n-type and p-type nitride semiconductor layers, an active layer, the active layer having a lamination of quantum barrier layers and quantum well layers, a thermal stress control layer disposed between the n-type nitride semiconductor layer and the active layer, and formed of a material having a smaller thermal expansion coefficient than the n-type and p-type nitride semiconductor layers, and a lattice stress control layer disposed between the thermal stress control layer and the active layer, and including a first layer and a second layer.
    Type: Grant
    Filed: October 15, 2009
    Date of Patent: July 5, 2011
    Assignee: Samsung Led Co., Ltd.
    Inventors: Tan Sakong, Youn Joon Sung, Jeong Wook Lee
  • Patent number: 7968864
    Abstract: A group-III nitride light-emitting device is provided. An active layer having a quantum well structure is grown on a basal plane of a gallium nitride based semiconductor region. The quantum well structure is formed in such a way as to have an emission peak wavelength of 410 nm or more. The thickness of a well layer is 4 nm or more, and 10 nm or less. The well layer is composed of InXGa1-XN (0.15?X<1, where X is a strained composition). The basal plane of the gallium nitride based semiconductor region is inclined at an inclination angle within the range of 15 degrees or more, and 85 degrees or less with reference to a {0001} plane or a {000-1} plane of a hexagonal system group III nitride. The basal plane in this range is a semipolar plane.
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: June 28, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Katsushi Akita, Hitoshi Kasai, Takashi Kyono, Kensaku Motoki
  • Patent number: 7968865
    Abstract: A heterostructure having a heterojunction comprising: a diamond layer; and a boron aluminum nitride (B(x)Al(1-x)N) layer disposed in contact with a surface of the diamond layer, where x is between 0 and 1.
    Type: Grant
    Filed: July 6, 2009
    Date of Patent: June 28, 2011
    Assignee: Raytheon Company
    Inventors: Jeffrey R. LaRoche, William E. Hoke, Steven D. Bernstein, Ralph Korenstein
  • Patent number: 7968909
    Abstract: Reconditioned donor substrates that include a remainder substrate from a donor substrate wherein the remainder substrate has a detachment surface where a transfer layer was detached and an opposite surface; and an additional layer deposited upon the opposite surface of the remainder substrate to increase its thickness and to form the reconditioned substrate. The reconditioned substrate is recycled as a donor substrate for fabricating compound material wafers and is typically made from gallium nitride donor substrates.
    Type: Grant
    Filed: November 4, 2010
    Date of Patent: June 28, 2011
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventor: Frederic Dupont
  • Patent number: 7943964
    Abstract: An AlxGayIn1-x-yN crystal substrate of the present invention has a main plane having an area of at least 10 cm2. The main plane has an outer region located within 5 mm from an outer periphery of the main plane, and an inner region corresponding to a region other than the outer region. The inner region has a total dislocation density of at least 1×102 cm?2 and at most 1×106 cm?2. It is thereby possible to provide an AlxGayIn1-x-yN crystal substrate having a large size and a suitable dislocation density for serving as a substrate for a semiconductor device, a semiconductor device including the AlxGayIn1-x-yN crystal substrate, and a method of manufacturing the same.
    Type: Grant
    Filed: October 16, 2006
    Date of Patent: May 17, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shinsuke Fujiwara, Tomoki Uemura, Takuji Okahisa, Koji Uematsu, Manabu Okui, Muneyuki Nishioka, Shin Hashimoto
  • Patent number: 7943924
    Abstract: Light emitting devices include a gallium nitride-based epitaxial structure that includes an active light emitting region and a gallium nitride-based outer layer, for example gallium nitride. A indium nitride-based layer, such as indium gallium nitride, is provided directly on the outer layer. A reflective metal layer or a transparent conductive oxide layer is provided directly on the indium gallium nitride layer opposite the outer layer. The indium gallium nitride layer forms a direct ohmic contact with the outer layer. An ohmic metal layer need not be used. Related fabrication methods are also disclosed.
    Type: Grant
    Filed: August 5, 2010
    Date of Patent: May 17, 2011
    Assignee: Cree, Inc.
    Inventors: Michael John Bergmann, Daniel Carleton Driscoll, David Todd Emerson
  • Patent number: 7935615
    Abstract: A self-supported III-V nitride semiconductor substrate having a substantially uniform carrier concentration distribution in a surface layer existing from a top surface to a depth of at least 10 ?m is produced by growing a III-V nitride semiconductor crystal while forming a plurality of projections on a crystal growth interface at the initial or intermediate stage of crystal growth; conducting the crystal growth until recesses between the projections are buried, so that the crystal growth interface becomes flat; and continuing the crystal growth to a thickness of 10 ?m or more while keeping the crystal growth interface flat.
    Type: Grant
    Filed: September 18, 2007
    Date of Patent: May 3, 2011
    Assignee: Hitachi Cable, Ltd.
    Inventor: Masatomo Shibata
  • Patent number: 7935955
    Abstract: An object of the present invention is to provide a Group III nitride semiconductor multilayer structure having a smooth surface and exhibiting excellent crystallinity, which multilayer structure employs a low-cost substrate that can be easily processed. Another object is to provide a Group III nitride semiconductor light-emitting device comprising the multilayer structure. The inventive Group III nitride semiconductor multilayer structure comprises a substrate; an AlxGa1-xN (0?x?1) buffer layer which is provided on the substrate and has a columnar or island-like crystal structure; and an AlxInyGa1-x-yN (0?x?1, 0?y?1, 0?x+y?1) single-crystal layer provided on the buffer layer, wherein the substrate has, on its surface, non-periodically distributed grooves having an average depth of 0.01 to 5 ?m.
    Type: Grant
    Filed: January 25, 2005
    Date of Patent: May 3, 2011
    Assignee: Showa Denko K.K.
    Inventor: Yasuhito Urashima
  • Publication number: 20110089397
    Abstract: To provide implement a spin-polarized electron generating device having high spin polarization and high external quantum efficiency while allowing a certain degree of freedom in selecting materials of a substrate, a buffer layer, and a strained superlattice layer. In a spin-polarized electron generating device having a substrate, a buffer layer, and a strained superlattice layer formed on the buffer layer, an intermediate layer formed of a crystal having a lattice constant greater than that of a crystal used to form the buffer layer intervenes between the substrate and the buffer layer. With this arrangement, tensile strain causes cracks to be formed in the buffer layer in a direction perpendicular to the substrate, whereby the buffer layer has mosaic-like appearance. As a result, glide dislocations in an oblique direction do not propagate to the strained superlattice layer to be grown on the buffer layer, thereby improving crystallinity of the strained superlattice layer.
    Type: Application
    Filed: March 24, 2009
    Publication date: April 21, 2011
    Inventors: Toru Ujihara, Xiuguang Jin, Yoshikazu Takeda, Tsutomu Nakanishi, Naoto Yamamoto, Takashi Saka, Toshihiro Kato
  • Patent number: 7915640
    Abstract: A metamorphic buffer layer is formed on a semi-insulating substrate by an epitaxial growth method, a collector layer, a base layer, an emitter layer and an emitter cap layer are sequentially laminated on the metamorphic buffer layer, and a collector electrode is provided in contact with an upper layer of the metamorphic buffer layer. The metamorphic buffer layer is doped with an impurity, in a concentration equivalent to or higher than that in a conventional sub-collector layer, by an impurity doping process during crystal growth so that the metamorphic buffer layer will be able to play the role of guiding the collector current to the collector electrode. Since the sub-collector layer, which is often formed of a ternary mixed crystal or the like having a high thermal resistance, can be omitted, the heat generated in the semiconductor device can be rapidly released into the substrate.
    Type: Grant
    Filed: May 19, 2006
    Date of Patent: March 29, 2011
    Assignee: Sony Corporation
    Inventor: Masaya Uemura
  • Patent number: 7902737
    Abstract: A light emission device and a display having the light emission device are provided. The light emission device includes first and second substrates arranged opposite to each other, an electron emission unit provided on the first substrate, a light emission unit provided on the second substrate, and spacers that are supportably disposed between the first and second substrates. The spacers are formed in a pillar configuration and each side of the spacers is arranged at an acute angle with respect to an edge of driving electrodes of the electron emission unit.
    Type: Grant
    Filed: May 2, 2008
    Date of Patent: March 8, 2011
    Assignee: Samsung SDI Co., Ltd.
    Inventor: Byong-Gon Lee
  • Patent number: 7902561
    Abstract: The present invention relates to a nitride semiconductor light emitting device including: a first nitride semiconductor layer having a super lattice structure of AlGaN/n-GaN or AlGaN/GaN/n-GaN; an active layer formed on the first nitride semiconductor layer to emit light; a second nitride semiconductor layer formed on the active layer; and a third nitride semiconductor layer formed on the second nitride semiconductor layer. According to the present invention, the crystallinity of the active layer is enhanced, and optical power and reliability are also enhanced.
    Type: Grant
    Filed: December 5, 2005
    Date of Patent: March 8, 2011
    Assignee: LG Innotek Co., Ltd.
    Inventor: Suk Hun Lee
  • Patent number: 7812427
    Abstract: A semiconductor component includes a semiconductor body and a second semiconductor zone of a first conductivity type that serves as a rear side emitter. The second semiconductor zone is preceded by a plurality of third semiconductor zones of a second conductivity type that is opposite to the first conductivity type. The third semiconductor zones are spaced apart from one another in a lateral direction. In addition, provided within the semiconductor body is a field stop zone spaced apart from the second semiconductor zone, thereby reducing an electric field in the direction toward the second semiconductor zone.
    Type: Grant
    Filed: June 4, 2007
    Date of Patent: October 12, 2010
    Assignee: Infineon Technologies AG
    Inventors: Anton Mauder, Hans-Peter Felsl, Manfred Pfaffenlehner, Hans-Joachim Schulze
  • Publication number: 20100252805
    Abstract: A method of preparing nanorod arrays using ion beam implantation is described that includes defining a pattern on a substrate and then implanting ions into the substrate using ion beam implantation. Next, a thin film is deposited on the substrate. During film growth, nanotrenches form and catalyze the formation of nanorods through capillary condensation. The resulting nanorods are aligned with the supporting matrix and are free from lattice and thermal strain effect. The density, size, and aspect ratios of the nanorods can be varied by changing the ion beam implantation and thin film growth conditions resulting in control of emission efficiency.
    Type: Application
    Filed: June 29, 2006
    Publication date: October 7, 2010
    Applicant: UNIVERSITY OF HOUSTON
    Inventors: Wei-Kan Chu, Hye-Won Seo, Quark Y. Chen, Li-Wei Tu, Ching-Lien Hsaio, Xuemei Wang, Yen-Jie Tu
  • Patent number: 7800097
    Abstract: A semiconductor device includes a semiconductor substrate of n-type silicon including, in an upper portion thereof, a first polarity inversion region and a second polarity inversion regions spaced from each other and doped with a p-type impurity. A first HFET including a first active layer and a second HFET including a second active layer both made of a group III-V nitride semiconductor are independently formed on the respective polarity inversion regions in the semiconductor substrate, and the HFETs are electrically connected to each other through interconnects.
    Type: Grant
    Filed: December 13, 2005
    Date of Patent: September 21, 2010
    Assignee: Panasonic Corporation
    Inventors: Yutaka Hirose, Tsuyoshi Tanaka
  • Patent number: 7795608
    Abstract: When to-be-detected light is made incident from a support substrate 2 side of a photocathode E1, a light absorbing layer 3 absorbs this to-be-detected light and produces photoelectrons. However, depending on the thickness and the like of the light absorbing layer 3, the to-be-detected light can be transmitted through the light absorbing layer 3 without being sufficiently absorbed by the light absorbing layer 3. The to-be-detected light transmitted through the light absorbing layer 3 reaches an electron emitting layer 4. A part of the to-be-detected light that has reached the electron emitting layer 4 proceeds toward a through-hole 5a of a contact layer 5. Since the length d1 of a diagonal line of the through-hole 5a is shorter than the wavelength of the to-be-detected light, the to-be-detected light can be suppressed from passing through the through-hole 5a and being emitted to the exterior.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: September 14, 2010
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Toru Hirohata, Minoru Niigaki
  • Patent number: 7781777
    Abstract: A pn junction type Group III nitride semiconductor light-emitting device 10 (11) of the present invention has a light-emitting layer 2 of multiple quantum well structure in which well layers 22 and barrier layers 21 including Group III nitride semiconductors are alternately stacked periodically between an n-type clad layer 105 and a p-type clad layer 107 which are formed on a crystal substrate and which include Group III nitride semiconductors, in which one end layer 21m of the light-emitting layer 2 is closest to and opposed to the n-type clad layer, and the other end layer 21n of the light-emitting layer 2 is closest to and opposed to the p-type clad layer, both the one and the other end layers are barrier layers, and the other end layer 21n is thicker than the barrier layer of the one end layer.
    Type: Grant
    Filed: March 8, 2005
    Date of Patent: August 24, 2010
    Assignee: Showa Denko K.K.
    Inventors: Takaki Yasuda, Hideki Tomozawa
  • Patent number: 7741654
    Abstract: The present invention provides a semiconductor laser excellent in the current injection efficiency. In an inner stripe type semiconductor laser according to the present invention, a p type cladding layer 309 has a superlattice structure composed of GaN layers and Al0.1Ga0.9N layers, which are alternately layered on each other. The p type cladding layer 309 has a portion of high dislocation density and a portion of low dislocation density. That is, the dislocation density is relatively low in a region directly above an opening of the current-confining region 308, whereas the dislocation density is relatively high in a region directly above a current-confining region 308.
    Type: Grant
    Filed: September 15, 2005
    Date of Patent: June 22, 2010
    Assignee: NEC Corporation
    Inventors: Kazuhisa Fukuda, Chiaki Sasaoka, Akitaka Kimura
  • Patent number: 7737429
    Abstract: Disclosed are a nitride based semiconductor device, including a high-quality GaN layer formed on a silicon substrate, and a process for preparing the same. A nitride based semiconductor device in accordance with the present invention comprises a plurality of nanorods aligned and formed on the silicone substrate in the vertical direction; an amorphous matrix layer filling spaces between nanorods so as to protrude some upper portion of the nanorods; and a GaN layer formed on the matrix layer.
    Type: Grant
    Filed: August 16, 2005
    Date of Patent: June 15, 2010
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Min Ho Kim, Masayoshi Koike, Kyeong Ik Min, Seong Suk Lee, Sung Hwan Jang
  • Patent number: 7714316
    Abstract: Disclosed is an acid etching resistance material comprising a compound having a repeating unit represented by the following general formula (1): (in the general formula (1), R1 is a hydrogen atom or methyl group; R3 is a cyclic group selected from an alicyclic group and an aromatic group; R4 is a polar group; R2 is a group represented by the following general formula (2); and j is 0 or 1): (in the general formula (2), R5 is a hydrogen atom or methyl group).
    Type: Grant
    Filed: May 13, 2008
    Date of Patent: May 11, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Asakawa, Kenichi Ohashi, Akira Fujimoto, Takashi Sasaki
  • Patent number: 7667278
    Abstract: A semiconductor device such as a complementary metal oxide semiconductor (CMOS) including at least one FET that includes a gate electrode including a metal carbide and method of fabrication are provided. The CMOS comprises dual work function metal gate electrodes whereby the dual work functions are provided by a metal and a carbide of a metal.
    Type: Grant
    Filed: March 10, 2006
    Date of Patent: February 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., Christophe Detavernier, Rajarao Jammy, Katherine L. Saenger
  • Patent number: 7649173
    Abstract: A method for preparing TEM sample, comprising the following steps: providing a sample with two pits and a failure region between the two pits, the failure region comprising a semiconductor device; milling the first surface of the failure region, till the cross section of the semiconductor device is exposed; etching the first surface of the failure region; cleaning the sample; milling the second surface of the failure region, till the failure region can be passed by electron beam. A sample can be prepared for a high resolution TEM through above steps. When the sample is observed, it is easy to distinguish the lightly doped drain, source/drain regions from the silicon substrate and observe the pattern and defects in the lightly doped drain, source/drain regions clearly; in addition, it is easy to distinguish the BPSG from the non-doped silicon dioxide in the failure region.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: January 19, 2010
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Jianqiang Hu, Zhixian Rui, Yanli Zhao, Yanjun Wang, Ming Li, Min Pan
  • Publication number: 20090273281
    Abstract: The photocathode of the present invention is provided with a supporting substrate composed of a single-crystal compound semiconductor, a light absorbing layer which is formed on the supporting substrate and smaller in an energy band gap than the supporting substrate to absorb incident light transmitted through the supporting substrate, thereby generating photoelectrons, and a surface layer which is formed on the light absorbing layer to lower a work function of the light absorbing layer, in which the supporting substrate comprises Al(1?x)GaxN (0?X<1) and the light absorbing layer comprises a compound semiconductor composed of at least one material selected from the group consisting of Al, Ga and In, and N.
    Type: Application
    Filed: April 30, 2009
    Publication date: November 5, 2009
    Applicant: HAMAMATSU PHOTONICS K.K.
    Inventors: Minoru Niigaki, Toru Hirohata, Harumasa Yoshida, Hirofumi Kan
  • Patent number: 7595498
    Abstract: The present invention provides an electromagnetic wave generation apparatus that is compact and generates a high power terahertz wave. An electromagnetic wave generation apparatus includes: a substrate; a first electrode, having a photoelectron emitting part, formed on one of the surfaces of the substrate; a second electrode formed on the surface of the substrate; a power supply source that applies voltage to between the first electrode and the second electrode so that the potential of the second electrode becomes higher than the potential of the first electrode; and a light source that radiates one of time modulated light and wavelength modulated light, and in the apparatus, the photoelectron emitting part (a) emits electrons when light is irradiated and (b) is placed at a position which an incident light from the light source enters and from which the emitted electrons run to the electron incidence plane of the second electrode.
    Type: Grant
    Filed: August 3, 2005
    Date of Patent: September 29, 2009
    Assignee: Panasonic Corporation
    Inventors: Shinichi Takigawa, Daisuke Ueda
  • Patent number: 7576351
    Abstract: A nitride semiconductor light generating device comprises an n-type gallium nitride based semiconductor layer, a quantum well active layer including an InX1AlY1Ga1-X1-Y1N (1>X1>0, 1>Y1>0) well layer and an InX2AlY2Ga1-X2-Y2N (1>X2>0, 1>Y2>0) barrier layer, an InX3AlY3Ga1-X3-Y3N (1>X3>0, 1>Y3>0) layer provided between the quantum well active layer and the n-type gallium nitride based semiconductor layer, and a p-type AlGaN layer having a bandgap energy greater than that of the InX2AlY2Ga1-X2-Y2N barrier layer. The indium composition X3 is greater than an indium composition X1. The indium composition X3 is greater than an indium composition X2. The aluminum composition Y2 is smaller than an aluminum composition Y3. The aluminum composition Y1 is smaller than an aluminum composition Y3. The oxygen concentration of the quantum well active layer is lower than that of the InX3AlY3Ga1-X3-Y3N layer.
    Type: Grant
    Filed: January 26, 2007
    Date of Patent: August 18, 2009
    Assignees: Sumitomo Electric Industries, Ltd., Riken
    Inventors: Takashi Kyono, Hideki Hirayama
  • Patent number: 7547908
    Abstract: In a III-nitride light emitting device, the device layers including the light emitting layer are grown over a template designed to reduce strain in the device, in particular in the light emitting layer. Reducing the strain in the light emitting device may improve the performance of the device. The template may expand the lattice constant in the light emitting layer over the range of lattice constants available from conventional growth templates. Strain is defined as follows: a given layer has a bulk lattice constant abulk corresponding to a lattice constant of a free standing material of a same composition as that layer and an in-plane lattice constant ain-plane corresponding to a lattice constant of that layer as grown in the structure. The amount of strain in a layer is |(ain-plane?abulk)|/abulk. In some embodiments, the strain in the light emitting layer is less than 1%.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: June 16, 2009
    Assignee: Philips Lumilieds Lighting Co, LLC
    Inventors: Patrick N. Grillot, Nathan F. Gardner, Werner K. Goetz, Linda T. Romano
  • Patent number: 7531826
    Abstract: A novel photocathode employing a rectifying junction is described that permits color imaging extending applications for photocathodes in a variety of instruments and night vision devices.
    Type: Grant
    Filed: June 1, 2005
    Date of Patent: May 12, 2009
    Assignee: Intevac, Inc.
    Inventors: Kenneth A Costello, Verle W. Aebi
  • Patent number: 7525131
    Abstract: Disclosed is a photoelectric surface including: a first group III nitride semiconductor layer that produces photoelectrons according to incidence of ultraviolet rays; and a second group III nitride semiconductor layer provided adjacent to the first group III nitride semiconductor layer and made of a thin-film crystal having c-axis orientation in a thickness direction, the second group III nitride semiconductor layer having an Al composition higher than that of the first group III nitride semiconductor layer.
    Type: Grant
    Filed: August 29, 2006
    Date of Patent: April 28, 2009
    Assignees: National University Corporation Shizuoka University, Hamamatsu Photonics K.K.
    Inventors: Masatomo Sumiya, Shunro Fuke, Tokuaki Nihashi, Minoru Hagino
  • Patent number: 7518163
    Abstract: A gallium nitride-based compound semiconductor light-emitting device is disclosed which includes an n-type semiconductor layer of a gallium nitride-based compound semiconductor, a light-emitting layer of a gallium nitride-based compound semiconductor and a p-type semiconductor layer of a gallium nitride-based compound semiconductor formed on a substrate in this order, and has a negative electrode and a positive electrode provided on the n-type semiconductor layer and the p-type semiconductor layer, respectively. The negative electrode includes a bonding pad layer and a contact metal layer which is in contact with the n-type semiconductor layer, and the contact metal layer is composed of a Cr—Al alloy.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: April 14, 2009
    Assignee: Showa Denko K.K.
    Inventor: Koji Kamei
  • Patent number: 7492988
    Abstract: Planar AWG circuits and systems are disclosed that use air trench bends to increase planar circuit compactness.
    Type: Grant
    Filed: December 4, 2007
    Date of Patent: February 17, 2009
    Inventors: Gregory P. Nordin, Yongbin Lin, Seunghyun Kim
  • Patent number: 7485950
    Abstract: An input signal comprising electronic carriers is injected into an impact ionization device with a high electric field whereupon the electronic carriers are accelerated toward an electron collector or hole sink and subsequently ionize additional electrons and holes that accelerated toward the electron collector and hole sink respectively. When properly biased an avalanche effect may occur that is proportional to the current injected into the impact ionization device via the input electrode. As a result, the input signal is amplified to provide an amplified signal. The described amplifier may be integrated with an input device such as a photodiode, and a transimpedance output amplifier onto a common substrate resulting in high performance high density sensor arrays and the like.
    Type: Grant
    Filed: July 14, 2006
    Date of Patent: February 3, 2009
    Assignee: Brigham Young University
    Inventors: Aaron R. Hawkins, Hong-Wei Lee