Incoherent Light Emitter Patents (Class 257/13)
  • Patent number: 10651628
    Abstract: The invention discloses a semiconductor optoelectronic micro-device comprising at least one cavity and at least one multilayer interference reflector. The device represents a micrometer-scale pillar with an arbitrary shape of the cross section. The device includes a vertical optical cavity, a gain medium and means of injection of nonequilibrium carriers into the gain medium, most preferably, via current injection in a p-n-junction geometry. To allow high electric-to-optic power conversion at least one contact is placed on the sidewalls of the micropillar overlapping with at least one doped section of the device. Means for the current path towards the contacts and for the heat dissipation from the gain medium are provided. Arrays of micro-devices can be fabricated on single wafer or mounted on single carrier. Devices with different cross-section of the micropillar emit light at different wavelengths.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: May 12, 2020
    Assignee: VI Systems GmbH
    Inventors: Nikolay Ledentsov, Vitaly Shchukin
  • Patent number: 10644258
    Abstract: An organic light emitting diode (OLED) panel includes an OLED module layer, and a first adhesive layer formed on a surface of the OLED module layer. A neutral plane is formed at an interface between the first adhesive layer and the OLED module layer. A bending deformation and a stress of the OLED module layer may be avoided, and damages of the OLED module layer may be reduced.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: May 5, 2020
    Assignee: DONGWOO FINE-CHEM CO., LTD.
    Inventors: In Kyu Song, Jun Hee Sung
  • Patent number: 10644197
    Abstract: There is herein described a process for providing improved device performance and fabrication techniques for semiconductors. More particularly, the present invention relates to a process for forming features, such as pixels, on GaN semiconductors using a p-GaN modification and annealing process. The process also relates to a plasma and thermal anneal process which results in a p-GaN modified layer where the annealing simultaneously enables the formation of conductive p-GaN and modified p-GaN regions that behave in an n-like manner and block vertical current flow. The process also extends to Resonant-Cavity Light Emitting Diodes (RCLEDs), pixels with a variety of sizes and electrically insulating planar layer for electrical tracks and bond pads.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: May 5, 2020
    Assignee: Facebook Technologies, LLC
    Inventors: James Ronald Bonar, Gareth John Valentine, Stephen Warren Gorton, Zheng Gong, James Small
  • Patent number: 10641439
    Abstract: The present invention relates to a nano-scale light emitting diode (LED) electrode assembly emitting polarized light, a method of manufacturing the same, and a polarized LED lamp having the same, and more particularly, to a nano-scale LED electrode assembly in which partially polarized light close to light that is linearly polarized having one direction is emitted as an emitted light when applying a driving voltage to the nano-scale LED electrode assembly and also nano-scale LED devices are connected to a nano-scale electrode without defects such as an electrical short circuit while maximizing a light extraction efficiency, a method of manufacturing the same, and a polarized LED lamp having the same.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: May 5, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Young Rag Do, Yeon Goog Sung
  • Patent number: 10629838
    Abstract: A metal nanowire according to an embodiment of the invention includes at least one bent portion. An angle (?) between an n-th wire portion and an (n+1)-th wire portion connected to the n-th wire portion through an n-th bent portion satisfies an inequation of 0°<?<180°. Also, a metal nanowire according to another embodiment of the invention includes at least two wire portions. The metal nanowire includes an n-th wire portion and an (n+1)-th wire portion connected to the n-th wire portion. A diameter of the n-th wire portion is different from a diameter of the (n+1)-th wire portion. In addition, a core-shell nanowire according to yet another embodiment includes a nanowire core; and a metal-compound shell formed on the nanowire core. A method of manufacturing a metal nanowire according to an embodiment includes preparing a reaction mixture and synthesizing a nanowire.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: April 21, 2020
    Assignee: DUKSAN HI-METAL CO., LTD.
    Inventors: Young Zo Yoo, Yoon Soo Choi, Yeong Jin Lim
  • Patent number: 10630058
    Abstract: A quantum cascade laser having a laser structure that includes a semiconductor mesa, a first end surface, a second end surface, and a first electrode provided on the semiconductor mesa. The laser structure includes a first region having the first end surface and a second region located between the second end surface and the first region. The semiconductor mesa includes a first mesa portion and a second mesa portion that are respectively included in the first region and the second region. The semiconductor mesa includes a first superlattice layer, a second superlattice layer, and a conductive semiconductor region. The first superlattice layer extends from the first end surface in the second axis direction and is included in the first mesa portion and the second mesa portion, and the second superlattice layer is provided in one of the first mesa portion and the second mesa portion.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: April 21, 2020
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Jun-ichi Hashimoto
  • Patent number: 10629778
    Abstract: A light emitting diode structure including a substrate, a semiconductor epitaxial structure, a first insulating layer, a first reflective layer, a second reflective layer, a second insulating layer and at least one electrode. The substrate has a tilt surface. The semiconductor epitaxial structure at least exposes the tilt surface. The first insulating layer exposes a portion of the semiconductor epitaxial structure. The first reflective layer is at least partially disposed on the portion of the semiconductor epitaxial structure and electrically connected to the semiconductor epitaxial structure. The second reflective layer is disposed on the first reflective layer and the first insulating layer, and covers at least the portion of the tilt surface. The second insulating layer is disposed on the second reflective layer. The electrode is disposed on the second reflective layer and electrically connected to the first reflective layer and the semiconductor epitaxial structure.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: April 21, 2020
    Assignee: Genesis Photonics Inc.
    Inventors: Yi-Ru Huang, Yu-Yun Lo, Chih-Ling Wu, Jing-En Huang, Shao-Ying Ting
  • Patent number: 10629663
    Abstract: An electroluminescence display apparatus includes: a substrate including: an active area, and a dummy area, a bank on the substrate, the bank being configured to define: a plurality of emission areas in the active area, and a plurality of dummy emission areas in the dummy area, a light-emitting layer in each of the plurality of emission areas, and a dummy light-emitting layer in each of the plurality of dummy emission areas, a thickness of the dummy light-emitting layer being greater than a thickness of the light-emitting layer.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: April 21, 2020
    Assignee: LG Display Co., Ltd.
    Inventors: Nackyoun Jung, Sangbin Lee, Jeongmook Choi
  • Patent number: 10627064
    Abstract: Provided is a lighting device, comprising: a light source module comprising: at least one light source disposed on a printed circuit board; and a resin layer disposed on the printed circuit board so that the light source is embedded; a light reflection member formed on at least any one of one side surface and another side surface of the resin layer; and a diffusion plate having an upper surface formed on the light source module, and a side wall which is integrally formed with the upper surface and formed to extend in a lower side direction and which is adhered onto the light reflection member, wherein a first separated space is formed between the light source module and the upper surface of the diffusion plate, whereby flexibility of the product itself can be secured, and durability and reliability of the product can be also improved.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: April 21, 2020
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Kwang Ho Park, Chul Hong Kim, Hyun Duck Yang, Moo Ryong Park, Jun Chul Hyun
  • Patent number: 10615574
    Abstract: Superlattice structures composed of single-crystal semiconductor wells and amorphous barriers are provided. Also provided are methods for fabricating the superlattice structures and electronic, optoelectronic, and photonic devices that include the superlattice structures. The superlattice structures include alternating quantum barrier layers and quantum well layers, the quantum barrier layers comprising an amorphous inorganic material and the quantum well layers comprising a single-crystalline semiconductor.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: April 7, 2020
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Zhenqiang Ma, Munho Kim, Jung-Hun Seo, Sang June Cho
  • Patent number: 10613382
    Abstract: The embodiments of the present disclosure disclose a backlight module, a method for manufacturing the same and a display device. The backlight module comprises: a substrate and a plurality of light emitting areas provided on the substrate. The light emitting area comprises a light source and a photonic crystal structure corresponding to the light source; the photonic crystal structure is internally provided with a cavity for accommodating the corresponding light source, and at least one defect channel for connecting the cavity and a surface, on a side of the photonic crystal structure away from the substrate, of the photonic crystal structure; a frequency of emergent light of each of the light sources is within a photonic forbidden band of the corresponding photonic crystal structure; extension directions of each of the defect channels are parallel to each other. The backlight module enables the light emergent to be collimated light.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: April 7, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Zhenhua Lv, Yanfeng Wang, Yuanxin Du, Yang You, Hongbo Feng
  • Patent number: 10615358
    Abstract: A light-emitting device includes an emissive layer in which first and second charge carriers recombine to emit light; a first electrode from which the first charge carriers are generated and a second electrode from which the second charge carriers are generated; a first charge transport layer that injects the first charge carriers from the first electrode into the emissive layer; and a second charge transport layer that injects the second charge carriers from the second electrode into the emissive layer. The emissive layer includes quantum dots having a core in which the first and second charge carriers recombine and a shell, and at least a portion of the quantum dots have a Quasi-Type II configuration in which the first charge carriers are confined to the core and the second charge carriers are non-confined charge carriers that are not confined to the core or the shell. The confined charge carriers may be the electrons and the non-confined charge carriers may be the holes, or vice versa.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: April 7, 2020
    Assignee: Sharp Kabushiki Kaisha
    Inventor: James Andrew Roberts Palles-Dimmock
  • Patent number: 10615372
    Abstract: A light emitting device including a micro cavity having a phase modulation surface and a display apparatus including the light emitting device are provided. The light emitting device includes a reflective layer including a phase modulation surface; a first electrode disposed on the phase modulation surface of the reflective layer; a light emitting structure disposed on the first electrode; and a second electrode disposed on the light emitting structure. The phase modulation surface may include a plurality of nano scale patterns that are regularly or irregularly arranged. The reflective layer and the second electrode may constitute the micro cavity having a resonance wavelength of the light emitting device.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: April 7, 2020
    Assignees: SAMSUNG ELECTRONICS CO., LTD., THE BOARD OF TRUSTEES OF THE LELAND STANFORD JUNIOR UNIVERSITY
    Inventors: Wonjae Joo, Mark L. Brongersma, Majid Esfandyarpour
  • Patent number: 10606393
    Abstract: A display device includes a display substrate, at least one micro light-emitting diode (LED) chip, and at least one reflective layer. The display substrate includes at least one sub-pixel circuit. The micro LED chip is electrically connected to the sub-pixel circuit. The micro LED chip is at least partially disposed between the reflective layer and the sub-pixel circuit.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: March 31, 2020
    Assignee: HANNSTOUCH SOLUTION INCORPORATED
    Inventors: Chih-Jen Cheng, Ching-Feng Tsai
  • Patent number: 10593828
    Abstract: A UV LED element, which is an exemplary ultraviolet light-emitting diode according to the present invention, includes an n-type conductive layer, a light-emitting layer, an electron block layer, and a p-type contact layer, all of which are arranged in this order. Bandgap energy of the electron block layer satisfies Econtact?EEBL, where Econtact designates bandgap energy of the p-type contact layer and EEBL designates the bandgap energy of the electron block layer. The electric apparatus includes the UV LED element as a light source for emitting an ultraviolet ray.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: March 17, 2020
    Assignees: RIKEN, PANASONIC CORPORATION
    Inventors: Hideki Hirayama, Masafumi Jo, Takuya Mino, Norimichi Noguchi, Takayoshi Takano, Jun Sakai
  • Patent number: 10593902
    Abstract: An ultrabright bright quantum dot light-emitting diode (QLED) device and associated method of manufacture. The QLED device includes quantum dots (QD) as emitters and a mixture of metal oxide nanoparticles and alkali metal compounds for simultaneous electron injection and hole blocking to achieve charging balance at high driving current conditions. The ultrabright QLEDs are useful for many light source applications including, but not limited to display, solid state lighting, optical sensor, phototherapy, photomedicine and photobiomedicine.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: March 17, 2020
    Assignee: University of Central Florida Research Foundation, Inc.
    Inventors: Yajie Dong, Hao Chen, Shin-Tson Wu, Juan He
  • Patent number: 10581225
    Abstract: A light-emitting device includes a substrate having a first surface and an opposing second surface, and an epitaxial structure having a first surface and an opposing second surface. The second surface of the epitaxial structure is positioned in proximity with the first surface of the substrate. The light-emitting device includes a first metal layer having a first surface and an opposing second surface. The light-emitting device further includes at least one light confinement structure configured to confine light produced within the epitaxial structure. The at least one light confinement structure provides a low-refraction index boundary that confines the light in a mesa structure that is at least partially surrounded by the at least one light confinement structure. The at least one light confinement structure can also be arranged to create separate confinement regions to serve as bandwidth enhancement coupled cavities for the active region of the light-emitting device.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: March 3, 2020
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventor: Chung-Yi Su
  • Patent number: 10573424
    Abstract: A method of manufacturing a high aspect ratio structure includes: a hole forming step of forming a plurality of holes in at least one principal surface of a substrate; a resist forming step of forming a first area with a resist layer and a second area without the resist layer on the principal surface provided with the plurality of holes after the hole forming step ends; and a concave portion forming step of immersing the substrate into an etching solution to form a concave portion in the substrate corresponding to the second area.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: February 25, 2020
    Assignee: Konica Minolta, Inc.
    Inventor: Mitsuru Yokoyama
  • Patent number: 10573515
    Abstract: There is provided a method for producing a semiconductor device, the method facilitating removal of a growth substrate from a semiconductor layer. A decomposition layer formation step involves extension of a plurality of threading dislocations during growth of a decomposition layer. A bridging portion formation step involves exposure of the threading dislocations to the surface of a bridging portion. A decomposition step involves widening of the threading dislocations exposed to the surface of the bridging portion, to thereby provide a plurality of through holes penetrating the bridging portion; decomposition of at least a portion of the decomposition layer exposed in the interior of the through holes; and discharge of a decomposition product generated through decomposition of the decomposition layer via the through holes to the outside of the bridging portion, to thereby provide a first void in a portion of a region where the decomposition layer has remained.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: February 25, 2020
    Assignee: TOYODA GOSEI CO., LTD.
    Inventor: Koji Okuno
  • Patent number: 10566382
    Abstract: A semiconductor light emitting device includes a plurality of light emitting cells including a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer between the first and second conductivity type semiconductor layers, an insulating layer on the plurality of light emitting cells and having a first opening and a second opening defining a first contact region of the first conductivity type semiconductor layer and a second contact region of the second conductivity type semiconductor layer, respectively, in each of the plurality of light emitting cells, a connection electrode on the insulating layer and connecting the first contact region and the second contact region to electrically connect the plurality of light emitting cells to each other, a transparent support substrate on the insulating layer and the connection electrode, and a transparent bonding layer between the insulating layer and the transparent support substrate.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: February 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji Hye Yeon, Han Kyu Seong, Wan Tae Lim, Sung Hyun Sim, Hanul Yoo
  • Patent number: 10554020
    Abstract: A light emitting device includes a substrate, a buffer layer, a first active layer, and a plurality of mesa regions. A portion of the first active layer includes a first electrical polarity. The plurality of mesa regions includes at least a portion of the first active layer, a light emitting region on the portion of the first active layer, and a second active layer on the light emitting region. A portion of the second active layer includes a second electrical polarity. The light emitting region is configured to emit light which has a target wavelength between 200 nm to 300 nm. A thickness of the light emitting region is a multiple of the target wavelength, and a dimension of the light emitting region parallel to the substrate is smaller than 10 times the target wavelength, such that the emitted light is confined to fewer than 10 transverse modes.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: February 4, 2020
    Assignee: Silanna UV Technologies Pte Ltd
    Inventors: Johnny Cai Tang, Petar Atanackovic
  • Patent number: 10553640
    Abstract: An electrodeless LED display and a method for fabricating the same are disclosed. In the method, an epitaxial layer is provided and a transparent conduction layer is formed on the epitaxial layer to bond a substrate. The epitaxial layer is etched to form dies deposition metal films on the transparent conduction layer. Conduction channels are formed on the substrate, and two ends of each conduction channel are respectively provided two conduction metal blocks. First metal members are formed on the metal film formed on the dies and the conduction metal blocks to connect with the dies on the different conduction channels. Then, second metal members are formed on the first metal members formed on the conduction metal blocks, whereby the second metal members and the first metal members formed on the dies are located on an identical plane.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: February 4, 2020
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Ray-Hua Horng, Huan-Yu Chien, Ken-Yen Chen
  • Patent number: 10553676
    Abstract: In a semiconductor element having a compound semiconductor layer epitaxially grown on a silicon substrate, an object is to suppress generation of deficiency or problems of reliability deriving from the ends of the element that are generated when dividing into semiconductor devices by dicing. A compound semiconductor layer epitaxially grown on a silicon substrate is formed via a buffer layer made of aluminum nitride. In the periphery of the semiconductor device, a scribe lane is present to surround a semiconductor element region. Along the scribe lane, the aluminum nitride layer is covered with a coating film for protection against humidity and moisture.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: February 4, 2020
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Hideki Mizuhara, Yoshihiro Matsushima, Shinichi Oohashi
  • Patent number: 10541348
    Abstract: A method comprising: depositing a quantum dot solution onto an as-grown layer of channel material to form a layer of quantum dot material having a substantially uniform thickness across the area of the layer of quantum dot material; and transferring the layers of channel and quantum dot material as a single stack onto a substrate comprising source and drain electrodes such that both the layers of channel and quantum dot material substantially conform to the topography of the underlying substrate and electrodes whilst maintaining the substantially uniform thickness of quantum dot material, the source and drain electrodes configured to enable a flow of electrical current through the layer of channel material, the layer of quantum dot material configured to generate electron-hole pairs on exposure to incident electromagnetic radiation to produce a detectable change in the flow of electrical current which is indicative of one or more of the presence and magnitude of the incident electromagnetic radiation.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: January 21, 2020
    Assignee: LYTEN, INC.
    Inventor: Richard White
  • Patent number: 10535708
    Abstract: An electrodeless LED display and a method for fabricating the same are disclosed. In the method, an epitaxial layer is provided and a transparent conduction layer is formed on the epitaxial layer to bond a substrate. The epitaxial layer is etched to form dies deposition metal films on the transparent conduction layer. Conduction channels are formed on the substrate, and two ends of each conduction channel are respectively provided two conduction metal blocks. First metal members are formed on the metal film formed on the dies and the conduction metal blocks to connect with the dies on the different conduction channels. Then, second metal members are formed on the first metal members formed on the conduction metal blocks, whereby the second metal members and the first metal members formed on the dies are located on an identical plane.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: January 14, 2020
    Assignee: National Chiao Tung University
    Inventors: Ray-Hua Horng, Huan-Yu Chien, Ken-Yen Chen
  • Patent number: 10535796
    Abstract: A semiconductor light emitting device includes a multi-quantum-well structure, a first potential barrier layer, a first capping layer, a second capping layer, and an electron barrier layer stacked in order on a growth substrate. The multi-quantum-well structure includes a plurality of alternately-stacked second potential barrier layers and potential well layers. The first capping layer is an undoped semiconductor layer and the second capping layer is a p-doped semiconductor layer. Each of the first and second capping layers has a band gap larger than that of each of the second potential barrier layers and the electron barrier layer. A method of preparing the semiconductor light emitting device is also provided.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: January 14, 2020
    Assignee: XIAMEN SAN'AN OPTOELECTRONICS CO., LTD.
    Inventors: Yung-Ling Lan, Chan-Chan Ling, Chi-Ming Tsai, Chia-Hung Chang
  • Patent number: 10535799
    Abstract: A semiconductor device includes a first reflective structure, a second reflective structure and a cavity region between the first reflective structure and the second reflective structure. The cavity region includes a first surface and a second surface opposite to the first surface. The semiconductor device further includes a first electrode on the first surface and electrically connected to the first reflective structure. The semiconductor device further includes a second electrode on the first surface and electrically connected to the second reflective structure. The semiconductor device further includes a first conductive layer on the second surface of the cavity region and including a hole formed therethrough.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: January 14, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Tzu-Chieh Hsu, Yi-Wen Huang, Shou-Lung Chen, Hsin-Kang Chen
  • Patent number: 10529771
    Abstract: A method of fabrication of an array of optoelectronic structures includes first providing a crystalline substrate having cells corresponding to individual optoelectronic structures to be obtained. Each of the cells includes an opening to the substrate. Then, several first layer portions of a first compound semiconductor material are grown in each the opening to at least partly fill a respective one of the cells and form an essentially planar film portion therein. Next, several second layer portions of a second compound semiconductor material are grown over the first layer portions that coalesce to form a coalescent film extending over the first layer portions. Finally, excess portions of materials are removed, to obtain the array of optoelectronic structures. Each optoelectronic structure comprises a stack protruding from the substrate of: a residual portion of one of the second layer portions; and a residual portion of one of the first layer portions.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: January 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Mattias B. Borg, Lukas Czornomaz, Veeresh V. Deshpande, Vladimir Djara, Heike E. Riel, Heinz Schmid
  • Patent number: 10517967
    Abstract: An aqueous approach to synthesize capped SnS quantum dots (QDs) followed by optional capping molecule extension by attaching one or more extending molecules to the capping molecule via peptide bond formation at elevated temperature. The capped SnS QDs may have a capping molecule:Sn:S molar ratio of 16:3:1 to 16:12:1. A suspension of SnS QDs was heat-treated at 200° C. for 0.5-4 hrs. The obtained SnS QDs showed an NIR emission peak at 820-835 nm with an excitation wavelength at 690 nm. The as synthesized SnS QDs were found to have high positive zeta potential of ˜30 mV and thus were toxic to cells. By neutralizing the SnS QDs the cytotoxicity was reduced to an accepted level. The heat-treatment step can be obviated by adding a glycerol solution containing S2? anions and capping molecule to a glycerol solution of Sn2+ ions.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: December 31, 2019
    Assignee: Drexel University
    Inventors: Wei-Heng Shih, Wan Y. Shih, Song Han, Xiaomin Niu, Shi Fang
  • Patent number: 10522725
    Abstract: An LED structure includes a substrate, an LED chip disposed on the substrate, a wavelength conversion layer disposed above a light-emitting surface of the LED chip, and a cut-on optical filter disposed on a central region of the wavelength conversion layer.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: December 31, 2019
    Assignee: LITE-ON OPTO TECHNOLOGY (CHANGZHOU) CO., LTD.
    Inventors: Ke-qin Guo, Wen Lee, Mu-qi Lee, Shu-yong Jia
  • Patent number: 10522716
    Abstract: Described herein is a semiconductor light emitting device. The semiconductor light emitting device comprises: an n-type semiconductor layer; a V-pit formed through at least part of the n-type semiconductor layer; an active layer disposed on the n-type semiconductor layer and filling the V-pit; and a p-type semiconductor layer disposed on the active layer, wherein the active layer includes a plurality of layers and part of the plural layers has a flat shape on the V-pit.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: December 31, 2019
    Assignee: SEOUL VIOSYS CO., LTD.
    Inventors: Seung Chul Park, Woo Chul Gwak, Jun Ho Yun
  • Patent number: 10510535
    Abstract: The invention relates to a method for manufacturing an optoelectronic device (50) including wire-like, conical, or frustoconical semiconductor elements (20) predominantly comprising a III-V compound. Each semiconductor element extends along an axis and includes a portion (54), the side surfaces (55) of which are covered with a shell (56) including at least one active region (31), wherein the portions are created by continuous growth in a reactor, and wherein the temperature in the reactor varies in an uninterrupted manner from a first temperature value that favors growth of first crystallographic planes perpendicular to said axis, to a second temperature value that is strictly lower than the first temperature value and favors growth of second crystallographic planes parallel to said axis.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: December 17, 2019
    Assignees: Aledia, Commissariat à l'Énergie Atomique et aux Énergies Alternatives, Universite Grenoble Alpes
    Inventors: Philipe Gilet, Amélie Dussaigne, Damien Salomon, Joel Eymery, Christophe Durand
  • Patent number: 10510990
    Abstract: The invention provides a groove structure for printing OLED display and manufacturing method for OLED display. By dividing the causeway surrounding the groove into a first and a second branch causeway layers provided in stack, the inclining inner peripheral surface of groove formed by first branch causeway forms a contact angle ranging 10-45° with the HIL ink, and the inclining inner peripheral surface of groove formed by second branch causeway forms a contact angle ranging 30-60° with the HIL ink, the inclining inner peripheral surface of groove formed by second branch causeway forms a contact angle ranging 10-45° with HTL ink and EML ink to restrict the height of HIL climbing upwards so that the top surface of HIL is flat or has a slightly convex in the middle to prevent current leakage at the edge of HIL, and improve the OLED display quality.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: December 17, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Yawei Liu
  • Patent number: 10505152
    Abstract: The present disclosure provides a quantum rod, a method of manufacturing a quantum rod and a display panel, wherein the quantum rod comprises a core and a shell covering the core, and the core and/or the shell is further covered with a conductive material layer.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: December 10, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jiuxia Yang, Feng Bai
  • Patent number: 10497894
    Abstract: It is an object of the present invention to provide a light-emitting element having a layer containing a light-emitting material and a transparent conductive film between a pair of electrodes, in which electric erosion of the transparent conductive film and metal can be prevented, and also to provide a light-emitting device using the light-emitting element. According to one feature of the invention, a light-emitting element includes a first layer 102 containing a light-emitting material, a second layer 103 containing a material having a donor level, a third layer 104 including a transparent conductive film, and a fourth layer 105 containing a hole-transporting medium between a first electrode 101 and a second electrode 106, in which the first layer 102, the second layer 103, the third layer 104, the fourth layer 105, and the second electrode 106 are provided sequentially, in which the second electrode 106 has a layer containing metal.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: December 3, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Daisuke Kumaki, Satoshi Seo
  • Patent number: 10492300
    Abstract: A light-emitting module includes: a first flexible insulating substrate having a plurality of conductor patterns formed on a surface; and a light-emitting element having a first electrode placed in a first region on a surface facing the first insulating substrate and connected to a first conductor pattern out of the plurality of conductor patterns through a first bump, and a second electrode placed in a second region different from the first region on a surface facing the first insulating substrate and connected to a second conductor pattern different from the first conductor pattern through a second bump, wherein a ratio of a distance from the first region to a contact point between the first bump and the first conductor pattern against a distance from the first electrode to a position where an outer edge of the first conductor pattern intersects with an outer edge of the second region is equal to or greater than 0.1.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: November 26, 2019
    Assignee: Toshiba Hokuto Electronics Corporation
    Inventor: Keiichi Maki
  • Patent number: 10483319
    Abstract: A pixelated display device and a method for making the same are disclosed. The device may include an array of nanowire LEDs located above a substrate. When the nanowire LEDs are initially grown, they may emit first-wavelength light proximally to the substrate and second-wavelength light distally from the substrate. The nanowires may remain as initially grown, in which case only second-wavelength light is visible, or the second-wavelength light emitting portions may be etched away such that only first-wavelength light is visible.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: November 19, 2019
    Assignee: GLO AB
    Inventors: Nathan Gardner, Ronald Kaneshiro, Daniel Bryce Thompson, Fariba Danesh, Martin Schubert
  • Patent number: 10483433
    Abstract: An embodiment of the present inventive concept provides an ultraviolet light emitting device comprising: a substrate having a concave or convex edge pattern disposed along an edge of an upper surface thereof; a semiconductor laminate disposed on the substrate and including first and second conductivity-type AlGaN semiconductor layers and an active layer disposed between the first and second conductivity-type AlGaN semiconductor layers and having an AlGaN semiconductor; a plurality of uneven portions extending from the edge pattern along the side surface of the semiconductor laminate in a stacking direction; and first and second electrodes connected to the first and second conductivity-type AlGaN semiconductor layers, respectively.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: November 19, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young Hwan Park, Joo Sung Kim, Young Jo Tak
  • Patent number: 10483438
    Abstract: A component includes a main body, a first layer, and a second layer. The main body includes a bottom surface. The first layer is provided on the bottom surface of the main body and includes a bottom surface. The second layer is bonded to a metal bonding material on a substrate to be provided physically integrally. The second layer has higher wettability with respect to the metal bonding material in a molten state than the first layer, and protrudes from the bottom surface side of the first layer such that at least a part of the bottom surface of the first layer is exposed on an entire outer circumference side of the second layer.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: November 19, 2019
    Assignee: SONY CORPORATION
    Inventor: Hiizu Ootorii
  • Patent number: 10483431
    Abstract: A light source module includes a quantum dot cell, a light emitting element, and an adhesive layer. The quantum dot cell includes a first glass substrate, a second glass substrate, a quantum dot region, and a reflective sealant disposed between the first glass substrate and the second glass substrate and surrounding the quantum dot region. The light emitting element is disposed at a side of the first glass substrate opposite to the quantum dot region and emits a light with a specific wavelength range. The quantum dot material in the quantum dot region converts the light with the specific wavelength range into another wavelength range. The adhesive layer is disposed at an outer side of the light emitting element for attaching the light emitting element to a surface of the first glass substrate.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: November 19, 2019
    Assignee: InnoLux Corporation
    Inventors: Shu-Ming Kuo, Chung-Kuang Wei, Chin-Lung Ting, Ruey-Jer Weng
  • Patent number: 10475963
    Abstract: A light-emitting diode with a stacked structure, having a first region and a second region and a third region, wherein all three regions have a substrate and an n-doped lower cladding layer and an active layer generating electromagnetic radiation, wherein the active layer includes a quantum well structure, and a p-doped upper cladding layer, and the first region additionally has a tunnel diode formed on the upper cladding layer and composed of a p+ layer and an n+ layer, and an n-doped current distribution layer. The current distribution layer and the n-doped contact layer are covered with a conductive trace. At least the lower cladding layer, the active layer, the upper cladding layer, the tunnel diode, and the current distribution layer are monolithic in design. The second region has a contact hole with a bottom region.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: November 12, 2019
    Assignee: Azur Space Solar Power GmbH
    Inventors: Thomas Lauermann, Wolfgang Koestler, Bianca Fuhrmann
  • Patent number: 10477174
    Abstract: An image display device includes an image forming unit, an optical unit, a temperature measuring unit, and a control unit. The optical unit is configured to input and output light that is output from the image forming unit. The temperature measuring unit is configured to measure a temperature of the image forming unit. The control unit is configured to control an operation of the image forming unit based on a result of a temperature measurement by the temperature measuring unit.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: November 12, 2019
    Assignee: Sony Corporation
    Inventor: Hiroshi Mukawa
  • Patent number: 10475954
    Abstract: A superlattice and method for forming that superlattice are disclosed. In particular, an engineered layered single crystal structure forming a superlattice is disclosed. The superlattice provides p-type or n-type conductivity, and comprises alternating host layers and impurity layers, wherein: the host layers consist essentially of a semiconductor material; and the impurity layers consist of a donor or acceptor material.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: November 12, 2019
    Assignee: Silanna UV Technologies Pte Ltd
    Inventor: Petar Atanackovic
  • Patent number: 10475961
    Abstract: An optoelectronic semiconductor chip is disclosed. In an embodiment an optoelectronic semiconductor chip includes a semiconductor layer sequence composed of AlInGaN comprising an n-conducting n-region, a p-conducting p-region and an intermediate active zone having at least one quantum well for generating a radiation, wherein the p-region comprises an electron barrier layer, a contact layer and an intermediate decomposition stop layer, the contact layer being directly adjacent to a contact metallization, wherein the decomposition stop layer comprises an aluminum content of at least 5% and at most 30% in places, wherein an intermediate region arranged between the electron barrier layer and the decomposition stop layer has a thickness between 2 nm and 15 nm inclusive, the intermediate region being free of aluminum, and wherein the aluminum content in the decomposition stop layer varies and increases on average in a direction towards the contact layer.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: November 12, 2019
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Werner Bergbauer, Joachim Hertkorn
  • Patent number: 10475950
    Abstract: A light-emitting device includes an active structure, wherein the active structure includes a well layer and a barrier layer. A first semiconductor layer of first conductivity type and a second semiconductor layer of second conductivity type sandwich the active structure. A first intermediate layer is between the first semiconductor layer and the active structure, wherein the first semiconductor layer has a first band gap, the second semiconductor layer has a second band gap, the well layer has a third band gap, and the first intermediate layer has a fourth band gap, wherein the first band gap and the second band gap are both larger than the fourth band gap, and the fourth band gap is larger than the third band gap. A first window layer is on the first semiconductor layer, wherein the first intermediate layer includes Alz1Ga1?z1As, the first window layer includes Alz2Ga1?z2As, and z1>z2.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: November 12, 2019
    Assignee: EPISTAR CORPORATION
    Inventor: Yi-Chieh Lin
  • Patent number: 10475962
    Abstract: An optoelectronic device includes a substrate; a semiconductor stack, formed on the substrate; a current blocking region, formed above the semiconductor stack and comprising a first pad portion and a first finger portion; a first opening, formed in the first pad portion, wherein in a top view, the first opening comprises an elongated shape defined by the first pad portion; a transparent conductive layer formed on the current blocking region and/or a surface of the semiconductor stack; and a first electrode formed above the current blocking region; wherein the transparent conductive layer comprises a second opening to expose the first opening, and the first electrode electrically connects the semiconductor stack through the first opening and the second opening.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: November 12, 2019
    Assignee: EPISTAR CORPORATION
    Inventors: Tzung-Shiun Yeh, Li-Ming Chang, Chien-Fu Shen
  • Patent number: 10472715
    Abstract: A nitride semiconductor template includes a heterogeneous substrate, a first nitride semiconductor layer that is formed on one surface of the heterogeneous substrate, includes a nitride semiconductor and has an in-plane thickness variation of not more than 4.0%, and a second nitride semiconductor layer that is formed on an annular region including an outer periphery of an other surface of the heterogeneous substrate, includes the nitride semiconductor and has a thickness of not less than 1 ?m.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: November 12, 2019
    Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Shusei Nemoto, Taichiro Konno, Hajime Fujikura
  • Patent number: 10468549
    Abstract: A nitrogen-containing semiconductor device including a first type doped semiconductor layer, a multiple quantum well layer and a second type doped semiconductor layer is provided. The multiple quantum well layer includes barrier layers and well layers, and the well layers and the barrier layers are arranged alternately. The multiple quantum well layer is located between the first type doped semiconductor layer and the second type doped semiconductor layer, and one of the well layers of the multiple quantum well layer is connected to the second type doped semiconductor layer.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: November 5, 2019
    Assignee: Genesis Photonics Inc.
    Inventors: Hsin-Chiao Fang, Cheng-Hsueh Lu, Cheng-Hung Lin, Chi-Hao Cheng, Chi-Feng Huang
  • Patent number: 10459147
    Abstract: Dual-direction collimation and a dual surface collimator provide dual-direction collimated light at a non-zero propagation angle. The dual surface collimator includes an entrance surface and a reflector surface each having a curved shape. The entrance surface is configured to refract incident light and the reflector surface is configured to reflect the refracted light back toward the entrance surface. The entrance surface is further configured to re-reflect the reflected light by total internal reflection toward an output aperture. Curved shapes and relative orientation of the entrance and reflector surfaces, in combination, are configured to convert the incident light into dual-direction collimated light having the non-zero propagation angle. A three-dimensional (3D) display includes the dual surface collimator, a plate light guide and an array of multibeam diffraction gratings to provide a plurality of light beams corresponding to different 3D view of the display.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: October 29, 2019
    Assignee: LEIA INC.
    Inventors: Ming Ma, David A. Fattal
  • Patent number: 10453387
    Abstract: A display panel, a display device, a pixel driving circuit, and a control method for the pixel driving circuit. The pixel driving circuit includes a data writing module for transmitting signal of the data signal end to the first node in response to enable signal of the first control signal end; a coupling writing module for transmitting signal of the first power source voltage end to the first node in response to enable signal of the second control signal end; a storage capacitor; a driving transistor; a first switch unit; a second switch unit; a reset module for transmitting signal of the reset signal line to the fourth node in response to enable signal of the fifth control signal end; and a light emitting element, an anode thereof being electrically connected to the fourth node, an cathode thereof being electrically connected to a second power source voltage end.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: October 22, 2019
    Assignee: SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Xingyao Zhou, Chang-ho Tseng, Yuan Li