Abstract: The purpose of the present invention is to provide a scintillator for a charged particle beam device and a charged particle beam device which achieve both an increase in emission intensity and a reduction in afterglow intensity. This scintillator for a charged particle beam device is characterized by comprising a substrate (13), a buffer layer (14) formed on a surface of the substrate (13), a stack (12) of a light emitting layer (15) and a barrier layer (16) formed on a surface of the buffer layer (14), and a conductive layer (17) formed on a surface of the stack (12) and by being configured such that the light emitting layer (15) contains InGaN, the barrier layer (16) contains GaN, and the ratio b/a of the thickness b of the barrier layer (16) to the thickness a of the light emitting layer (15) is 11 to 25.

Abstract: Shockley-Read-Hall (SRH) generation and/or recombination in heterojunction devices is suppressed by unconventional doping at or near the heterointerface. The effect of this doping is to shift SRH generation and/or recombination preferentially into the wider band gap material of the heterojunction. This reduces total SRH generation and/or recombination in the device by decreasing the intrinsic carrier concentration ni at locations where most of the SRH generation and/or recombination occurs. The physical basis for this effect is that the SRH generation and/or recombination rate tends to decrease as ni around the depletion region decreases, so decreasing the effective ni in this manner is a way to decrease SRH recombination.

Abstract: Some embodiments include a ferroelectric transistor having a first electrode and a second electrode. The second electrode is offset from the first electrode by an active region. A transistor gate is along a portion of the active region. The active region includes a first source/drain region adjacent the first electrode, a second source/drain region adjacent the second electrode, and a body region between the first and second source/drain regions. The body region includes a gated channel region adjacent the transistor gate. The active region includes at least one barrier between the second electrode and the gated channel region which is permeable to electrons but not to holes. Ferroelectric material is between the transistor gate and the gated channel region.

Abstract: A light emitting diode device comprising: a plurality of nanowires or nanopyramids grown on a graphitic substrate, said nanowires or nanopyramids having a p-n or p-i-n junction, a first electrode in electrical contact with said graphitic substrate; a light reflective layer in contact with the top of at least a portion of said nanowires or nanopyramids, said light reflective layer optionally acting as a second electrode; optionally a second electrode in electrical contact with the top of at least a portion of said nanowires or nanopyramids, said second electrode being essential where said light reflective layer does not act as an electrode; wherein said nanowires or nanopyramids comprise at least one group III-V compound semiconductor; and wherein in use light is emitted from said device in a direction substantially opposite to said light reflective layer.

Abstract: A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, in which the buffer layer includes a first buffer layer and a second buffer layer. Preferably, the first buffer layer includes a first layer of the first buffer layer comprising AlyGa1-yN on the substrate and a second layer of the first buffer layer comprising AlxGa1-xN on the first layer of the first buffer layer. The second buffer layer includes a first layer of the second buffer layer comprising AlwGa1-wN on the first buffer layer and a second layer of the second buffer layer comprising AlzGa1-zN on the first layer of the second buffer layer, in which x>z>y>w.

Abstract: Some embodiments include an integrated assembly having a semiconductor material with a more-doped region adjacent to a less-doped region. A two-dimensional material is between the more-doped region and a portion of the less-doped region. Some embodiments include an integrated assembly which contains a semiconductor material, a metal-containing material over the semiconductor material, and a two-dimensional material between a portion of the semiconductor material and the metal-containing material. Some embodiments include a transistor having a first source/drain region, a second source/drain region, a channel region between the first and second source/drain regions, and a two-dimensional material between the channel region and the first source; drain region.

Abstract: Transistor structures may include a metal oxide contact buffer between a portion of a channel material and source or drain contact metallization. The contact buffer may improve control of transistor channel length by limiting reaction between contact metallization and the channel material. The channel material may be of a first composition and the contact buffer may be of a second composition.

Abstract: Enhancement/depletion device pairs and methods of producing the same are disclosed. A disclosed example multilayered die includes a depletion mode device that includes a first polarization layer and a voltage tuning layer, and an enhancement mode device adjacent the depletion mode device, where the enhancement mode device includes a second polarization layer, and where the second polarization layer includes an opening corresponding to a gate of the enhancement mode device.

Abstract: Embodiments of the present disclosure include a photodiode that can detect optical radiation at a broad range of wavelengths. The photodiode can be used as a detector of a non-invasive sensor, which can be used for measuring physiological parameters of a monitored patient. The photodiode can be part of an integrated semiconductor structure that generates a detector signal responsive to optical radiation at both visible and infrared wavelengths incident on the photodiode. The photodiode can include a layer that forms part of an external surface of the photodiode, which is disposed to receive the optical radiation incident on the photodiode and pass the optical radiation to one or more other layers of the photodiode.

Abstract: A semiconductor power device includes a substrate, a buffer structure formed on the substrate, a barrier structure formed on the buffer structure, a channel layer formed on the barrier structure, and a barrier layer formed on the channel layer. The barrier structure includes a first functional layer on the buffer structure, a first back-barrier layer on the first functional layer, and an interlayer between the first back-barrier layer and the first functional layer. A material of the first back-barrier layer comprises Alx1Ga1-x1N, a material of the first functional layer comprises Alx2Ga1-x2N, 0<x1?1, 0?x2?1, and x1?x2. The interlayer includes a carbon doped or an iron doped material.

Abstract: Certain aspects of the present disclosure generally relate to an integrated circuit (IC) having a heterojunction bipolar transistor (HBT) device. The HBT device generally includes an emitter region and a collector region. The collector region may include a proton implant region having an edge aligned with an edge of the emitter region. In certain aspects, the HBT device also includes a base region disposed between the emitter region and the collector region.

Abstract: A maze-solving method includes converting extracted channel surface-shaped data into channel boundary lines; extending extension lines from two end points at a start point and at a terminal point, to two sides outside a maze, and constructing, outside the maze, a virtual connection line I and a virtual connection line II connecting base points on the extension lines of the start point and the terminal point; respectively enclosing a polygon I and a polygon II by means of the virtual connection line I and the channel boundary lines and by means of the virtual connection line II and the channel boundary lines, in which paths connecting the start point and the terminal point, between the polygon I and the polygon II are alternative solution paths for the maze; and selecting an alternative solution path with the shortest length as the optimal solution path for the maze.

Abstract: A semiconductor wafer includes a substrate (1), a buffer layer (2) deposited on the substrate (1), and an epitaxial layer (4) above the buffer layer (2). The buffer layer (2) includes a plurality of semiconductor material layers (22) and a plurality of oxygen-doped material layers (21). The semiconductor material layers (22) and the oxygen-doped material layers (21) are deposited in an alternating arrangement on top of each other. Oxygen concentrations of the oxygen-doped material layers (21) gradually decrease along a direction from the substrate (1) to the epitaxial layer (4).

Abstract: The present disclosure provides one embodiment of a semiconductor structure that includes an interconnection structure formed on a semiconductor substrate; and a capacitor disposed in the interconnection structure. The interconnection structure includes a top electrode; a bottom electrode; a dielectric material layer sandwiched between the top and bottom electrodes; and a nanocrystal layer embedded in the dielectric material layer.

Abstract: Apparatuses, systems, and methods are disclosed for magnetoresistive random access memory. A magnetic tunnel junction (MTJ) for storing data may include a reference layer. A free layer of an MTJ may be separated from a reference layer by a barrier layer. A free layer may be configured such that one or more resistance states for an MTJ correspond to one or more positions of a magnetic domain wall within the free layer. A domain stabilization layer may be coupled to a portion of a free layer, and may be configured to prevent migration of a domain wall into the portion of the free layer.

Abstract: A method includes forming a first epitaxial layer having a first dopant over a substrate; etching the first epitaxial layer to form a fin with a polar sidewall; and forming in sequence a semiconductor interlayer and a second epitaxial layer to surround the fin, in which the second epitaxial layer has a second dopant with a different conductivity type than the first dopant.

Abstract: A method for making a metal oxide semiconductor carbon nanotube thin film transistor circuit. A p-type carbon nanotube thin film transistor and a n-type carbon nanotube thin film transistor are formed on an insulating substrate and stacked with each other. The p-type carbon nanotube thin film transistor includes a first semiconductor carbon nanotube layer, a first drain electrode, a first source electrode, a functional dielectric layer, and a first gate electrode. The n-type carbon nanotube thin film transistor includes a second semiconductor carbon nanotube layer, a second drain electrode, a second source electrode, a first insulating layer, and a second gate electrode. The first drain electrode and the second drain electrode are electrically connected with each other. The first gate electrode and the second gate electrode are electrically connected with each other.

Abstract: A power device package includes a substrate, a high side power device, a low side power device and a driver device. The substrate includes a top surface, a bottom surface and a plurality of vias that extend through the substrate. The high side and low side power devices are disposed on the top surface of the substrate and connected with each other. The driver device is disposed on the bottom surface of the substrate and electrically connected with the high side and low side power devices through the vias to drive the high side and low side power devices in response to a control signal. The distance between the driver device and the high side and low side power devices is determined by the thickness of the substrate such that that a parasitic inductance between the driver device and the high side power device or the low side power device is reduced.

Abstract: A device having a multi-junction solar cell and a protection diode structure, whereby the multi-junction solar cell and the protection diode structure have a common rear surface and front sides separated by a mesa trench. The common rear surface comprises an electrically conductive layer, and the light enters through the front side into the multi-junction solar cell. The cell includes a stack of a plurality of solar cells, and has a top cell, placed closest to the front side, and a bottom solar cell, placed closest to the rear side, and a tunnel diode is placed between adjacent solar cells. The number of semiconductor layers in the protection diode structure is smaller than the number of semiconductor layers in the multi-junction solar cell. The sequence of the semiconductor layers in the protection diode structure corresponds to the sequence of semiconductor layers of the multi-junction solar cell.

Abstract: A semiconductor device is provided with, a group-III nitride semiconductor layered structure that includes a heterojunction, an insulating layer which has a gate opening that reaches the group-III nitride semiconductor layered structure and which is disposed on the group-III nitride semiconductor layered structure, a gate insulating film that covers the bottom and the side of the gate opening, a gate electrode defined on the gate insulating film inside the gate opening, a source electrode and a drain electrode which are disposed to be spaced apart from the gate electrode so as to sandwich the gate electrode, a first conductive layer embedded in the insulating layer between the gate electrode and the drain electrode, and a second conductive layer that is embedded in the insulating layer above the first conductive layer in a region closer to the drain electrode side than the first conductive layer.

Abstract: A semiconductor device includes: a substrate; a first nitride semiconductor layer disposed on the substrate; a second nitride semiconductor layer disposed on the first nitride semiconductor layer; a first opening penetrating the second nitride semiconductor layer; an electron transit layer and an electron supply layer which are formed along an upper surface of the second nitride semiconductor layer and a recessed surface of the first opening; a gate electrode disposed above the electron supply layer; a second opening penetrating the electron supply layer and the electron transit layer; a source electrode disposed to cover the second opening and electrically connected to the second nitride semiconductor layer; and a drain electrode disposed on a back surface of the substrate. The electron supply layer has a side surface formed along a side surface of the first opening. The gate electrode is not disposed on the side surface of the electron supply layer.

Abstract: In a method of manufacturing a semiconductor integrated circuit device, an active region including a nano-wire may be formed on a bulk insulating layer. A hard mask pattern may be formed to partially expose the nano-wire. A work function-controlling region may be formed on the nano-wire exposed through the hard mask pattern. The hard mask pattern may be removed. A gate insulating layer may be formed on the nano-wire. A gate may be formed to surround the nano-wire.

Abstract: Substrates, assemblies, and techniques for enabling a p-channel oxide semiconductor. For example, some embodiments can include an oxide semiconductor, where the oxide semiconductor includes an indium gallium zinc oxide (IGZO) sulfur alloy as a semiconducting material. The semiconducting material can be included in a thin-film-transistor that includes one or more p-channels.

Abstract: A method for manufacturing a quantum dot and a quantum dot are provided. The method includes adding a core semiconductor precursor solution into a seed composition solution. The seed composition solution includes a seed composition, and the seed composition is a dendrimer-metal nanoparticle composite. The core semiconductor precursor solution includes a first semiconductor ion and a second semiconductor ion. The method also includes carrying out a first synthesis reaction to form a core semiconductor material wrapping the seed composition. The core semiconductor material is formed by combining the first semiconductor ion with the second semiconductor ion.

Abstract: Described herein are metallic excavated nanoframes and methods for producing metallic excavated nanoframes. A method may include providing a solution including a plurality of excavated nanoparticles dispersed in a solvent, and exposing the solution to chemical corrosion to convert the plurality of excavated nanoparticles into a plurality of excavated nanoframes.

Abstract: A semiconductor device includes a type III-V semiconductor body having a main surface and a rear surface opposite the main surface. A barrier region is disposed beneath the main surface. A buffer region is disposed beneath the barrier region. A first two-dimensional charge carrier gas region forms near an interface between the barrier region and the buffer region. A second two-dimensional charge carrier gas region forms near an interface between the buffer region and the first back-barrier region. A third two-dimensional charge carrier gas region forms near an interface between the first back-barrier region and the second back-barrier region. Both of the second and third two-dimensional charge carrier gas regions have an opposite carrier type as the first two-dimensional charge carrier gas region. The third two-dimensional charge carrier gas region is more densely populated with charge carriers than the second two-dimensional charge carrier gas region.

Abstract: A collector layer of an HBT includes a high-concentration collector layer and a low-concentration collector layer thereon. The low-concentration collector layer includes a graded collector layer in which the energy band gap varies to narrow with increasing distance from the base layer. The electron affinity of the semiconductor material for the base layer is greater than that of the semiconductor material for the graded collector layer at the point of the largest energy band gap by about 0.15 eV or less. The electron velocity in the graded collector layer peaks at a certain electric field strength. In the graded collector layer, the strength of the quasi-electric field, an electric field that acts on electrons as a result of the varying energy band gap, is between about 0.3 times and about 1.8 times the peak electric field strength, the electric field strength at which the electron velocity peaks.

Abstract: Embodiments of the present disclosure include a photodiode that can detect optical radiation at a broad range of wavelengths. The photodiode can be used as a detector of a non-invasive sensor, which can be used for measuring physiological parameters of a monitored patient. The photodiode can be part of an integrated semiconductor structure that generates a detector signal responsive to optical radiation at both visible and infrared wavelengths incident on the photodiode. The photodiode can include a layer that forms part of an external surface of the photodiode, which is disposed to receive the optical radiation incident on the photodiode and pass the optical radiation to one or more other layers of the photodiode.

Abstract: Provided is a photon detector. The photon detector includes an optical waveguide including input and detection regions, which are spaced apart from each other in a first direction, and a conversion region between the input region and the detection region, a nano pattern disposed on the optical waveguide in the conversion region, and a nanowire disposed on the optical waveguide in the detection region. The nano pattern includes a first pattern and a second pattern, which extend in the first direction, and the first pattern and the second pattern are spaced apart from each other in a second direction crossing the first direction.

Abstract: A gallium nitride based monolithic microwave integrated circuit includes a substrate, a channel layer on the substrate and a barrier layer on the channel layer. A recess is provided in a top surface of the barrier layer. First gate, source and drain electrodes are provided on the barrier layer opposite the channel layer, with a bottom surface of the first gate electrode in direct contact with the barrier layer. Second gate, source and drain electrodes are also provided on the barrier layer opposite the channel layer. A gate insulating layer is provided in the recess in the barrier layer, and the second gate electrode is on the gate insulating layer opposite the barrier layer and extending into the recess. The first gate, source and drain electrodes comprise the electrodes of a depletion mode transistor, and the second gate, source and drain electrodes comprise the electrodes of an enhancement mode transistor.

Abstract: Disclosed herein is a semiconducting nanoparticle comprising a one-dimensional semiconducting nanoparticle having a first end and a second end; where the second end is opposed to the first end; and two first endcaps, one of which contacts the first end and the other of which contacts the second end respectively of the one-dimensional semiconducting nanoparticle; where the first endcap that contacts the first end comprises a first semiconductor and where the first endcap extends from the first end of the one-dimensional semiconducting nanoparticle to form a first nanocrystal heterojunction; where the first endcap that contacts the second end comprises a second semiconductor; where the first endcap extends from the second end of the one-dimensional semiconducting nanoparticle to form a second nanocrystal heterojunction; and where the first semiconductor and the second semiconductor are chemically different from each other.

Abstract: A method for patterning a piece of carbon nanomaterial. The method comprises generating a first light pulse sequence with first light pulse sequence property values, the first light pulse sequence comprising at least one light pulse and exposing a first area of the piece of carbon nanomaterial to said first light pulse sequence in a first process environment having a first oxygen content, without exposing at least part of the piece of carbon nanomaterial to said first light pulse sequence. In this way, the method comprises oxidizing locally, in the first area, at least some carbon atoms of the piece of carbon nanomaterial in such a way that at most 10% of the carbon atoms of the first area are removed from the first area; thereby patterning the first area of the piece of carbon nanomaterial. In addition a processed piece of carbon nanomaterial.

Abstract: Embodiments of the present disclosure include a photodiode that can detect optical radiation at a broad range of wavelengths. The photodiode can be used as a detector of a non-invasive sensor, which can be used for measuring physiological parameters of a monitored patient. The photodiode can be part of an integrated semiconductor structure that generates a detector signal responsive to optical radiation at both visible and infrared wavelengths incident on the photodiode. The photodiode can include a layer that forms part of an external surface of the photodiode, which is disposed to receive the optical radiation incident on the photodiode and pass the optical radiation to one or more other layers of the photodiode.

Abstract: This invention discloses a light emitting element to solve the problem of lattice mismatch and inequality of electron holes and electrons of the conventional light emitting elements. The light emitting element comprises a gallium nitride layer, a gallium nitride pyramid, an insulating layer, a first electrode and a second electrode. The gallium nitride pyramid contacts with the gallium nitride layer, with a c-axis of the gallium nitride layer opposite in direction to a c-axis of the gallium nitride pyramid, and with an M-plane of the gallium nitride layer parallel to an M-plane of the gallium nitride pyramid, with broken bonds at the mounting face of the gallium nitride layer and the larger end face of the gallium nitride pyramid welded with each other, with the gallium nitride layer and the gallium nitride pyramid being used as a p-type semiconductor and an n-type semiconductor respectively.

Abstract: An apparatus and method, the apparatus including a charge carrier wherein the charge carrier includes a continuous three dimensional framework including a plurality of cavities throughout the framework; sensor material provided throughout the charge carrier; wherein the sensor material is configured to transduce a detected input and change conductivity of the charge carrier in dependence of the detected input.

Abstract: Disclosed herein are fabrication techniques for providing metal gates in quantum devices, as well as related quantum devices. For example, in some embodiments, a method of manufacturing a quantum device may include providing a gate dielectric over a qubit device layer, providing over the gate dielectric a pattern of non-metallic elements referred to as “gate support elements,” and depositing a gate metal on sidewalls of the gate support elements to form a plurality of gates of the quantum device.

Abstract: A composition of matter comprising: a graphitic substrate optionally carried on a support; a seed layer having a thickness of no more than 50 nm deposited directly on top of said substrate, opposite any support; and an oxide or nitride masking layer directly on top of said seed layer; wherein a plurality of holes are present through said seed layer and through said masking layer to said graphitic substrate; and wherein a plurality of nanowires or nanopyramids are grown from said substrate in said holes, said nanowires or nanopyramids comprising at least one semiconducting group III-V compound.

Abstract: A fin structure disposed over a substrate and a method of forming a fin structure are disclosed. The fin structure includes a mesa, a channel disposed over the mesa, and a convex-shaped feature disposed between the channel and the mesa. The mesa has a first semiconductor material, and the channel has a second semiconductor material different from the first semiconductor material. The convex-shaped feature is stepped-shaped, stair-shaped, or ladder-shaped. The convex-shaped feature includes a first isolation feature disposed between the channel and the mesa, and a second isolation feature disposed between the channel and the first isolation feature. The first isolation feature is U-shaped, and the second isolation feature is rectangular-shaped. A portion of the second isolation feature is surrounded by the channel and another portion of the second isolation feature is surrounded by the first isolation feature.

Abstract: A semiconductor device comprises: a substrate; a multi-layer semiconductor layer located on the substrate, the multi-layer semiconductor layer being divided into an active area and a passive area outside the active area; a gate electrode, a source electrode and a drain electrode all located on the multi-layer semiconductor layer and within the active area; and a heat dissipation layer covering at least one portion of the active area and containing a heat dissipation material. In embodiments of the present invention, a heat dissipation layer covering at least one portion of the active area is provided in the semiconductor device. The arrangement of the heat dissipation layer adds a heat dissipation approach for the semiconductor device in the planar direction, thus the heat dissipation effect of the semiconductor device is improved.

Abstract: A method of making a magnetic field sensor using in situ solid source graphene and graphene induced anti-ferromagnetic coupling and spin filtering, comprising providing a substrate comprising silicon wafers and thermal oxide, performing DC magnetron sputtering, back-sputtering the substrate, growing amorphous carbon on the substrate, sputtering and growing a first ferromagnetic metal surface on the amorphous carbon, annealing the substrate and the amorphous carbon and the first ferromagnetic metal surface, forming a graphene film on the first ferromagnetic metal surface, wherein the first ferromagnetic metal surface comprises NiFe, sputtering and growing a second ferromagnetic film on the graphene film, and capping the second ferromagnetic film with a platinum layer.

Abstract: A laser package for use in a dermatological treatment device may include a conductive carrier, an insulation layer arranged over a first region of a first side of the conductive carrier, a semiconductor laser device mounted to a second region of the first side of the conductive carrier, and a conductive film secured to the semiconductor laser device and extending over at least a portion of the insulation layer, such that the conductive film is insulated from the conductive carrier by the insulation layer, and wherein a coefficient of thermal expansion of the semiconductor laser device differs from a coefficient of the conductive carrier to which it is mounted by more than 20%.

Abstract: A method for making a metal oxide semiconductor carbon nanotube thin film transistor circuit. A p-type carbon nanotube thin film transistor and a n-type carbon nanotube thin film transistor are formed on an insulating substrate and stacked with each other. The p-type carbon nanotube thin film transistor includes a first semiconductor carbon nanotube layer, a first drain electrode, a first source electrode, a functional dielectric layer, and a first gate electrode. The n-type carbon nanotube thin film transistor includes a second semiconductor carbon nanotube layer, a second drain electrode, a second source electrode, a first insulating layer, and a second gate electrode. The first drain electrode and the second drain electrode are electrically connected with each other. The first gate electrode and the second gate electrode are electrically connected with each other.

Abstract: This disclosure relates to methods of forming bipolar transistors, such as heterojunction bipolar transistors. The methods may include forming a sub-collector over a substrate, forming a first portion of a collector over the sub-collector and doping a second portion of the collector to form a doping spike. The method may further include forming a third portion of the collector over the doping spike and forming a base of the bipolar transistor over the third portion of the collector.

Abstract: In a method of manufacturing a semiconductor integrated circuit device, an active region including a nano-wire may be formed on a bulk insulating layer. A hard mask pattern may be formed to partially expose the nano-wire. A work function-controlling region may be formed on the nano-wire exposed through the hard mask pattern. The hard mask pattern may be removed. A gate insulating layer may be formed on the nano-wire. A gate may be formed to surround the nano-wire.

Abstract: A light-emitting diode (LED) epitaxial structure includes, from bottom to up, a substrate, a first conductive type semiconductor layer, a super lattice, a multi-quantum well layer with V pits, a hole injection layer and a second conductive type semiconductor layer. The hole injection layer appears in the shape of dual hexagonal pyramid, which fills up the V pits and embeds in the second conductive type semiconductor layer. Various embodiments of the present disclosures can effectively reduce point defect density and dislocation density of semiconductor material and effectively enlarge hole injection area and improves hole injection efficiency.

Abstract: A field effect transistor according to the present invention includes a semiconductor layer including a groove, an insulating film formed on an upper surface of the semiconductor layer and having an opening above the groove and a gate electrode buried in the opening to be in contact with side surfaces and a bottom surface of the groove and having parts being in contact with an upper surface of the insulating film on both sides of the opening, wherein the gate electrode has a T-shaped sectional shape in which a width of an upper end is larger than a width of the upper surface of the insulating film.

Abstract: Described herein are materials and systems for efficient upconversion of photons. The materials may be disposed in a system comprising two semiconductor materials with an interface therebetween, the interface comprising a valence and/or conduction band offset between the semiconducting materials of about ?0.5 eV to about 0.5 eV, including 0, wherein one of the semiconductor materials is a material with discrete energy states and the other is a material with a graded composition and/or controlled band gap. The system can upconvert photons by: a) controlling energy levels of discrete energy states of a semiconducting material in a system to direct tunneling and exciton separation; b) controlling a compositional profile of another semiconducting material in the system to funnel charges away from an upconversion region and into a recombination zone; and c) utilizing the discrete energy states of the semiconducting material in the system to inhibit phonon relaxation.

Abstract: Provided are a group 13 nitride composite substrate allowing for the production of a semiconductor device suitable for high-frequency applications while including a conductive GaN substrate, and a semiconductor device produced using this substrate. The group 13 nitride composite substrate includes a base material of an n-conductivity type formed of GaN, a base layer located on the base material, being a group 13 nitride layer having a resistivity of 1×106 ?·cm or more, a channel layer located on the base layer, being a GaN layer having a total impurity density of 1×1017/cm3 or less, and a barrier layer that is located on the channel layer and is formed of a group 13 nitride having a composition AlxInyGa1?x?yN (0?x?1, 0?y?1).

Abstract: A laser-oscillation cooling device includes a laser excitation unit that excites a laser beam and locally emits heat, a storage tank that is capable of storing a cryogenic liquid at an atmospheric pressure and discharge the cryogenic liquid which is evaporated, a pressurization and supply unit that pressurizes the cryogenic liquid stored in the storage tank and supplies the pressurized cryogenic liquid to the laser excitation unit, and a decompression and return unit that decompresses the cryogenic liquid which is supplied to the laser excitation unit and used to cool the laser excitation unit and returns the cryogenic liquid to the storage tank.

Abstract: A radiation dosimeter comprising a thermal micro-platform with a plurality of nanowires having phononic structures providing improved thermal isolation of the micro-platform. In embodiments, thermo-luminescent, MOS transistor and PIN diode sensors for x-ray, gamma, charged particles and neutron irradiation are disposed on the micro-platform. In a preferred embodiment the dosimeter is fabricated using a silicon SOI starting wafer.