Heterojunction Patents (Class 257/12)
  • Patent number: 10383520
    Abstract: Embodiments of the present disclosure include a photodiode that can detect optical radiation at a broad range of wavelengths. The photodiode can be used as a detector of a non-invasive sensor, which can be used for measuring physiological parameters of a monitored patient. The photodiode can be part of an integrated semiconductor structure that generates a detector signal responsive to optical radiation at both visible and infrared wavelengths incident on the photodiode. The photodiode can include a layer that forms part of an external surface of the photodiode, which is disposed to receive the optical radiation incident on the photodiode and pass the optical radiation to one or more other layers of the photodiode.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: August 20, 2019
    Assignee: MASIMO SEMICONDUCTOR, INC.
    Inventors: Steven J. Wojtczuk, Xuebing Zhang, William J. MacNeish, III
  • Patent number: 10381508
    Abstract: This invention discloses a light emitting element to solve the problem of lattice mismatch and inequality of electron holes and electrons of the conventional light emitting elements. The light emitting element comprises a gallium nitride layer, a gallium nitride pyramid, an insulating layer, a first electrode and a second electrode. The gallium nitride pyramid contacts with the gallium nitride layer, with a c-axis of the gallium nitride layer opposite in direction to a c-axis of the gallium nitride pyramid, and with an M-plane of the gallium nitride layer parallel to an M-plane of the gallium nitride pyramid, with broken bonds at the mounting face of the gallium nitride layer and the larger end face of the gallium nitride pyramid welded with each other, with the gallium nitride layer and the gallium nitride pyramid being used as a p-type semiconductor and an n-type semiconductor respectively.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: August 13, 2019
    Assignee: NATIONAL SUN YAT-SEN UNIVERSITY
    Inventors: I-Kai Lo, Ying-Chieh Wang, Yu-Chi Hsu, Cheng-Hung Shih
  • Patent number: 10374110
    Abstract: An apparatus and method, the apparatus including a charge carrier wherein the charge carrier includes a continuous three dimensional framework including a plurality of cavities throughout the framework; sensor material provided throughout the charge carrier; wherein the sensor material is configured to transduce a detected input and change conductivity of the charge carrier in dependence of the detected input.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: August 6, 2019
    Assignee: Nokia Technologies Oy
    Inventors: Richard White, Elisabetta Spigone
  • Patent number: 10361353
    Abstract: Disclosed herein are fabrication techniques for providing metal gates in quantum devices, as well as related quantum devices. For example, in some embodiments, a method of manufacturing a quantum device may include providing a gate dielectric over a qubit device layer, providing over the gate dielectric a pattern of non-metallic elements referred to as “gate support elements,” and depositing a gate metal on sidewalls of the gate support elements to form a plurality of gates of the quantum device.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: July 23, 2019
    Assignee: Intel Corporation
    Inventors: Hubert C. George, Zachary R. Yoscovits, Nicole K. Thomas, Lester Lampert, James S. Clarke, Jeanette M. Roberts, Ravi Pillarisetty, David J. Michalak, Kanwaljit Singh, Roman Caudillo
  • Patent number: 10347791
    Abstract: A composition of matter comprising: a graphitic substrate optionally carried on a support; a seed layer having a thickness of no more than 50 nm deposited directly on top of said substrate, opposite any support; and an oxide or nitride masking layer directly on top of said seed layer; wherein a plurality of holes are present through said seed layer and through said masking layer to said graphitic substrate; and wherein a plurality of nanowires or nanopyramids are grown from said substrate in said holes, said nanowires or nanopyramids comprising at least one semiconducting group III-V compound.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: July 9, 2019
    Assignees: CRAYONANO AS, NORWEGIAN UNIVERSITY OF SCIENCE AND TECHNOLOGY (NTNU)
    Inventors: Dong Chul Kim, Ida Marie E. Høiaas, Carl Philip J. Heimdal, Bjørn Ove M. Fimland, Helge Weman
  • Patent number: 10333001
    Abstract: A fin structure disposed over a substrate and a method of forming a fin structure are disclosed. The fin structure includes a mesa, a channel disposed over the mesa, and a convex-shaped feature disposed between the channel and the mesa. The mesa has a first semiconductor material, and the channel has a second semiconductor material different from the first semiconductor material. The convex-shaped feature is stepped-shaped, stair-shaped, or ladder-shaped. The convex-shaped feature includes a first isolation feature disposed between the channel and the mesa, and a second isolation feature disposed between the channel and the first isolation feature. The first isolation feature is U-shaped, and the second isolation feature is rectangular-shaped. A portion of the second isolation feature is surrounded by the channel and another portion of the second isolation feature is surrounded by the first isolation feature.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: June 25, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Gin-Chen Huang, Ching-Hong Jiang, Neng-Kuo Chen, Sey-Ping Sun, Clement Hsingjen Wann
  • Patent number: 10312176
    Abstract: A semiconductor device comprises: a substrate; a multi-layer semiconductor layer located on the substrate, the multi-layer semiconductor layer being divided into an active area and a passive area outside the active area; a gate electrode, a source electrode and a drain electrode all located on the multi-layer semiconductor layer and within the active area; and a heat dissipation layer covering at least one portion of the active area and containing a heat dissipation material. In embodiments of the present invention, a heat dissipation layer covering at least one portion of the active area is provided in the semiconductor device. The arrangement of the heat dissipation layer adds a heat dissipation approach for the semiconductor device in the planar direction, thus the heat dissipation effect of the semiconductor device is improved.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: June 4, 2019
    Assignee: GPOWER SEMICONDUCTOR, INC.
    Inventors: Yi Pei, Mengjie Zhou
  • Patent number: 10261139
    Abstract: A method of making a magnetic field sensor using in situ solid source graphene and graphene induced anti-ferromagnetic coupling and spin filtering, comprising providing a substrate comprising silicon wafers and thermal oxide, performing DC magnetron sputtering, back-sputtering the substrate, growing amorphous carbon on the substrate, sputtering and growing a first ferromagnetic metal surface on the amorphous carbon, annealing the substrate and the amorphous carbon and the first ferromagnetic metal surface, forming a graphene film on the first ferromagnetic metal surface, wherein the first ferromagnetic metal surface comprises NiFe, sputtering and growing a second ferromagnetic film on the graphene film, and capping the second ferromagnetic film with a platinum layer.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: April 16, 2019
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Olaf M. J. van 't Erve, Enrique Cobas, Shu-Fan Cheng, Berend T. Jonker
  • Patent number: 10243321
    Abstract: A laser package for use in a dermatological treatment device may include a conductive carrier, an insulation layer arranged over a first region of a first side of the conductive carrier, a semiconductor laser device mounted to a second region of the first side of the conductive carrier, and a conductive film secured to the semiconductor laser device and extending over at least a portion of the insulation layer, such that the conductive film is insulated from the conductive carrier by the insulation layer, and wherein a coefficient of thermal expansion of the semiconductor laser device differs from a coefficient of the conductive carrier to which it is mounted by more than 20%.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: March 26, 2019
    Assignee: CHANNEL INVESTMENTS, LLC
    Inventors: Patrick Reichert, Harvey I-Heng Liu
  • Patent number: 10177199
    Abstract: A method for making a metal oxide semiconductor carbon nanotube thin film transistor circuit. A p-type carbon nanotube thin film transistor and a n-type carbon nanotube thin film transistor are formed on an insulating substrate and stacked with each other. The p-type carbon nanotube thin film transistor includes a first semiconductor carbon nanotube layer, a first drain electrode, a first source electrode, a functional dielectric layer, and a first gate electrode. The n-type carbon nanotube thin film transistor includes a second semiconductor carbon nanotube layer, a second drain electrode, a second source electrode, a first insulating layer, and a second gate electrode. The first drain electrode and the second drain electrode are electrically connected with each other. The first gate electrode and the second gate electrode are electrically connected with each other.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: January 8, 2019
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yu-Dan Zhao, Qun-Qing Li, Xiao-Yang Xiao, Guan-Hong Li, Yuan-Hao Jin, Shou-Shan Fan
  • Patent number: 10158010
    Abstract: This disclosure relates to methods of forming bipolar transistors, such as heterojunction bipolar transistors. The methods may include forming a sub-collector over a substrate, forming a first portion of a collector over the sub-collector and doping a second portion of the collector to form a doping spike. The method may further include forming a third portion of the collector over the doping spike and forming a base of the bipolar transistor over the third portion of the collector.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: December 18, 2018
    Assignee: Skyworks Solutions, Inc.
    Inventors: Peter J. Zampardi, Jr., Kai Hay Kwok
  • Patent number: 10121902
    Abstract: In a method of manufacturing a semiconductor integrated circuit device, an active region including a nano-wire may be formed on a bulk insulating layer. A hard mask pattern may be formed to partially expose the nano-wire. A work function-controlling region may be formed on the nano-wire exposed through the hard mask pattern. The hard mask pattern may be removed. A gate insulating layer may be formed on the nano-wire. A gate may be formed to surround the nano-wire.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: November 6, 2018
    Assignee: SK Hynix Inc.
    Inventor: Dong Yean Oh
  • Patent number: 10043944
    Abstract: A light-emitting diode (LED) epitaxial structure includes, from bottom to up, a substrate, a first conductive type semiconductor layer, a super lattice, a multi-quantum well layer with V pits, a hole injection layer and a second conductive type semiconductor layer. The hole injection layer appears in the shape of dual hexagonal pyramid, which fills up the V pits and embeds in the second conductive type semiconductor layer. Various embodiments of the present disclosures can effectively reduce point defect density and dislocation density of semiconductor material and effectively enlarge hole injection area and improves hole injection efficiency.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: August 7, 2018
    Assignee: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Jie Zhang, Xueliang Zhu, Chengxiao Du, Jianming Liu, Chen-ke Hsu
  • Patent number: 9960263
    Abstract: A field effect transistor according to the present invention includes a semiconductor layer including a groove, an insulating film formed on an upper surface of the semiconductor layer and having an opening above the groove and a gate electrode buried in the opening to be in contact with side surfaces and a bottom surface of the groove and having parts being in contact with an upper surface of the insulating film on both sides of the opening, wherein the gate electrode has a T-shaped sectional shape in which a width of an upper end is larger than a width of the upper surface of the insulating film.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: May 1, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventor: Takahiro Nakamoto
  • Patent number: 9954129
    Abstract: Described herein are materials and systems for efficient upconversion of photons. The materials may be disposed in a system comprising two semiconductor materials with an interface therebetween, the interface comprising a valence and/or conduction band offset between the semiconducting materials of about ?0.5 eV to about 0.5 eV, including 0, wherein one of the semiconductor materials is a material with discrete energy states and the other is a material with a graded composition and/or controlled band gap. The system can upconvert photons by: a) controlling energy levels of discrete energy states of a semiconducting material in a system to direct tunneling and exciton separation; b) controlling a compositional profile of another semiconducting material in the system to funnel charges away from an upconversion region and into a recombination zone; and c) utilizing the discrete energy states of the semiconducting material in the system to inhibit phonon relaxation.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 24, 2018
    Assignee: UNIVERSITY OF DELAWARE
    Inventors: Matthew Doty, Joshua Zide
  • Patent number: 9882042
    Abstract: Provided are a group 13 nitride composite substrate allowing for the production of a semiconductor device suitable for high-frequency applications while including a conductive GaN substrate, and a semiconductor device produced using this substrate. The group 13 nitride composite substrate includes a base material of an n-conductivity type formed of GaN, a base layer located on the base material, being a group 13 nitride layer having a resistivity of 1×106 ?·cm or more, a channel layer located on the base layer, being a GaN layer having a total impurity density of 1×1017/cm3 or less, and a barrier layer that is located on the channel layer and is formed of a group 13 nitride having a composition AlxInyGa1?x?yN (0?x?1, 0?y?1).
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: January 30, 2018
    Assignee: NGK INSULATORS, LTD.
    Inventors: Yoshitaka Kuraoka, Mikiya Ichimura, Makoto Iwai
  • Patent number: 9825418
    Abstract: A laser-oscillation cooling device includes a laser excitation unit that excites a laser beam and locally emits heat, a storage tank that is capable of storing a cryogenic liquid at an atmospheric pressure and discharge the cryogenic liquid which is evaporated, a pressurization and supply unit that pressurizes the cryogenic liquid stored in the storage tank and supplies the pressurized cryogenic liquid to the laser excitation unit, and a decompression and return unit that decompresses the cryogenic liquid which is supplied to the laser excitation unit and used to cool the laser excitation unit and returns the cryogenic liquid to the storage tank.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: November 21, 2017
    Assignee: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Jiro Kasahara, Yoshiyuki Kondo, Shinya Ishii, Koichi Hamamoto
  • Patent number: 9817130
    Abstract: A radiation dosimeter comprising a thermal micro-platform with a plurality of nanowires having phononic structures providing improved thermal isolation of the micro-platform. In embodiments, thermo-luminescent, MOS transistor and PIN diode sensors for x-ray, gamma, charged particles and neutron irradiation are disposed on the micro-platform. In a preferred embodiment the dosimeter is fabricated using a silicon SOI starting wafer.
    Type: Grant
    Filed: June 18, 2017
    Date of Patent: November 14, 2017
    Inventor: William N. Carr
  • Patent number: 9761686
    Abstract: Techniques are provided that can impart sufficient electrical conductivity to a semiconductor crystal exhibiting low doping efficiency for silicon atoms, such as InGaAs, by implanting only a small amount of silicon atoms. Such a semiconductor wafer may include a first semiconductor crystal layer, a second semiconductor crystal layer exhibiting a conductivity type that is different from the first layer, a third semiconductor crystal layer exhibiting the conductivity type of the first layer and having a larger band gap than the second semiconductor crystal layer, and a fourth semiconductor crystal layer exhibiting the conductivity type of the first layer and having a smaller band gap than the third semiconductor crystal layer. The fourth semiconductor crystal layer contains a first element that generates a first carrier of a corresponding conductivity type and a second element that generates a second carrier of a corresponding conductivity type.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: September 12, 2017
    Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Sadanori Yamanaka, Naohiro Nishikawa, Tsuyoshi Nakano
  • Patent number: 9755093
    Abstract: Disclosed are a photoelectronic device using a hybrid structure of silica nanoparticles and graphene quantum dots and a method of manufacturing the same. The photoelectronic device according to the present disclosure has a hybrid structure including graphene quantum dots (GQDs) bonded to surfaces of silica nanoparticles (SNPs), thereby increasing energy transfer efficiency.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: September 5, 2017
    Assignee: UNIVERSITY-INDUSTRY COOPERATION GROUP OF KYUNG HEE UNIVERSITY
    Inventors: Suk Ho Choi, Sung Kim
  • Patent number: 9748976
    Abstract: Systems and methods are provided for quantum error correction. A quantum system includes an array of qubits configured to store an item of quantum information. The array of qubits includes a plurality of data qubits and a plurality of measurement qubits configured to extract a syndrome representing agreement among the plurality of data qubits. The quantum system further includes an integrated circuit comprising validation logic configured to determine if the syndrome is valid, decoding logic configured to determine evaluate the syndrome to determine location of errors within the plurality of data qubits, and an error register configured to store locations of the determined errors.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: August 29, 2017
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Ofer Naaman, Bryan K. Eastin
  • Patent number: 9735292
    Abstract: A Schottky diode is formed on a silicon support. A non-doped GaN layer overlies the silicon support. An AlGaN layer overlies the non-doped GaN layer. A first metallization forming an ohmic contact and a second metallization forming a Schottky contact are provided in and on the AlGaN layer. First vias extend from the first metallization towards the silicon support. Second vias extend from the second metallization towards an upper surface.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: August 15, 2017
    Assignee: STMicroelectronics (Tours) SAS
    Inventor: Arnaud Yvon
  • Patent number: 9735547
    Abstract: Optical devices having a structured active region configured for selected wavelengths of light emissions are disclosed.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: August 15, 2017
    Assignee: Soraa Laser Diode, Inc.
    Inventor: James W. Raring
  • Patent number: 9722058
    Abstract: This disclosure relates to bipolar transistors, such as heterojunction bipolar transistors, having at a doping spike in the collector. The doping spike can be disposed relatively near an interface between the collector and the base. For instance, the doping spike can be disposed within half of the thickness of the collector from the interface between the collector and the base. Such bipolar transistors can be implemented, for example, in power amplifiers.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: August 1, 2017
    Assignee: Skyworks Solutions, Inc.
    Inventors: Peter J. Zampardi, Jr., Kai Hay Kwok
  • Patent number: 9722165
    Abstract: A thermoelectric pixel includes a micro-platform and a device layer having one or more support layers suspended at a perimeter thereof. The pixel includes structures which reduce thermal conductivity and improve platform planarity. In embodiments providing an infrared sensor, carbon nanotubes are used to enhance infrared absorption into the sensor pixel. In other embodiments, the pixel provides a thermoelectric energy harvester.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: August 1, 2017
    Inventor: William N. Carr
  • Patent number: 9647084
    Abstract: A semiconductor device includes: a first electrode; a second electrode; an interlayer insulating film made of a porous insulating material and formed above the first electrode and the second electrode; and connection parts electrically connected to the first electrode and the second electrode respectively, wherein a cavity is formed between the interlayer insulating film and a surface of the first electrode, a surface of the second electrode, and parts of surfaces of the connection parts.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: May 9, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Shirou Ozaki, Naoya Okamoto, Kozo Makiyama, Toshihiro Ohki
  • Patent number: 9620618
    Abstract: A method for forming a transistor is provided. The method includes: forming a channel layer over a substrate; forming a barrier layer between the channel layer and the substrate; forming a recess that extends into the barrier layer through the channel layer; and forming a source layer in the recess.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: April 11, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chien-Hsun Wang, Mao-Lin Huang, Chun-Hsiung Lin
  • Patent number: 9614056
    Abstract: One illustrative method disclosed herein includes, among other things, forming a fin that is positioned above and vertically spaced apart from an upper surface of a semiconductor substrate, the fin having an upper surface, a lower surface and first and second side surfaces, wherein an axis of the fin in a height direction of the fin is oriented substantially parallel to the upper surface of the substrate, and wherein a first side surface of the fin contacts a first insulating material, forming a gate structure around the upper surface, the second side surface and the lower surface of the fin, and forming a gate contact structure that is conductively coupled to the gate structure.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: April 4, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Andreas Knorr
  • Patent number: 9608075
    Abstract: A compound semiconductor device includes a first III-nitride buffer layer doped with carbon and/or iron, a second III-nitride buffer layer above the first III-nitride buffer layer and doped with carbon and/or iron, a first III-nitride device layer above the second III-nitride buffer layer, and a second III-nitride device layer above the first III-nitride device layer and having a different band gap than the first III-nitride device layer. A two-dimensional charge carrier gas arises along an interface between the first and second III-nitride device layers. The first III-nitride buffer layer has an average doping concentration of carbon and/or iron which is greater than that of the second III-nitride buffer layer. The second III-nitride buffer layer has an average doping concentration of carbon and/or iron which is comparable to or greater than that of the first III-nitride device layer. A method of manufacturing the compound semiconductor device is described.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: March 28, 2017
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Jianwei Wan, Mihir Tungare, Peter Kim, Seong-Eun Park, Scott Nelson, Srinivasan Kannan
  • Patent number: 9608094
    Abstract: A Tunnel Field-Effect Transistor (TFET) device is provided comprising at least one heterosection between the source region and the channel region. The at least one heterosection has a low dielectric constant and thickness below 10 nm. Additionally a pocket region and another heterosection may be added in between the at least one heterosection and the channel region.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: March 28, 2017
    Assignee: IMEC VZW
    Inventors: Anne S. Verhulst, Geoffrey Pourtois, Rita Rooyackers
  • Patent number: 9601529
    Abstract: A nanowire array is described herein. The nanowire array comprises a substrate and a plurality of nanowires extending essentially vertically from the substrate; wherein: each of the nanowires has uniform chemical along its entire length; a refractive index of the nanowires is at least two times of a refractive index of a cladding of the nanowires. This nanowire array is useful as a photodetector, a submicron color filter, a static color display or a dynamic color display.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: March 21, 2017
    Assignees: ZENA TECHNOLOGIES, INC., PRESIDENT AND FELLOWS OF HARVARD COLLEGE
    Inventors: Kwanyong Seo, Munib Wober, Paul Steinvurzel, Ethan Schonbrun, Yaping Dan, Kenneth Crozier
  • Patent number: 9570300
    Abstract: A strain relaxed buffer layer of a second semiconductor material and of a second lattice constant and containing misfit dislocation defects and threading dislocation defects is formed atop a surface of a first semiconductor material of a first lattice constant that differs from the second lattice constant. The surface of the first semiconductor material includes at least one recessed region and adjoining non-recessed regions. An anneal is then performed on the strain relaxed buffer layer to propagate and amass the misfit dislocation defects and threading dislocation defects at a sidewall of each of the non-recessed regions of the first semiconductor material.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: February 14, 2017
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Patent number: 9568750
    Abstract: An optical modulator includes an input port, a first waveguide region comprising silicon and optically coupled to the input port, and a waveguide splitter optically coupled to the first waveguide region and having a first output and a second output. The optical modulator also includes a first phase adjustment section optically coupled to the first output and comprising a first III-V diode and a second phase adjustment section optically coupled to the second output and comprising a second III-V diode. The optical modulator further includes a waveguide coupler optically coupled to the first phase adjustment section and the second phase adjustment section, a second waveguide region comprising silicon and optically coupled to the waveguide coupler, and an output port optically coupled to the second waveguide region.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: February 14, 2017
    Assignee: Skorpios Technologies, Inc.
    Inventors: John Y. Spann, Derek Van Orden, Amit Mizrahi, Timothy Creazzo, Elton Marchena, Robert J. Stone, Stephen B. Krasulick
  • Patent number: 9553426
    Abstract: Optical devices having a structured active region configured for selected wavelengths of light emissions are disclosed.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: January 24, 2017
    Assignee: SORAA LASER DIODE, INC.
    Inventor: James W. Raring
  • Patent number: 9536967
    Abstract: A device includes a III-N layer having an upper side and a lower side, the lower side being opposite the upper side, and at least one conductive contact on the upper side of the III-N layer, the conductive contact extending into the III-N layer. The conductive contact comprises a top side facing away from the lower side of the III-N layer, and a bottom side facing towards the lower side of the III-N layer. The bottom side includes a first end and a second end opposite the first end, a first side rising from the first end to an intermediate point closer to the top side than the first end, and a second side falling from the intermediate point to the second end further from the top side than the intermediate point.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: January 3, 2017
    Assignee: Transphorm Inc.
    Inventors: Toshihide Kikkawa, Kenji Kiuchi, Tsutomu Hosoda, Masahito Kanamura, Akitoshi Mochizuki
  • Patent number: 9523815
    Abstract: A thyristor may include a first optical waveguide segment in a semiconductor material, having first and second complementary longitudinal parts of opposite conductivity types configured to form a longitudinal bipolar junction therebetween. The thyristor may further include a second optical waveguide segment in a semiconductor material, adjacent the first waveguide segment and having first and second complementary longitudinal parts of opposite conductivity types configured to form a longitudinal bipolar junction therebetween. A transverse bipolar junction may be between the second longitudinal portions of the first and second waveguide segments. An electrical insulator may separate each of the first longitudinal portions from the waveguide segment adjacent thereto.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: December 20, 2016
    Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Jean-Robert Manouvrier, Estelle Batail
  • Patent number: 9520526
    Abstract: A manufacturing method of an avalanche photodiode includes: forming a p-type field relaxation layer on a substrate; forming a cap layer on the p-type field relaxation layer; and forming a light absorbing layer on the cap layer, wherein a carbon is doped in the p-type field relaxation layer as a p-type dopant, the p-type field relaxation layer contains Al in a crystal composition, and a temperature-rise process from a growth temperature of the cap layer to a growth temperature of the light absorbing layer is performed in an inactive gas atmosphere without introducing a group V raw material.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: December 13, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Harunaka Yamaguchi, Susumu Hatakenaka
  • Patent number: 9472686
    Abstract: One aspect of the invention relates to a gate-tunable p-n heterojunction diode including a vertical stacked heterojunction of two ultrathin semiconductors. In one embodiment, single-layer molybdenum disulphide of an n-type semiconductor are stacked below semiconducting single-walled carbon nanotubes of a p-type semiconductor with each of them connected to a gold electrodes to form a p-n heterojunction. The electrical properties of the p-n heterojunction can be modulated by a gate voltage applied to a gate electrode and range from an insulator to a linear-response resistor to a highly rectifying diode. The gate tunability of the p-n heterojunction also allows spectral control over the photoresponse.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: October 18, 2016
    Assignee: NORTHWESTERN UNIVERSITY
    Inventors: Mark C. Hersam, Deep M. Jariwala, Vinod K. Sangwan
  • Patent number: 9466746
    Abstract: Using a multiple layer, varied composition barrier layer in place of the typical single layer barrier layer of an infrared photodetector results in a device with increased sensitivity and reduced dark current. A first barrier is adjacent the semiconductor contact; a second barrier layer is between the first barrier layer and the absorber layer. The barrier layers may be doped N type or P type with Beryllium, Carbon, Silicon or Tellurium. The energy bandgap is designed to facilitate minority carrier current flow in the contact region and block minority current flow outside the contact region.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: October 11, 2016
    Assignee: HRL Laboratories, LLC
    Inventors: Terence J De Lyon, Rajesh D Rajavel, Hasan Sharifi
  • Patent number: 9437725
    Abstract: A semiconductor device is provided, which includes a barrier layer 14 formed on a substrate 10 and made of InxAlyGa1-x-yN, a channel layer 16 formed on the barrier layer and made of GaN or InGaN, an electron supplying layer 18 formed on the channel layer and made of AlGaN, InAlN, or InAlGaN, and a gate electrode and ohmic electrodes 24 and 26 formed on the electron supplying layer. Relations between x and y for the barrier layer of x>0, y>0, x+y?1, and 0.533x<y<4.20x are satisfied.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: September 6, 2016
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Ken Nakata
  • Patent number: 9391140
    Abstract: A method of fabricating raised fin structures is provided, the fabricating including: providing a substrate and at least one dielectric layer over the substrate; forming a trench in the at least one dielectric layer, the trench having a lower portion, a lateral portion, and an upper portion, the upper portion being at least partially laterally offset from the lower portion and being joined to the lower portion by the lateral portion; and, growing a material in the trench to form the raised fin structure, wherein the trench is formed to ensure that any growth defect in the lower portion of the trench terminates either in the lower portion or the lateral portion of the trench and does not extend into the upper portion of the trench.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: July 12, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yi Qi, Xunyuan Zhang, Catherine B. Labelle
  • Patent number: 9356430
    Abstract: Optical devices having a structured active region configured for selected wavelengths of light emissions are disclosed.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: May 31, 2016
    Assignee: Soraa Laser Diode, Inc.
    Inventor: James W. Raring
  • Patent number: 9312442
    Abstract: A light emitting diode (LED) structure includes a plurality of devices arranged side by side on a support layer. Each device includes a first conductivity type semiconductor nanowire core and an enclosing second conductivity type semiconductor shell for forming a pn or pin junction that in operation provides an active region for light generation. A first electrode layer extends over the plurality of devices and is in electrical contact with at least a top portion of the devices to connect to the shell. The first electrode layer is at least partly air-bridged between the devices.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: April 12, 2016
    Assignee: GLO AB
    Inventor: Truls Lowgren
  • Patent number: 9312436
    Abstract: According to one embodiment, a nitride semiconductor device includes a first layer and a functional layer. The first layer is formed on an amorphous layer, includes aluminum nitride, and has a compressive strain or a tensile strain. The functional layer is formed on the first layer and includes a nitride semiconductor.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 12, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Ono, Tomonari Shioda, Naoharu Sugiyama, Toshiyuki Oka, Shinya Nunoue
  • Patent number: 9293612
    Abstract: Using a multiple layer, varied composition barrier layer in place of the typical single layer barrier layer of an infrared photodetector results in a device with increased sensitivity and reduced dark current. A first barrier is adjacent the semiconductor contact; a second barrier layer is between the first barrier layer and the absorber layer. The barrier layers may be doped N type or P type with Beryllium, Carbon, Silicon or Tellurium. The energy bandgap is designed to facilitate minority carrier current flow in the contact region and block minority current flow outside the contact region.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: March 22, 2016
    Assignee: HRL Laboratories, LLC
    Inventors: Terence J De Lyon, Rajesh D Rajavel, Hasan Sharifi
  • Patent number: 9281363
    Abstract: A semiconductor structure includes a first gate-all-around (GAA) structure configured to form a first circuit and a second GAA structure configured to form a second circuit similar to the first circuit. The first GAA structure and the second GAA structure have a same of at least one of the following exemplary features: a number of GAA devices in which current flows from a first oxide definition (OD) region to a second OD region; a number of GAA devices in which current flows from the second OD region to the first OD region; a number of first OD region contact elements; a number of second OD region contact elements.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: March 8, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Chung-Hui Chen
  • Patent number: 9276084
    Abstract: A method for forming a transistor is provided. The method includes: forming a channel layer over a substrate; patterning the channel layer to form a recess; and forming a source layer in the recess, such that at least a portion of the channel layer protrudes to form the fin-type channel.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: March 1, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chien-Hsun Wang, Mao-Lin Huang, Chun-Hsiung Lin
  • Patent number: 9269788
    Abstract: A solution for forming an ohmic contact to a semiconductor layer is provided. A masking material is applied to a set of contact regions on the surface of the semiconductor layer. Subsequently, one or more layers of a device heterostructure are formed on the non-masked region(s) of the semiconductor layer. The ohmic contact can be formed after the one or more layers of the device heterostructure are formed. The ohmic contact formation can be performed at a processing temperature lower than a temperature range within which a quality of a material forming any semiconductor layer in the device heterostructure is damaged.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: February 23, 2016
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Remigijus Gaska, Michael Shur, Jinwei Yang, Alexander Dobrinsky, Maxim S Shatalov
  • Patent number: 9257500
    Abstract: A method for fabricating a vertical GaN power device includes providing a first GaN material having a first conductivity type and forming a second GaN material having a second conductivity type and coupled to the first GaN material to create a junction. The method further includes implanting ions through the second GaN material and into a first portion of the first GaN material to increase a doping concentration of the first conductivity type. The first portion of the junction is characterized by a reduced breakdown voltage relative to a breakdown voltage of a second portion of the junction.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: February 9, 2016
    Assignee: Avogy, Inc.
    Inventor: Donald R. Disney
  • Patent number: 9240516
    Abstract: Amongst the candidates for very high efficiency electronics, solid state light sources, photovoltaics, and photoelectrochemical devices, and photobiological devices are those based upon metal-nitride nanowires. Enhanced nanowire performance typically require heterostructures, quantum dots, etc which requirement that these structures are grown with relatively few defects and in a controllable reproducible manner. Additionally flexibility according to the device design requires that the nanowire at the substrate may be either InN or GaN. Methods of growing relatively defect free nanowires and associated structures for group IIIA-nitrides are presented without the requirement for foreign metal catalysts, overcoming the non-uniform growth of prior art techniques and allowing self-organizing quantum dot, quantum well and quantum dot-in-a-dot structures to be formed.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: January 19, 2016
    Assignee: The Royal Institution for the Advancement of Learning/McGill University
    Inventors: Zetian Mi, Md Golam Kibria