Heterojunction Patents (Class 257/12)
  • Patent number: 10790335
    Abstract: A method for making a metal oxide semiconductor carbon nanotube thin film transistor circuit. A p-type carbon nanotube thin film transistor and a n-type carbon nanotube thin film transistor are formed on an insulating substrate and stacked with each other. The p-type carbon nanotube thin film transistor includes a first semiconductor carbon nanotube layer, a first drain electrode, a first source electrode, a functional dielectric layer, and a first gate electrode. The n-type carbon nanotube thin film transistor includes a second semiconductor carbon nanotube layer, a second drain electrode, a second source electrode, a first insulating layer, and a second gate electrode. The first drain electrode and the second drain electrode are electrically connected with each other. The first gate electrode and the second gate electrode are electrically connected with each other.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: September 29, 2020
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yu-Dan Zhao, Qun-Qing Li, Xiao-Yang Xiao, Guan-Hong Li, Yuan-Hao Jin, Shou-Shan Fan
  • Patent number: 10784213
    Abstract: A power device package includes a substrate, a high side power device, a low side power device and a driver device. The substrate includes a top surface, a bottom surface and a plurality of vias that extend through the substrate. The high side and low side power devices are disposed on the top surface of the substrate and connected with each other. The driver device is disposed on the bottom surface of the substrate and electrically connected with the high side and low side power devices through the vias to drive the high side and low side power devices in response to a control signal. The distance between the driver device and the high side and low side power devices is determined by the thickness of the substrate such that that a parasitic inductance between the driver device and the high side power device or the low side power device is reduced.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: September 22, 2020
    Assignee: Hong Kong Applied Science and Technology Research Institute Company Limited
    Inventors: Ziyang Gao, Shek Mong Wong, Tak Lok Shum
  • Patent number: 10763385
    Abstract: A device having a multi-junction solar cell and a protection diode structure, whereby the multi-junction solar cell and the protection diode structure have a common rear surface and front sides separated by a mesa trench. The common rear surface comprises an electrically conductive layer, and the light enters through the front side into the multi-junction solar cell. The cell includes a stack of a plurality of solar cells, and has a top cell, placed closest to the front side, and a bottom solar cell, placed closest to the rear side, and a tunnel diode is placed between adjacent solar cells. The number of semiconductor layers in the protection diode structure is smaller than the number of semiconductor layers in the multi-junction solar cell. The sequence of the semiconductor layers in the protection diode structure corresponds to the sequence of semiconductor layers of the multi-junction solar cell.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: September 1, 2020
    Assignee: Azur Space Solar Power GmbH
    Inventors: Matthias Meusel, Wolfgang Koestler, Daniel Fuhrmann, Thomas Lauermann
  • Patent number: 10700188
    Abstract: A semiconductor device is provided with, a group-III nitride semiconductor layered structure that includes a heterojunction, an insulating layer which has a gate opening that reaches the group-III nitride semiconductor layered structure and which is disposed on the group-III nitride semiconductor layered structure, a gate insulating film that covers the bottom and the side of the gate opening, a gate electrode defined on the gate insulating film inside the gate opening, a source electrode and a drain electrode which are disposed to be spaced apart from the gate electrode so as to sandwich the gate electrode, a first conductive layer embedded in the insulating layer between the gate electrode and the drain electrode, and a second conductive layer that is embedded in the insulating layer above the first conductive layer in a region closer to the drain electrode side than the first conductive layer.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: June 30, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Kentaro Chikamatsu
  • Patent number: 10686042
    Abstract: A semiconductor device includes: a substrate; a first nitride semiconductor layer disposed on the substrate; a second nitride semiconductor layer disposed on the first nitride semiconductor layer; a first opening penetrating the second nitride semiconductor layer; an electron transit layer and an electron supply layer which are formed along an upper surface of the second nitride semiconductor layer and a recessed surface of the first opening; a gate electrode disposed above the electron supply layer; a second opening penetrating the electron supply layer and the electron transit layer; a source electrode disposed to cover the second opening and electrically connected to the second nitride semiconductor layer; and a drain electrode disposed on a back surface of the substrate. The electron supply layer has a side surface formed along a side surface of the first opening. The gate electrode is not disposed on the side surface of the electron supply layer.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: June 16, 2020
    Assignee: PANASONIC CORPORATION
    Inventors: Shinji Ujita, Daisuke Shibata, Satoshi Tamura
  • Patent number: 10680118
    Abstract: In a method of manufacturing a semiconductor integrated circuit device, an active region including a nano-wire may be formed on a bulk insulating layer. A hard mask pattern may be formed to partially expose the nano-wire. A work function-controlling region may be formed on the nano-wire exposed through the hard mask pattern. The hard mask pattern may be removed. A gate insulating layer may be formed on the nano-wire. A gate may be formed to surround the nano-wire.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: June 9, 2020
    Assignee: SK hynix Inc.
    Inventor: Dong Yean Oh
  • Patent number: 10680115
    Abstract: Substrates, assemblies, and techniques for enabling a p-channel oxide semiconductor. For example, some embodiments can include an oxide semiconductor, where the oxide semiconductor includes an indium gallium zinc oxide (IGZO) sulfur alloy as a semiconducting material. The semiconducting material can be included in a thin-film-transistor that includes one or more p-channels.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: June 9, 2020
    Assignee: Intel Corporation
    Inventors: Khaled Ahmed, Prashant Majhi
  • Patent number: 10669477
    Abstract: A method for manufacturing a quantum dot and a quantum dot are provided. The method includes adding a core semiconductor precursor solution into a seed composition solution. The seed composition solution includes a seed composition, and the seed composition is a dendrimer-metal nanoparticle composite. The core semiconductor precursor solution includes a first semiconductor ion and a second semiconductor ion. The method also includes carrying out a first synthesis reaction to form a core semiconductor material wrapping the seed composition. The core semiconductor material is formed by combining the first semiconductor ion with the second semiconductor ion.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: June 2, 2020
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yi-Chun Liu, Yu-Yang Su, Chun-Hsiang Wen
  • Patent number: 10646921
    Abstract: Described herein are metallic excavated nanoframes and methods for producing metallic excavated nanoframes. A method may include providing a solution including a plurality of excavated nanoparticles dispersed in a solvent, and exposing the solution to chemical corrosion to convert the plurality of excavated nanoparticles into a plurality of excavated nanoframes.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: May 12, 2020
    Assignee: The Regents of the University of California
    Inventors: Peidong Yang, Nigel H. Becknell, Yoonkook Son
  • Patent number: 10636899
    Abstract: A semiconductor device includes a type III-V semiconductor body having a main surface and a rear surface opposite the main surface. A barrier region is disposed beneath the main surface. A buffer region is disposed beneath the barrier region. A first two-dimensional charge carrier gas region forms near an interface between the barrier region and the buffer region. A second two-dimensional charge carrier gas region forms near an interface between the buffer region and the first back-barrier region. A third two-dimensional charge carrier gas region forms near an interface between the first back-barrier region and the second back-barrier region. Both of the second and third two-dimensional charge carrier gas regions have an opposite carrier type as the first two-dimensional charge carrier gas region. The third two-dimensional charge carrier gas region is more densely populated with charge carriers than the second two-dimensional charge carrier gas region.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: April 28, 2020
    Assignee: Infineon Technologies Austria AG
    Inventor: Gilberto Curatola
  • Patent number: 10629712
    Abstract: A collector layer of an HBT includes a high-concentration collector layer and a low-concentration collector layer thereon. The low-concentration collector layer includes a graded collector layer in which the energy band gap varies to narrow with increasing distance from the base layer. The electron affinity of the semiconductor material for the base layer is greater than that of the semiconductor material for the graded collector layer at the point of the largest energy band gap by about 0.15 eV or less. The electron velocity in the graded collector layer peaks at a certain electric field strength. In the graded collector layer, the strength of the quasi-electric field, an electric field that acts on electrons as a result of the varying energy band gap, is between about 0.3 times and about 1.8 times the peak electric field strength, the electric field strength at which the electron velocity peaks.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: April 21, 2020
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari Umemoto, Shigeki Koya, Isao Obu
  • Patent number: 10568514
    Abstract: Embodiments of the present disclosure include a photodiode that can detect optical radiation at a broad range of wavelengths. The photodiode can be used as a detector of a non-invasive sensor, which can be used for measuring physiological parameters of a monitored patient. The photodiode can be part of an integrated semiconductor structure that generates a detector signal responsive to optical radiation at both visible and infrared wavelengths incident on the photodiode. The photodiode can include a layer that forms part of an external surface of the photodiode, which is disposed to receive the optical radiation incident on the photodiode and pass the optical radiation to one or more other layers of the photodiode.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: February 25, 2020
    Assignee: MASIMO SEMICONDUCTOR, INC.
    Inventors: Steven J. Wojtczuk, Xuebing Zhang, William J. MacNeish, III
  • Patent number: 10551244
    Abstract: Provided is a photon detector. The photon detector includes an optical waveguide including input and detection regions, which are spaced apart from each other in a first direction, and a conversion region between the input region and the detection region, a nano pattern disposed on the optical waveguide in the conversion region, and a nanowire disposed on the optical waveguide in the detection region. The nano pattern includes a first pattern and a second pattern, which extend in the first direction, and the first pattern and the second pattern are spaced apart from each other in a second direction crossing the first direction.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: February 4, 2020
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Wook-Jae Lee, Jung Jin Ju
  • Patent number: 10516043
    Abstract: A gallium nitride based monolithic microwave integrated circuit includes a substrate, a channel layer on the substrate and a barrier layer on the channel layer. A recess is provided in a top surface of the barrier layer. First gate, source and drain electrodes are provided on the barrier layer opposite the channel layer, with a bottom surface of the first gate electrode in direct contact with the barrier layer. Second gate, source and drain electrodes are also provided on the barrier layer opposite the channel layer. A gate insulating layer is provided in the recess in the barrier layer, and the second gate electrode is on the gate insulating layer opposite the barrier layer and extending into the recess. The first gate, source and drain electrodes comprise the electrodes of a depletion mode transistor, and the second gate, source and drain electrodes comprise the electrodes of an enhancement mode transistor.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: December 24, 2019
    Assignee: Cree, Inc.
    Inventors: Saptharishi Sriram, Jennifer Qingzhu Gao, Jeremy Fisher, Scott Sheppard
  • Patent number: 10510924
    Abstract: Disclosed herein is a semiconducting nanoparticle comprising a one-dimensional semiconducting nanoparticle having a first end and a second end; where the second end is opposed to the first end; and two first endcaps, one of which contacts the first end and the other of which contacts the second end respectively of the one-dimensional semiconducting nanoparticle; where the first endcap that contacts the first end comprises a first semiconductor and where the first endcap extends from the first end of the one-dimensional semiconducting nanoparticle to form a first nanocrystal heterojunction; where the first endcap that contacts the second end comprises a second semiconductor; where the first endcap extends from the second end of the one-dimensional semiconducting nanoparticle to form a second nanocrystal heterojunction; and where the first semiconductor and the second semiconductor are chemically different from each other.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: December 17, 2019
    Assignees: The Board of Trustees of the University of Illinois, Rohm and Haas Electronic Materials LLC, Dow Global Technologies LLC
    Inventors: Moonsub Shim, Nuri Oh, You Zhai, Sooji Nam, Peter Trefonas, III, Kishori Deshpande, Jake Joo
  • Patent number: 10475651
    Abstract: A method for patterning a piece of carbon nanomaterial. The method comprises generating a first light pulse sequence with first light pulse sequence property values, the first light pulse sequence comprising at least one light pulse and exposing a first area of the piece of carbon nanomaterial to said first light pulse sequence in a first process environment having a first oxygen content, without exposing at least part of the piece of carbon nanomaterial to said first light pulse sequence. In this way, the method comprises oxidizing locally, in the first area, at least some carbon atoms of the piece of carbon nanomaterial in such a way that at most 10% of the carbon atoms of the first area are removed from the first area; thereby patterning the first area of the piece of carbon nanomaterial. In addition a processed piece of carbon nanomaterial.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: November 12, 2019
    Assignee: Jyv¿skyl¿nYliopisto
    Inventors: Mika Pettersson, Andreas Johansson, Jukka Aumanen, Pasi Myllyperkiö, Juha Koivistoinen
  • Patent number: 10383520
    Abstract: Embodiments of the present disclosure include a photodiode that can detect optical radiation at a broad range of wavelengths. The photodiode can be used as a detector of a non-invasive sensor, which can be used for measuring physiological parameters of a monitored patient. The photodiode can be part of an integrated semiconductor structure that generates a detector signal responsive to optical radiation at both visible and infrared wavelengths incident on the photodiode. The photodiode can include a layer that forms part of an external surface of the photodiode, which is disposed to receive the optical radiation incident on the photodiode and pass the optical radiation to one or more other layers of the photodiode.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: August 20, 2019
    Assignee: MASIMO SEMICONDUCTOR, INC.
    Inventors: Steven J. Wojtczuk, Xuebing Zhang, William J. MacNeish, III
  • Patent number: 10381508
    Abstract: This invention discloses a light emitting element to solve the problem of lattice mismatch and inequality of electron holes and electrons of the conventional light emitting elements. The light emitting element comprises a gallium nitride layer, a gallium nitride pyramid, an insulating layer, a first electrode and a second electrode. The gallium nitride pyramid contacts with the gallium nitride layer, with a c-axis of the gallium nitride layer opposite in direction to a c-axis of the gallium nitride pyramid, and with an M-plane of the gallium nitride layer parallel to an M-plane of the gallium nitride pyramid, with broken bonds at the mounting face of the gallium nitride layer and the larger end face of the gallium nitride pyramid welded with each other, with the gallium nitride layer and the gallium nitride pyramid being used as a p-type semiconductor and an n-type semiconductor respectively.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: August 13, 2019
    Assignee: NATIONAL SUN YAT-SEN UNIVERSITY
    Inventors: I-Kai Lo, Ying-Chieh Wang, Yu-Chi Hsu, Cheng-Hung Shih
  • Patent number: 10374110
    Abstract: An apparatus and method, the apparatus including a charge carrier wherein the charge carrier includes a continuous three dimensional framework including a plurality of cavities throughout the framework; sensor material provided throughout the charge carrier; wherein the sensor material is configured to transduce a detected input and change conductivity of the charge carrier in dependence of the detected input.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: August 6, 2019
    Assignee: Nokia Technologies Oy
    Inventors: Richard White, Elisabetta Spigone
  • Patent number: 10361353
    Abstract: Disclosed herein are fabrication techniques for providing metal gates in quantum devices, as well as related quantum devices. For example, in some embodiments, a method of manufacturing a quantum device may include providing a gate dielectric over a qubit device layer, providing over the gate dielectric a pattern of non-metallic elements referred to as “gate support elements,” and depositing a gate metal on sidewalls of the gate support elements to form a plurality of gates of the quantum device.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: July 23, 2019
    Assignee: Intel Corporation
    Inventors: Hubert C. George, Zachary R. Yoscovits, Nicole K. Thomas, Lester Lampert, James S. Clarke, Jeanette M. Roberts, Ravi Pillarisetty, David J. Michalak, Kanwaljit Singh, Roman Caudillo
  • Patent number: 10347791
    Abstract: A composition of matter comprising: a graphitic substrate optionally carried on a support; a seed layer having a thickness of no more than 50 nm deposited directly on top of said substrate, opposite any support; and an oxide or nitride masking layer directly on top of said seed layer; wherein a plurality of holes are present through said seed layer and through said masking layer to said graphitic substrate; and wherein a plurality of nanowires or nanopyramids are grown from said substrate in said holes, said nanowires or nanopyramids comprising at least one semiconducting group III-V compound.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: July 9, 2019
    Assignees: CRAYONANO AS, NORWEGIAN UNIVERSITY OF SCIENCE AND TECHNOLOGY (NTNU)
    Inventors: Dong Chul Kim, Ida Marie E. Høiaas, Carl Philip J. Heimdal, Bjørn Ove M. Fimland, Helge Weman
  • Patent number: 10333001
    Abstract: A fin structure disposed over a substrate and a method of forming a fin structure are disclosed. The fin structure includes a mesa, a channel disposed over the mesa, and a convex-shaped feature disposed between the channel and the mesa. The mesa has a first semiconductor material, and the channel has a second semiconductor material different from the first semiconductor material. The convex-shaped feature is stepped-shaped, stair-shaped, or ladder-shaped. The convex-shaped feature includes a first isolation feature disposed between the channel and the mesa, and a second isolation feature disposed between the channel and the first isolation feature. The first isolation feature is U-shaped, and the second isolation feature is rectangular-shaped. A portion of the second isolation feature is surrounded by the channel and another portion of the second isolation feature is surrounded by the first isolation feature.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: June 25, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Gin-Chen Huang, Ching-Hong Jiang, Neng-Kuo Chen, Sey-Ping Sun, Clement Hsingjen Wann
  • Patent number: 10312176
    Abstract: A semiconductor device comprises: a substrate; a multi-layer semiconductor layer located on the substrate, the multi-layer semiconductor layer being divided into an active area and a passive area outside the active area; a gate electrode, a source electrode and a drain electrode all located on the multi-layer semiconductor layer and within the active area; and a heat dissipation layer covering at least one portion of the active area and containing a heat dissipation material. In embodiments of the present invention, a heat dissipation layer covering at least one portion of the active area is provided in the semiconductor device. The arrangement of the heat dissipation layer adds a heat dissipation approach for the semiconductor device in the planar direction, thus the heat dissipation effect of the semiconductor device is improved.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: June 4, 2019
    Assignee: GPOWER SEMICONDUCTOR, INC.
    Inventors: Yi Pei, Mengjie Zhou
  • Patent number: 10261139
    Abstract: A method of making a magnetic field sensor using in situ solid source graphene and graphene induced anti-ferromagnetic coupling and spin filtering, comprising providing a substrate comprising silicon wafers and thermal oxide, performing DC magnetron sputtering, back-sputtering the substrate, growing amorphous carbon on the substrate, sputtering and growing a first ferromagnetic metal surface on the amorphous carbon, annealing the substrate and the amorphous carbon and the first ferromagnetic metal surface, forming a graphene film on the first ferromagnetic metal surface, wherein the first ferromagnetic metal surface comprises NiFe, sputtering and growing a second ferromagnetic film on the graphene film, and capping the second ferromagnetic film with a platinum layer.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: April 16, 2019
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Olaf M. J. van 't Erve, Enrique Cobas, Shu-Fan Cheng, Berend T. Jonker
  • Patent number: 10243321
    Abstract: A laser package for use in a dermatological treatment device may include a conductive carrier, an insulation layer arranged over a first region of a first side of the conductive carrier, a semiconductor laser device mounted to a second region of the first side of the conductive carrier, and a conductive film secured to the semiconductor laser device and extending over at least a portion of the insulation layer, such that the conductive film is insulated from the conductive carrier by the insulation layer, and wherein a coefficient of thermal expansion of the semiconductor laser device differs from a coefficient of the conductive carrier to which it is mounted by more than 20%.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: March 26, 2019
    Assignee: CHANNEL INVESTMENTS, LLC
    Inventors: Patrick Reichert, Harvey I-Heng Liu
  • Patent number: 10177199
    Abstract: A method for making a metal oxide semiconductor carbon nanotube thin film transistor circuit. A p-type carbon nanotube thin film transistor and a n-type carbon nanotube thin film transistor are formed on an insulating substrate and stacked with each other. The p-type carbon nanotube thin film transistor includes a first semiconductor carbon nanotube layer, a first drain electrode, a first source electrode, a functional dielectric layer, and a first gate electrode. The n-type carbon nanotube thin film transistor includes a second semiconductor carbon nanotube layer, a second drain electrode, a second source electrode, a first insulating layer, and a second gate electrode. The first drain electrode and the second drain electrode are electrically connected with each other. The first gate electrode and the second gate electrode are electrically connected with each other.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: January 8, 2019
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yu-Dan Zhao, Qun-Qing Li, Xiao-Yang Xiao, Guan-Hong Li, Yuan-Hao Jin, Shou-Shan Fan
  • Patent number: 10158010
    Abstract: This disclosure relates to methods of forming bipolar transistors, such as heterojunction bipolar transistors. The methods may include forming a sub-collector over a substrate, forming a first portion of a collector over the sub-collector and doping a second portion of the collector to form a doping spike. The method may further include forming a third portion of the collector over the doping spike and forming a base of the bipolar transistor over the third portion of the collector.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: December 18, 2018
    Assignee: Skyworks Solutions, Inc.
    Inventors: Peter J. Zampardi, Jr., Kai Hay Kwok
  • Patent number: 10121902
    Abstract: In a method of manufacturing a semiconductor integrated circuit device, an active region including a nano-wire may be formed on a bulk insulating layer. A hard mask pattern may be formed to partially expose the nano-wire. A work function-controlling region may be formed on the nano-wire exposed through the hard mask pattern. The hard mask pattern may be removed. A gate insulating layer may be formed on the nano-wire. A gate may be formed to surround the nano-wire.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: November 6, 2018
    Assignee: SK Hynix Inc.
    Inventor: Dong Yean Oh
  • Patent number: 10043944
    Abstract: A light-emitting diode (LED) epitaxial structure includes, from bottom to up, a substrate, a first conductive type semiconductor layer, a super lattice, a multi-quantum well layer with V pits, a hole injection layer and a second conductive type semiconductor layer. The hole injection layer appears in the shape of dual hexagonal pyramid, which fills up the V pits and embeds in the second conductive type semiconductor layer. Various embodiments of the present disclosures can effectively reduce point defect density and dislocation density of semiconductor material and effectively enlarge hole injection area and improves hole injection efficiency.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: August 7, 2018
    Assignee: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Jie Zhang, Xueliang Zhu, Chengxiao Du, Jianming Liu, Chen-ke Hsu
  • Patent number: 9960263
    Abstract: A field effect transistor according to the present invention includes a semiconductor layer including a groove, an insulating film formed on an upper surface of the semiconductor layer and having an opening above the groove and a gate electrode buried in the opening to be in contact with side surfaces and a bottom surface of the groove and having parts being in contact with an upper surface of the insulating film on both sides of the opening, wherein the gate electrode has a T-shaped sectional shape in which a width of an upper end is larger than a width of the upper surface of the insulating film.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: May 1, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventor: Takahiro Nakamoto
  • Patent number: 9954129
    Abstract: Described herein are materials and systems for efficient upconversion of photons. The materials may be disposed in a system comprising two semiconductor materials with an interface therebetween, the interface comprising a valence and/or conduction band offset between the semiconducting materials of about ?0.5 eV to about 0.5 eV, including 0, wherein one of the semiconductor materials is a material with discrete energy states and the other is a material with a graded composition and/or controlled band gap. The system can upconvert photons by: a) controlling energy levels of discrete energy states of a semiconducting material in a system to direct tunneling and exciton separation; b) controlling a compositional profile of another semiconducting material in the system to funnel charges away from an upconversion region and into a recombination zone; and c) utilizing the discrete energy states of the semiconducting material in the system to inhibit phonon relaxation.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 24, 2018
    Assignee: UNIVERSITY OF DELAWARE
    Inventors: Matthew Doty, Joshua Zide
  • Patent number: 9882042
    Abstract: Provided are a group 13 nitride composite substrate allowing for the production of a semiconductor device suitable for high-frequency applications while including a conductive GaN substrate, and a semiconductor device produced using this substrate. The group 13 nitride composite substrate includes a base material of an n-conductivity type formed of GaN, a base layer located on the base material, being a group 13 nitride layer having a resistivity of 1×106 ?·cm or more, a channel layer located on the base layer, being a GaN layer having a total impurity density of 1×1017/cm3 or less, and a barrier layer that is located on the channel layer and is formed of a group 13 nitride having a composition AlxInyGa1?x?yN (0?x?1, 0?y?1).
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: January 30, 2018
    Assignee: NGK INSULATORS, LTD.
    Inventors: Yoshitaka Kuraoka, Mikiya Ichimura, Makoto Iwai
  • Patent number: 9825418
    Abstract: A laser-oscillation cooling device includes a laser excitation unit that excites a laser beam and locally emits heat, a storage tank that is capable of storing a cryogenic liquid at an atmospheric pressure and discharge the cryogenic liquid which is evaporated, a pressurization and supply unit that pressurizes the cryogenic liquid stored in the storage tank and supplies the pressurized cryogenic liquid to the laser excitation unit, and a decompression and return unit that decompresses the cryogenic liquid which is supplied to the laser excitation unit and used to cool the laser excitation unit and returns the cryogenic liquid to the storage tank.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: November 21, 2017
    Assignee: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Jiro Kasahara, Yoshiyuki Kondo, Shinya Ishii, Koichi Hamamoto
  • Patent number: 9817130
    Abstract: A radiation dosimeter comprising a thermal micro-platform with a plurality of nanowires having phononic structures providing improved thermal isolation of the micro-platform. In embodiments, thermo-luminescent, MOS transistor and PIN diode sensors for x-ray, gamma, charged particles and neutron irradiation are disposed on the micro-platform. In a preferred embodiment the dosimeter is fabricated using a silicon SOI starting wafer.
    Type: Grant
    Filed: June 18, 2017
    Date of Patent: November 14, 2017
    Inventor: William N. Carr
  • Patent number: 9761686
    Abstract: Techniques are provided that can impart sufficient electrical conductivity to a semiconductor crystal exhibiting low doping efficiency for silicon atoms, such as InGaAs, by implanting only a small amount of silicon atoms. Such a semiconductor wafer may include a first semiconductor crystal layer, a second semiconductor crystal layer exhibiting a conductivity type that is different from the first layer, a third semiconductor crystal layer exhibiting the conductivity type of the first layer and having a larger band gap than the second semiconductor crystal layer, and a fourth semiconductor crystal layer exhibiting the conductivity type of the first layer and having a smaller band gap than the third semiconductor crystal layer. The fourth semiconductor crystal layer contains a first element that generates a first carrier of a corresponding conductivity type and a second element that generates a second carrier of a corresponding conductivity type.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: September 12, 2017
    Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Sadanori Yamanaka, Naohiro Nishikawa, Tsuyoshi Nakano
  • Patent number: 9755093
    Abstract: Disclosed are a photoelectronic device using a hybrid structure of silica nanoparticles and graphene quantum dots and a method of manufacturing the same. The photoelectronic device according to the present disclosure has a hybrid structure including graphene quantum dots (GQDs) bonded to surfaces of silica nanoparticles (SNPs), thereby increasing energy transfer efficiency.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: September 5, 2017
    Assignee: UNIVERSITY-INDUSTRY COOPERATION GROUP OF KYUNG HEE UNIVERSITY
    Inventors: Suk Ho Choi, Sung Kim
  • Patent number: 9748976
    Abstract: Systems and methods are provided for quantum error correction. A quantum system includes an array of qubits configured to store an item of quantum information. The array of qubits includes a plurality of data qubits and a plurality of measurement qubits configured to extract a syndrome representing agreement among the plurality of data qubits. The quantum system further includes an integrated circuit comprising validation logic configured to determine if the syndrome is valid, decoding logic configured to determine evaluate the syndrome to determine location of errors within the plurality of data qubits, and an error register configured to store locations of the determined errors.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: August 29, 2017
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Ofer Naaman, Bryan K. Eastin
  • Patent number: 9735292
    Abstract: A Schottky diode is formed on a silicon support. A non-doped GaN layer overlies the silicon support. An AlGaN layer overlies the non-doped GaN layer. A first metallization forming an ohmic contact and a second metallization forming a Schottky contact are provided in and on the AlGaN layer. First vias extend from the first metallization towards the silicon support. Second vias extend from the second metallization towards an upper surface.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: August 15, 2017
    Assignee: STMicroelectronics (Tours) SAS
    Inventor: Arnaud Yvon
  • Patent number: 9735547
    Abstract: Optical devices having a structured active region configured for selected wavelengths of light emissions are disclosed.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: August 15, 2017
    Assignee: Soraa Laser Diode, Inc.
    Inventor: James W. Raring
  • Patent number: 9722058
    Abstract: This disclosure relates to bipolar transistors, such as heterojunction bipolar transistors, having at a doping spike in the collector. The doping spike can be disposed relatively near an interface between the collector and the base. For instance, the doping spike can be disposed within half of the thickness of the collector from the interface between the collector and the base. Such bipolar transistors can be implemented, for example, in power amplifiers.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: August 1, 2017
    Assignee: Skyworks Solutions, Inc.
    Inventors: Peter J. Zampardi, Jr., Kai Hay Kwok
  • Patent number: 9722165
    Abstract: A thermoelectric pixel includes a micro-platform and a device layer having one or more support layers suspended at a perimeter thereof. The pixel includes structures which reduce thermal conductivity and improve platform planarity. In embodiments providing an infrared sensor, carbon nanotubes are used to enhance infrared absorption into the sensor pixel. In other embodiments, the pixel provides a thermoelectric energy harvester.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: August 1, 2017
    Inventor: William N. Carr
  • Patent number: 9647084
    Abstract: A semiconductor device includes: a first electrode; a second electrode; an interlayer insulating film made of a porous insulating material and formed above the first electrode and the second electrode; and connection parts electrically connected to the first electrode and the second electrode respectively, wherein a cavity is formed between the interlayer insulating film and a surface of the first electrode, a surface of the second electrode, and parts of surfaces of the connection parts.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: May 9, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Shirou Ozaki, Naoya Okamoto, Kozo Makiyama, Toshihiro Ohki
  • Patent number: 9620618
    Abstract: A method for forming a transistor is provided. The method includes: forming a channel layer over a substrate; forming a barrier layer between the channel layer and the substrate; forming a recess that extends into the barrier layer through the channel layer; and forming a source layer in the recess.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: April 11, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chien-Hsun Wang, Mao-Lin Huang, Chun-Hsiung Lin
  • Patent number: 9614056
    Abstract: One illustrative method disclosed herein includes, among other things, forming a fin that is positioned above and vertically spaced apart from an upper surface of a semiconductor substrate, the fin having an upper surface, a lower surface and first and second side surfaces, wherein an axis of the fin in a height direction of the fin is oriented substantially parallel to the upper surface of the substrate, and wherein a first side surface of the fin contacts a first insulating material, forming a gate structure around the upper surface, the second side surface and the lower surface of the fin, and forming a gate contact structure that is conductively coupled to the gate structure.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: April 4, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Andreas Knorr
  • Patent number: 9608094
    Abstract: A Tunnel Field-Effect Transistor (TFET) device is provided comprising at least one heterosection between the source region and the channel region. The at least one heterosection has a low dielectric constant and thickness below 10 nm. Additionally a pocket region and another heterosection may be added in between the at least one heterosection and the channel region.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: March 28, 2017
    Assignee: IMEC VZW
    Inventors: Anne S. Verhulst, Geoffrey Pourtois, Rita Rooyackers
  • Patent number: 9608075
    Abstract: A compound semiconductor device includes a first III-nitride buffer layer doped with carbon and/or iron, a second III-nitride buffer layer above the first III-nitride buffer layer and doped with carbon and/or iron, a first III-nitride device layer above the second III-nitride buffer layer, and a second III-nitride device layer above the first III-nitride device layer and having a different band gap than the first III-nitride device layer. A two-dimensional charge carrier gas arises along an interface between the first and second III-nitride device layers. The first III-nitride buffer layer has an average doping concentration of carbon and/or iron which is greater than that of the second III-nitride buffer layer. The second III-nitride buffer layer has an average doping concentration of carbon and/or iron which is comparable to or greater than that of the first III-nitride device layer. A method of manufacturing the compound semiconductor device is described.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: March 28, 2017
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Jianwei Wan, Mihir Tungare, Peter Kim, Seong-Eun Park, Scott Nelson, Srinivasan Kannan
  • Patent number: 9601529
    Abstract: A nanowire array is described herein. The nanowire array comprises a substrate and a plurality of nanowires extending essentially vertically from the substrate; wherein: each of the nanowires has uniform chemical along its entire length; a refractive index of the nanowires is at least two times of a refractive index of a cladding of the nanowires. This nanowire array is useful as a photodetector, a submicron color filter, a static color display or a dynamic color display.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: March 21, 2017
    Assignees: ZENA TECHNOLOGIES, INC., PRESIDENT AND FELLOWS OF HARVARD COLLEGE
    Inventors: Kwanyong Seo, Munib Wober, Paul Steinvurzel, Ethan Schonbrun, Yaping Dan, Kenneth Crozier
  • Patent number: 9570300
    Abstract: A strain relaxed buffer layer of a second semiconductor material and of a second lattice constant and containing misfit dislocation defects and threading dislocation defects is formed atop a surface of a first semiconductor material of a first lattice constant that differs from the second lattice constant. The surface of the first semiconductor material includes at least one recessed region and adjoining non-recessed regions. An anneal is then performed on the strain relaxed buffer layer to propagate and amass the misfit dislocation defects and threading dislocation defects at a sidewall of each of the non-recessed regions of the first semiconductor material.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: February 14, 2017
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Patent number: 9568750
    Abstract: An optical modulator includes an input port, a first waveguide region comprising silicon and optically coupled to the input port, and a waveguide splitter optically coupled to the first waveguide region and having a first output and a second output. The optical modulator also includes a first phase adjustment section optically coupled to the first output and comprising a first III-V diode and a second phase adjustment section optically coupled to the second output and comprising a second III-V diode. The optical modulator further includes a waveguide coupler optically coupled to the first phase adjustment section and the second phase adjustment section, a second waveguide region comprising silicon and optically coupled to the waveguide coupler, and an output port optically coupled to the second waveguide region.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: February 14, 2017
    Assignee: Skorpios Technologies, Inc.
    Inventors: John Y. Spann, Derek Van Orden, Amit Mizrahi, Timothy Creazzo, Elton Marchena, Robert J. Stone, Stephen B. Krasulick
  • Patent number: 9553426
    Abstract: Optical devices having a structured active region configured for selected wavelengths of light emissions are disclosed.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: January 24, 2017
    Assignee: SORAA LASER DIODE, INC.
    Inventor: James W. Raring