Abstract: A field-effect transistor involves a drain electrode, a drift region, a body region, a source region, a gate insulator layer, and a gate electrode. The drift region is disposed above the drain electrode. The body region extends down into the drift region from a first upper semiconductor surface. The source region is ladder-shaped and extends down in the body region from a second upper semiconductor surface. The first and second upper semiconductor surfaces are substantially planar and are not coplanar. A first portion of the body region is surrounded laterally by a second portion of the body region. The second portion of the body region and the drift region meet at a body-to-drift boundary. The body-to-drift boundary has a central portion that is non-planar. A gate insulator layer is disposed over the source region and a gate electrode is disposed over the gate insulator.

Abstract: A semiconductor memory device includes: a lower pillar protruding from a substrate in a vertical direction and extending in a first direction by a trench formed in the first direction; an upper pillar protruding on the lower pillar in a second direction perpendicular to the first direction; a buried bit line junction region disposed on one sidewall of the lower pillar; a buried bit line contacting the buried bit line junction region and filling a portion of the trench; an etch stop film disposed on an exposed surface of the buried bit line; a first interlayer dielectric film recessed to expose a portion of an outer side of at least the upper pillar disposed on the etch stop film; a second interlayer dielectric film disposed on the first interlayer dielectric film; and a gate surrounding the exposed outer side of the upper pillar and crossing the buried bit line.

Abstract: In general, according to one embodiment, a power semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a trench, a gate insulating film, and a gate electrode. The second semiconductor layer is provided on the first semiconductor layer. The trench is provided from the second semiconductor layer to the first semiconductor layer. The gate insulating film is composed of an oxide film and a protective layer formed on the oxide film. The protective layer is opposed to the second semiconductor layer across the oxide film in the trench. The oxide film covers the second semiconductor layer exposed at a sidewall of the trench and includes at least one of aluminum and yttrium. The gate electrode is made of n-type polysilicon buried in the trench in direct contact with the gate insulating film.

Abstract: An electronic component includes a semiconductor substrate defined by a generally planar first face, a generally planar second face and side faces extending between the generally planar second face and the generally planar first face. The semiconductor substrate has a curved contour between the generally planar second face and the side faces.

Abstract: Improved MOSFET devices are obtained by incorporating strain inducing source-drain regions whose closest facing “nose” portions underlying the gate are located at different depths from the device surface. In a preferred embodiment, the spaced-apart source-drain regions may laterally overlap. This close proximity increases the favorable impact of the strain inducing source-drain regions on the carrier mobility in an induced channel region between the source and drain. The source-drain regions are formed by epitaxially refilling asymmetric cavities etched from both sides of the gate. Cavity asymmetry is obtained by forming an initial cavity proximate only one sidewall of the gate and then etching the final spaced-apart source-drain cavities proximate both sidewalls of the gate along predetermined crystallographic directions.

Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type, disposed on a surface of the first semiconductor region, and having an impurity concentration higher than that of the first semiconductor region; a trench that penetrates the second semiconductor region to reach the first semiconductor region; a first electrode disposed inside the trench via an insulating film; a first recess portion disposed deeper than an upper end of the first electrode, in a surface layer of the second semiconductor region, so as to be in contact with the trench; and a second electrode embedded in the first recess portion.

Abstract: A method is provided for fabricating a vertical insulated gate transistor. A horizontal isolation region is formed in a substrate to separate and electrically isolate upper and lower portions of the substrate. A vertical semiconductor pillar with one or more flanks and a cavity is formed so as to rest on the upper portion, and a dielectrically isolated gate is formed so as to include an internal portion within the cavity and an external portion resting on the flanks and on the upper portion. One or more internal walls of the cavity are coated with an isolating layer and the cavity is filled with a gate material so as to form the internal portion of the gate within the cavity and the external portion of the gate that rests on the flanks, and to form two connecting semiconductor regions extending between source and drain regions of the transistor.

Abstract: In order to obtain a silicon carbide semiconductor device that ensures both stability of withstand voltage and reliability in high-temperature operations in its termination end-portion provided for electric-field relaxation in the perimeter of a cell portion driven as a semiconductor element, the termination end-portion is provided with an inorganic protection film having high heat resistance that is formed on an exposed surface of a well region as a first region formed on a side of the cell portion, and an organic protection film having a high electrical insulation capability with a little influence by electric charges that is formed on a surface of an electric-field relaxation region formed in contact relation to an outer lateral surface of the well region and apart from the cell portion, and on an exposed surface of the silicon carbide layer.

Abstract: Provided is a method of manufacturing a semiconductor device. The method may include etching a first conductive type semiconductor substrate to form a first trench, forming a second trench extending from the first trench, diffusing impurities into inner walls of the second trench to form a second conductive type impurity region surrounding the second trench, forming a floating dielectric layer covering inner walls of the second trench and a floating electrode filling the second trench, and forming a gate dielectric layer covering inner walls of the first trench and a gate electrode filling the first trench.

Abstract: A wide-band-gap reverse-blocking MOS-type semiconductor device includes a SiC n?-type drift layer; a p+-type substrate on the first major surface side of the drift layer; a trench extending through a p+-type substrate into the drift layer; a titanium electrode in the trench bottom that forms a Schottky junction with the SiC n?-type drift layer; an active section including a MOS-gate structure on the second major surface side of the drift layer facing to the area, in which the Schottky junctions are formed; a breakdown withstanding section surrounding the active section; and a trench isolation layer surrounding the breakdown withstanding section, the trench isolation layer extending from the second major surface of the drift layer into p+-type substrate and including insulator film buried therein. The device facilitates making a high current flow with a low ON-voltage and exhibits a very reliable reverse blocking capability.

Abstract: A memory cell includes a thyristor having a plurality of alternately doped, vertically superposed semiconductor regions; a vertically oriented access transistor having an access gate; and a control gate operatively laterally adjacent one of the alternately doped, vertically superposed semiconductor regions. The control gate is spaced laterally of the access gate. Other embodiments are disclosed, including methods of forming memory cells and methods of forming a shared doped semiconductor region of a vertically oriented thyristor and a vertically oriented access transistor.

Abstract: Methods of making semiconductor devices such as vertical junction field effect transistors (VJFETs) or bipolar junction transistors (BJTs) are described. The methods do not require ion implantation. The VJFET device has an epitaxially regrown n-type channel layer and an epitaxially regrown p-type gate layer as well as an epitaxially grown buried gate layer. Devices made by the methods are also described.

Abstract: A semiconductor device includes: a semiconductor layer having a first end portion and a second end portion; a first main electrode provided on the first end portion and electrically connected to the semiconductor layer; a second main electrode provided on the second end portion and electrically connected to the semiconductor layer; a first gate electrode provided via a first gate insulating film in a plurality of first trenches formed from the first end portion toward the second end portion; and a second gate electrode provided via a second gate insulating film in a plurality of second trenches formed from the second end portion toward the first end portion. Spacing between a plurality of the first gate electrodes and spacing between a plurality of the second gate electrodes are 200 nm or less.

Abstract: A silicon carbide semiconductor device having a JFET or a MOSFET includes a semiconductor substrate and a trench. The semiconductor substrate has a silicon carbide substrate, a drift layer on the silicon carbide substrate, a first gate region on the drift layer, and a source region on the first gate region. The trench has a strip shape with a longitudinal direction and reaches the drift layer by penetrating the source region and the first gate region. The trench is filled with a channel layer and a second gate region on the channel layer. The source region is not located at an end portion of the trench in the longitudinal direction.

Abstract: A semiconductor layer has a first layer of first conductive type, a second layer of second conductive type, and a third layer. The third layer has a first region of first conductive type, and a second region of second conductive type. A second electrode is in contact with each of the first and second regions. A trench is formed on the semiconductor layer at a surface opposite to its surface facing a first electrode. A gate electrode is embedded in the trench with a gate insulating film interposed therebetween. The gate electrode includes a first portion projecting into the first layer through the first region and the second layer, a second portion projecting into the first layer through the second region and the second layer. The second portion projects into the first layer deeper than a depth in which the first portion projects into the first layer.

Abstract: A SiC semiconductor device includes: a SiC substrate including a first or second conductive type layer and a first conductive type drift layer and including a principal surface having an offset direction; a trench disposed on the drift layer and having a longitudinal direction; and a gate electrode disposed in the trench via a gate insulation film. A sidewall of the trench provides a channel formation surface. The vertical semiconductor device flows current along with the channel formation surface of the trench according to a gate voltage applied to the gate electrode. The offset direction of the SiC substrate is perpendicular to the longitudinal direction of the trench.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductive type, and a periodic array structure having a second semiconductor layer of a first conductive type and a third semiconductor layer of a second conductive type periodically arrayed on the first semiconductor layer in a direction parallel with a major surface of the first semiconductor layer. The second semiconductor layer and the third semiconductor layer are disposed in dots on the first semiconductor layer. A periodic structure in the outermost peripheral portion of the periodic array structure is different from a periodic structure of the periodic array structure in a portion other than the outermost peripheral portion.

Abstract: A semiconductor device includes a first trench and a second trench extending into a semiconductor body from a surface. A body region of a first conductivity type adjoins a first sidewall of the first trench and a first sidewall of the second trench, the body region including a channel portion adjoining to a source structure and being configured to be controlled in its conductivity by a gate structure. The channel portion is formed at the first sidewall of the second trench and is not formed at the first sidewall of the first trench. An electrically floating semiconductor zone of the first conductivity type adjoins the first trench and has a bottom side located deeper within the semiconductor body than the bottom side of the body region.

Abstract: A semiconductor device 100 includes: a body region 105 of a first conductivity type placed on a principal surface of a substrate 101; a silicon carbide layer 102 including a drift region 107 of a second conductivity type; a channel layer 115 of the second conductivity type formed by silicon carbide and placed on the body region 105 and the drift region 107 on a surface of the silicon carbide layer 102; a gate insulating film 111 placed on the channel layer 115; a gate electrode 113 insulated from the silicon carbide layer 102 by the gate insulating film 111; a source electrode 116 provided on the silicon carbide layer 102; and a drain electrode 114 provided on a reverse surface of the substrate 101, wherein the source electrode 116 is in contact with the body region 105 and the channel layer 115; and a second conductivity type impurity concentration on a surface of the silicon carbide layer 102 that is in contact with the source electrode 116 is less than or equal to a second conductivity type impurity concen

Abstract: In a junction FET of a normally-off type, a technique capable of achieving both of improvement of a blocking voltage and reduction of an ON resistance is provided. In a junction FET using silicon carbide as a substrate material, impurities are doped to a vicinity of a p-n junction between a gate region and a channel-formed region, the impurities having a conductive type which is reverse to that of impurities doped in the gate region and same as that of impurities doped in the channel-formed region. In this manner, an impurity profile of the p-n junction becomes abrupt, and further, an impurity concentration of a junction region forming the p-n junction with the gate region in the channel-formed region is higher than those of a center region in the channel-formed region and of an epitaxial layer.

Abstract: A method of manufacturing a semiconductor device, the method including providing a substrate, the substrate including single crystalline silicon and having the first region and a second region; growing a pillar from a top surface of the substrate in the first region; forming a vertical channel transistor including a first gate structure such that first gate structure surrounds a central portion of the pillar; and forming a second transistor on the second region of the substrate such that the second transistor includes a second gate structure.

Abstract: A light emitting device includes a light emitting structure formed from an active layer located between two semiconductor layers. An insulator extends through the active layer and at least partially through the semiconductor layers, and the light emitting structure is located between a first electrode and a second electrode layer. The first electrode and insulator overlap one another and may have the same or different widths.

Abstract: A GaN related compound semiconductor element includes: a channel layer made of a GaN related compound semiconductor; and a source layer and a drain layer, which are disposed in a manner of sandwiching the channel layer. The source layer includes two adjacent ridge portions which are formed by selective growth. A source electrode is formed over the surface, sandwiched by the ridge portions, of the channel layer, and the surfaces of the respective two adjacent ridge portions. The selective-growth mask formed between the two ridge portions is removed by wet etching. In addition, as another embodiment, a gate electrode is formed in a manner that the direction of the longer dimension of the gate electrode is aligned with the m plane of the channel layer. Moreover, as still another embodiment, the channel layer has a multilayer structure in which a GaN layer doped with no impurity is used as an intermediate layer.

Abstract: A semiconductor device of the present invention includes vertical double diffused MOS transistor. A gate electrode of the vertical double diffused MOS transistor is disposed within a trench formed on a semiconductor substrate and projects from a surface of the semiconductor substrate. On a side surface of the gate electrode, a side wall is formed. On the surface of the semiconductor substrate and a surface of the gate electrode, a metal silicide film is formed.

Abstract: A semiconductor device includes a semiconductor substrate; a well of a first conductivity type in the semiconductor substrate; a first element; and a first vertical transistor. The first element supplies potential to the well, the first element being in the well. The first element may include, but is not limited to, a first pillar body of the first conductivity type. The first pillar body has an upper portion that includes a first diffusion layer of the first conductivity type. The first diffusion layer is greater in impurity concentration than the well. The first vertical transistor is in the well. The first vertical transistor may include a second pillar body of the first conductivity type. The second pillar body has an upper portion that includes a second diffusion layer of a second conductivity type.

Abstract: A power semiconductor structure with a field effect rectifier having a drain region, a body region, a source region, a gate channel, and a current channel is provided. The body region is substantially located above the drain region. The source region is located in the body region. The gate channel is located in the body region and adjacent to a gate structure. The current channel is located in the body region and is extended from the source region downward to the drain region. The current channel is adjacent to a conductive structure coupled to the source region.

Abstract: Methods of making semiconductor devices such as vertical junction field effect transistors (VJFETs) or bipolar junction transistors (BJTs) are described. The methods do not require ion implantation. The VJFET device has an epitaxially regrown n-type channel layer and an epitaxially regrown p-type gate layer as well as an epitaxially grown buried gate layer. Devices made by the methods are also described.

Abstract: In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall of each of the single-crystalline semiconductor patterns. The transistors are arranged in a vertical direction of the single-crystalline semiconductor pattern, and thus the memory device may be highly integrated.

Abstract: A semiconductor device includes a first trench and a second trench extending into a semiconductor body from a surface. A body region of a first conductivity type adjoins a first sidewall of the first trench and a first sidewall of the second trench, the body region including a channel portion adjoining to a source structure and being configured to be controlled in its conductivity by a gate structure. The channel portion is formed at the first sidewall of the second trench and is not formed at the first sidewall of the first trench. An electrically floating semiconductor zone of the first conductivity type adjoins the first trench and has a bottom side located deeper within the semiconductor body than the bottom side of the body region.

Abstract: Semiconductor devices and semiconductor apparatuses including the same are provided. The semiconductor devices include a body region disposed on a semiconductor substrate, gate patterns disposed on the semiconductor substrate and on opposing sides of the body region, and first and second impurity doped regions disposed on an upper surface of the body region. The gate patterns may be separated from the first and second impurity doped regions by, or greater than, a desired distance, such that the gate patterns do not to overlap the first and second impurity doped regions in a direction perpendicular to the first and second impurity doped regions.

Abstract: A semiconductor device and a method of manufacturing the same, to appropriately determine an impurity concentration distribution of a field relieving region and reduce an ON-resistance. The semiconductor device includes a substrate, a first drift layer, a second drift layer, a first well region, a second well region, a current control region, and a field relieving region. The first well region is disposed continuously from an end portion adjacent to the vicinity of outer peripheral portion of the second drift layer to a portion of the first drift layer below the vicinity of outer peripheral portion. The field relieving region is so disposed in the first drift layer as to be adjacent to the first well region.

Abstract: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of <5° from vertical. The devices can be made using normal (i.e., 0°) or near normal incident ion implantation. The devices have relatively uniform sidewall doping and can be made without angled implantation.

Abstract: A semiconductor component including a drift zone and a drift control zone. One embodiment provides a transistor component having a drift zone, a body zone, a source zone and a drain zone. The drift zone is arranged between the body zone and the drain zone. The body zone is arranged between the source zone and the drift zone.

Abstract: A semiconductor device having a vertical transistor comprises a silicon substrate; a drain region, a channel region and a source region vertically stacked on the silicon substrate; a buried type bit line formed under the drain region in the silicon substrate to contact with the drain region and to extend in one direction; and gates respectively formed on both side walls of the stacked drain region, channel region and source region.

Abstract: A Self-Synchronized Radio Frequency RF-Interconnect (SSRFI), based on capacitor coupling and peak detection, for vertically interconnecting active device layers in three-dimensional (3D) integrated circuits (IC), as well as wireless communication and RF signal transmission/receiving.

Abstract: A semiconductor device is provided, which includes a substrate; a P-N column layer disposed on the substrate; a second conductivity type epitaxial layer disposed on the P-N column layer. The P-N column layer includes first conductivity type columns and second conductivity type columns, which are alternately arranged. Each column has a tapered shape. A portion of the first conductivity type column located around the substrate has a smaller impurity concentration than another portion of the first conductivity type column located around the second conductivity type epitaxial layer. A portion of the second conductivity type column located around the substrate has a larger impurity concentration than another portion of the first conductivity type column located around the second conductivity type epitaxial layer.

Abstract: In one embodiment, a vertical MOS transistor is formed without a thick field oxide and particularly without a thick field oxide in the termination region of the transistor.

Abstract: A high-voltage metal oxide semiconductor device comprising a main body of a first conductivity type, a conductive structure, a first well of a second conductivity type, a source region of the first conductivity type, and a second well of the second conductivity type is provided. The conductive structure has a first portion and a second portion. The first portion is extended from an upper surface of the main body into the main body. The second portion is extended along the upper surface of the main body. The first well is located in the main body and below the second portion. The first well is kept away from the first portion with a predetermined distance. The source region is located in the first well. The second well is located in the main body and extends from a bottom of the first portion to a place close to a drain region.

Abstract: In one embodiment, a semiconductor device is formed having sub-surface charge compensation regions in proximity to channel regions of the device. The charge compensation trenches comprise at least two opposite conductivity type semiconductor layers. A channel connecting region electrically couples the channel region to one of the at least two opposite conductivity type semiconductor layers.

Abstract: A semiconductor device having a super junction MOS transistor includes: a semiconductor substrate; a first semiconductor layer on the substrate; a second semiconductor layer on the first semiconductor layer; a channel forming region on a first surface portion of the second semiconductor layer; a source region on a first surface portion of the channel forming region; a source contact region on a second surface portion of the channel forming region; a gate electrode on a third surface portion of the channel forming region; a source electrode on the source region and the source contact region; a drain electrode on a backside of the substrate; and an anode electrode on a second surface portion of the second semiconductor layer. The anode electrode provides a Schottky barrier diode.

Abstract: The present invention provides a MOSFET and so forth that offer high breakdown voltage and low on-state loss (high channel mobility and low gate threshold voltage) and that can easily achieve normally OFF. A drift layer 2 of a MOSFET made of silicon carbide according to the present invention has a first region 2a and a second region 2b. The first region 2a is a region from the surface to a first given depth. The second region 2b is formed in a region deeper than the first given depth. The impurity concentration of the first region 2a is lower than the impurity concentration of the second region 2b.

Abstract: A switching device has an S (Superconductor)-N (Normal Metal)-S superlattice to control the stream of electrons without any dielectric materials. Each layer of said Superconductor has own terminal. The superlattice spacing is selected based on “Dimensional Crossover Effect”. This device can operate at a high frequency without such energy losses as devices breaking the superconducting state. The limit of the operation frequency in the case of the Nb/Cu superlattice is expected to be in the order of 1018 Hz concerning plasmon loss energy of the normal metals (Cu; in the order of 103 eV).

Abstract: A semiconductor device includes a first conductive type SiC semiconductor substrate; a second conductive type well formed on the SiC semiconductor substrate; a first impurity diffusion layer formed by introducing a first conductive type impurity so as to be partly overlapped with the well in a region surrounding the well; a second impurity diffusion layer formed by introducing the first conductive type impurity in a region spaced apart for a predetermined distance from the impurity diffusion layer in the well; and a gate electrode opposed to a channel region between the first and the second impurity diffusion layers with gate insulating film sandwiched therebetween.

Abstract: A vertically conducting semiconductor device includes a semiconductor substrate having a topside surface and a backside surface. The semiconductor substrate serves as a terminal of the vertically conducting device for biasing the vertically conducting device during operation. An epitaxial layer extends over the topside surface of the semiconductor substrate but terminates prior to reaching an edge of the semiconductor substrate so as to form a recessed region along a periphery of the semiconductor substrate. An interconnect layer extends into the recessed region but terminates prior to reaching an edge of the semiconductor substrate. The interconnect layer electrically contacts the topside surface of the semiconductor substrate in the recessed region to thereby provide a topside contact to the semiconductor substrate.

Abstract: A memory cell device having a vertical channel and a double gate structure is provided. More specifically, a memory cell device having a vertical channel and a double gate structure is characterized by having a pillar active region with a predetermined height, which is including a first semiconductor layer forming a first source/drain region, a second semiconductor layer being placed under the first semiconductor layer with a predetermined distance and forming a second source/drain region, and a third semiconductor layer forming a body region and a channel region between the first semiconductor layer and the second semiconductor layer, and therefore, there is no need for unnecessary contacts when it is used as a unit cell for any type of memory array, not to speak of NOR type flash memory array. And the present invention makes to program/erase more effectively and increase the read speed and the amount of sensing current.

Abstract: A single-chip common-drain JFET device comprises a Drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.

Abstract: A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.

Abstract: A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.

Abstract: A SiC JFET that includes a plurality of trenches formed in a SiC semiconductor body of one conductivity each trench having a region of another conductivity formed in the bottom and sidewalls thereof.

Abstract: A normally-off type junction FET in which a channel resistance is reduced without lowering its blocking voltage is provided. In a junction FET formed with using a substrate made of silicon carbide, an impurity concentration of a channel region (second epitaxial layer) is made higher than an impurity concentration of a first epitaxial layer to be a drift layer. The channel region is formed of a first region in which a channel width is constant and a second region below the first region in which the channel width becomes wider toward the drain (substrate) side. A boundary between the first epitaxial layer and the second epitaxial layer is positioned in the second region in which the channel width becomes wider toward the drain (substrate) side.