Vertical (i.e., Where The Source Is Located Above The Drain Or Vice Versa) Patents (Class 257/135)
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Patent number: 6936866Abstract: A vertical or lateral semiconductor component derives a signal from a high load voltage. This signal can be used directly for driving the semiconductor component or, alternatively, a control device.Type: GrantFiled: October 22, 2001Date of Patent: August 30, 2005Assignee: Infineon Technologies AGInventors: Gerald Deboy, Gerald Mündel
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Patent number: 6917060Abstract: A vertical semiconductor device including a first conductivity type base layer having resistance higher then of a first conductivity type buffer layer, the first conductivity type buffer layer formed in one surface portion of the first conductivity type base layer, a second conductivity type drain layer selectively formed in a surface portion of the first conductivity type buffer layer, a second conductivity type base layer selectively formed in the other surface portion of the first conductivity type base layer, a first conductivity type source layer selectively formed in a surface portion of the second conductivity type base layer, a gate insulating film formed on the second conductivity type base layer between the first conductivity type source layer and the first conductivity type base layer, a gate electrode formed on the second conductivity type base layer via the gate insulating film, a drain electrode electrically connected to the second conductivity type drain layer, and a source electrode electricalType: GrantFiled: September 16, 2003Date of Patent: July 12, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Yoshihiro Yamaguchi, Hideaki Ninomiya, Tomoki Inoue
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Patent number: 6909125Abstract: We disclose the structure of an electronic device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It has, near the top surface, a buried layer that is electrically communicable to a drain terminal. The device has a body region over the buried layer. A portion of the body region contacts a gate region connected to a gate terminal. The device has a channel region, of which the length spans the distance between the buried layer and a source region, which projects upward from the channel region and is connected to a source terminal. The device current flows in the channel substantially perpendicularly to the top surface of the substrate.Type: GrantFiled: July 8, 2003Date of Patent: June 21, 2005Assignee: Texas Instruments IncorporatedInventors: Gregory E. Howard, Leland S. Swanson
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Patent number: 6906356Abstract: A high power switch includes diode and BJT structures interdigitated in a drift layer and separated by insulated trench gates; electrodes contacting the diode and BJT structures provide anode and cathode connections. Shallow N+ regions extend below and around the corners of the oxide side-walls and bottoms of respective gates. A voltage applied across the anode and cathode sufficient to forward bias the diode's p-n junction causes electrons to be injected which provide a base drive current to the BJT sufficient to turn it on and enable current to flow from anode to cathode via the diode and BJT structures. A gate voltage sufficient to reverse bias the junction between the shallow N+ regions and the drift layer forms a potential barrier which blocks current flow through the diode and BJT structures and eliminates the base drive current such that the BJT and said switch are turned off.Type: GrantFiled: September 27, 2004Date of Patent: June 14, 2005Assignee: Rockwell Scientific Licensing, LLCInventor: Hsueh-Rong Chang
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Patent number: 6897493Abstract: A pin diode is formed by a p+ collector region, an n type buffer region, an n? region and an n+ cathode region. A trench is formed from the surface of n+ cathode region through n+ cathode region to reach n? region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n+ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n+ cathode region. An anode electrode is formed to be electrically connected to p+ collector region. The n+ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.Type: GrantFiled: June 10, 2003Date of Patent: May 24, 2005Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tetsuo Takahashi, Katsumi Nakamura, Tadaharu Minato, Masana Harada
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Patent number: 6894319Abstract: A MOS semiconductor device includes n?-type surface regions, which are extended portions of an n?-type drift layer 12 extended to the surface of the semiconductor chip. Each n?-type surface region 14 is shaped with a stripe surrounded by a p-type well region. The surface area ratio between n?-type surface regions 14 and p-type well region 13 including an n+-type region 15 is from 0.01 to 0.2. The MOS semiconductor device further includes, in the breakdown withstanding region thereof, a plurality of guard rings, the number of which is equal to or more than the number n calculated from the following equation n=(Breakdown voltage Vbr (V))/100, and the spacing between the adjacent guard rings is set at 1 ?m or less.Type: GrantFiled: October 31, 2001Date of Patent: May 17, 2005Assignee: Fuji Electric Co., Ltd.Inventors: Takashi Kobayashi, Tatsuhiko Fujihira, Hitoshi Abe, Yasushi Niimura, Masanori Inoue
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Patent number: 6894346Abstract: A structure is provided that ensures a low on-resistance and a better blocking effect. In a lateral type SIT (Static Induction Transistor) in which a first region is used as a p+ gate and a gate electrode is formed on the bottom of the first region, the structure is built such that the p+ gate and an n+ source are contiguous. An insulating film is formed on the surface of an n? channel, and an auxiliary gate electrode is formed on the insulating film. In addition, the auxiliary gate electrode and the source electrode are shorted.Type: GrantFiled: August 13, 2003Date of Patent: May 17, 2005Assignee: Hitachi, Ltd.Inventors: Hidekatsu Onose, Atsuo Watanabe
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Patent number: 6867437Abstract: A pin diode is formed by a p+ collector region, an n type buffer region, an n? region and an n+ cathode region. A trench is formed from the surface of n+ cathode region through n+ cathode region to reach n? region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n+ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n+ cathode region. An anode electrode is formed to be electrically connected to p+ collector region. The n+ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.Type: GrantFiled: August 20, 2002Date of Patent: March 15, 2005Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tetsuo Takahashi, Katsumi Nakamura, Tadaharu Minato, Masana Harada
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Patent number: 6861678Abstract: We disclose the structure of a JFET device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It has a buried layer that is electrically communicable to a drain terminal. It has a body region above the buried layer. A portion of the body region contacts a gate region connected to a gate terminal. The device has a channel region, of which the length spans the distance between the buried layer and a source region, which projects upward from the channel region and is connected to a source terminal. The device current flows in the channel substantially perpendicularly to the top surface of the substrate.Type: GrantFiled: July 18, 2003Date of Patent: March 1, 2005Assignee: Texas Instruments IncorporatedInventors: Gregory E. Howard, Leland S. Swanson
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Patent number: 6861706Abstract: A compensation semiconductor component has a drift zone formed in a semiconductor body and at least one compensation zone formed in the edge region of the semiconductor body in the drift zone. The compensation zone is doped complementarily to the drift zone and connected by at least one connecting zone to a channel zone, which is doped complementarily to the drift zone and isolates the drift zone from a first terminal zone of the same conductivity type as the drift zone. A control electrode is formed in a manner insulated from the channel zone.Type: GrantFiled: June 16, 2003Date of Patent: March 1, 2005Assignee: Infineon Technologies AGInventor: Jenoe Tihanyi
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Patent number: 6855603Abstract: The present invention provide a vertical nano-sized transistor using carbon nanotubes capable of achieving high-density integration, that is, tera-bit scale integration, and a manufacturing method thereof, wherein in the vertical nano-sized transistor using carbon nanotubes, holes having diameters of several nanometers are formed in an insulating layer and are spaced at intervals of several nanometers. Carbon nanotubes are vertically aligned in the nano-sized holes by chemical vapor deposition, electrophoresis or mechanical compression to be used as channels. A gate is formed in the vicinity of the carbon nanotubes using an ordinary semiconductor manufacturing method, and then a source and a drain are formed at lower and upper parts of each of the carbon nanotubes thereby fabricating the vertical nano-sized transistor having an electrically switching characteristic.Type: GrantFiled: March 14, 2003Date of Patent: February 15, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Won-bong Choi, Jo-won Lee, Young-hee Lee
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Patent number: 6855981Abstract: A silicon carbide power device includes a junction field effect transistor and a protective diode, which is a Zener or PN junction diode. The PN junction of the protective diode has a breakdown voltage lower than the PN junction of the transistor. Another silicon carbide power device includes a protective diode, which is a Schottky diode. The Schottky diode has a breakdown voltage lower than the PN junction of the transistor by adjusting Schottky barrier height or the depletion layer formed in the semiconductor included in the Schottky diode. Another silicon carbide power device includes three protective diodes, which are Zener diodes. Two of the protective diodes are used to clamp the voltages applied to the gate and the drain of the transistor due to surge energy and used to release the surge energy. The last diode is a thermo-sensitive diode, with which the temperature of the JFET is measured.Type: GrantFiled: August 29, 2002Date of Patent: February 15, 2005Assignee: Denso CorporationInventors: Rajesh Kumar, Hiroki Nakamura, Tsuyoshi Yamamoto, Toshiyuki Morishita
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Patent number: 6849880Abstract: A power semiconductor device includes second layers of a second conductivity type disposed in a first layer of a first conductivity type. The second layers extend in a depth direction and are arrayed at intervals. Third layers of the second conductivity type are disposed respectively in contact with the second layers. Fourth layers of the first conductivity type are respectively formed in surfaces of the third layers. A gate electrode faces, through a first insulating film, a channel region, which is each of portions of the third layers interposed between the fourth layers and the first layer. An additional electrode is disposed on each of the second layers through a second insulating film, and faces, through each of the second layers, the first main electrode. The additional electrode is electrically connected to the gate electrode.Type: GrantFiled: March 9, 2004Date of Patent: February 1, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Ichiro Omura, Satoshi Aida
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Patent number: 6838729Abstract: The invention relates to a semiconductor component with enhanced avalanche ruggedness. At the nominal current of this semiconductor component, in the event of an avalanche the voltage applied between two electrodes is 6 % or more above the static reverse voltage at the same temperature.Type: GrantFiled: April 29, 2002Date of Patent: January 4, 2005Assignee: Infineon Technologies AGInventors: Andreas Schlögl, Markus Schmitt, Hans-Joachim Schulze, Markus Vossebürger, Armin Willmeroth
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Patent number: 6833567Abstract: The present invention provide a vertical nano-sized transistor using carbon nanotubes capable of achieving high-density integration, that is, tera-bit scale integration, and a manufacturing method thereof, wherein in the vertical nano-sized transistor using carbon nanotubes, holes having diameters of several nanometers are formed in an insulating layer and are spaced at intervals of several nanometers. Carbon nanotubes are vertically aligned in the nano-sized holes by chemical vapor deposition, electrophoresis or mechanical compression to be used as channels. A gate is formed in the vicinity of the carbon nanotubes using an ordinary semiconductor manufacturing method, and then a source and a drain are formed at lower and upper parts of each of the carbon nanotubes thereby fabricating the vertical nano-sized transistor having an electrically switching characteristic.Type: GrantFiled: March 13, 2003Date of Patent: December 21, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Won-bong Choi, Jo-won Lee, Young-hee Lee
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Patent number: 6787881Abstract: An integrated power device having a power transistor made up of a first diode and a second diode that are connected together in series between a collector region and emitter-contact region of the power transistor to define a common intermediate node, a control circuit including a high-voltage region bonded on the emitter-contact region (14) by means of an adhesive layer, and biasing circuit connected between the common intermediate node and the high-voltage region. The biasing circuit including a contact pad electrically connected to the common intermediate node, an electrical connection region that is in electrical contact with the high-voltage region (30), and a wire having a first end soldered on the contact pad and a second end soldered on said electrical connection region.Type: GrantFiled: January 4, 2002Date of Patent: September 7, 2004Assignee: STMicroelectronics S.r.l.Inventors: Romeo Letor, Antonino Torres, Leonardo Fragapane
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Publication number: 20040137666Abstract: A power semiconductor switching device such as a power MOSFET that includes breakdown voltage enhancement regions formed by self-alignment.Type: ApplicationFiled: December 23, 2003Publication date: July 15, 2004Applicant: International Rectifier CorporationInventors: Timothy Henson, Jianjun Cao
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Publication number: 20040119088Abstract: A method for manufacturing a semiconductor device with a substrate having a device layer and a backside electrode is disclosed. Here, a surface roughness of the substrate is defined as a ratio between a substantial area and a projected area. The method includes polishing and wet-etching a backside surface of the substrate mechanically with using predetermined abrasive grains so that a surface roughness of the backside surface of the substrate becomes to be equal to or larger than 1.04, and forming the backside electrode on the backside surface of the substrate after polishing and wet-etching the backside surface of the substrate.Type: ApplicationFiled: December 11, 2003Publication date: June 24, 2004Applicant: DENSO CORPORATIONInventors: Yutaka Fukuda, Naohiko Hirano, Chikage Noritake, Shoji Miura
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Publication number: 20040113200Abstract: A MOS semiconductor device includes n−-type surface regions, which are extended portions of an n−-type drift layer 12 extended to the surface of the semiconductor chip. Each n−-type surface region 14 is shaped with a stripe surrounded by a p-type well region. The surface area ratio between n−-type surface regions 14 and p-type well region 13 including an n+-type region 15 is from 0.01 to 0.2. The MOS semiconductor device further includes, in the breakdown withstanding region thereof, a plurality of guard rings, the number of which is equal to or more than the number n calculated from the following equation n=(Breakdown voltage Vbr (V))/100, and the spacing between the adjacent guard rings is set at 1 &mgr;m or less.Type: ApplicationFiled: August 22, 2003Publication date: June 17, 2004Applicant: Fuji Electric Co., Ltd.Inventors: Takashi Kobayashi, Tatsuhiko Fujihira, Hitoshi Abe, Yasushi Niimura, Masanori Inoue
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Patent number: 6696706Abstract: An apparatus and method for a semiconductor device with reduced gate capacitance. Specifically, an n-channel or p-channel junction field effect transistor (JFET) is described comprising an appropriately doped substrate forming a drain region, an epitaxial layer formed on top of the substrate, a control structure comprising a gate region implanted into the epitaxial layer, a source region sharing a p-n junction with the gate region, and an altered epitaxial region. The altered epitaxial region is formed by implanting either n− or p− dopants directly below the gate region of either the n-channel or p-channel JFET for widening a depletion region surrounding the gate region. The enlarged depletion region reduces the gate capacitance of the JFET between the gate and drain regions.Type: GrantFiled: October 22, 2002Date of Patent: February 24, 2004Assignee: Lovoltech, Inc.Inventor: Pete L. Pegler
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Patent number: 6693310Abstract: A pin diode is formed by a p+ collector region, an n type buffer region, an n− region and an n+ cathode region. A trench is formed from the surface of n+ cathode region through n+ cathode region to reach n− region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n+ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n+ cathode region. An anode electrode is formed to be electrically connected to p+ collector region. The n+ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.Type: GrantFiled: May 23, 2001Date of Patent: February 17, 2004Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tetsuo Takahashi, Katsumi Nakamura, Tadaharu Minato, Masana Harada
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Patent number: 6690040Abstract: A vertical JFET architecture. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain doped region formed in the surface. A second doped region forming a channel of different conductivity type than the first region is disposed over the first region. A third doped region is formed over the second doped region having an opposite conductivity type with respect to the second doped region, and forming a source/drain region. A gate is formed over the channel to form a vertical JFET.Type: GrantFiled: September 10, 2001Date of Patent: February 10, 2004Assignee: Agere Systems Inc.Inventors: Samir Chaudhry, Paul Arthur Layman, John Russell McMacken, Ross Thomson, Jack Qingsheng Zhao
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Patent number: 6661056Abstract: The present invention relates to a circuit configuration for protecting against polarity reversal of a DMOS transistor. A charge carrier zone (30) is provided, situated in the drift zone (14) of DMOS transistor (10), made up of individual partial charge carrier zones (32) situated at a distance from one another and connected to one another in a conducting manner, the charge carrier zone (30) having an opposite charge carrier doping from that of the drift zone (14), and being able to be acted upon by a potential that is negative with respect to a potential present at a drain terminal (24) of the DMOS transistor (10), so that a short-circuit current is prevented.Type: GrantFiled: September 26, 2002Date of Patent: December 9, 2003Assignee: Robert Bosch GmbHInventors: Robert Plikat, Wolfgang Feiler
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Patent number: 6653666Abstract: J-FET having a first semiconductor region (2, 3), which comprises a first contact (7) with a highly doped contact layer (8) serving as a source disposed between two second contacts (9) serving as a gate on its first surface (4). The three contacts (7, 9) are each connected to a respective second semiconductor region (5, 6). The first and second semiconductor regions (2, 3, 5, 6) are of opposite conductivity types. The second semiconductor regions (5) connected to the second contacts (9) extend in the first semiconductor region (2, 3) below the second semiconductor region (6) that is connected to the first contact (7), with the result that the three second semiconductor regions (5, 6) at least partially overlap in a projection onto a horizontal plane and a channel region (11) is formed between the three second semiconductor regions (5, 6) in the first semiconductor region (2, 3).Type: GrantFiled: January 23, 2001Date of Patent: November 25, 2003Assignee: SiCED Electronics Development GmbH & Co. KGInventors: Heinz Mitlehner, Ulrich Weinert
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Publication number: 20030201455Abstract: A pin diode is formed by a p+ collector region, an n type buffer region, an n− region and an n+ cathode region. A trench is formed from the surface of n+ cathode region through n+ cathode region to reach n− region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n+ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n+ cathode region. An anode electrode is formed to be electrically connected to p+ collector region. The n+ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.Type: ApplicationFiled: June 10, 2003Publication date: October 30, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Tetsuo Takahashi, Katsumi Nakamura, Tadaharu Minato, Masana Harada
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Patent number: 6635926Abstract: A field effect transistor with a high withstand voltage and a low resistance is provided. A ring-shaped channel region is disposed inside a source region formed in a ring, and the inside of the channel region is taken as a drain region. A depletion layer extends toward the inside of the drain region, resulting in a high withstand voltage. In the portion, except the portion within a prescribed distance from the corner portion of the channel region, a low resistance conductive layer is disposed, thereby resulting in high withstand voltage.Type: GrantFiled: July 20, 2001Date of Patent: October 21, 2003Assignee: Shindengen Electric Manufacturing Co., Ltd.Inventors: Nobuki Miyakoshi, Toshiki Matsubara, Hideyuki Nakamura
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Patent number: 6632723Abstract: A semiconductor device is disclosed, which includes a semiconductor substrate, drain and source regions of a MOS transistor, a gate electrode formed on a surface of a channel region of the MOS transistor trench type element isolation regions in each of which an insulating film is formed on a surface of a trench formed in the surface of the semiconductor substrate, the element isolation regions sandwiching the channel region from opposite sides thereof in a channel width direction, and a conductive material layer for a back gate electrode, which is embedded in a trench of at least one of the element isolation regions, configured to be supplied with a predetermined voltage to make an depletion layer in a region of the semiconductor substrate under the channel region of the MOS transistor or to voltage-control the semiconductor substrate region.Type: GrantFiled: April 26, 2002Date of Patent: October 14, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Shinichi Watanabe, Takashi Ohsawa, Kazumasa Sunouchi, Yoichi Takegawa, Takeshi Kajiyama
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Patent number: 6566708Abstract: Trench-gate field-effect transistors, for example power MOSFETs, are disclosed having trenched electrode configurations (11,23) that permit fast switching of the transistor, while also providing over-voltage protection for the gate dielectric (21) and facilitating manufacture. The gate electrode (11) comprising a semiconductor material of one conductivity type (n) is present in an upper part of a deeper insulated trench (20,21) that extends into a drain region (14,14a) of the transistor. A lower electrode (23) connected to a source (13,33) of the transistor is present in the lower part of the trench. This lower electrode (23) comprises a semiconductor material of opposite conductivity type (p) that adjoins the semiconductor material of the gate electrode (11) to form a p-n junction (31) between the gate electrode (11) and the lower electrode (23). The p-n junction (31) provides a protection diode (D) between the gate electrode (11) and the source (13,33).Type: GrantFiled: November 16, 2001Date of Patent: May 20, 2003Assignee: Koninklijke Philips Electronics N.V.Inventors: Raymond J. Grover, Steven T. Peake
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Publication number: 20030080346Abstract: In DRAM memory cells, individual memory cells are isolated from one another by an isolation trench (STI). In such a case, a vertical transistor is formed by the isolation trench as SOI transistor because its channel region is isolated from a substrate by the isolation trench. A vertical transistor that is used, for example, in a DRAM memory cell and a method for making the transistor includes connecting the channel region of the vertical transistor to the substrate by disposing a conductive layer in the isolation trench between a lower insulation filling and an upper insulation filling.Type: ApplicationFiled: November 18, 2002Publication date: May 1, 2003Inventor: Rolf Weis
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Patent number: 6551865Abstract: Openings are formed in a laminate of a polycrystalline silicon film and an LTO film on a channel layer. While the laminate is used as a mask, impurities are implanted into a place in the channel layer which is assigned to a source region. Also, impurities are implanted into another place in the channel layer which is assigned to a portion of a second gate region. A portion of the polycrystalline silicon film which extends from the related opening is thermally oxidated. The LTO film and the oxidated portion of the polycrystalline silicon film are removed. While a remaining portion of the polycrystalline silicon film is used as a mask, impurities are implanted into a place in the channel layer which is assigned to the second gate region. Accordingly, the source region and the second gate region are formed on a self-alignment basis which suppresses a variation in channel length.Type: GrantFiled: March 28, 2002Date of Patent: April 22, 2003Assignee: Denso CorporationInventors: Rajesh Kumar, Hiroki Nakamura, Jun Kojima
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Patent number: 6548872Abstract: A method of defining at least two different field effect transistor channel lengths includes forming a channel defining layer over a substrate, the semiconductor substrate having a mean global outer surface extending along a plane. First and second openings are etched into the channel defining layer. The first and second openings respectively have a pair of opposing sidewalls having substantially straight linear segments which are angled from the plane. The straight linear segments of the opposing sidewalls of the first opening are angled differently from the plane than the straight linear segments of the opposing sidewalls of the second opening and are thereby of different lengths. Integrated circuitry includes a first field effect transistor and a second field effect transistor. The first and second field effect transistors have respective channel lengths defined along their gate dielectric layers and respectively have at least some portion which is substantially straight linear.Type: GrantFiled: June 27, 2001Date of Patent: April 15, 2003Assignee: Micron Technology, Inc.Inventor: Alan R. Reinberg
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Patent number: 6545297Abstract: Area efficient static memory cells and arrays containing p-n-p-n transistors which can be latched in a bistable on state. Each transistor memory cell includes a gate which is pulse biased during the write operation to latch the cell. Also provided is a CMOS fabrication process to create the cells and arrays.Type: GrantFiled: May 13, 1998Date of Patent: April 8, 2003Assignee: Micron Technology, Inc.Inventors: Wendell P. Noble, Jr., Leonard Forbes
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Patent number: 6541817Abstract: In a trench-gate semiconductor device, for example a cellular power MOSFET, the gate (11) is present in a trench (20) that extends through the channel-accommodating region (15) of the device. An underlying body portion (16) that carries a high voltage in an off state of the device is present adjacent to a side wall of a lower part (20b) of the trench (20). Instead of being a single high-resistivity region, this body portion (16) comprises first regions (61) of a first conductivity type interposed with second regions (62) of the opposite second conductivity type. In the conducting state of the device, the first regions (61) provide parallel current paths through the thick body portion (16), from the conduction channel (12) in the channel-accommodating region (15). In an off-state of the device, the body portion (16) carries a depletion layer (50).Type: GrantFiled: November 29, 1999Date of Patent: April 1, 2003Assignee: Koninklijke Philips Electronics N.V.Inventors: Godefridus A. M. Hurkx, Raymond J. E. Hueting
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Publication number: 20030057435Abstract: There is provided a semiconductor device, such as a TFT, with a vertical drain offset region. The device contains a substrate having an upper first surface, a semiconductor channel region of a first conductivity type over the first surface, a gate electrode and a gate insulating layer between the gate electrode and the channel region. The device also contains a heavily doped semiconductor source region of a second conductivity type, a heavily doped semiconductor drain region of a second conductivity type. An intrinsic or lightly doped semiconductor drain offset region is located between the drain region and the channel region, such that the drain region is offset from the channel region at least partially in a direction perpendicular to the first surface.Type: ApplicationFiled: September 25, 2001Publication date: March 27, 2003Applicant: Matrix Semiconductor, Inc.Inventor: Andrew J. Walker
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Publication number: 20030052329Abstract: A MOS semiconductor device includes n−-type surface regions, which are extended portions of an n−-type drift layer 12 extended to the surface of the semiconductor chip. Each n−-type surface region 14 is shaped with a stripe surrounded by a p-type well region. The surface area ratio between n−-type surface regions 14 and p-type well region 13 including an n+-type region 15 is from 0.01 to 0.2. The MOS semiconductor device further includes, in the breakdown withstanding region thereof, a plurality of guard rings, the number of which is equal to or more than the number n calculated from the following equation n=(Breakdown voltage Vbr (V))/100, and the spacing between the adjacent guard rings is set at 1 &mgr;m or less.Type: ApplicationFiled: October 31, 2001Publication date: March 20, 2003Inventors: Takashi Kobayashi, Tatsuhiko Fujihira, Hitoshi Abe, Yasushi Niimura, Masanori Inoue
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Publication number: 20030047749Abstract: An architecture for creating a vertical JFET. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain doped region formed in the surface. A second doped region forming a channel of different conductivity type than the first region is positioned over the first region. A third doped region is formed over the second doped region having an opposite conductivity type with respect to the second doped region, and forming a source/drain region. A gate is formed over the channel to form a vertical JFET.Type: ApplicationFiled: September 10, 2001Publication date: March 13, 2003Inventors: Samir Chaudhry, Paul Arthur Layman, John Russell McMacken, Ross Thomson, Jack Qingsheng Zhao
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Patent number: 6524894Abstract: An N+ buffer layer formed on the underside of an N− layer includes an inactive region having incompletely activated ions and an active region having highly activated ions. The carrier concentration of the active region is higher than that of the inactive region. In the inactive region, the electrical activation rate X of the ions is expressed as 1%≦X≦30%. It is thus possible to achieve a PT structure using a Raw wafer, which reduces manufacturing costs and suppresses power consumption.Type: GrantFiled: February 15, 2001Date of Patent: February 25, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Hideki Nozaki, Yoshiro Baba, Motoshige Kobayashi
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Patent number: 6521992Abstract: An electrode wiring structure is disclosed which realizes a semiconductor apparatus as a power semiconductor module with the current path set as shortest as possible and uniformly. The semiconductor apparatus includes: a plurality of semiconductor devices mounted in one array or more on a substrate; a main current electrode mounted along the array(s) of the semiconductor devices, and commonly connected to each of the plurality of semiconductor devices through the substrate. The substrate is connected to the main current electrode through a plurality of wires arranged along the array(s) at equal or substantially equal distances.Type: GrantFiled: April 16, 2001Date of Patent: February 18, 2003Assignee: Kabushiki Kaisha Toyoda Jidoshokki SeisakushoInventor: Eiji Kono
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Publication number: 20030030092Abstract: Trench MIS devices including a thick insulative layer at the bottom of the trench are disclosed, along with methods of fabricating such devices. An exemplary trench MOSFET embodiment includes a thick oxide layer at the bottom of the trench, with no appreciable change in stress in the substrate along the trench bottom. The thick insulative layer separates the trench gate from the drain region at the bottom of the trench yielding a reduced gate-to-drain capacitance making such MOSFETs suitable for high frequency applications. In an exemplary fabrication process embodiment, the thick insulative layer is deposited on the bottom of the trench. A thin insulative gate dielectric is formed on the exposed sidewall and is coupled to the thick insulative layer. A gate is formed in the remaining trench volume. The process is completed with body and source implants, passivation, and metallization.Type: ApplicationFiled: August 10, 2001Publication date: February 13, 2003Inventors: Mohamed N. Darwish, Frederick P. Giles, Kam Hong Lui, Kuo-In Chen, Kyle Terrill
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Patent number: 6518622Abstract: The present invention provides a VRG structure formed on a semiconductor wafer substrate. The VRG structure has a first source/drain region located in a semiconductor wafer substrate, and a conductive layer located adjacent the source/drain region, a second source/drain region and a conductive channel that extends from the first source/drain region to the second source/drain region. The conductive layer provides an electrical connection to the first source/drain region. The conductive layer may have a low sheet resistance that may be less than about 50 &OHgr;/square or less than about 20 &OHgr;/square, to the first source/drain region.Type: GrantFiled: March 20, 2000Date of Patent: February 11, 2003Assignee: Agere Systems Inc.Inventors: Hongzong Chew, Yih-Feng Chyan, John M. Hergenrother, Yi Ma, Donald P. Monroe
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Publication number: 20030025152Abstract: A semiconductor component includes a first connection zone of a first conductivity type for providing a contact at a first side of a semiconductor body and a second connection zone of the first conductivity type for providing a contact at the second side of the semiconductor body. A drift zone adjoins the first connection zone and extends in a vertical direction of the semiconductor body as far as the second side of the semiconductor body. A body zone of a second conductivity type is disposed between the second connection zone and the first connection zone or the drift zone. A control electrode is insulated from the semiconductor body and disposed above the body zone such that the control electrode substantially does not overlap with the drift zone and the second connection zone in a lateral direction. A method for manufacturing a semiconductor component is also provided.Type: ApplicationFiled: June 19, 2002Publication date: February 6, 2003Inventors: Wolfgang Werner, Franz Hirler
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Patent number: 6512251Abstract: The semiconductor switching element blocks in both directions between a first and a second load terminal. The switching element has a field effect transistor and a bipolar transistor. The field effect transistor has a controlled gate, a source connected to the first load terminal, a drain connected to the second load terminal and a body connection. The bipolar transistor has a base, an emitter, and a collector. The emitter is connected to the body connection of the field effect transistor.Type: GrantFiled: May 30, 2001Date of Patent: January 28, 2003Assignee: Infineon Technologies AGInventor: Wolfgang Werner
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Publication number: 20020139992Abstract: Openings are formed in a laminate of a polycrystalline silicon film and an LTO film on a channel layer. While the laminate is used as a mask, impurities are implanted into a place in the channel layer which is assigned to a source region. Also, impurities are implanted into another place in the channel layer which is assigned to a portion of a second gate region. A portion of the polycrystalline silicon film which extends from the related opening is thermally oxidated. The LTO film and the oxidated portion of the polycrystalline silicon film are removed. While a remaining portion of the polycrystalline silicon film is used as a mask, impurities are implanted into a place in the channel layer which is assigned to the second gate region. Accordingly, the source region and the second gate region are formed on a self-alignment basis which suppresses a variation in channel length.Type: ApplicationFiled: March 28, 2002Publication date: October 3, 2002Inventors: Rajesh Kumar, Hiroki Nakamura, Jun Kojima
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Patent number: 6445012Abstract: A pin diode is formed by a p+ collector region, an n type buffer region, an n− region and an n+ cathode region. A trench is formed from the surface of n+ cathode region through n+ cathode region to reach n− region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n+ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n+ cathode region. An anode electrode is formed to be electrically connected to p+ collector region. The n+ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.Type: GrantFiled: May 23, 2001Date of Patent: September 3, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tetsuo Takahashi, Katsumi Nakamura, Tadaharu Minato, Masana Harada
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Publication number: 20020117732Abstract: An integrated power device having a power transistor made up of a first diode and a second diode that are connected together in series between a collector region and emitter-contact region of the power transistor to define a common intermediate node, a control circuit including a high-voltage region bonded on the emitter-contact region (14) by means of an adhesive layer, and biasing circuit connected between the common intermediate node and the high-voltage region. The biasing circuit including a contact pad electrically connected to the common intermediate node, an electrical connection region that is in electrical contact with the high-voltage region (30), and a wire having a first end soldered on the contact pad and a second end soldered on said electrical connection region.Type: ApplicationFiled: January 4, 2002Publication date: August 29, 2002Applicant: STMicroelectronics S.r.l.Inventors: Romeo Letor, Antonino Torres, Leonardo Fragapane
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Publication number: 20020088989Abstract: A MOS control diode is provided for power switching. In the MOS control diode, a switching speed is high and a reverse leakage current characteristic is improved without additionally needing processes for improving reverse recovery time by converting a power MOSFET which is a majority carrier device to diode having two terminals. Such a MOS control diode can be achieved by forming a discontinuous area in a gate oxide film formed on the surface of a semiconductor substrate so that the conductive gate electrode is connected to the semiconductor substrate. Also, it is possible to form a trench in the semiconductor substrate, to form the gate oxide films on the sidewall of a trench, and to connect the gate electrode to the semiconductor substrate through the bottom of the trench.Type: ApplicationFiled: January 28, 2002Publication date: July 11, 2002Applicant: Samsung Electronics Co., Ltd.Inventor: Ho-Hyun Kim
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Publication number: 20020081784Abstract: An insulated gate bipolar transistor is disclosed, which comprises a first conductivity type base layer, a second conductivity type base layer and an emitter layer which are selectively formed in an upper surface of the first conductivity type base layer, a buffer layer and a collector layer which are formed on a back surface of the first conductivity type base layer. A requirement of d2/d1>1.5 is satisfied, where d1 is a depth in the buffer layer, as measured from an interface of the buffer layer and the collector layer, at which a first conductivity type impurity concentration in the buffer layer shows a peak value, and d2 is a shallowest depth in the buffer layer, as measured from the interface of the buffer layer and the collector layer, at which an activation ratio of the first conductivity type impurity in the buffer layer is a predetermined value.Type: ApplicationFiled: December 26, 2001Publication date: June 27, 2002Inventors: Motoshige Kobayashi, Hideki Nozaki
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Publication number: 20020074585Abstract: A power MOSFET transistor is formed on a substrate including a source, body layer, and drain layer and an optional fourth layer for an IGBT. The device is characterized by a conductive gate having a high conductivity metal layer coextensive with a polysilicon layer for high power and high speed operation.Type: ApplicationFiled: February 22, 2002Publication date: June 20, 2002Applicant: ADVANCED POWER TECHNOLOGY, INC., Delaware corporationInventors: Dah Wen Tsang, John W. Mosier, Douglas A. Pike, Theodore O. Meyer
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Patent number: 6396085Abstract: A vertical field effect transistor having an MES-type structure high in withstand voltage and capable of high current operation is realized through effective use of GaN-type semiconductors. Specifically, a source electrode and a drain electrode are formed on the top and the bottom of a GaN-type semiconductor multilayer film, respectively, to realize the vertical-structured field effect transistor. The field effect transistor has a device structure in which an n−-GaN layer (first semiconductor layer) of low carrier concentration, constituting the source-to-drain current path, is provided with an n+-GaN layer (fourth semiconductor layer) via an undoped i-GaN layer (second semiconductor layer), a p+-GaN layer, and a p−-GaN layer (third semiconductor layer). Then, an n+-GaN layer (fifth semiconductor layer) for constituting a channel layer is formed thinly in the top of the n−-GaN layer beneath a gate electrode.Type: GrantFiled: April 25, 2001Date of Patent: May 28, 2002Assignee: The Furukawa Electric Co., LTDInventor: Seikoh Yoshida
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Patent number: 6380565Abstract: A monolithic bidirectional switch formed in a semiconductor substrate of a first conductivity type having a front surface and a rear surface, including a first main vertical thyristor, the rear surface layer of which is of the second conductivity type, a second main vertical thyristor, the rear surface layer of which is of the first conductivity type. A structure for triggering each of the first and second main thyristors is arranged to face regions mutually distant from the two main thyristors, the neighboring portions of which correspond to a region for which, for the first main thyristor, a short-circuit area between cathode and cathode gate is formed.Type: GrantFiled: August 8, 2000Date of Patent: April 30, 2002Assignee: STMicroelectronics S.A.Inventors: Franck Duclos, Jean-Michel Simonnet, Olivier Ladiray