With Lattice Constant Mismatch (e.g., With Buffer Layer To Accommodate Mismatch) Patents (Class 257/190)
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Patent number: 9953872Abstract: Embodiments of the present invention provide a semiconductor structure having a strain relaxed buffer, and method of fabrication. A strain relaxed buffer is disposed on a semiconductor substrate. A silicon region and silicon germanium region are disposed adjacent to each other on the strain relaxed buffer. An additional region of silicon or silicon germanium provides quantum well isolation.Type: GrantFiled: September 8, 2017Date of Patent: April 24, 2018Assignee: GLOBALFOUNDRIES INC.Inventor: David P. Brunco
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Patent number: 9947591Abstract: A device and method for manufacturing a Si-based high-mobility CMOS device is provided.Type: GrantFiled: November 16, 2016Date of Patent: April 17, 2018Assignee: IMEC VZWInventors: Clement Merckling, Guillaume Boccardi
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Patent number: 9947789Abstract: A vertical transistor includes a semiconductor substrate, and fin(s) over the semiconductor substrate (n-type fin(s) and/or p-type fin(s)), the fin(s) acting as vertical transistor channels for vertical transistors. Each of the fin(s) is lattice mismatched at one or more interface(s), being stressed from below, from above, from fin sidewalls or combination(s) thereof. The vertical transistors can be realized by providing a semiconductor substrate, forming stressed fin(s) of vertical transistor(s) acting as vertical transistor channels, the stressed fin(s) being lattice mismatched at one or more interfaces and being stressed from below, above, sidewalls or combination(s) thereof.Type: GrantFiled: October 17, 2016Date of Patent: April 17, 2018Assignee: GLOBALFOUNDRIES INC.Inventor: Puneet Harischandra Suvarna
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Patent number: 9935019Abstract: Method for creation of stressed channel structure transistors wherein at least one amorphizing ion implantation of the surface layer of a substrate of the semiconductor-on-insulator type is carried out through openings in a mask, so as to render zones of the surface layers amorphous and to induce relaxation of a zone intended to form a channel and located between the zones that have been rendered amorphous, the relaxation being carried out in a direction orthogonal to that in which it is intended that the channel current flows.Type: GrantFiled: September 9, 2016Date of Patent: April 3, 2018Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Shay Reboh, Laurent Grenouillet, Frederic Milesi, Yves Morand, Francois Rieutord
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Patent number: 9923088Abstract: The present disclosure relates to a semiconductor device with vertically integrated pseudomorphic high electron mobility transistors (pHEMTs). The disclosed semiconductor device includes a substrate, a lower pHEMT structure with a lower pHEMT, an isolation layer, and an upper pHEMT structure with an upper pHEMT. The lower pHEMT structure is formed over the substrate and has a first region and a second region that is laterally disposed with the first region. The lower pHEMT is formed in or on the second region. The isolation layer resides over the first region. The upper pHEMT structure is formed over the isolation layer and does not extend over the second region. Herein, the isolation layer separates the lower pHEMT structure from the upper pHEMT structure such that the lower pHEMT and the upper pHEMT operate independently from each other.Type: GrantFiled: August 17, 2016Date of Patent: March 20, 2018Assignee: Qorvo US, Inc.Inventors: Corey A. Nevers, Sheila K. Hurtt, Dana A. Schwartz
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Patent number: 9917004Abstract: Provided are a group III nitride composite substrate having a low sheet resistance and produced with a high yield, and a method for manufacturing the same, as well as a method for manufacturing a group III nitride semiconductor device using the group III nitride composite substrate. A group III nitride composite substrate includes a group III nitride film and a support substrate formed from a material different in chemical composition from the group III nitride film. The group III nitride film is joined to the support substrate in one of a direct manner and an indirect manner. The group III nitride film has a thickness of 10 ?m or more. A sheet resistance of a group III-nitride-film-side main surface is 200 ?/sq or less.Type: GrantFiled: September 4, 2013Date of Patent: March 13, 2018Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Keiji Ishibashi, Akihiro Hachigo, Yuki Hiromura, Naoki Matsumoto, Seiji Nakahata, Fumitake Nakanishi, Takuya Yanagisawa, Koji Uematsu, Yuki Seki, Yoshiyuki Yamamoto, Yusuke Yoshizumi, Hidenori Mikami
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Patent number: 9917153Abstract: A crystalline layer is produced from a crystalline substrate made from a first material on which a masking layer has previously been deposited; the masking layer containing at least one trench forming an access to the substrate, by: forming a crystalline buffer layer situated at least partly in the trench in the masking layer, extending from the substrate and forming a projection beyond the masking layer so that an upper part of the lateral flanks of said buffer layer is left uncovered, the formation step comprising a growth of the buffer layer from the substrate, and forming a crystalline epitaxial layer in a second material, different from the material of the buffer layer, by growth from said upper part of the lateral flanks of the buffer layer left uncovered.Type: GrantFiled: June 29, 2015Date of Patent: March 13, 2018Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Emmanuel Augendre, Thierry Baron
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Patent number: 9905479Abstract: Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack.Type: GrantFiled: January 5, 2017Date of Patent: February 27, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Balasubramanian Pranatharthiharan, Soon-Cheon Seo
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Patent number: 9899525Abstract: This disclosure relates to a fin field effect transistor including a gate structure formed on a fin. Source and drain (S/D) regions are epitaxially grown on the fin adjacent to the gate structure. The S/D regions include a diamond-shaped cross section wherein the diamond-shaped cross section includes: internal sidewalls where the fin was recessed to a reduced height, and an external top portion of the diamond-shaped cross section of the S/D regions. A contact liner is formed over the internal sidewalls and the top portion of the diamond-shaped cross section of the S/D regions; and contacts are formed over the contact liner and over the internal sidewalls and the top portion of the diamond-shaped cross section of the S/D regions.Type: GrantFiled: May 11, 2017Date of Patent: February 20, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Veeraraghavan S. Basker, Chung-Hsun Lin, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh
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Patent number: 9893070Abstract: A method of fabricating a semiconductor device. The method includes forming a dummy structure over a substrate, forming conductive features on opposite sides of the dummy gate structure, removing the dummy structure and a portion of the substrate beneath the dummy gate structure to form a trench, and filling the trench with a dielectric material.Type: GrantFiled: June 10, 2016Date of Patent: February 13, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Shan Wang, Shun-Yi Lee
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Patent number: 9887139Abstract: A method of producing a semiconductor component is provided. The method includes providing a silicon substrate having a <111>-surface defining a vertical direction, forming in the silicon substrate at least one electronic component, forming at least two epitaxial semiconductor layers on the silicon substrate to form a heterojunction above the <111>-surface, and forming a HEMT-structure above the <111>-surface.Type: GrantFiled: December 28, 2011Date of Patent: February 6, 2018Assignee: Infineon Technologies Austria AGInventors: Gerhard Prechtl, Gebhart Dippold
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Patent number: 9875901Abstract: A manufacturing method of MOS transistor, the MOS transistor includes a substrate, a gate oxide, a gate, a source/drain region and a silicide layer. The gate oxide is disposed on the substrate and the gate is disposed on the gate oxide. The source/drain region is disposed in the substrate at two sides of the gate. The silicide layer is disposed on the source/drain region, wherein the silicide layer includes a curved bottom surface and a curved top surface, both the curved top surface and the curved bottom surface bend toward the substrate and the curved top surface is sunken from two sides thereof, two ends of the silicide layer point tips raised up over the source/drain region and the silicide layer in the middle is thicker than the silicide layer in the peripheral, thereby forming a crescent structure. The present invention further provides a manufacturing method of the MOS transistor.Type: GrantFiled: November 15, 2015Date of Patent: January 23, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wen-Tai Chiang, Chun-Hsien Lin
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Patent number: 9876136Abstract: Disclosed herein is a method of separating a GaN substrate by wet etching. The method employs chemical lift-off, and includes forming oxide layers separated from each other and a GaN column in each space between the oxide layers on a substrate, forming an n-GaN layer covering an upper space on the oxide layers and the n-GaN columns, sequentially forming an active layer, a p-GaN layer, and a p-type electrode on the n-GaN layer, and removing the oxide layers and wet etching the n-GaN columns to separate the substrate. The method can achieve improvement in epitaxial growth of GaN and reduction in fabrication costs through a simple process. In addition, the method can increase a luminous area and light extraction efficiency.Type: GrantFiled: August 13, 2014Date of Patent: January 23, 2018Assignee: GWANGJU INSTITUTE OF SCIENCE AND TECHNOLOGYInventors: Dong-Seon Lee, Duk-Jo Kong, Junyoub Lee, Chang Mo Kang
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Patent number: 9870926Abstract: A method of manufacturing a source structure for a p-type metal-oxide-semiconductor (PMOS) field effect transistor (FET) is provided. In the method, a first epitaxial layer comprising Si1-xGex is formed on a source region of an FET, a second epitaxial layer comprising Si1-yGey is formed on the first epitaxial layer, a third epitaxial layer comprising Si1-zGez is formed on the second epitaxial layer. Z is smaller than y.Type: GrantFiled: July 28, 2016Date of Patent: January 16, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Min Huang, Hsiu-Ting Chen, Shih-Chieh Chang
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Patent number: 9865511Abstract: In an aspect of the present invention, a field-effect transistor (FET) structure is formed. The FET structure comprises a plurality of fins formed on a semiconductor substrate, wherein the plurality of fins includes a set of fins that include a base portion that is comprised of relaxed silicon-germanium (SiGe) and an upper portion that is comprised of semiconductor material. In one aspect, a first set of one or more fins that include an upper portion comprised of a first semiconductor material. In another aspect, a second set of one or more fins that include an upper portion comprised of a second semiconductor material.Type: GrantFiled: September 13, 2016Date of Patent: January 9, 2018Assignee: International Business Machines CorporationInventors: Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
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Patent number: 9865719Abstract: A method of fabricating a semiconductor device can include forming a III-N semiconductor layer in a reactor and injecting a hydrocarbon precursor into the reactor, thereby carbon doping the III-N semiconductor layer and causing the III-N semiconductor layer to be insulating or semi-insulating. A semiconductor device can include a substrate and a carbon doped insulating or semi-insulating III-N semiconductor layer on the substrate. The carbon doping density in the III-N semiconductor layer is greater than 5×1018 cm?3 and the dislocation density in the III-N semiconductor layer is less than 2×109 cm?2.Type: GrantFiled: January 8, 2016Date of Patent: January 9, 2018Assignee: Transphorm Inc.Inventors: Stacia Keller, Brian L. Swenson, Nicholas Fichtenbaum
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Patent number: 9865460Abstract: A method for forming a semiconductor device having a fin-type channel is provided. The method may include the following operations: forming a first buffer layer over a substrate; forming a first dielectric layer over the first buffer layer; patterning the first dielectric layer over the first buffer layer; forming a barrier layer over the first buffer layer; forming a second dielectric layer over the barrier layer; patterning the second dielectric layer over the barrier layer; forming a channel layer over the barrier layer; and patterning the second dielectric layer, such that at least a portion of the channel layer protrudes to form the fin-type channel.Type: GrantFiled: September 23, 2015Date of Patent: January 9, 2018Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chien-Hsun Wang, Chun-Hsiung Lin, Mao-Lin Huang
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Patent number: 9853118Abstract: In accordance with an embodiment, a diode comprises a substrate, a dielectric material including an opening that exposes a portion of the substrate, the opening having an aspect ratio of at least 1, a bottom diode material including a lower region disposed at least partly in the opening and an upper region extending above the opening, the bottom diode material comprising a semiconductor material that is lattice mismatched to the substrate, a top diode material proximate the upper region of the bottom diode material, and an active diode region between the top and bottom diode materials, the active diode region including a surface extending away from the top surface of the substrate.Type: GrantFiled: December 9, 2016Date of Patent: December 26, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Anthony J. Lochtefeld
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Patent number: 9847334Abstract: Structures and formation methods of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate with a first lattice constant and having a PMOS region and an NMOS region. The semiconductor device further includes first and second fin structures over the PMOS region and NMOS region respectively. The first fin structure includes a buffer layer with a second lattice constant and a first channel layer. The lattice constant difference between the first channel layer and the buffer layer is smaller than that between the first channel layer and the semiconductor layer. The first channel layer has a third lattice constant, which is greater than the second lattice constant. The first lattice constant is greater than the second lattice constant. The second fin structure includes a second channel layer. The second channel layer has a fourth lattice constant which is less than the first lattice constant.Type: GrantFiled: November 18, 2016Date of Patent: December 19, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shahaji B. More, Zheng-Yang Pan, Tsung-Lin Lee, Shih-Chieh Chang
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Patent number: 9841657Abstract: Photosensitive logic inverter, in particular of the CMOS type, formed of a transistor of type P and of a transistor of type N of which the respective threshold voltages can be modulated according to the quantity of photons received by a photosensitive zone provided opposite these transistors.Type: GrantFiled: May 22, 2015Date of Patent: December 12, 2017Assignee: Commissariat à l'énergie atomique et aux énergies alternativesInventors: Laurent Grenouillet, Olivier Rozeau
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Patent number: 9842930Abstract: A semiconductor device includes a first gate stack and a second gate stack over a substrate, an isolation structure in the substrate, a first epitaxial (epi) material in the substrate between the first gate stack and the isolation structure, and a second epi material in the substrate between the first gate stack and the second gate stack. The first gate stack is between the isolation structure and the second gate stack. The first epi material includes a first upper surface having a first crystal plane. The second epi material includes a second upper surface having a second crystal plane and a third upper surface having a third crystal plane, and first crystal plane is different from both the second crystal plane and the third crystal plane.Type: GrantFiled: July 13, 2016Date of Patent: December 12, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Lilly Su, Pang-Yen Tsai, Tze-Liang Lee, Chii-Horng Li, Yen-Ru Lee, Ming-Hua Yu
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Patent number: 9842944Abstract: A solid source-diffused junction is described for fin-based electronics. In one example, a fin is formed on a substrate. A glass of a first dopant type is deposited over the substrate and over a lower portion of the fin. A glass of a second dopant type is deposited over the substrate and the fin. The glass is annealed to drive the dopants into the fin and the substrate. The glass is removed and a first and a second contact are formed over the fin without contacting the lower portion of the fin.Type: GrantFiled: July 14, 2014Date of Patent: December 12, 2017Assignee: Intel CorporationInventors: Walid M. Hafez, Chia-Hong Jan
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Patent number: 9842741Abstract: After semiconductor material portions and gate structures are formed on a substrate, a dielectric material layer is deposited on the semiconductor material portions and the gate structures. An anisotropic etch is performed on the dielectric material layer to form gate spacers, while a mask layer protects peripheral portions of the semiconductor material portions and the gate structures to avoid unwanted physical exposure of semiconductor surfaces. A selective epitaxy can be performed to form raised active regions on the semiconductor material portions. Formation of semiconductor growth defects during the selective epitaxy is prevented by the dielectric material layer. Alternately, a selective semiconductor deposition process can be performed after formation of dielectric gate spacers on gate structures overlying semiconductor material portions. Semiconductor growth defects can be removed by an etch while a mask layer protects raised active regions on the semiconductor material portions.Type: GrantFiled: November 3, 2016Date of Patent: December 12, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Soon-cheon Seo, Linus Jang
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Patent number: 9837511Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having at least a fin-shaped structure thereon and the fin-shaped structure includes a top portion and a bottom portion; forming a gate structure on the fin-shaped structure; forming a cap layer on the top portion of the fin-shaped structure not covered by the gate structure; performing an annealing process to drive germanium from the cap layer to the top portion of the fin-shaped structure; removing the cap layer; and forming an epitaxial layer around the top portion of the fin-shaped structure.Type: GrantFiled: January 11, 2017Date of Patent: December 5, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yu-Cheng Tung, En-Chiuan Liou
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Patent number: 9837321Abstract: A nonplanar circuit device having a strain-producing structure disposed under the channel region is provided. In an exemplary embodiment, the integrated circuit device includes a substrate with a first fin structure and a second fin structure disposed on the substrate. An isolation feature trench is defined between the first fin structure and the second fin structure. The circuit device also includes a strain feature disposed on a horizontal surface of the substrate within the isolation feature trench. The strain feature may be configured to produce a strain on a channel region of a transistor formed on the first fin structure. The circuit device also includes a fill dielectric disposed on the strain feature within the isolation feature trench. In some such embodiments, the strain feature is further disposed on a vertical surface of the first fin structure and on a vertical surface of the second fin structure.Type: GrantFiled: April 1, 2016Date of Patent: December 5, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Cheng Ching, Ka-Hing Fung, Zhiqiang Wu
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Patent number: 9837509Abstract: A semiconductor device includes at least one semiconductor fin on an upper surface of a base substrate. The at least one semiconductor fin includes a strained active semiconductor portion interposed between a protective cap layer and the base substrate. A gate stack wraps around the at least one semiconductor fin. The gate stack includes a metal gate element interposed between a pair of first cap segments of the protective cap layer. The strained active semiconductor portion is preserved following formation of the fin via the protective cap layer.Type: GrantFiled: June 23, 2015Date of Patent: December 5, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
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Patent number: 9837524Abstract: A semiconductor device includes a buffer layer, a channel layer, a barrier layer, and agate electrode over a substrate, the gate electrode being disposed in a first opening with agate insulating film in between, the first opening running up to the middle of the channel layer through the barrier layer. The concentration of two-dimensional electron gas in a first region on either side of a second opening that will have a channel is controlled to be lower than the concentration of two-dimensional electron gas in a second region between an end of the first region and a source or drain electrode. The concentration of the two-dimensional electron gas in the first region is thus decreased, thereby the conduction band-raising effect of polarization charge is prevented from being reduced. This prevents a decrease in threshold potential, and thus improves normally-off operability.Type: GrantFiled: November 1, 2016Date of Patent: December 5, 2017Assignee: Renesas Electronics CorporationInventors: Shinichi Miyake, Tatsuo Nakayama
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Patent number: 9831382Abstract: A solution for fabricating a semiconductor structure is provided. The semiconductor structure includes a plurality of semiconductor layers grown over a substrate using a set of epitaxial growth periods. During each epitaxial growth period, a first semiconductor layer having one of: a tensile stress or a compressive stress is grown followed by growth of a second semiconductor layer having the other of: the tensile stress or the compressive stress directly on the first semiconductor layer.Type: GrantFiled: December 3, 2012Date of Patent: November 28, 2017Assignee: Sensor Electronic Technology, Inc.Inventors: Rakesh Jain, Wenhong Sun, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Remigijus Gaska, Michael Shur
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Patent number: 9812358Abstract: FinFET structures and methods of forming the same are disclosed. In a method, a recess is formed exposing a plurality of semiconductor fins on a wafer. A dummy contact material is formed in the recess. The dummy contact material contains carbon. The dummy contact material is cured with one or more baking steps. The one or more baking steps harden the dummy contact material. A first portion of the dummy contact material is replaced with an inter-layer dielectric. A second portion of the dummy contact material is replaced with a plurality of contacts. The plurality of contacts are electrically coupled to source/drain regions of the plurality of semiconductor fins.Type: GrantFiled: September 14, 2016Date of Patent: November 7, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yen-Chun Huang, Ting-Ting Chen, Yu-Chung Su, Ling-Fu Nieh, Pin-Chuan Su, Teng-Chun Tsai, Tai-Chun Huang, Joy Cheng
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Patent number: 9812570Abstract: A semiconductor device includes a substrate, a liner, and an epitaxy structure. The substrate has a recess. The liner is disposed in the recess. The liner is denser than the substrate. The epitaxy structure is disposed in the recess. The liner is disposed between the epitaxy structure and the substrate.Type: GrantFiled: June 30, 2015Date of Patent: November 7, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Fen Chen, Chui-Ya Peng, Ching Yu, Pin-Hen Lin, Yen Chuang, Yuh-Ta Fan
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Patent number: 9805982Abstract: A method of adjusting work-function metal thickness includes providing a structure having a substrate, the substrate including a longitudinally extending array of fins disposed thereon. Spacers are then formed on sidewalls of fins of the array. Pillars are formed between and adjacent the spacers. A gate having dummy gate material is formed over the structure, the gate extending laterally across the spacers and fins of the array. The dummy gate material and spacers are removed from the gate to form work-function (WF) metal trenches defined by the pillars and fins within the gate. The WF metal trenches have a first trench width. A thickness of the pillars is adjusted to provide a second trench width, different from the first trench width, for the WF metal trenches. A WF metal structure is disposed within the WF metal trenches.Type: GrantFiled: May 17, 2016Date of Patent: October 31, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Hui Zang, Min-hwa Chi, Jinping Liu
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Patent number: 9793380Abstract: A method for making a semiconductor device. A substrate having a fin structure is provided. A continuous dummy gate line is formed on the substrate. The dummy gate line strides across the fin structure. A source/drain structure is formed on the fin structure on both sides of the dummy gate line. An interlayer dielectric (ILD) is formed on the dummy gate line and around the dummy gate line. The ILD is polished to reveal a top surface of the dummy gate line. After polishing the ILD, the dummy gate line is segmented into separate dummy gates.Type: GrantFiled: July 9, 2015Date of Patent: October 17, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Kai Hsu, Yu-Hsiang Hung, Ssu-I Fu, Jyh-Shyang Jenq
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Patent number: 9793401Abstract: A vertical field effect transistor (FET) includes a first source/drain region formed on an upper surface of a semiconductor substrate, and a semiconductor channel material that extends vertically from the first source/drain region to a second source/drain region. A metal gate structure encapsulating the semiconductor channel material. The vertical FET further includes a stressor region that contacts the semiconductor channel material and the first source/drain region. The combination of the semiconductor channel material and the stressor region defines a total length of a strained channel region of the vertical field effect transistor.Type: GrantFiled: May 25, 2016Date of Patent: October 17, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
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Patent number: 9793398Abstract: A method of forming a strained channel for a field effect transistor, including forming a sacrificial layer on a substrate, forming a channel layer on the sacrificial layer, forming a stressor layer on the channel layer, wherein the stressor layer applies a stress to the channel layer, forming at least one etching trench by removing at least a portion of the stressor layer, channel layer, and sacrificial layer, wherein the etching trench exposes at least a portion of a sidewall of the sacrificial layer, and separates the stressor layer, channel layer, and sacrificial layer into two or more stressor islands, channel blocks, and sacrificial slabs, and removing the sacrificial slabs to release the channel blocks from the substrate using a selective etch, wherein the channel blocks adhere to the substrate surface.Type: GrantFiled: August 2, 2016Date of Patent: October 17, 2017Assignee: International Business Machines CorporationInventors: Isaac Lauer, Jiaxing Liu, Renee T. Mo
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Patent number: 9793115Abstract: Methods of forming germanium-tin films using germane as a precursor are disclosed. Exemplary methods include growing films including germanium and tin in an epitaxial chemical vapor deposition reactor, wherein a ratio of a tin precursor to germane is less than 0.1. Also disclosed are structures and devices including germanium-tin films formed using the methods described herein.Type: GrantFiled: July 6, 2016Date of Patent: October 17, 2017Assignee: ASM IP Holding B.V.Inventor: John Tolle
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Patent number: 9793168Abstract: Embodiments of the present invention provide a semiconductor structure having a strain relaxed buffer, and method of fabrication. A strain relaxed buffer is disposed on a semiconductor substrate. A silicon region and silicon germanium region are disposed adjacent to each other on the strain relaxed buffer. An additional region of silicon or silicon germanium provides quantum well isolation.Type: GrantFiled: December 21, 2015Date of Patent: October 17, 2017Assignee: GLOBALFOUNDRIES INC.Inventor: David P. Brunco
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Patent number: 9786782Abstract: A semiconductor structure includes a material stack of, from bottom to top, an insulator structure and a semiconductor fin portion located on a pedestal portion of a semiconductor substrate portion, wherein a doped epitaxial semiconductor material structure extends from each sidewall surface of the semiconductor fin portion, each doped epitaxial semiconductor material structure introduces a stress on the semiconductor fin portion. A gate structure straddles the semiconductor fin portion. A source-side stressor structure having a bottommost surface contacting a first subsurface of the semiconductor substrate portion and covering one of the doped epitaxial semiconductor material structure is located on a source-side of the gate structure. A drain-side stressor structure having a bottommost surface contacting a second subsurface of the semiconductor substrate portion and covering another of the doped epitaxial semiconductor material structure is located on a drain-side of the gate structure.Type: GrantFiled: October 23, 2015Date of Patent: October 10, 2017Assignee: International Business Machines CorporationInventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
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Patent number: 9779934Abstract: A nitride semiconductor free-standing substrate includes a diameter of not less than 40 mm, a thickness of not less than 100 ?m, a dislocation density of not more than 5×106/cm2, an impurity concentration of not more than 4×1019/cm3, and a nanoindentation hardness of not less than 19.0 GPa at a maximum load in a range of not less than 1 mN and not more than 50 mN.Type: GrantFiled: November 19, 2009Date of Patent: October 3, 2017Assignee: SUMITOMO CHEMICAL COMPANY, LIMITEDInventor: Hajime Fujikura
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Patent number: 9780174Abstract: A structure includes a semiconductor substrate including a first semiconductor material. A portion of the semiconductor substrate extends between insulation regions in the semiconductor substrate. The portion of the semiconductor substrate has a (111) surface and a bottom surface. The (111) surface is slanted and has a top edge and a bottom edge. The bottom surface is parallel to a top surface of the insulation regions, and is connected to the bottom edge. A semiconductor region overlaps the portion of the semiconductor substrate, wherein the semiconductor region includes a second semiconductor material different from the first semiconductor material. The top edge and the bottom edge of the (111) surface are at a first depth and a second depth, respectively, relative to a top surface of the semiconductor region. A ratio of the first depth to the second depth is smaller than about 0.6.Type: GrantFiled: July 15, 2015Date of Patent: October 3, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Jing Lee, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
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Patent number: 9780175Abstract: A nitride semiconductor epitaxial wafer includes a substrate, a GaN layer provided over the substrate, and an AlGaN layer provided over the GaN layer. The GaN layer has a wurtzite crystal structure, and a ratio c/a of a lattice constant c in a c-axis orientation of the GaN layer to a lattice constant a in an a-axis orientation of the GaN layer is not more than 1.6266.Type: GrantFiled: December 20, 2012Date of Patent: October 3, 2017Assignee: SUMITOMO CHEMICAL COMPANY, LIMITEDInventors: Takeshi Tanaka, Naoki Kaneda, Yoshinobu Narita
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Patent number: 9773887Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon, a first spacer around the gate structure, and a contact etch stop layer (CESL) adjacent to the first spacer; forming a cap layer on the gate structure, the first spacer, and the CESL; and removing part of the cap layer for forming a second spacer adjacent to the CESL.Type: GrantFiled: December 3, 2015Date of Patent: September 26, 2017Assignee: UNITED MICORELECTRONICS CORP.Inventors: Ying-Chiao Wang, Chao-Hung Lin, Ssu-I Fu, Jyh-Shyang Jenq, Li-Wei Feng, Yu-Hsiang Hung
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Patent number: 9761755Abstract: A method of producing a semiconductor layer sequence includes providing a growth substrate having a growth surface on a growth side, growing a first nitride semiconductor layer on the growth side, growing a second nitride semiconductor layer on the first nitride semiconductor layer, wherein the second nitride semiconductor layer includes at least one opening or at least one opening is produced in the second nitride semiconductor layer or at least one opening is created in the second nitride semiconductor layer during the growing process, removing at least one part of the first nitride semiconductor layer through the openings in the second nitride semiconductor layer, and growing a third nitride semiconductor layer on the second nitride semiconductor layer, wherein the third nitride semiconductor layer covers the openings at least in places.Type: GrantFiled: February 24, 2015Date of Patent: September 12, 2017Assignee: OSRAM Opto Semiconductors GmbHInventors: Joachim Hertkorn, Werner Bergbauer, Philipp Drechsel
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Patent number: 9752252Abstract: A method of epitaxially growing nitrogen-based compound semiconductor thin films on a semiconductor substrate, which is periodically patterned with grooves. The method can provide an epitaxial growth of a first crystalline phase epitaxial film on the substrate, and block the growth of an initial crystalline phase with barrier materials prepared at the sides of the grooves. Semiconductor devices employing the epitaxial films are also disclosed.Type: GrantFiled: September 21, 2016Date of Patent: September 5, 2017Assignee: STC.UNMInventors: Seung-Chang Lee, Steven R. J. Brueck
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Patent number: 9755077Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and a silicon germanium region extending into the semiconductor substrate and adjacent to the gate stack. The silicon germanium region has a top surface, with a center portion of the top surface recessed from edge portions of the top surface to form a recess. The edge portions are on opposite sides of the center portion.Type: GrantFiled: February 27, 2017Date of Patent: September 5, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kun-Mu Li, Tsz-Mei Kwok, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee
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Patent number: 9748357Abstract: Embodiments include a method for fabricating a semiconductor device and the resulting structure comprising forming a semi-insulating bottom barrier on a semiconductor substrate. A channel is formed on the bottom barrier. A semi-insulating layer is epitaxially formed on the bottom barrier, laterally adjacent to the channel. The semi-insulating layer is formed in such a way that stress is induced onto the channel. A CMOS transistor is formed on the channel.Type: GrantFiled: August 5, 2016Date of Patent: August 29, 2017Assignee: International Business Machines CorporationInventors: Anirban Basu, Guy Cohen, Amlan Majumdar
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Patent number: 9748098Abstract: After forming a seed layer over a first end of a sacrificial semiconductor layer composed of silicon germanium, a remaining portion of the sacrificial semiconductor layer is removed to provide a trench. Next, a semiconductor barrier layer is formed on a sidewall of the seed layer that is exposed by the trench. A III-V compound semiconductor layer is formed within the trench by a lateral epitaxial semiconductor regrowth process.Type: GrantFiled: August 15, 2016Date of Patent: August 29, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Karthik Balakrishnan, Lukas Czornomaz, Pouya Hashemi, Alexander Reznicek
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Patent number: 9748453Abstract: A semiconductor light emitting device includes a substrate formed of a first material; and a convex portion protruding from the substrate and including: a first layer formed of the first material as that of the substrate; and a second layer formed of a second material different from the first material and disposed on the first layer. A second height of the second layer is greater than a first height of the first layer.Type: GrantFiled: May 4, 2016Date of Patent: August 29, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong Hak Kim, Tan Sakong, Eun Deok Sim, Jeong Wook Lee, Jin Young Lim, Byoung Kyun Kim
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Patent number: 9741765Abstract: Provided is a monolithic integration of resistive memory with complementary metal oxide semiconductor using integrated circuit foundry processes. A memory device is provided that includes a substrate comprising one or more complementary metal-oxide semiconductor devices, a first insulator layer formed on the substrate; and a monolithic stack. The monolithic stack includes multiple layers fabricated as part of a monolithic process over the first insulator layer. The multiple layers include a first metal layer, a second insulator layer, and a second metal layer. A resistive memory device structure is formed within the second insulator layer and within a thermal budget of the one or more complementary metal-oxide semiconductor devices. The resistive memory device structure is implemented as a pillar device or as a via device. Further, the first metal layer is coupled to the second metal layer.Type: GrantFiled: December 31, 2014Date of Patent: August 22, 2017Assignee: CROSSBAR, INC.Inventors: Sundar Narayanan, Steve Maxwell, Natividad Vasquez, Jr., Harry Yue Gee
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Patent number: 9735155Abstract: A bulk SiGe FinFET which includes: a plurality of SiGe fins and a bulk semiconductor substrate, the SiGe fins extending from the bulk semiconductor substrate; the SiGe fins having a top portion and a bottom portion, a part of the bottom portion being doped to form a punchthrough stop; the bulk semiconductor substrate having a top portion in contact with the SiGe fins and comprising a gradient of germanium and silicon, and a bottom portion of silicon in contact with the top portion such that the gradient has a composition of SiGe at the top portion in contact with the SiGe fins that is the same composition of SiGe as in the SiGe fins, the proportion of germanium atoms in the gradient gradually decreasing and the proportion of silicon atoms in the gradient gradually increasing in the gradient until the top portion contacts the bottom portion.Type: GrantFiled: December 14, 2015Date of Patent: August 15, 2017Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Juntao Li, Shogo Mochizuki
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Patent number: 9735058Abstract: A performance optimized CMOS FET structure and methods of manufacture are disclosed. The method includes forming source and drain regions for a first type device and a second type device. The method further includes lowering the source and drain regions for the first type device, while protecting the source and drain regions for the second type device. The method further includes performing silicide processes to form silicide regions on the lowered source and drain regions for the first type device and the source and drain regions for the second type device.Type: GrantFiled: July 15, 2016Date of Patent: August 15, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul Chang, Katsunori Onishi, Jian Yu