Abstract: A nitride semiconductor template includes a Ga2O3 substrate, a buffer layer that includes as a main component AlN and is formed on the Ga2O3 substrate, a first nitride semiconductor layer that includes as a main component AlxGa1-xN (0.2<x?1) and is formed on the buffer layer, a second nitride semiconductor layer that includes as a main component AlyGa1-yN (0.2?y?0.55, y<x) and is formed on the first nitride semiconductor layer, and a third nitride semiconductor layer that is formed on the second nitride semiconductor layer and includes a multilayer structure including an Inu1Alv1Gaw1N (0.02?u1?0.03, u1+v1+w1=1) layer and Inu2Alv2Gaw2N (0.02?u2?0.03, u2+v2+w2=1, v1+0.05?v2?v1+0.2) layers on both sides of the Inu1Alv1Gaw1N layer.

Abstract: A method includes forming a semiconductor fin, which forms a ring, forming a plurality of gate stacks on sidewalls and a top surface of each of sides of the ring, epitaxially growing a plurality of epitaxy regions between the plurality of gate stacks, and forming a plurality of metal contact plugs. Each of the plurality of metal contact plugs is over, and is electrically coupling to, one of the plurality of epitaxy regions.

Abstract: A semiconductor device includes a substrate, a semiconductor layer having a buffer layer, a spacer layer, and barrier layer sequentially stacked on the substrate, and first and second ohmic electrodes installed on an upper surface of the barrier layer in the substrate to be separated from each other. Each of the first and second ohmic electrodes includes a portion formed on the upper surface of the barrier layer and electrode portions filling a plurality of grooves penetrating from the upper surface of the barrier layer through the barrier layer and the spacer layer and reaching a region of a two-dimensional electron gas layer formed in a spacer-layer side of the buffer layer, the electrode portions being in contact with side walls of each of the plurality of the grooves, and the portion formed on the upper surface of the barrier layer and the electrode portions are integrally formed.

Abstract: An integrated circuit (IC) device may include a first active transistor of a first-type in a first-type region. The first active transistor may have a first-type work function material and a low channel dopant concentration in an active portion of the first active transistor. The IC device may also include a first isolation transistor of the first-type in the first-type region. The second active transistor may have a second-type work function material and the low channel dopant concentration in an active portion of the first isolation transistor. The first isolation transistor may be arranged adjacent to the first active transistor.

Abstract: An image sensor device includes a silicon-based substrate, a silicon-germanium epitaxy layer, an isolation feature, an active pixel cell and a logic circuit. The silicon-germanium epitaxy layer is on the silicon-based substrate, in which the silicon-germanium epitaxy layer has a composition of Si1-xGex, where 0<x<1. The isolation feature is disposed in the silicon-germanium epitaxy layer to define a pixel region and a periphery region of the silicon-germanium epitaxy layer. The active pixel cell is disposed in the pixel region of the silicon-germanium epitaxy layer. The logic circuit is disposed in the periphery region.

Abstract: An embodiment of a method of manufacturing a compound semiconductor device includes: forming an initial layer over a substrate; forming a buffer layer over the initial layer; forming an electron transport layer and an electron supply layer over the buffer layer; and forming a gate electrode, a source electrode and a gate electrode over the electron supply layer. The forming an initial layer includes: forming a first compound semiconductor film with a flow rate ratio being a first value, the flow rate ratio being a ratio of a flow rate of a V-group element source gas to a flow rate of a III-group element source gas; and forming a second compound semiconductor film with the flow rate ratio being a second value different from the first value over the first compound semiconductor film. The method further includes forming an Fe-doped region between the buffer layer and the electron transport layer.

Abstract: A method of forming a semiconductor device includes: providing a patterned structure comprising a silicon substrate and dielectric stacks deposited on the silicon substrate, the dielectric stacks forming trenches exposing a plurality of surface portions of the substrate within the trenches; forming one or more epitaxial buffer layers within the trenches on the exposed surface portions of the substrate; and growing a semiconductor material on the epitaxial buffer layer that is the furthest away from the substrate; wherein each of the one or more epitaxial buffer layers and the semiconductor material has less than about 3% lattice mismatch to the layer immediately beneath the one or more epitaxial buffer layer and the semiconductor material.

Abstract: Uniaxially strained nanowire structures are described. For example, a semiconductor device includes a plurality of vertically stacked uniaxially strained nanowires disposed above a substrate. Each of the uniaxially strained nanowires includes a discrete channel region disposed in the uniaxially strained nanowire. The discrete channel region has a current flow direction along the direction of the uniaxial strain. Source and drain regions are disposed in the nanowire, on either side of the discrete channel region. A gate electrode stack completely surrounds the discrete channel regions.

Abstract: Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers.

Abstract: A method for forming a semiconductor structure having a transistor device with a control electrode for controlling a flow of carriers between a first electrode and a second electrode. A passivation layer is deposited over the first electrode, the second electrode and the control electrode. An etch stop layer is deposited on the passivation layer over the control electrode. The etch stop layer includes the etch stop layer comprising: a first etch stop layer on the passivation layer, a buffer layer on the first etch stop layer, and a second etch stop layer on the buffer layer. A dielectric layer is formed over the etch stop layer. A window is etched through a selected region in the dielectric layer over the control electrode, to expose a portion of the etch stop layer disposed over the control electrode. A metal layer is formed on a portion of the etch stop layer and the dielectric layer is also formed on the metal layer.

Abstract: Techniques are disclosed for converting a strain-inducing semiconductor buffer layer into an electrical insulator at one or more locations of the buffer layer, thereby allowing an above device layer to have a number of benefits, which in some embodiments include those that arise from being grown on a strain-inducing buffer and having a buried electrical insulator layer. For instance, having a buried electrical insulator layer (initially used as a strain-inducing buffer during fabrication of the above active device layer) between the Fin and substrate of a non-planar integrated transistor circuit may simultaneously enable a low-doped Fin with high mobility, desirable device electrostatics and elimination or otherwise reduction of substrate junction leakage. Also, the presence of such an electrical insulator under the source and drain regions may further significantly reduce junction leakage. In some embodiments, substantially the entire buffer layer is converted to an electrical insulator.

Abstract: In an aspect of the present invention, a field-effect transistor (FET) structure is formed. The FET structure comprises a plurality of fins formed on a semiconductor substrate, wherein the plurality of fins includes a set of fins that include a base portion that is comprised of relaxed silicon-germanium (SiGe) and an upper portion that is comprised of semiconductor material. In one aspect, a first set of one or more fins that include an upper portion comprised of a first semiconductor material. In another aspect, a second set of one or more fins that include an upper portion comprised of a second semiconductor material.

Abstract: A method of fabricating a single crystal gallium nitride substrate the step of cutting an ingot of single crystal gallium nitride along predetermined planes to make one or more signal crystal gallium nitride substrates. The ingot of single crystal gallium nitride is grown by vapor phase epitaxy in a direction of a predetermined axis. Each predetermined plane is inclined to the predetermined axis. Each substrate has a minor polished primary surface. The primary surface has a first area and a second area. The first area is between an edge of the substrate and a line 3 millimeter away from the edge. The first area surrounds the second area. An qaxis perpendicular to the primary surface forms an off-angle with c-axis of the substrate. The off-angle takes a minimum value at a first position in the first area of the primary surface.

Abstract: Embodiments include a method for fabricating a semiconductor device and the resulting structure comprising forming a semi-insulating bottom barrier on a semiconductor substrate. A channel is formed on the bottom barrier. A semi-insulating layer is epitaxially formed on the bottom barrier, laterally adjacent to the channel. The semi-insulating layer is formed in such a way that stress is induced onto the channel. A CMOS transistor is formed on the channel.

Abstract: A production method of a substrate for nitride semiconductor device comprising a mask formation step of using a metal nitride as a base material and forming a mask having a prescribed shape on the above-described base material, a three-dimensional structure growth step of growing a three-dimensional structure made of the same material as the base material on the base material having the mask formed thereon using a selective growth technique so that a layer having a higher index plane is formed on the lateral face, and an active layer growth step of growing an active layer containing a rare earth element on the lateral face of the above-described three-dimensional structure using an organometallic vapor phase epitaxial method.

Abstract: A semiconductor device includes a substrate, a compound semiconductor layer, and first and second semiconductor patterns. The substrate includes first and second regions. The first semiconductor pattern is on the compound semiconductor layer of the first region and includes an element semiconductor. The second semiconductor pattern is on the compound semiconductor layer of the second region and includes a Group III-V semiconductor material.

Abstract: A semiconductor device includes a substrate, a buffer layer on the substrate, and a plurality of nitride semiconductor layers on the buffer layer. The semiconductor device further includes at least one masking layer and at least one inter layer between the plurality of nitride semiconductor layers. The at least one inter layer is on the at least one masking layer.

Abstract: A method includes forming a gate stack over top surfaces of a semiconductor strip and insulation regions on opposite sides of the semiconductor strip. The insulation regions include first portions overlapped by the gate stack, and second portions misaligned from the gate stack. An end portion of the semiconductor strip is etched to form a recess, wherein the recess is located between the second portions of the insulation regions. An epitaxy is performed to grow a source/drain region from the recess. After the epitaxy, a recessing is performed to recess the second portions of the insulation regions, with the second portions of the insulation regions having first top surfaces after the first recessing. After the recessing, a dielectric mask layer is formed on the first top surfaces of the second portions of the insulation regions, wherein the dielectric mask layer further extends on a sidewall of the gate stack.

Abstract: A group-III nitride compound semiconductor light emitting element includes a substrate that has a main face on which an concave and convex portion is formed, a group-III nitride compound semiconductor layer that is formed on the main face of the substrate, and a clearance that is formed between the substrate and the group-III nitride compound semiconductor layer at a first region of the semiconductor light emitting element. In the first region, a portion of the group-III nitride compound semiconductor layer and a portion of the clearance are disposed in a concave of the concave and convex portion on a section through two adjacent top portions of the concave and convex portion and a bottom portion located between the adjacent top portions.

Abstract: In some embodiments, an FET structure comprises a heterostructure, and a gate structure. The heterostructure comprises a first section, a barrier section and a second section such that a portion of the first section, the barrier section, and a portion of the second section form a channel region, and portions of the first section and the second section on opposite sides of the channel region form at least portions of source and drain regions, respectively. When the channel region is p type, the barrier section has a positive valence band offset with respect to each of the first section and the second section, or when the channel region is n type, the barrier section has a positive conduction band offset with respect to each of the first section and the second section. A gate structure is configured over the channel region.

Abstract: A method of forming a semiconductor device is provided. The method includes forming a mask layer, such as an oxidized layer, over first source/drain regions in a first device region. A dielectric layer, such as an interlayer dielectric layer, is formed and patterned to expose the first source/drain regions and second source/drain regions in a second device region. A silicide treatment is performed on the second source/drain regions while the mask layer protects the first source/drain regions. The mask layer is then removed and a silicide treatment is performed on the first source/drain regions.

Abstract: A GaN HFET includes a silicon substrate with an Al2O3 layer above the silicon substrate. The Al2O3 layer has voids formed therein. A plurality of alternating GaN and AlN layers are above the Al2O3 layer. The GaN and AlN layers are under continuous compressive stress.

Abstract: A method of forming a semiconductor device substrate includes forming a donor wafer having a surface comprising regions of relaxed silicon and regions of relaxed silicon germanium (SiGe); epitaxially growing a silicon device layer on the surface of the donor wafer, wherein the silicon device layer comprises tensile strained silicon on the regions of relaxed silicon germanium of the donor wafer, and wherein the silicon device layer comprises relaxed silicon on the regions of relaxed silicon of the donor wafer; and transferring the silicon device layer from the donor wafer to a handle wafer comprising a bulk substrate and an insulator layer, so as to form a silicon-on-insulator (SOI) substrate with the silicon device layer maintaining regions of tensile strained silicon and regions of relaxed silicon.

Abstract: A CMOS semiconductor FinFET device and a method for manufacturing a CMOS semiconductor FinFET device are disclosed. The device may comprise an nFinFET and a pFinFET having a channel region comprising Ge on a common strain-relaxed buffer layer comprising SiGe. The concentration of Ge in the channel regions is higher than the concentration of Ge in the strain-relaxed buffer layer. The device further comprises a source/drain region for the nFinFET, the source/drain region comprising SiGe; and a source/drain region for the pFinFET, the second source/drain region comprising Ge.

Abstract: Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.

Abstract: A semiconductor light emitting device including a first conductive semiconductor base layer on a substrate; an insulating layer on the first conductive semiconductor base layer, the insulating layer including a plurality of openings through which the first conductive semiconductor base layer is exposed; and a plurality of nanoscale light emitting structures on the first conductive semiconductor base layer, the nanoscale light emitting structures respectively including a first conductive semiconductor core on an exposed region of the first conductive semiconductor base layer, and an active layer, and a second conductive semiconductor layer sequentially disposed on a surface of the first conductive semiconductor core, wherein a lower edge of a side portion of each nanoscale light emitting structure is on an inner side wall of the opening in the insulating layer.

Abstract: A lateral bipolar junction transistor including a base region on a dielectric substrate layer. The base region includes a layered stack of alternating material layers of a first lattice dimension semiconductor material and a second lattice dimension semiconductor material. The first lattice dimension semiconductor material is different from the second lattice dimension semiconductor material to provide a strained base region. A collector region is present on the dielectric substrate layer in contact with a first side of the base region. An emitter region is present on the dielectric substrate in contact with a second side of the base region that is opposite the first side of the base region.

Abstract: A semiconductor structure and formation thereof. The semiconductor structure has a fin of a first semiconductor material. The fin has a first side surface opposite a second side surface. The semiconductor structure has a portion of a second semiconductor material that has a third side surface opposite a fourth side surface. The fourth side surface of the second semiconductor material abuts and covers the first side surface of the fin. The semiconductor structure has a portion of a third semiconductor material that abuts and covers the second side surface of the fin. The semiconductor structure has a single gate structure that covers the fin, the portion of the second semiconductor material and the portion of the third semiconductor material. The fin manifests an asymmetry due to the portion of the second semiconductor material and the portion of the third semiconductor material.

Abstract: A semiconductor device and method of formation are provided herein. A semiconductor device includes a fin having a doped region, in some embodiments. The semiconductor device includes a gate over a channel portion of the fin. The gate including a gate electrode over a gate dielectric between a first sidewall spacer and a second sidewall spacer. The first sidewall spacer includes an initial first sidewall spacer over a first portion of a dielectric material. The second sidewall spacer includes an initial second sidewall spacer over a second portion of the dielectric material.

Abstract: A display device that includes a first flexible substrate, a first bonding layer over the first flexible substrate, a first insulating film over the first bonding layer, a first element layer over the first insulating film, a second element layer over the first element layer, a second insulating film over the second element layer, a second bonding layer over the second insulating film, and a second flexible substrate over the second bonding layer is provided. The first element layer includes a pixel portion and a circuit portion. The pixel portion includes a display element and a first transistor, and the circuit portion includes a second transistor. The second element layer includes a coloring layer and a light-blocking layer.

Abstract: A semiconductor structure including a (100) silicon substrate having a plurality openings located within the silicon substrate, wherein each opening exposes a surface of the silicon substrate having a (111) crystal plane. This structure further includes an epitaxial semiconductor material located on an uppermost surface of the (100) silicon substrate, and a gallium nitride material located adjacent to the surface of the silicon substrate having the (111) crystal plane and adjacent a portion of the epitaxial semiconductor material. The structure also includes at least one semiconductor device located upon and within the gallium nitride material and at least one other semiconductor device located upon and within the epitaxial semiconductor material.

Abstract: A method includes forming a relaxed layer in a semiconductor device. The method also includes forming a tensile layer over the relaxed layer, where the tensile layer has tensile stress. The method further includes forming a compressive layer over the relaxed layer, where the compressive layer has compressive stress. The compressive layer has a piezoelectric polarization that is approximately equal to or greater than a spontaneous polarization in the relaxed, tensile, and compressive layers. The piezoelectric polarization in the compressive layer could be in an opposite direction than the spontaneous polarization in the compressive layer. The relaxed layer could include gallium nitride, the tensile layer could include aluminum gallium nitride, and the compressive layer could include aluminum indium gallium nitride.

Abstract: Disclosed is a light emitting device. A light emitting device comprises a plurality of N-type semiconductor layers including a first N-type semiconductor layer and a second N-type semiconductor layer on the first N-type semiconductor layer, an active layer on the second N-type semiconductor layer, and a P-type semiconductor layer on the active layer, wherein the first N-type semiconductor layer comprises a Si doped Nitride layer and the second N-type semiconductor layer comprises a Si doped Nitride layer, and wherein the first and second N-type semiconductor layers have a Si impurity concentration different from each other.

Abstract: A semiconductor device includes a substrate that has a surface. The semiconductor further includes a fin disposed on the surface and including a semiconductor member. The semiconductor further includes a spacer disposed on the surface, having a type of stress, and overlapping the semiconductor member in a direction parallel to the surface. A thickness of the spacer in a direction perpendicular to the surface is less than a height of the semiconductor member in the direction perpendicular to the surface.

Abstract: A method of manufacturing a semiconductor device includes forming an active pattern protruding from a semiconductor substrate, forming a dummy gate pattern crossing over the active pattern, forming gate spacers on opposite first and second sidewalls of the dummy gate pattern, removing the dummy gate pattern to form a gate region exposing an upper surface and sidewalls of the active pattern between the gate spacers, recessing the upper surface of the active pattern exposed by the gate region to form a channel recess region, forming a channel pattern in the channel recess region by a selective epitaxial growth (SEG) process, and sequentially forming a gate dielectric layer and a gate electrode covering an upper surface and sidewalls of the channel pattern in the gate region. The channel pattern has a lattice constant different from that of the semiconductor substrate.

Abstract: A compound semiconductor device includes: a compound semiconductor layer; a protective insulating film that covers a top of the compound semiconductor layer; and a gate electrode formed on the protective insulating film, wherein the protective insulating film has a first trench and a second trench which is formed side by side with the first trench and in which the protective insulating film remains with only a predetermined thickness on the compound semiconductor layer, and wherein the gate electrode fills the first trench, and one end of the gate electrode is away from the first trench and located at least in the second trench.

Abstract: One method of forming epi semiconductor cladding materials in the channel region of a semiconductor device is disclosed which includes forming an initial epi semiconductor cladding material around the exposed portion of a fin for an entire axial length of the fin, forming a sacrificial gate structure around a portion of the fin and the initial cladding material, removing the sacrificial gate structure so as to thereby define a replacement gate cavity, performing an etching process through the replacement gate cavity to remove at least the exposed portion of the initial cladding material and thereby expose a surface of the fin within the replacement gate cavity, forming at least one replacement epi semiconductor cladding material around the exposed surface of the fin, and forming a replacement gate structure within the replacement gate cavity around the at least one replacement epi semiconductor cladding material.

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first semiconductor material and a first reactivity; and a low reactivity capping layer of disposed on the semiconductor substrate, wherein the low reactivity capping layer includes a second semiconductor material and a second reactivity less than the first reactivity, the low reactivity capping layer includes silicon germanium Si1-xGex and x is less than about 30%.

Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is overlying the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage. A metal silicide region is over and in contact with the second silicon germanium region.

Abstract: Methods of forming semiconductor devices and fin field effect transistors (FinFETs), and FinFET devices, are disclosed. In some embodiments, a method of forming a semiconductor device includes forming a barrier material comprising AlInAsSb over a substrate, and forming a channel material of a transistor over the barrier layer.

Abstract: Semiconductor micro- and nanotubes allow the incorporation of ordered structures such as quantum wells and quantum dots into them providing the potential for ultralow threshold micro- and nanoscale lasers for use in applications such as future ultrahigh-speed photonic systems as well as quantum information processing. According to the invention a means of manufacturing these with high reproducibility, low processing complexity, and at high densities is provided. Also provided is a means of releasing these micro- and nanotubes with low stress and a method of “pick-and-place” allowing micro- and nanotubes to be exploited in devices integrated on substrates that are either incompatible with the manufacturing technique or where the area of substrate required to manufacture them is detrimental to the cost or performance of the circuit.

Abstract: A method for forming a semiconductor device including a GaN FET, an overvoltage clamping component, and a voltage dropping component. The GaN FET is formed by forming a low-defect layer comprising gallium nitride, a barrier layer comprising AlxGa1?xN, a gate, and source and drain contacts. The overvoltage clamping component is coupled to a drain node of the GaN FET. The overvoltage clamping component conducts insignificant current when a voltage at the drain node is less than a safe voltage limit and conducts significant current when the voltage rises above the safe voltage limit. The voltage dropping component is coupled to the overvoltage clamping component and to a terminal for a bias potential. The voltage dropping component provides a voltage drop which increases as current from the overvoltage clamping component increases. The GaN FET turns on when the voltage drop reaches a threshold value.

Abstract: A method includes forming a semiconductor fin over top surfaces of insulation regions, and forming a gate stack on a top surface and sidewalls of a middle portion of the semiconductor fin. The insulation regions include first portions overlapped by the gate stack, and second portions misaligned from the gate stack. An end portion of the semiconductor fin is etched to form a recess located between the second portions of the insulation regions. An epitaxy is performed to grow a source/drain region from the recess. After the epitaxy, a recessing is performed to recess the second portions of the insulation regions, with the second portions of the insulation regions having first top surfaces after the first recessing. A dielectric mask layer is formed on the first top surfaces of the second portions of the insulation regions. The dielectric mask layer further extends on a sidewall of the gate stack.

Abstract: A method of forming a semiconductor device substrate includes forming a donor wafer having a surface comprising regions of relaxed silicon and regions of relaxed silicon germanium (SiGe); epitaxially growing a silicon device layer on the surface of the donor wafer, wherein the silicon device layer comprises tensile strained silicon on the regions of relaxed silicon germanium of the donor wafer, and wherein the silicon device layer comprises relaxed silicon on the regions of relaxed silicon of the donor wafer; and transferring the silicon device layer from the donor wafer to a handle wafer comprising a bulk substrate and an insulator layer, so as to form a silicon-on-insulator (SOI) substrate with the silicon device layer maintaining regions of tensile strained silicon and regions of relaxed silicon.

Abstract: A semiconductor structure comprises a substrate comprising a first crystalline semiconductor material, a dielectric layer, above the substrate, defining an opening, a second crystalline semiconductor material at least partially filling the opening, and a crystalline interlayer between the substrate and the second crystalline semiconductor material. The first crystalline semiconductor material and the second crystalline semiconductor material are lattice mismatched, and the crystalline interlayer comprises an oxygen compound. A method for fabricating semiconductor structure comprises the steps of providing a substrate including a first crystalline semiconductor material, patterning an opening in a dielectric layer above the substrate, the opening having a bottom, forming a crystalline interlayer on the substrate at least partially covering the bottom, and growing a second crystalline semiconductor material on the crystalline interlayer thereby at least partially filling the opening.

Abstract: A method for manufacturing a sapphire substrate in which a plurality of projections are formed on a C-plane of the sapphire substrate by etching, includes: forming a patterned etching mask on the C-plane of the sapphire substrate; etching the sapphire substrate until the projections are formed, wherein each of the projections formed by the etching has a substantially triangular pyramidal-shape and has a plurality of side surfaces, a pointed top and a bottom, wherein the bottom of each of the projections has a substantially triangular shape having three outwardly curved arc-shaped sides. The projections are arranged on vertexes of a triangular lattice, and an orientation of the bottom of the projections conforms with an orientation that is rotated by about 30 degrees from an orientation of a triangle of the triangular lattice; and removing the etching mask from the sapphire substrate.

Abstract: Atomic layer deposition (ALD) or ALD-like deposition processes are used to fabricate dilute nitride III-V semiconductor materials. A first composition of process gases may be caused to flow into a deposition chamber, and a group V element other than nitrogen and one or more group III elements may be adsorbed over the substrate (in atomic or molecular form). Afterward, a second composition of process gases may be caused to flow into the deposition chamber, and N and one or more group III elements may be adsorbed over the substrate in the deposition chamber. An epitaxial layer of dilute nitride III-V semiconductor material may be formed over the substrate in the deposition chamber from the sequentially adsorbed elements.

Abstract: A semiconductor device having dislocations and a method of fabricating the semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate having an isolation feature therein and two gate stacks overlying the substrate, wherein one of the gate stacks is atop the isolation feature. The method further includes performing a pre-amorphous implantation process on the substrate. The method further includes forming a stress film over the substrate. The method also includes performing an annealing process on the substrate and the stress film.

Abstract: A method of forming a semiconductor structure includes forming a multilayer lattice matched structure having an unstrained layer, a first strained layer, and a second strained layer formed between the unstrained and the first strained layer. A first opening in the multilayer structure is etched and a second strained fill material having a same material as the second strained layer is deposited. A second opening in the multilayer structure is etched and an unstrained fill material having a same material as the unstrained layer is deposited. A first strained fill material having a same material as the first strained layer is then deposited between the unstrained fill and the second strained fill. A second strained fin is formed from the deposited second strained fill material, a first strained fin is formed from the deposited first strained fill material, and an unstrained fin is formed from the deposited unstrained fill material.

Abstract: The present invention provides a method for manufacturing a semiconductor device, which comprises: providing an SOI substrate, which comprises a base layer, an insulating layer located on the base layer and a active layer located on the insulating layer; forming a gate stack on the SOI substrate; etching the active layer, the insulating layer and a part of the base layer of the SOI substrate with the gate stack as a mask, so as to form trenches on both sides of the gate stack; forming a crystal dielectric layer within the trenches, wherein the upper surface of the crystal dielectric layer is lower than the upper surface of the insulating layer and not lower than the lower surface of the insulating layer; and forming source/drain regions on the crystal dielectric layer. The present invention further provides a semiconductor device.