Doping On Side Of Heterojunction With Lower Carrier Affinity (e.g., High Electron Mobility Transistor (hemt)) Patents (Class 257/194)
  • Patent number: 10347755
    Abstract: Provided are a group 13 nitride composite substrate allowing for the production of a semiconductor device suitable for high-frequency applications while including a conductive GaN substrate, and a semiconductor device produced using this substrate. The group 13 nitride composite substrate includes a base material of an n-conductivity type formed of GaN, a base layer located on the base material, being a group 13 nitride layer having a resistivity of 1×106 ?·cm or more, a channel layer located on the base layer, being a GaN layer having a total impurity density of 1×1017/cm3 or less, and a barrier layer that is located on the channel layer and is formed of a group 13 nitride having a composition AlxInyGa1-x-yN (0?x?1, 0?y?1).
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: July 9, 2019
    Assignee: NGK INSULATORS, LTD.
    Inventors: Yoshitaka Kuraoka, Mikiya Ichimura, Makoto Iwai
  • Patent number: 10347738
    Abstract: Fabrication of a dual enhancement-mode/depletion-mode (E-Mode/D-Mode) high electron mobility transistor (HEMT) called a threshold control terminal HEMT (TCT-HEMT) is performed which reduces capacitance between the TCT electrode and the source and drain electrodes of a TCT-HEMT, since such a capacitance may be parasitic, and which fabricates a TCT-HEMT capable of high-frequency operation. A method for fabricating a field-effect transistor (FET) includes: providing a substrate; disposing a back barrier on the substrate to form a base stack; forming a doped layer on the base stack; grow additional layers, including a threshold-control terminal (TCT) access layer; etch a pattern in at least one of the doped layer and the additional layers; and disposing a TCT contact on the TCT access layer.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: July 9, 2019
    Assignee: Duet Microelectronics, Inc.
    Inventors: Ashok T. Ramu, Keun-Yong Ban, John Bayruns, Robert J. Bayruns
  • Patent number: 10325982
    Abstract: A transistor device comprises a base structure and a superlattice of conducting channels overlying the base structure. The superlattice of conducting channels includes source and drain access regions spaced-apart from each other, a ledge between and spaced-apart from the source and drain access regions, and source-side alternating multichannel ridges and trenches that extend from the source access region to the ledge, each ridge having a topside and opposing sidewalls that each extend from the ledge to the source access region. The transistor device includes gate metal that covers each ridge continuously from the ledge to the source access region, such that the gate metal completely covers the topside of the ridge and edges of the conducting channels that intersect the sidewalls of the ridge.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: June 18, 2019
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Josephine Chang, Ken Alfred Nagamatsu, Robert Samuel Howell, Shalini Gupta
  • Patent number: 10326046
    Abstract: A growth method of aluminum gallium nitride is disclosed. The method includes the steps of: providing a substrate; forming a first aluminum gallium nitride layer on the substrate at a first temperature; and forming a second aluminum gallium nitride layer, on the first aluminum gallium nitride layer, at a second temperature. The first temperature is higher than the second temperature.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: June 18, 2019
    Assignee: Epileds Technologies, Inc.
    Inventors: Kung-Hsieh Hsu, Ming-Sen Hsu
  • Patent number: 10319580
    Abstract: A semiconductor device structure comprising: a layer of compound semiconductor material; and a layer of polycrystalline CVD diamond material, wherein the layer of polycrystalline CVD diamond material is bonded to the layer of compound semiconductor material via a layer of nano-crystalline diamond which is directly bonded to the layer of compound semiconductor material, the layer of nano-crystalline diamond having a thickness in a range 5 to 50 nm and configured such that an effective thermal boundary resistance (TBReff) as measured by transient thermoreflectance at an interface between the layer of compound semiconductor material and the layer of polycrystalline CVD diamond material is no more than 50 m2K/GW.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: June 11, 2019
    Assignee: RFHIC CORPORATION
    Inventors: Firooz Nasser-Faili, Daniel Francis, Frank Yantis Lowe, Daniel James Twitchen
  • Patent number: 10319646
    Abstract: Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventors: Marko Radosavljevic, Ravi Pillarisetty, Gilbert Dewey, Niloy Mukherjee, Jack Kavalieros, Willy Rachmady, Van Le, Benjamin Chu-Kung, Matthew Metz, Robert Chau
  • Patent number: 10304923
    Abstract: A method of manufacturing a semiconductor die includes forming a semiconductor body on a substrate. The semiconductor body has a periphery which is devoid of active devices and terminates at an edge face of the semiconductor die. The semiconductor body includes a first III-nitride semiconductor layer and a plurality of second III-nitride semiconductor layers below the first III-nitride semiconductor layer. The method further includes forming an uninsulated connection structure which extends vertically in the periphery of the semiconductor body and provides a vertical leakage path for at least some of the second III-nitride semiconductor layers either to the substrate or to a metallization layer disposed above the semiconductor body, but not to both. Additional semiconductor die manufacturing methods are provided.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: May 28, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Clemens Ostermaier, Gerhard Prechtl, Oliver Häberlen
  • Patent number: 10290708
    Abstract: Semiconductor devices and methods of forming the same are provided. A first gate electrode layer is formed over a substrate. A first gate dielectric layer is formed over the first gate electrode layer. A first channel layer is formed over the first gate dielectric layer. An isolation layer is formed over the first channel layer. A second channel layer is formed over the isolation layer. A second gate dielectric layer is formed over the second channel layer. The second gate dielectric layer, the second channel layer, the isolation layer and the first channel layer are patterned to form a first opening, the first opening extending through the first gate dielectric layer, the second channel layer and the isolation layer, and into the first channel layer. A first source/drain region is formed in the first opening.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: May 14, 2019
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University
    Inventors: Pin-Shiang Chen, Samuel C. Pan, Chee-Wee Liu, Sheng-Ting Fan
  • Patent number: 10290730
    Abstract: A semiconductor power device includes an engineered aluminum-nitride substrate structure, and method of fabricating the same are described. The engineered substrate structure is effectively integrated with a transition layer of AlN/AlGaN disposed thereon, a buffer layer disposed on the transition layer having a C—(Al)GaN/u-GaN multiple stacking layered structure, a channel layer, a barrier layer, and an optional SiNx interlayer together, to form a GaN-based semiconductor power device. The GaN buffer layer is capable of achieving sufficient thickness for higher performance. The engineered substrate structure has a core region made of an aluminum nitride (AlN) substrate, a single crystal silicon layer as top material layer thereof, and bonded together with an encapsulated multi-layered structure containing adhesive layers, thin film layers and the AlN substrate.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: May 14, 2019
    Assignee: Epistar Corporation
    Inventors: Ya-Yu Yang, Yu-Jiun Shen, Chia-Cheng Liu
  • Patent number: 10283599
    Abstract: A transistor includes a first layer over a substrate. The transistor also includes a second layer over the first layer. The transistor further includes a carrier channel layer at an interface of the first layer and the second layer. The transistor additionally includes a gate structure, a drain, and a source over the second layer. The transistor also includes a passivation material in the second layer between an edge of the gate structure and an edge of the drain in a top-side view. The carrier channel layer has a smaller surface area than the first layer between the edge of the gate structure and the edge of the drain in the top-side view.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: May 7, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fu-Wei Yao, Chun-Wei Hsu, Chen-Ju Yu, Jiun-Lei Jerry Yu, Fu-Chih Yang, Chih-Wen Hsiung, King-Yuen Wong
  • Patent number: 10283598
    Abstract: Disclosed is a novel III-V heterojunction field effect transistor comprising a substrate layer, a first semiconductor layer, a second semiconductor layer, a drain electrode, a source electrode, a gate electrode, a first dielectric layer, second dielectric layers and the like, wherein the first semiconductor layer has a greater bandgap compared with the second semiconductor layer, and the second semiconductor layer and the first semiconductor layer are combined to form a heterostructure. The thickness of the first semiconductor layer is not greater than the critical thickness of two-dimensional electron gas formed in a heterojunction channel, and thus natural 2DEG in the heterojunction channel is depleted. The novel III-V heterojunction field effect transistor has the advantages of being simple in structure, simple in preparation process, stable in performance, high in reliability and the like.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: May 7, 2019
    Assignee: Hangzhou Dianzi University
    Inventors: Zhihua Dong, Zhiqun Cheng, Guohua Liu, Huajie Ke
  • Patent number: 10276703
    Abstract: A compound semiconductor device includes: a carrier transit layer; a carrier supply layer over the carrier transit layer; a source electrode and a drain electrode above the carrier supply layer; a gate electrode above the carrier supply layer between the source electrode and the drain electrode; and a first insulating film and a second insulating film above the carrier supply layer between the gate electrode and the drain electrode. The gate electrode includes a portion above the second insulating film, the second insulating film covers a side surface of the first insulating film from the drain electrode side, and a second concentration of electron traps in the second insulating film is higher than a first concentration of electron traps in the first insulating film.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: April 30, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Youichi Kamada, Shirou Ozaki
  • Patent number: 10276712
    Abstract: A field effect transistor (FET) includes a III-nitride channel layer, a III-nitride barrier layer on the channel layer, a first dielectric on the barrier layer, a first gate trench extending through the first dielectric, and partially or entirely through the barrier layer, a second dielectric on a bottom and walls of the first gate trench, a source electrode on a first side of the first gate trench, a drain electrode on a second side of the first gate trench opposite the first side, a first gate electrode on the second dielectric and filling the first gate trench, a third dielectric between the first gate trench and the drain electrode, a second gate trench extending through the third dielectric and laterally located between the first gate trench and the drain electrode, and a second gate electrode filling the second gate trench.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: April 30, 2019
    Assignee: HRL Laboratories, LLC
    Inventor: Rongming Chu
  • Patent number: 10269947
    Abstract: An electronic device can include a transistor. The transistor can include a first layer including a first III-V material, a second layer overlying the first layer and including a second III-V material, and a third layer overlying the first layer and including a third III-V material. In an embodiment, each of the first and second layers includes Al, and the second layer has a higher Al content as compared to the first layer. In another embodiment, the transistor can further include a gate dielectric layer overlying the third layer, and a gate electrode of the transistor overlying the gate dielectric layer and the third layer. The transistor can be an enhancement-mode high electron mobility transistor. The configuration of layers can allow for a relatively higher threshold voltage, as compared to conventional enhancement-mode high electron mobility transistor, to be achieved without significantly affecting RDSON.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: April 23, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Peter Moens, Piet Vanmeerbeek, Abhishek Banerjee
  • Patent number: 10269791
    Abstract: A transistor that is formed with a transition metal dichalcogenide material is provided. The transition metal dichalcogenide material is formed using a direct deposition process and patterned into one or more fins. A gate dielectric and a gate electrode are formed over the one or more fins. Alternatively, the transition metal dichalcogenide material may be formed using a deposition of a non-transition metal dichalcogenide material followed by a treatment to form a transition metal dichalcogenide material. Additionally, fins that utilized the transition metal dichalcogenide material may be formed with sidewalls that are either perpendicular to a substrate or else are sloped relative to the substrate.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yee-Chia Yeo, Ling-Yen Yeh, Yuan-Chen Sun
  • Patent number: 10263103
    Abstract: A semiconductor apparatus includes an electron transit layer formed of a nitride semiconductor over a substrate; an electron supply layer formed of a nitride semiconductor including In over the electron transit layer; a cap layer formed of a nitride semiconductor over the electron supply layer; an insulation film formed over the cap layer; a source electrode and a drain electrode formed over the electron transit layer or the electron supply layer; and a gate electrode formed over the cap layer. A quantum well is formed by the cap layer.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: April 16, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Kozo Makiyama
  • Patent number: 10263104
    Abstract: A method of manufacturing a III-V semiconductor circuit; the method comprising: forming a first layer of a III-V material on a growth substrate; forming a second layer of a III-V material on the first layer of III-V material; forming a FET transistor having a source electrode and a drain electrode in contact with a top surface of the second layer of a III-V material; forming a top dielectric layer above the FET transistor; forming a metal layer above the top dielectric layer, wherein said metal layer is connected to said source electrode; attaching a handle substrate to a top surface of the metal layer; removing the growth substrate from the bottom of the first layer of a III-V material; and forming a bottom dielectric layer on the bottom of the first layer of a III-V material.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: April 16, 2019
    Assignee: HRL Laboratories, LLC
    Inventors: Zijian “Ray” Li, Rongming Chu
  • Patent number: 10256294
    Abstract: The present disclosure relates to a vertical gallium-nitride (GaN) power field-effect transistor (FET) with a field plate structure. The vertical GaN power FET includes a conductive substrate, a drift region, a field plate structure, a channel region with tapered side walls, a gate dielectric region, a gate contact, a drain contact and source contacts. The field plate structure includes a lower layer formed of pi p-type graded AlGaN and a upper layer formed of p-type GaN. The field plate structure utilizes the charge separation at the interface between the lower layer and the upper layer to achieve high breakdown voltage.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: April 9, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Subrahmanyam V. Pilla, Tso-Min Chou
  • Patent number: 10256332
    Abstract: A high hole mobility transistor includes a substrate, a back-barrier layer, a conducting layer, a doping layer, a gate electrode, source/drain electrodes, and a band adjustment layer. The back-barrier layer is disposed on the substrate. The conducting layer is disposed on the back-barrier layer. A channel region is disposed in the conducting layer and is adjacent to the interface between the conducting layer and the back-barrier layer. The doping layer is disposed on the conducting layer. The gate electrode is disposed on the doping layer. The source/drain electrodes are disposed on opposite sides of the gate electrode. The band adjustment layer is disposed on the doping layer and electrically connected to the gate electrode. The band adjustment layer is an N-type doped III-V semiconductor.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: April 9, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Fu-Hsin Chen, Yung-Hao Lin, Shin-Cheng Lin, Hsin-Chih Lin, Chia-Ching Huang
  • Patent number: 10229912
    Abstract: According to the present invention, a semiconductor device includes a semiconductor layer, a source electrode provided in the semiconductor layer, a drain electrode provided in the semiconductor layer and disposed away from the source electrode, a first gate electrode provided between the source electrode and the drain electrode and a second gate electrode provided between the source electrode and the drain electrode, the second gate electrode having at least a part thereof located closer to the drain electrode than the first gate electrode. The semiconductor layer includes a first facing part that is a part facing the first gate electrode; and a second facing part that is a part facing the second gate electrode. The first facing part does not conduct when a first gate voltage is 0 V or less. The second facing part does not conduct when a second gate voltage is 0 V or less.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: March 12, 2019
    Assignee: ADVANTEST CORPORATION
    Inventors: Taku Sato, Kazuya Uryu, Kazuyuki Shouji
  • Patent number: 10224401
    Abstract: A III-N device includes a III-N layer structure including a III-N channel layer, a III-N barrier layer over the III-N channel layer, and a graded III-N layer over the III-N barrier layer having a first side adjacent to the III-N barrier layer and a second side opposite the first side; a first power electrode and a second power electrode; and a gate between the first and second power electrodes, the gate being over the III-N layer structure. A composition of the graded III-N layer is graded so the bandgap of the graded III-N layer adjacent to the first side is greater than the bandgap of the graded III-N layer adjacent to the second side. A region of the graded III-N layer is (i) between the gate and the second power electrode, and (ii) electrically connected to the first power electrode and electrically isolated from the second power electrode.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: March 5, 2019
    Assignee: Transphorm Inc.
    Inventors: Umesh Mishra, Rakesh K. Lal, Geetak Gupta, Carl Joseph Neufeld, David Rhodes
  • Patent number: 10224426
    Abstract: A device includes a first high electronic mobility transistor (HEMT) and a second HEMT. The first HEMT includes a first gate, a source coupled to the first gate, and a drain coupled to the first gate. The second HEMT includes a second gate coupled to the source and to the drain. The second HEMT has a lower threshold voltage than the first HEMT.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: March 5, 2019
    Assignee: Vishay-Siliconix
    Inventors: Ayman Shibib, Kyle Terrill
  • Patent number: 10217855
    Abstract: A semiconductor substrate and a semiconductor device are disclosed. The semiconductor substrate includes a base layer, a buffer layer disposed on the base layer, a channel layer disposed on the buffer layer, a barrier layer disposed on the channel layer, and a buried field plate region embedded in the channel layer. In an embodiment, the channel layer includes a two-dimensional electron gas (2DEG), and the buried field plate region is located below the two-dimensional electron gas.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: February 26, 2019
    Assignee: Nuvoton Technology Corporation
    Inventors: Chih-Wei Chen, Heng-Kuang Lin
  • Patent number: 10217829
    Abstract: A compound semiconductor device disclosed herein includes a substrate, an electron transit layer formed on the substrate, a compound semiconductor layer containing gallium and formed on the electron transit layer, a diffusion preventing layer containing gallium oxide and formed on the compound semiconductor layer, an insulation layer formed on the diffusion preventing layer, and a source electrode, a drain electrode, and a gate electrode formed over the electron transit layer at a distance from one another.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: February 26, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Kozo Makiyama
  • Patent number: 10217854
    Abstract: The embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a first III-V compound layer disposed over a substrate and a second III-V compound layer disposed over the first III-V compound layer, wherein a first carrier channel is formed in the interface between the first III-V compound layer and the second III-V compound layer. The semiconductor device also includes a third III-V compound layer disposed over the second III-V compound layer and a fourth III-V compound layer disposed over the third III-V compound layer, wherein a second carrier channel is formed in an interface between the third III-V compound layer and the fourth III-V compound layer. The semiconductor device includes a gate structure and S/D regions disposed on two opposite sides of the gate structure, wherein the first carrier channel and the second carrier channel are extended between the S/D regions.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: February 26, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Yung-Hao Lin, Shin-Cheng Lin, Hsin-Chih Lin
  • Patent number: 10217641
    Abstract: A GaN device is formed on a semiconductor substrate having a plurality of recessed regions formed in a surface thereof. A seed layer, optional buffer layer, and gallium nitride layer such as a carbon-doped gallium nitride layer are successively deposited within the recessed regions. Improved current collapse response of the GaN device is attributed to maximum length and width dimensions of the multilayer stack.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: February 26, 2019
    Assignees: International Business Machines Corporation, MASSACHUSETTS INSTITUTE OF TECHNOLOGY
    Inventors: William J. Gallagher, Marinus Johannes Petrus Hopstaken, Ko-Tao Lee, Tomas Palacios, Daniel Piedra, Devendra K. Sadana
  • Patent number: 10199476
    Abstract: A mesa portion of a semiconductor device, which includes a channel base layer formed of a first nitride semiconductor layer, a channel layer formed of a second nitride semiconductor layer, a barrier layer formed of a third nitride semiconductor layer, a mesa-type fourth nitride semiconductor layer, a gate insulating film that covers the mesa portion, and a gate electrode formed over the gate insulating film, is used as a co-doped layer. The mesa portion is used as the co-doped layer, so that interface charges generated at an interface between the gate insulating film and the mesa portion can be cancelled by p-type impurity or n-type impurity in the co-doped layer and a threshold potential can be improved. Further, the fourth nitride semiconductor layer is n-type until the gate insulating film is formed, and the fourth nitride semiconductor layer is made neutral or p-type after the gate insulating film is formed.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: February 5, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsuo Nakayama, Hironobu Miyamoto, Yasuhiro Okamoto
  • Patent number: 10181532
    Abstract: An electronic device includes a drift region having a first conductivity type and a grid including a plurality of doped regions formed in the drift region and having a second conductivity type. The doped regions have a dopant concentration greater than 2.2×1019 cm?3. Related methods are also disclosed.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: January 15, 2019
    Assignee: Cree, Inc.
    Inventors: Mrinal Kanti Das, Doyle Craig Capell
  • Patent number: 10177219
    Abstract: A semiconductor device, including a semiconductor layer of a first conductivity type, and a parallel pn layer formed on a surface of the semiconductor layer. The parallel pn layer includes a plurality of first semiconductor regions of the first conductivity type, and a plurality of second semiconductor regions of a second conductivity type. The first and second semiconductor regions are alternatingly arranged in a direction parallel to the surface of the semiconductor layer. Each second semiconductor region has at least one first region that is a region having a group 18 element introduced therein.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: January 8, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Shuhei Tatemichi, Shunji Takenoiri
  • Patent number: 10170613
    Abstract: A semiconductor device includes a transistor, a semiconductor layer, an active region and a conductive layer. The active region is in the semiconductor layer. The conductive layer is configured to maintain a channel in the active region when the transistor is triggered to be conducted.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: January 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Syuan Lin, Jiun-Lei Yu, Ming-Cheng Lin, Chun Lin Tsai
  • Patent number: 10170580
    Abstract: A GaN-based transistor device comprises a substrate; a buffer layer disposed on the substrate; a channel layer disposed on the buffer layer; a barrier layer disposed on a part of the channel layer; a passivation layer disposed on the barrier layer; wherein the barrier layer and the passivation layer comprise a first side wall and a second side wall; a barrier metal layer disposed on the passivation layer has a first opening that exposes a part of the passivation layer, and the passivation layer has a second opening located in the first opening; a gate electrode disposed on the exposed part of the barrier layer, a source electrode disposed on the channel layer covers the first side wall and a part of the barrier metal layer, and a drain electrode disposed on the channel layer covers the second side wall and another part of the barrier metal layer.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: January 1, 2019
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Kan-Hsueh Tsai, Heng-Yuan Lee
  • Patent number: 10170438
    Abstract: A semiconductor circuit includes a three-terminal high voltage semiconductor device, a charge distribution structure and a static discharge system. The charge distribution structure has a plurality of conductors with a floating potential. The charge distribution structure is capacitively coupled to a first terminal of the semiconductor device. The static discharge system removes charge that accumulates on at least a subset of the conductors. The static discharge system removes the charge that accumulates on the subset of conductors when the semiconductor device is in a first state while allowing charge to accumulate on the subset of conductors when the semiconductor device is in a second state.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: January 1, 2019
    Assignee: POWER INTEGRATIONS. INC.
    Inventors: Alexey Kudymov, Jamal Ramdani
  • Patent number: 10164011
    Abstract: A nitride semiconductor device includes a substrate; a nitride semiconductor layered structure disposed on the substrate and having a channel region; a first electrode and a second electrode both disposed on the nitride semiconductor layered structure; a first p-type nitride semiconductor layer disposed between the first electrode and the second electrode; and a first gate electrode disposed on the first p-type nitride semiconductor layer. The nitride semiconductor layered structure includes a first recess. The first p-type nitride semiconductor layer is at least partially disposed inside the first recess, and is separated from a side surface of the first recess.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: December 25, 2018
    Assignee: PANASONIC CORPORATION
    Inventors: Yusuke Kinoshita, Hidekazu Umeda, Satoshi Tamura
  • Patent number: 10157994
    Abstract: A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A dielectric passivation layer is disposed on the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer, and extend through the dielectric passivation layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. The gate electrode has an exterior surface. An oxygen containing region is embedded at least in the second III-V compound layer under the gate electrode. A gate dielectric layer has a first portion and a second portion. The first portion is under the gate electrode and on the oxygen containing region. The second portion is on a portion of the exterior surface of the gate electrode.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Han-Chin Chiu, Chi-Ming Chen, Chung-Yi Yu, Chia-Shiung Tsai
  • Patent number: 10147811
    Abstract: A process of forming a High Electron Mobility Transistor (HEMT) is disclosed. The HEMT includes a substrate, a channel layer, a barrier layer, and heavily doped regions made of metal oxide. The channel layer and the barrier layer provide recesses and a mesa therebetween. The heavily doped regions are formed by partially removing portions of a heavily doped layer on the mesa so as to have slant surfaces facing the gate electrode. The slant surfaces make angle of 135° to 160° relative to the top horizontal level of the mesa.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: December 4, 2018
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Ken Nakata
  • Patent number: 10128338
    Abstract: Within examples, a semiconductor device includes a first structure that includes a first doped semiconductor material of a first doping type. The semiconductor device further includes a metal in contact with the first structure, and a second structure that includes a second doped semiconductor material of the first doping type in contact with the first structure. A band off-set for majority charge carriers between the first doped semiconductor material and the second doped semiconductor material is sufficiently large for charge carriers from the second doped semiconductor material to be transferred into the first doped semiconductor material.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: November 13, 2018
    Assignee: IMEC VZW
    Inventors: Hao Yu, Geoffrey Pourtois
  • Patent number: 10128362
    Abstract: A layer structure for a normally-off transistor has an electron-supply layer made of a group-III-nitride material, a back-barrier layer made of a group-III-nitride material, a channel layer between the electron-supply layer and the back-barrier layer, made of a group-III-nitride material having a band-gap energy that is lower than the band-gap energies of the other layer mentioned. The material of the back-barrier layer is of p-type conductivity, while the material of the electron-supply layer and the material of the channel layer are not of p-type conductivity, the band-gap energy of the electron-supply layer is smaller than the band-gap energy of the back-barrier layer. In absence of an external voltage a lower conduction-band-edge of the third group-III-nitride material in the channel layer is higher in energy than a Fermi level of the material in the channel layer.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: November 13, 2018
    Assignee: AZURSPACE Solar Power GmbH
    Inventors: Stephan Lutgen, Saad Murad
  • Patent number: 10128363
    Abstract: Provided is a field-effect transistor (FET) that achieves compatibility between a higher current density and lower contact resistance and exhibits excellent properties, and a method for producing the FET. The FET includes: a channel layer above a substrate; an InAlN layer above the channel layer; an InxAlyGa1-(x+y)N layer on the InAlN layer, where 0<x<1, 0<y<1, and x+y<1; and a source electrode and a drain electrode formed on the InxAlyGa1-(x+y)N layer.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: November 13, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Satoshi Nakazawa, Tetsuzo Ueda
  • Patent number: 10103064
    Abstract: The present disclosure provides an integrated circuit device including n-channel and p-channel MOSFETs. The MOSFETs include epitaxial grown raised source/drain regions and epitaxial grown channel regions. An epitaxially grown diffusion barrier layer separates the epitaxial grown channel regions from underlying deep n-wells and p-wells. The epitaxial source/drain regions allow for a low thermal budget that in combination with the diffusion barrier layer allows the deep n-wells and p-wells to be heavily doped while preserving high purity in the channel layers.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: October 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kun-Mu Li, Chii-Horng Li, Tze-Liang Lee
  • Patent number: 10096683
    Abstract: A III-N semiconductor channel is formed on a III-N transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the III-N epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness. In embodiments, a transition layer is GaN and the semiconductor channel comprises Indium (In) to increase a conduction band offset from the silicon fin. In other embodiments, the fin is sacrificial and either removed or oxidized, or otherwise converted into a dielectric structure during transistor fabrication. In certain embodiments employing a sacrificial fin, the III-N transition layer and semiconductor channel is substantially pure GaN, permitting a breakdown voltage higher than would be sustainable in the presence of the silicon fin.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: October 9, 2018
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic, Benjamin Chu-Kung, Sanaz Gardner, Seung Hoon Sung, Robert S. Chau
  • Patent number: 10096550
    Abstract: A semiconductor structure having a Group III-N semiconductor layer disposed on a substrate. A multi-layer, electrical contact structure in contact with the Group III-N semiconductor layer includes a gold-free contact layer in contact with the Group III-N semiconductor layer; and a gold-free electrically conductive etch stop layer electrically connected to the gold-free contact layer. An electrically conductive via passes through the substrate to the etch stop layer. The structure includes a plurality of electrode structures, each one providing a corresponding one of a source electrode structure, drain electrode structure and a gate electrode structure. The source electrode structure, drain electrode structure and gate electrode structure include: an electrical contact structure and an electrode contact. The electrode contacts have the same gold-free structure and have co-planar upper surfaces.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: October 9, 2018
    Assignee: RAYTHEON COMPANY
    Inventors: Jeffrey R. LaRoche, Eduardo M. Chumbes, Kelly P. Ip, Thomas E. Kazior
  • Patent number: 10090172
    Abstract: The present disclosure relates to a process of forming a semiconductor device with a high thermal conductivity substrate. According to an exemplary process, a semiconductor precursor including a substrate structure, a buffer structure over the substrate structure, and a channel structure over the buffer structure is provided. The channel structure has a first channel surface and a second channel surface, which is opposite the first channel surface, adjacent to the buffer structure, and has a first polarity. Next, a high thermal conductivity substrate with a thermal conductivity greater than 400 W/mK is formed over the first channel surface. A heat sink carrier is then provided over the high thermal conductivity substrate. Next, the substrate structure and the buffer structure are removed to provide a thermally enhanced semiconductor device with an exposed surface, which has the first polarity.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: October 2, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Xing Gu, Jinqiao Xie, Edward A. Beam, III, Cathy Lee
  • Patent number: 10084074
    Abstract: A compound semiconductor transistor may include a channel layer. The compound semiconductor transistor may also include a dielectric layer on the channel layer. The compound semiconductor transistor may further include a gate. The gate may include a vertical base portion through the dielectric layer and electrically contacting the channel layer. The gate may also include a head portion on the dielectric layer and electrically coupled to the vertical base portion of the gate.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: September 25, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Bin Yang, Gengming Tao, Xia Li, Periannan Chidambaram
  • Patent number: 10084047
    Abstract: A semiconductor structure includes a substrate, a transition body over the substrate, a group III-V intermediate body having a bottom surface over the transition body and a group III-V device layer over a top surface of the group III-V intermediate body. The group III-V intermediate body has a first impurity concentration at the bottom surface, a second impurity concentration at the top surface, and a variable impurity concentration that rises and falls between the bottom surface and the top surface. The first impurity concentration is greater than the second impurity concentration.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: September 25, 2018
    Assignee: Infineon Technologies Americas Corp.
    Inventor: Michael A. Briere
  • Patent number: 10079285
    Abstract: A semiconductor device according to an embodiment includes a nitride semiconductor layer, an insulating layer provided on the nitride semiconductor layer, a first region provided in the nitride semiconductor layer, and a second region which is provided between the first region and the insulating layer in the nitride semiconductor layer and has a higher electric resistivity than the first region.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: September 18, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Hisashi Saito
  • Patent number: 10068974
    Abstract: A field plate power device comprises: a substrate; a multilayer semiconductor layer disposed on the substrate; a source electrode, a drain electrode, and a gate electrode located between the source electrode and the drain electrode disposed on the multilayer semiconductor layer; a dielectric layer disposed on the gate electrode, a part of the multilayer semiconductor layer between the gate electrode and the source electrode and another part of the multilayer semiconductor layer between the gate electrode and the drain electrode; a groove disposed in a part of the dielectric layer between the gate electrode and the drain electrode; and a field plate disposed on the groove. The field plate comprises a first portion away from the gate electrode in a horizontal direction, the first portion has an overall upward tilted shape in the horizontal direction away from the gate electrode.
    Type: Grant
    Filed: February 25, 2017
    Date of Patent: September 4, 2018
    Assignee: GPOWER SEMICONDUCTOR, INC.
    Inventors: Yuan Li, Yi Pei, Feihang Liu
  • Patent number: 10056478
    Abstract: Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a semiconductive substrate. A donor-supply layer is over the semiconductive substrate. The donor-supply layer includes a top surface. A gate structure, a drain, and a source are over the donor-supply layer. A passivation layer covers conformally over the gate structure and the donor-supply layer. A gate electrode is over the gate structure. A field plate is disposed on the passivation layer between the gate electrode and the drain. The field plate includes a bottom edge. The gate electrode having a first edge in proximity to the field plate, the field plate comprising a second edge facing the first edge, a horizontal distance between the first edge and the second edge is in a range of from about 0.05 to about 0.5 micrometers.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: August 21, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ming-Wei Tsai, King-Yuen Wong, Chih-Wen Hsiung, Ming-Cheng Lin
  • Patent number: 10032899
    Abstract: A semiconductor crystal substrate includes a substrate, a first semiconductor layer including a nitride semiconductor and formed over the substrate, a second semiconductor layer including a nitride semiconductor and formed over the first semiconductor layer, a first cap layer formed on the second semiconductor layer, and a second cap layer formed on the first cap layer. Each of the first semiconductor layer and the second semiconductor layer has a single-crystal structure, the first cap layer has one of a single-crystal structure and a polycrystalline structure, and the second cap layer has an amorphous structure.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: July 24, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Junji Kotani, Norikazu Nakamura
  • Patent number: 10032770
    Abstract: A multi-layered semiconductor device and method of manufacture are provided. In an embodiment a first semiconductor layer, a first insulator layer, a second semiconductor layer, a second insulator layer, and a third semiconductor layer are formed over a substrate. A first transistor comprises the first semiconductor layer, the first insulator layer, and the second semiconductor layer, and a second transistor comprises the second semiconductor layer, the second insulator layer, and the third semiconductor layer.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: July 24, 2018
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University
    Inventors: Chi-Te Liang, Minghwei Hong, Fan-Hung Liu
  • Patent number: 10032880
    Abstract: Implementations of an ohmic contact for a gallium nitride (GaN) device may include: a first layer including aluminum coupled directly with the GaN device; the GaN having a heterostructure with an undoped GaN channel and a semi-insulating aluminum gallium nitride (AlGaN) barrier, all the foregoing operatively coupled with a substrate; a second layer including titanium coupled over the first layer; and a third layer including an anti-diffusion material coupled with the second layer. The passivation layer may be coupled between the AlGaN barrier and the first layer of the ohmic contact. The passivation layer may surround the ohmic contact.
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: July 24, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Aurore Constant, Peter Coppens