Doping On Side Of Heterojunction With Lower Carrier Affinity (e.g., High Electron Mobility Transistor (hemt)) Patents (Class 257/194)
  • Patent number: 12034070
    Abstract: Semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure includes a substrate, a first layer and a second layer. The first layer is disposed on and in contact with the substrate. The first layer includes AlX1Ga(1-X1)N, wherein 0.5?X1<1. The second layer is disposed on and in contact with the first layer. The second layer includes Al, Ga and N.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: July 9, 2024
    Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.
    Inventor: Peng-Yi Wu
  • Patent number: 12002853
    Abstract: The present invention provides a semiconductor device in which the contact resistance of the body electrode is reduced without reducing the channel mobility. The p-type layer is a Mg-doped p-GaN layer deposited on the first re-type layer. The p-type layer has a two-layer structure in which a first p-type layer and a second p-type layer are sequentially deposited. The second p-type layer has a Mg concentration higher than the Mg concentration of the first p-type layer. The recess is formed in a predetermined position on the surface of the second n-type layer, and has a depth passing through the second n-type layer and reaching the second p-type layer. The body electrode is formed on the bottom surface of the recess in contact with the p-type layer exposed thereon.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: June 4, 2024
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Toru Oka, Tsutomu Ina
  • Patent number: 11984496
    Abstract: A semiconductor device and a method for manufacturing the same are provided in this disclosure. The semiconductor device includes a semiconductor heterostructure layer. The semiconductor heterostructure layer includes alternating first semiconductor material layers and second semiconductor material layers. Two-dimensional electron gas (2DEG) may be generated between each first semiconductor material layer and adjacent second semiconductor material layer. A conductive structure, including a plurality of conductive fingers extends from a surface of the semiconductor heterostructure layer into the semiconductor heterostructure layer. The plurality of conductive fingers are arranged in a direction substantially parallel to the surface. The lengths of the plurality of conductive fingers progressively increase in that direction so that an end portion of each conductive finger is respectively positioned in a different first semiconductor material layer and is in contact with the 2DEG.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: May 14, 2024
    Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.
    Inventors: Anbang Zhang, King Yuen Wong, Hao Li, Haoning Zheng, Jian Wang
  • Patent number: 11978629
    Abstract: The present invention relates to a method of manufacturing an AlN-based transistor. An AlN-based high electron mobility transistor (HEMT) element according to the present invention may use an AlN buffer layer, and include an AlGaN composition change layer inserted into a GaN/AlN interface to remove or suppress a degree of generation of a two-dimensional hole gas (2DHG), thereby decreasing an influence of a coulomb drag on a two-dimensional electron gas (2DEG) layer and improving mobility of a two-dimensional electron gas (2DEG).
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: May 7, 2024
    Assignee: KOREA POLYTECHNIC UNIVERSITY INDUSTRY ACADEMIC COOPERATION FOUNDATION
    Inventors: Ok Hyun Nam, Ui Ho Choi
  • Patent number: 11929431
    Abstract: A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A shallow recess, a first deep recess and a second deep recess are disposed in the second III-V compound layer. The first deep recess and the second deep recess are respectively disposed at two sides of the shallow recess. The source electrode fills in the first deep recess and contacts the top surface of the first III-V compound layer. A drain electrode fills in the second deep recess and contacts the top surface of the first III-V compound layer. The shape of the source electrode and the shape of the drain electrode are different from each other. A gate electrode is disposed on the shallow recess.
    Type: Grant
    Filed: April 24, 2023
    Date of Patent: March 12, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Kuang Hsieh, Shih-Hung Tsai
  • Patent number: 11923445
    Abstract: A semiconductor contact structure including a two-dimensional electron gas (2DEG) between a first and a second semiconductor layer and a silicon implant extending into at least a part of the first semiconductor layer and into at least a part of the second semiconductor layer and connected to the 2DEG along an interface between the 2DEG and the silicon implant, wherein the interface has a nonlinear shape. The structure further includes a contact connected to the 2DEG via the silicon implant.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: March 5, 2024
    Assignee: X-FAB DRESDENT GMBH & CO. KG
    Inventor: Victor Sizov
  • Patent number: 11916068
    Abstract: A semiconductor die includes a barrier layer of type III-V semiconductor material, a channel layer of type III-V semiconductor material disposed below the barrier layer, the channel layer forming a heterojunction with the barrier layer such that a two-dimensional charge carrier gas is disposed in the channel layer near the heterojunction, and a capacitor monolithically formed in the semiconductor die, wherein a dielectric medium of the capacitor includes a first section of the barrier layer.
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: February 27, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Hyeongnam Kim, Mohamed Imam
  • Patent number: 11888055
    Abstract: A gallium nitride-on-silicon structure is disclosed in which the two-dimensional electron gas (2DEG) layer is a discontinuous layer that includes at least two 2DEG segments. Each 2DEG segment is separated from another 2DEG segment by a gap. The 2DEG layer can be depleted by a p-doped gallium nitride layer that is disposed over a portion of an aluminum gallium nitride layer. Additionally or alternatively, a trench may be formed in the structure through the 2DEG layer to produce a gap in the 2DEG layer. An electrical component is positioned over at least a portion of a gap.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: January 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jun-De Jin, Chan-Hong Chern
  • Patent number: 11888052
    Abstract: The present application discloses a semiconductor device and a manufacturing method thereof. The manufacturing method comprises manufacturing a semiconductor material layer comprising two laminated semiconductor layers between which an etching transition layer is provided; and etching a part of one of semiconductor layers located in a selected region until etching is stopped after reaching or entering the etching transition layer, subjecting the part of the etching transition layer located in the selected region to thermal decomposition through thermal treatment to be completely removed, and realizing termination of thermal decomposition on another semiconductor layer, so as to precisely form a trench structure in the semiconductor material layer.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: January 30, 2024
    Assignee: SUZHOU INSTITUTE OF NANO-TECH AND NANO-BIONICS (SINANO), CHINESE ACADEMY OF SCIENCES
    Inventors: Qian Sun, Shuai Su, Yu Zhou, Yaozong Zhong, Hongwei Gao, Jianxun Liu, Xiaoning Zhan, Meixin Feng, Hui Yang
  • Patent number: 11862721
    Abstract: A semiconductor device includes a semiconductor substrate, first and second nitride-based semiconductor layers, S/D electrodes, a gate electrode, and a first passivation layer. The first nitride-based semiconductor layer is disposed over the semiconductor substrate. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer, so as to form a 2DEG region. The S/D electrodes is disposed over the second nitride-based semiconductor layer. The gate electrode is disposed between the S/D electrodes. The first passivation layer is disposed over the second nitride-based semiconductor layer. Edges of the first and second nitride-based semiconductor layers and the first passivation layer collectively form a stepped sidewall over the semiconductor substrate.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: January 2, 2024
    Assignee: INNOSCIENCE (SUZHOU) TECHNOLOGY CO., LTD.
    Inventors: Yulong Zhang, Jue Ouyang, Wei Huang, Jheng-Sheng You
  • Patent number: 11837642
    Abstract: A semiconductor device includes a channel layer including a channel; a channel supply layer on the channel layer; a channel separation pattern on the channel supply layer; a gate electrode pattern on the channel separation pattern; and an electric-field relaxation pattern protruding from a first lateral surface of the gate electrode pattern in a first direction parallel with an upper surface of the channel layer. An interface between the channel layer and the channel supply layer is adjacent to channel. A size of the gate electrode pattern in the first direction is different from a size of the channel separation pattern in the first direction. The gate electrode pattern and the electric-field relaxation pattern form a single structure.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: December 5, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soogine Chong, Jongseob Kim, Joonyong Kim, Younghwan Park, Junhyuk Park, Dongchul Shin, Jaejoon Oh, Sunkyu Hwang, Injun Hwang
  • Patent number: 11824108
    Abstract: A semiconductor device includes: a base of a first nitride semiconductor; a buffer layer of a second nitride semiconductor provided on or above the base; a channel layer of a third nitride semiconductor provided on or above the buffer layer and having an opening portion; a barrier layer of a fourth nitride semiconductor provided on or above the channel layer; and an electrically conductive contact layer of a fifth nitride semiconductor provided in the opening portion and in contact with the buffer layer and the channel layer. A ratio of Al in a composition of the second nitride semiconductor is higher than or equal to that of the third nitride semiconductor. A ratio of Al in a composition of the first nitride semiconductor and a ratio of Al in a composition of the fourth nitride semiconductor are higher than that of the second nitride semiconductor.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: November 21, 2023
    Assignee: FUJITSU LIMITED
    Inventor: Atsushi Yamada
  • Patent number: 11776934
    Abstract: A semiconductor apparatus includes a channel layer, a barrier layer, a source contact and a drain contact, a first doped group III-V semiconductor, a group III-V semiconductor, and a second doped group III-V semiconductor. The barrier layer is disposed on the channel layer. The source contact and the drain contact are disposed on the channel layer. The first doped group III-V semiconductor is disposed on the barrier layer. The group III-V semiconductor is disposed on the first doped group III-V semiconductor and between the source contact and the drain contact. The second doped group III-V semiconductor is disposed on the group III-V semiconductor and between the source contact and the drain contact. The group III-V semiconductor has a central region covered by the second doped group III-V semiconductor and a peripheral region free from coverage by the second doped group III-V semiconductor.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: October 3, 2023
    Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.
    Inventor: Han-Chin Chiu
  • Patent number: 11747389
    Abstract: The application relates to a device and method for measuring a high electron mobility transistor. The device provided includes a controller, a protection circuit, a load circuit and a switching circuit electrically connected between the load circuit and the protection circuit. The controller is configured to provide a first control signal having a first value to a semiconductor component at a first time point and provide a second control signal having a second value to the switching circuit at a second time point. The semiconductor component is turned on by the first value of the first control signal, and the switching circuit is turned on by the second value of the second control signal. The second time point is later than the first time point.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: September 5, 2023
    Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.
    Inventors: Yulin Chen, Chunhua Zhou, Sichao Li, Wenjie Lin, Tao Zhang
  • Patent number: 11721743
    Abstract: A method of fabricating a high electron mobility transistor is disclosed. The method comprises using an ion implantation process to amorphize a portion of the barrier layer to a specific depth. The etch rate of this amorphized portion is much faster than that of the rest of the barrier layer. In this way, the depth of the recessed regions into which the source and drain contacts are disposed is more tightly controlled. Further, the etching process may be a wet or dry etch process. The roughness of the recessed region may also be improved using this approach.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: August 8, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Qintao Zhang, Wei Zou, Samphy Hong
  • Patent number: 11677018
    Abstract: A semiconductor device includes a substrate, a circuit element disposed on or above the upper surface of the substrate, an electrode disposed on or above the upper surface of the substrate and connected to the circuit element, and a conductor pillar bump for external connection which is disposed on the substrate and electrically connected to the electrode or the circuit element. The substrate includes a first base and a second base disposed on the first base. The circuit element and the electrode are disposed on the second base. The first base has lower thermal resistance than the second base.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: June 13, 2023
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Masayuki Aoike
  • Patent number: 11646345
    Abstract: A semiconductor structure and a manufacturing method thereof is provided.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: May 9, 2023
    Assignee: ENKRIS SEMICONDUCTOR, INC.
    Inventor: Kai Cheng
  • Patent number: 11605722
    Abstract: An ohmic contact for a multiple channel FET comprises a plurality of slit-shaped recesses in a wafer on which a multiple channel FET resides, with each recess having a depth at least equal to the depth of the lowermost channel layer. Ohmic metals in and on the sidewalls of each recess provide ohmic contact to each of the multiple channel layers. An ohmic metal-filled linear connecting recess contiguous with the outside edge of each recess may be provided, as well as an ohmic metal contact layer on the top surface of the wafer over and in contact with the ohmic metals in each of the recesses. The present ohmic contact typically serves as a source and/or drain contact for the multiple channel FET. Also described is the use of a regrown material to make ohmic contact with multiple channels, with the regrown material preferably having a corrugated structure.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: March 14, 2023
    Assignee: Teledyne Scientific & Imaging, LLC
    Inventors: Keisuke Shinohara, Casey King, Eric Regan
  • Patent number: 11587924
    Abstract: Disclosed herein are integrated circuit structures, packages, and devices that include resistors and/or capacitors which may be provided on the same substrate/die/chip as III-N devices, e.g., III-N transistors. An integrated circuit structure, comprising a base structure comprising a III-N material, the base structure having a conductive region of a doped III-N material. The IC structure further comprises a first contact element, including a first conductive element, a dielectric element, and a second conductive element, wherein the dielectric element is between the first conductive element and the second conductive element, and wherein the first conductive element is between the conductive region and the dielectric element. The IC structure further comprises a second contact element electrically coupled to the first contact element via the conductive region.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: February 21, 2023
    Assignee: Intel Corporation
    Inventors: Nidhi Nidhi, Rahul Ramaswamy, Han Wui Then, Marko Radosavljevic, Johann Christian Rode, Paul B. Fischer, Walid M. Hafez
  • Patent number: 11563088
    Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: January 24, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ming Hsu, Yu-Chi Wang, Yen-Hsing Chen, Tsung-Mu Yang, Yu-Ren Wang
  • Patent number: 11557668
    Abstract: A high electron mobility transistor (HEMT) made of primarily nitride semiconductor materials is disclosed. The HEMT, which is a type of reverse HEMT, includes, on a C-polar surface of a SiC substrate, a barrier layer and a channel layer each having N-polar surfaces in respective top surfaces thereof. The HEMT further includes an intermediate layer highly doped with impurities and a Schottky barrier layer on the channel layer. The Schottky barrier layer and a portion of the intermediate layer are removed in portions beneath non-rectifying electrodes but a gate electrode is provided on the Schottky barrier layer.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: January 17, 2023
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Ken Nakata
  • Patent number: 11552188
    Abstract: A semiconductor structure includes a substrate, a semiconductor epitaxial layer, a semiconductor barrier layer, a first semiconductor device, a doped isolation region, and at least one isolation pillar. The substrate includes a core layer and a composite material layer, the semiconductor epitaxial layer is disposed on the substrate, and the semiconductor barrier layer is disposed on the semiconductor epitaxial layer. The first semiconductor device is disposed on the substrate, where the first semiconductor device includes a first semiconductor cap layer disposed on the semiconductor barrier layer. The doped isolation region is disposed at one side of the first semiconductor device. At least a portion of the isolation pillar is disposed in the doped isolation region, and the isolation pillar surrounds at least a portion of the first semiconductor device and penetrates the composite material layer.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: January 10, 2023
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Yu-Chieh Chou, Tsung-Hsiang Lin
  • Patent number: 11545485
    Abstract: A semiconductor die includes a barrier layer of type III-V semiconductor material, a channel layer of type III-V semiconductor material disposed below the barrier layer, the channel layer forming a heterojunction with the barrier layer such that a two-dimensional charge carrier gas is disposed in the channel layer near the heterojunction, a high-electron mobility transistor disposed in a first lateral region of the semiconductor die, the high-electron mobility transistor comprising source and drain electrodes that each are in ohmic contact with the two-dimensional charge carrier gas and a gate structure that is configured to control a conductive connection between the source and drain electrodes, and a capacitor that is monolithically integrated into the semiconductor die and is disposed in a second lateral region of the semiconductor die, a dielectric medium of the capacitor includes a first section of the barrier layer.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: January 3, 2023
    Assignee: Infineon Technologies Austria AG
    Inventors: Hyeongnam Kim, Mohamed Imam
  • Patent number: 11538922
    Abstract: A manufacturing method of an HEMT includes: forming a heterostructure; forming a first gate layer of intrinsic semiconductor material on the heterostructure; forming a second gate layer, containing dopant impurities of a P type, on the first gate layer; removing first portions of the second gate layer so that second portions, not removed, of the second gate layer form a doped gate region; and carrying out a thermal annealing of the doped gate region so as to cause a diffusion of said dopant impurities of the P type in the first gate layer and in the heterostructure, with a concentration, in the heterostructure, that decreases as the lateral distance from the doped gate region increases.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: December 27, 2022
    Assignee: STMICROELECTRONICS S.r.l.
    Inventor: Ferdinando Iucolano
  • Patent number: 11522078
    Abstract: A High Electron Mobility Transistor (HEMT) having a reduced surface field (RESURF) junction is provided. The HEMT includes a source electrode at a first end and a drain electrode at a second end. A gate electrode is provided between the source electrode and the drain electrode. A reduced surface field (RESURF) junction extends from the first end to the second end. The gate electrode is provided above the RESURF junction. A buried channel layer is formed in the RESURF junction on application of a positive voltage at the gate electrode. The RESURF junction includes an n-type Gallium nitride (GaN) layer and a p-type GaN layer. The n-type GaN layer is provided between the p-type GaN layer and the gate electrode.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: December 6, 2022
    Assignee: INDIAN INSTITUTE OF SCIENCE
    Inventors: Rohith Soman, Ankit Soni, Mayank Shrivastava, Srinivasan Raghavan, Navakant Bhat
  • Patent number: 11515397
    Abstract: Semiconductor structures including electrical isolation and methods of forming a semiconductor structure including electrical isolation. A layer stack is formed on a semiconductor substrate comprised of a single-crystal semiconductor material. The layer stack includes a semiconductor layer comprised of a III-V compound semiconductor material. A polycrystalline layer is formed in the semiconductor substrate. The polycrystalline layer extends laterally beneath the layer stack.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: November 29, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Anthony K. Stamper, Siva P. Adusumilli, Vibhor Jain, Steven Bentley
  • Patent number: 11506707
    Abstract: A semiconductor device includes: a substrate; a circuit element disposed on a first surface side of the substrate; a first transmission line disposed on the first surface side; a first terminal disposed on the first surface side; a first dielectric disposed in a part of the first transmission line; a second terminal disposed on a side of the first dielectric opposite to the first transmission line; a second transmission line disposed on the first surface side and has one end coupled to the circuit element; a third terminal disposed on the first surface side and coupled to the other end of the second transmission line; a second dielectric disposed in a part of the second transmission line; a fourth terminal disposed on a side of the second dielectric opposite to the second transmission line; and a conductor disposed on a second surface side of the substrate.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: November 22, 2022
    Assignee: FUJITSU LIMITED
    Inventors: Ikuo Soga, Yoichi Kawano
  • Patent number: 11502178
    Abstract: A transistor device includes a semiconductor layer, a surface dielectric layer on the semiconductor layer, and at least a portion of a gate on the surface dielectric layer. The surface dielectric layer includes an aperture therein that is laterally spaced apart from the gate. The transistor device includes an interlayer dielectric layer on the surface dielectric layer, and a field plate on the interlayer dielectric layer. The field plate is laterally spaced apart from the gate, and at least a portion of the field plate includes a recessed portion above the aperture in the surface dielectric layer.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: November 15, 2022
    Assignee: Wolfspeed, Inc.
    Inventors: Kyle Bothe, Jia Guo, Terry Alcorn, Fabian Radulescu, Scott Sheppard
  • Patent number: 11502177
    Abstract: A high-electron mobility transistor includes a substrate, a GaN channel layer over the substrate, an AlGaN layer over the GaN channel layer, a gate recess in the AlGaN layer, a source region and a drain region on opposite sides of the gate recess, a GaN source layer and a GaN drain layer grown on the AlGaN layer within the source region and the drain region, respectively, a p-GaN gate layer in and on the gate recess; and a re-grown AlGaN film on the AlGaN layer, on the GaN source layer and the GaN drain layer, and on interior surface of the gate recess.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: November 15, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shin-Chuan Huang, Chih-Tung Yeh, Chun-Ming Chang, Bo-Rong Chen, Wen-Jung Liao, Chun-Liang Hou
  • Patent number: 11489048
    Abstract: A method for forming a high-electron mobility transistor is disclosed. A substrate is provided. A buffer layer is formed over the substrate. A GaN channel layer is formed over the buffer layer. An AlGaN layer is formed over the GaN channel layer. A GaN source layer and a GaN drain layer are formed on the AlGaN layer within a source region and a drain region, respectively. A gate recess is formed in the AlGaN layer between the source region and the drain region. A p-GaN gate layer is then formed in and on the gate recess.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: November 1, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shin-Chuan Huang, Chih-Tung Yeh, Chun-Ming Chang, Bo-Rong Chen, Wen-Jung Liao, Chun-Liang Hou
  • Patent number: 11476288
    Abstract: A method includes epitaxially growing a first III-V compound layer over a semiconductive substrate. A second III-V compound layer is epitaxially grown over the first III-V compound layer. A source/drain contact is formed over the second III-V compound layer. A gate structure is formed over the second III-V compound layer. A pattern is formed shielding the gate structure and the source/drain contact, in which a portion of the second III-V compound layer is free from coverage by the pattern.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: October 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Ying Wu, Li-Hsin Chu, Chung-Chuan Tseng, Chia-Wei Liu
  • Patent number: 11476115
    Abstract: A method for manufacturing a compound semiconductor substrate comprises: a step to form an SiC (silicon carbide) layer on a Si (silicon) substrate, a step to form a LT (Low Temperature)-AlN (aluminum nitride) layer with a thickness of 12 nanometers or more and 100 nanometers or less on the SiC layer at 700 degrees Celsius or more and 1000 degrees Celsius or less, a step to form a HT (High Temperature)-AlN layer on the LT-AlN layer at a temperature higher than the temperature at which the LT-AlN layer was formed, a step to form an Al (aluminum) nitride semiconductor layer on the HT-AlN layer, a step to form a GaN (gallium nitride) layer on the Al nitride semiconductor layer, and a step to form an Al nitride semiconductor layer on the GaN layer.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: October 18, 2022
    Assignee: Air Water Inc.
    Inventors: Mitsuhisa Narukawa, Hiroki Suzuki, Sumito Ouchi
  • Patent number: 11476336
    Abstract: According to one embodiment, a semiconductor device includes first, second and third electrodes, first and second semiconductor layers, and a first compound member. A position of the third electrode is between a position of the second electrode and a position of the first electrode. The first semiconductor layer includes first, second, third, fourth, and fifth partial regions. The fourth partial region is between the third and first partial regions. The fifth partial region is between the second and third partial regions. The second semiconductor layer includes first, second, and third semiconductor regions. The third semiconductor region is between the first partial region and the first electrode. The first compound member includes first compound portions between the third semiconductor region and the first electrode. A portion of the first electrode is between one of the first compound portions and an other one of the first compound portions.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: October 18, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hiroshi Ono, Akira Mukai, Yosuke Kajiwara, Daimotsu Kato, Aya Shindome, Masahiko Kuraguchi
  • Patent number: 11476325
    Abstract: A semiconductor apparatus includes a plurality of semiconductor devices with a single substrate, a plurality of trench regions, each trench region including a trench, wherein the single substrate includes a substrate layer, a first epitaxial layer of a first conductivity type, disposed on the substrate layer, and a second epitaxial layer of a second conductivity type, disposed on the first epitaxial layer, wherein each trench of the plurality of trench regions extends through the second epitaxial layer and into the first epitaxial layer, thereby isolating adjacent semiconductor devices of the plurality of semiconductor devices.
    Type: Grant
    Filed: January 19, 2020
    Date of Patent: October 18, 2022
    Inventor: Jin Wei
  • Patent number: 11448824
    Abstract: A hyperbolic metamaterial assembly comprising alternating one or more first layers and one or more second layers forming a hyperbolic metamaterial, the one or more first layers comprising an intrinsic or non-degenerate extrinsic semiconductor and the one or more second layers comprising a two-dimensional electron or hole gas, wherein one of in-plane or out-of-plane permittivity of the hyperbolic metamaterial assembly is negative and the other is positive.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: September 20, 2022
    Assignee: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventor: Michael A. Mastro
  • Patent number: 11424353
    Abstract: The present application provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a channel layer and a barrier layer that are sequentially superimposed, and a gate region being defined on a surface of the barrier layer; and a p-type semiconductor material layer formed in the gate region, the p-type semiconductor material layer including at least one composition change element, and a component of the composition change element changing along an epitaxial direction.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: August 23, 2022
    Assignee: ENKRIS SEMICONDUCTOR, INC.
    Inventor: Kai Cheng
  • Patent number: 11424352
    Abstract: The present application provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a channel layer, a barrier layer located on the channel layer, a composition change layer located on the barrier layer, and a p-type semiconductor material layer located in the gate region of the composition change layer, wherein a gate region is defined on a surface of the composition change layer, and a material of the composition change layer includes at least one composition change element.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: August 23, 2022
    Assignee: ENKRIS SEMICONDUCTOR, INC.
    Inventor: Kai Cheng
  • Patent number: 11404541
    Abstract: A HEMT comprising: a substrate; a channel layer coupled to the substrate; a source electrode coupled to the channel layer; a drain electrode coupled to the channel layer; and a gate electrode coupled to the channel layer between the source electrode and the drain electrode; wherein the channel layer comprises: at least a first GaN layer; and a first graded AlGaN layer on the first GaN layer, the Al proportion of the first graded AlGaN layer increasing with the distance from the first GaN layer.
    Type: Grant
    Filed: July 11, 2020
    Date of Patent: August 2, 2022
    Assignee: HRL LABORATORIES, LLC
    Inventors: Jeong-sun Moon, Fevzi Arkun
  • Patent number: 11398546
    Abstract: A semiconductor device is provided. The semiconductor device includes a channel layer disposed over a substrate, a barrier layer disposed over the channel layer, a compound semiconductor layer disposed over the barrier layer, a gate electrode disposed over the compound semiconductor layer, and a source electrode and a drain electrode disposed on opposite sides of the gate electrode. The source electrode and the drain electrode penetrate through at least a portion of the barrier layer. The semiconductor device also includes a source field plate connected to the source electrode through a source contact. The semiconductor device further includes a first electric field redistribution pattern disposed on the barrier layer and directly under the edge of the source field plate.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: July 26, 2022
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chun-Yi Wu, Chih-Yen Chen, Chang-Xiang Hung, Chia-Ching Huang
  • Patent number: 11393905
    Abstract: A nitride semiconductor device includes a first impurity layer made of an Al1-XGaXN (0<X?1) based material and containing a first impurity with which a depth of an acceptor level from a valence band (ET-EV) is made not less than 0.3 eV but less than 0.6 eV, an electron transit layer formed on the first impurity layer, an electron supply layer formed on the electron transit layer, agate electrode formed on the electron transit layer, and a source electrode and a drain electrode formed such that the source electrode and the drain electrode sandwich the gate electrode and electrically connected to the electron supply layer.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: July 19, 2022
    Assignee: ROHM CO., LTD.
    Inventors: Norikazu Ito, Taketoshi Tanaka, Ken Nakahara
  • Patent number: 11387328
    Abstract: Group-III nitride (III-N) tunnel devices with a device structure including multiple quantum wells. A bias voltage applied across first device terminals may align the band structure to permit carrier tunneling between a first carrier gas residing in a first of the wells to a second carrier gas residing in a second of the wells. A III-N tunnel device may be operable as a diode, or further include a gate electrode. The III-N tunnel device may display a non-linear current-voltage response with negative differential resistance, and be employed as a frequency mixer operable in the GHz and THz bands. In some examples, a GHz-THz input RF signal and local oscillator signal are coupled into a gate electrode of a III-N tunnel device biased within a non-linear regime to generate an output RF signal indicative of a frequency difference between the RF signal and a local oscillator signal.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: July 12, 2022
    Assignee: Intel Corporation
    Inventors: Rahul Ramaswamy, Walid M. Hafez, Marko Radosavljevic, Sansaptak Dasgupta, Han Wui Then, Nidhi Nidhi
  • Patent number: 11387236
    Abstract: A semiconductor device includes first and second active patterns on first and second active regions of a substrate, respectively, a pair of first source/drain patterns and a first channel pattern therebetween which are in an upper portion of the first active pattern, a pair of second source/drain patterns and a second channel pattern therebetween which are in an upper portion of the second active pattern, and first and second gate electrodes intersecting the first and second channel patterns, respectively. Each of the first and second gate electrodes includes a first metal pattern adjacent to a corresponding one of the first and second channel patterns. The first and second channel patterns include SiGe. A Ge concentration of the second channel pattern is higher than a Ge concentration of the first channel pattern. A thickness of the first metal pattern of the second gate electrode is greater than a thickness of the first metal pattern of the first gate electrode.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: July 12, 2022
    Inventors: Jongho Park, Jaeyeol Song, Wandon Kim, Byounghoon Lee, Musarrat Hasan
  • Patent number: 11367706
    Abstract: A semiconductor apparatus and a fabrication method thereof are disclosed. The semiconductor apparatus includes a substrate, a channel layer, a barrier layer, and a gate structure, and includes: a first doped group III-V semiconductor, a group III-V semiconductor, and a conductor. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The first doped group III-V semiconductor is disposed on the barrier layer. The group III-V semiconductor is disposed on the doped group III-V semiconductor. The conductor is disposed on the group III-V semiconductor, where a width of the first doped group III-V semiconductor is greater than a width of the conductor.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: June 21, 2022
    Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.
    Inventor: Han-Chin Chiu
  • Patent number: 11367779
    Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a first hard mask on the first barrier layer; removing the first hard mask and the first barrier layer to form a recess; forming a second barrier layer in the recess; and forming a p-type semiconductor layer on the second barrier layer.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: June 21, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Ming Chang, Che-Hung Huang, Wen-Jung Liao, Chun-Liang Hou
  • Patent number: 11362011
    Abstract: A power amplification device includes: a first semiconductor chip including a first main surface and a second main surface; a first field-effect transistor, a first drain finger part, a plurality of first gate finger parts, and a source finger part; a sub-mount substrate including a third main surface and a fourth main surface; and a first filled via provided penetrating from the third main surface to the fourth main surface. In plan view, the first filled via has a rectangular shape. A long side direction of the first filled via is parallel to a long side direction of the plurality of first gate finger parts. In plan view, the first filled via is positioned to overlap part of one first gate finger part included in the plurality of first gate finger parts.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: June 14, 2022
    Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
    Inventors: Kazuhiko Ohhashi, Masatoshi Kamitani, Kouki Yamamoto
  • Patent number: 11355625
    Abstract: A device includes a first transistor and a second transistor. The first transistor includes a first gate terminal coupled to the first source terminal, a first source terminal, and a first drain terminal. The second transistor includes a second gate terminal coupled to the first drain terminal, a second source terminal, and a second drain terminal.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: June 7, 2022
    Assignees: DELTA ELECTRONICS, INC., NATIONAL CENTRAL UNIVERSITY
    Inventors: Chun-Chieh Yang, Yue-Ming Hsin, Yi-Nan Zhong, Yu-Chen Lai
  • Patent number: 11355597
    Abstract: A transistor device includes a field plate that extends from a source runner layer and/or a source contact layer. The field plate can be coplanar with and/or below a gate runner layer. The gate runner layer is routed away from a region directly above the gate metal layer by a gate bridge, such that the field plate can extend directly above the gate metal layer without being interfered by the gate runner layer. Coplanar with the source runner layer or the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. By vertically overlapping the metal gate layer and the field plate, the disclosed HEMT device may achieve significant size efficiency without additional routings.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: June 7, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hiroyuki Tomomatsu, Sameer Pendharkar, Hiroshi Yamasaki
  • Patent number: 11335798
    Abstract: An Enhancement Mode (e-mode) Metal Insulator Semiconductor (MIS) High Electron Mobility Transistor (HEMT), or EMISHEMT, with GaN channel regrowth under a gate area, is described. The EMISHEMT with GaN channel regrowth under a gate area provides a normally-off device with a suitably high and stable threshold voltage, while providing a low gate leakage current. A channel layer provides a 2DEG and associated low on-resistance, while a channel-material layer extends through an etched recess and into the channel layer, and disrupts the 2DEG locally to enable the normally-off operation.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: May 17, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Peter Moens, Piet Vanmeerbeek, Abhishek Banerjee, Marnix Tack
  • Patent number: 11335801
    Abstract: A device including a III-N material is described. In an example, a device includes a first layer including a first group III-nitride (III-N) material and a polarization charge inducing layer, including a second III-N material, above the first layer. The device further includes a gate electrode above the polarization charge inducing layer and a source structure and a drain structure on opposite sides of the gate electrode. The source structure and the drain structure both include a first portion adjacent to the first layer and a second portion above the first portion, the first portion includes a third III-N material with an impurity dopant, and the second portion includes a fourth III-N material, where the fourth III-N material includes the impurity dopant and further includes indium, where the indium content increases with distance from the first portion.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: May 17, 2022
    Assignee: Intel Corporation
    Inventors: Marko Radosavljevic, Han Wui Then, Sansaptak Dasgupta
  • Patent number: 11335799
    Abstract: The present application discloses a group-III nitride semiconductor device, which comprises a substrate, a buffer layer, a semiconductor stack structure, and a passivation film. The buffer layer is disposed on the substrate. The semiconductor stack structure is disposed on the buffer layer and comprises a gate, a source, and a drain. In addition, a gate insulating layer is disposed between the gate and the semiconductor stack structure for forming a HEMT. The passivation film covers the HEMT and includes a plurality of openings corresponding to the gate, the source, and the drain, respectively. The material of the passivation film is silicon oxynitride.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: May 17, 2022
    Inventor: Wen-Jang Jiang