Doping On Side Of Heterojunction With Lower Carrier Affinity (e.g., High Electron Mobility Transistor (hemt)) Patents (Class 257/194)
  • Patent number: 11177216
    Abstract: A semiconductor structure having: a Group III-N semiconductor; a first dielectric disposed in direct contact with the Group III-N semiconductor; a second dielectric disposed over the first dielectric, the first dielectric having a higher dielectric constant than the second dielectric; a third dielectric layer disposed on the first dielectric layer, such third dielectric layer having sidewall abutting sides of the second dielectric layer; and a gate electrode contact structure. The gate electrode structure comprises: stem portion passing through, and in contact with, the first dielectric and the second dielectric having bottom in contact with the Group III-V semiconductor; and, an upper, horizontal portion extending beyond the stem portion and abutting sides of the third dielectric layer. An electrical interconnect structure has side portions passing through and in contact with the third dielectric layer and has a bottom portion in contact with the horizontal portion of the gate electrode contact structure.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: November 16, 2021
    Assignee: Raytheon Company
    Inventors: Jeffrey R. LaRoche, Eduardo M. Chumbes, Kelly P. Ip, Thomas E. Kazior
  • Patent number: 11152498
    Abstract: The present disclosure provides a semiconductor device and a method of fabricating the same. The device comprises a substrate; a first semiconductor layer formed on the substrate; a second semiconductor layer formed on the first semiconductor layer; the first semiconductor layer having a smaller forbidden band width than the second semiconductor layer; and a first electrode, a second electrode, and a third electrode formed on the second semiconductor layer; the first semiconductor layer corresponding to the third electrode has a strongly P-type doped first region, and the first semiconductor layer corresponding to the second electrode has a weakly P-type doped second region.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: October 19, 2021
    Assignee: GUANGDONG ZHINENG TECHNOLOGY CO., LTD.
    Inventor: Zilan Li
  • Patent number: 11152480
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first conductive member, a first semiconductor layer, a second semiconductor layer, and an insulating member. The third electrode is between the first electrode and the second electrode. The first conductive member is electrically connected to the first electrode. The first conductive member is between the third electrode and the second electrode. The first semiconductor layer includes Alx1Ga1?x1N and includes first, second, third, fourth, and fifth partial regions. The second semiconductor layer includes Alx2Ga1?x2N and includes a first semiconductor region and a second semiconductor region. The insulating member includes first, second, third, fourth, and fifth insulating regions. The first insulating region is between the third partial region and the third electrode. The second insulating region is between the fifth partial region and the first conductive member.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: October 19, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Aya Shindome, Masahiko Kuraguchi
  • Patent number: 11139393
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first to third nitride regions, and first and second insulating films. The first nitride region includes Alx1Ga1-x1N, and includes first and second partial regions, a third partial region between the first and second partial regions, a fourth partial region between the first and third partial regions, and a fifth partial region between the third and second partial regions. The first nitride region includes first to fifth partial regions. The second nitride region includes Alx2Ga1-x2N, and sixth and seventh partial regions. At least a portion of the third electrode is between the sixth and seventh partial regions. The first insulating film includes silicon and oxygen and includes first and second insulating regions. The third nitride region includes Alx3Ga1-x3N, and first to seventh portions. The second insulating film includes silicon and oxygen and includes third to seventh insulating regions.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: October 5, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Daimotsu Kato, Yosuke Kajiwara, Akira Mukai, Aya Shindome, Hiroshi Ono, Masahiko Kuraguchi
  • Patent number: 11127848
    Abstract: A semiconductor structure includes a substrate structure having a plurality of first trenches extending in a first direction, a nucleation layer disposed on the substrate structure, a compound semiconductor layer disposed on the nucleation layer, a gate disposed on the compound semiconductor layer, and a source and a drain disposed on the compound semiconductor layer and at opposite sides of the gate.
    Type: Grant
    Filed: November 29, 2019
    Date of Patent: September 21, 2021
    Assignee: Vanguard International Semiconductor Corporation
    Inventor: Chih-Yen Chen
  • Patent number: 11114539
    Abstract: A heterostructure semiconductor device includes a first active layer and a second active layer disposed on the first active layer. A two-dimensional electron gas layer is formed between the first and second active layers. A sandwich gate dielectric layer structure is disposed on the second active layer. A passivation layer is disposed over the sandwich gate dielectric layer structure. A gate extends through the passivation layer to the sandwich gate dielectric layer structure. First and second ohmic contacts electrically connected to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with the gate being disposed between the first and second ohmic contacts.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: September 7, 2021
    Assignee: POWER INTEGRATIONS, INC.
    Inventor: Jamal Ramdani
  • Patent number: 11114396
    Abstract: In a transistor formed on a semiconductor die mounted on a substrate, where the transistor output is connected to a circuit on the substrate, a bond pad electrically connected to a transistor drain finger manifold extends less than the full length of the manifold. By controlling the length of the bond pad, the parasitic capacitance it contributes may be controlled. In applications such as a Doherty amplifier, this parasitic capacitance forms part of the quarter-wave transmission line of an impedance inverter, and hence directly impacts amplifier performance. In particular, by reducing the parasitic capacitance contribution from transistor output bond pads, the bandwidth of a Doherty amplifier circuit may be improved. At GHz frequencies and with state of the art transistor device feature sizes, concerns about phase mismatch between drain finger outputs are largely moot.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: September 7, 2021
    Assignee: Cree, Inc.
    Inventors: Lei Zhao, Mario Bokatius
  • Patent number: 11107924
    Abstract: The disclosure illustrates systems and methods for removing at least some excess gate material of a FinFET transistor. A FinFET transistor with the excess gate material removed may include a gate with a T-shaped cross-section. The narrower portion of the cross-section may be processed using backside wafer processing. The width of the narrower portion may be defined by a spacer.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: August 31, 2021
    Assignee: Intel Corporation
    Inventors: Aaron D. Lilak, Rishabh Mehandru, Patrick Morrow
  • Patent number: 11101363
    Abstract: A method forms an HEMT transistor of the normally off type, including: a semiconductor heterostructure, which comprises at least one first layer and one second layer, the second layer being set on top of the first layer; a trench, which extends through the second layer and a portion of the first layer; a gate region of conductive material, which extends in the trench; and a dielectric region, which extends in the trench, coats the gate region, and contacts the semiconductor heterostructure. A part of the trench is delimited laterally by a lateral structure that forms at least one first step. The semiconductor heterostructure forms a first edge and a second edge of the first step, the first edge being formed by the first layer.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: August 24, 2021
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Ferdinando Iucolano, Alfonso Patti, Alessandro Chini
  • Patent number: 11101355
    Abstract: A semiconductor device according to an embodiment includes a nitride semiconductor layer, an insulating layer provided on the nitride semiconductor layer, a first region provided in the nitride semiconductor layer, and a second region which is provided between the first region in the nitride semiconductor layer and the insulating layer, has a higher electric resistivity than the first region, and includes carbon (C).
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: August 24, 2021
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tatsuo Shimizu
  • Patent number: 11088044
    Abstract: A compound semiconductor device includes a compound semiconductor stack structure, a protective film provided on the compound semiconductor stack structure and containing titanium oxide, and a polycrystalline diamond film provided on the protective film.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: August 10, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Shirou Ozaki, Toshihiro Ohki
  • Patent number: 11081579
    Abstract: An HEMT includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A source electrode and a drain electrode are disposed on the second III-V compound layer. The gate electrode is disposed on the second III-V compound layer between the source electrode and the drain electrode. An insulating layer is disposed between the drain electrode and the gate electrode and covers the second III-V compound layer. At least one electrode is disposed on the insulating layer and contacts the insulating layer, wherein a voltage is applied to the electrode.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: August 3, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Ming Chang, Chih-Tung Yeh
  • Patent number: 11081485
    Abstract: A monolithic integrated circuit device formed in a multi-layer structure comprises a low-pinch-off-voltage pHEMT and a high-pinch-off-voltage pHEMT. A Schottky layer in the multi-layer structure contains at least three stacked regions of semiconductor material, wherein each of the two adjacent stacked regions differs in material and provides a stacked region contact interface therebetween. The gate-sinking pHEMTs each includes a gate contact, a first gate metal layer, a gate-sinking region, and a gate-sinking bottom boundary. The first gate metal layers are in contact with the topmost stacked region of the Schottky layer. The gate-sinking regions are beneath the first gate metal layers. The gate-sinking bottom boundary of the high-pinch-off-voltage pHEMT, which is closer to the semiconductor substrate than the gate-sinking bottom boundary of the low-pinch-off-voltage pHEMT, locates within 10 ? above or below one of the stacked region contact interfaces of the Schottky layer.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: August 3, 2021
    Assignee: Win Semiconductors Corp.
    Inventors: Chia-Ming Chang, Jung-Tao Chung, Yan-Cheng Lin, Lung-Yi Tseng
  • Patent number: 11056584
    Abstract: In a semiconductor device having an active region and an inactive region, the active region includes a channel forming layer with a heterojunction structure having first and second semiconductor layers, a gate structure portion having a MOS gate electrode, a source electrode and a drain electrode disposed on the second semiconductor layer with the gate structure portion interposed therebetween, a third semiconductor layer disposed at a position away from the drain electrode between the gate structure portion and the drain electrode and not doped with an impurity, a p-type fourth semiconductor layer disposed on the third semiconductor layer, and a junction gate electrode brought into contact with the fourth semiconductor layer. The junction gate electrode is electrically connected to the source electrode to have a same potential as a potential of the source electrode, and is disposed only in the active region.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: July 6, 2021
    Assignee: DENSO CORPORATION
    Inventors: Kensuke Hata, Shinichi Hoshi, Hideo Matsuki, Youngshin Eum, Shigeki Takahashi
  • Patent number: 11049960
    Abstract: In some examples, a gallium nitride (GaN)-based transistor, comprises a substrate; a GaN layer supported by the substrate; an aluminum nitride gallium (AlGaN) layer supported by the GaN layer; a p-doped GaN structure supported by the AlGaN layer; and multiple p-doped GaN blocks supported by the AlGaN layer, each of the multiple p-doped GaN blocks physically separated from the remaining multiple p-doped GaN blocks, wherein first and second contours of a two-dimensional electron gas (2DEG) of the GaN-based transistor are at an interface of the AlGaN and GaN layers.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: June 29, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Chang Soo Suh, Sameer Prakash Pendharkar, Naveen Tipirneni, Jungwoo Joh
  • Patent number: 11038047
    Abstract: A normally-off HEMT transistor includes a heterostructure including a channel layer and a barrier layer on the channel layer; a 2DEG layer in the heterostructure; an insulation layer in contact with a first region of the barrier layer; and a gate electrode through the whole thickness of the insulation layer, terminating in contact with a second region of the barrier layer. The barrier layer and the insulation layer have a mismatch of the lattice constant (“lattice mismatch”), which generates a mechanical stress solely in the first region of the barrier layer, giving rise to a first concentration of electrons in a first portion of the two-dimensional conduction channel which is under the first region of the barrier layer which is greater than a second concentration of electrons in a second portion of the two-dimensional conduction channel which is under the second region of the barrier layer.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: June 15, 2021
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Ferdinando Iucolano, Giuseppe Greco, Fabrizio Roccaforte
  • Patent number: 11031402
    Abstract: The invention relates to a capacitorless DRAM cell, the cell comprising a heterostructure, a gate structure adjoining the heterostructure in a first direction, a drain structure adjoining the heterostructure in a second direction perpendicular to the first direction, and a source structure adjoining the heterostructure in the direction opposite the second direction, the heterostructure comprising one or more semiconducting channel layers and one or more electrically insulating barrier layers, the channel layers and the barrier layers being alternatingly stacked in the first direction.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: June 8, 2021
    Assignee: International Business Machines Corporation
    Inventors: Cezar Bogdan Zota, Clarissa Convertino, Lukas Czornomaz, Siegfried Friedrich Karg
  • Patent number: 11024730
    Abstract: A nitride semiconductor device includes a first nitride semiconductor layer; a back-barrier layer that contains InGaN provided on the first nitride semiconductor layer; and a second nitride semiconductor layer that is provided on the back-barrier layer, wherein, in the back-barrier layer, in a thickness direction, an In composition increases at a first interface with the first nitride semiconductor layer, and the In composition is continuously reduced toward a second interface with the second nitride semiconductor layer.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: June 1, 2021
    Assignee: FUJITSU LIMITED
    Inventor: Kozo Makiyama
  • Patent number: 11011519
    Abstract: A semiconductor device and a method for fabricating the same, the device including an active pattern extending in a first direction on a substrate; a field insulating film surrounding a part of the active pattern; a first gate structure extending in a second direction on the active pattern and the field insulating film, a second gate structure spaced apart from the first gate structure and extending in the second direction on the active pattern and the field insulating film; and a first device isolation film between the first and second gate structure, wherein a side wall of the first gate structure facing the first device isolation film includes an inclined surface having an acute angle with respect to an upper surface of the active pattern, and a lowermost surface of the first device isolation film is lower than or substantially coplanar with an uppermost surface of the field insulating film.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: May 18, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eui Chul Hwang, Ju Youn Kim, Hyung Joo Na, Bong Seok Suh, Sang Min Yoo, Joo Ho Jung, Sung Moon Lee
  • Patent number: 10998434
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first III-V compound layer disposed on the substrate, a second III-V compound layer disposed on the first III-V compound layer, a p-type doped III-V compound layer disposed on the second III-V compound layer, a gate disposed over the p-type doped III-V compound layer, a source and a drain disposed on opposite sides of the gate, and a dielectric layer disposed between the p-type doped III-V compound layer and the gate. A method for forming the above semiconductor device is also provided.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: May 4, 2021
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Hsin-Chih Lin, Shin-Cheng Lin, Yung-Hao Lin
  • Patent number: 10998433
    Abstract: A semiconductor device of an embodiment includes a first nitride semiconductor layer; a second nitride semiconductor layer placed on the first nitride semiconductor layer; a first electrode placed on the second nitride semiconductor layer; a second electrode placed on the first nitride semiconductor layer; a gate electrode placed between the first electrode and the second electrode; a first field plate electrode placed on the second nitride semiconductor layer, the first field plate electrode having the same height as the gate electrode; and a second field plate electrode provided on an upper side of the first field plate electrode, the second field plate electrode being placed on a side of the second electrode compared to the first field plate electrode.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: May 4, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Hung Hung, Yasuhiro Isobe, Akira Yoshioka, Toru Sugiyama, Masaaki Iwai, Naonori Hosokawa, Masaaki Onomura
  • Patent number: 10991817
    Abstract: Techniques are disclosed for forming group III-N transistors including a source to channel heterostructure design. As will be apparent in light of this disclosure, the source to channel heterostructure design may include inserting a relatively high bandgap material layer (e.g., relative to the bandgap of the channel material) between the source and channel of the III-N transistor. In some such embodiments, the relatively high bandgap material layer may be a portion of the polarization charge inducing layer formed over the III-N layer including the channel (e.g., to form a heterojunction/2DEG configuration) that is purposefully left in the source region when forming the source/drain trenches. The source to channel heterostructure design can be used to enhance the high frequency performance of the III-N transistor. Other embodiments may be described and/or disclosed.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: April 27, 2021
    Assignee: Intel Corporation
    Inventors: Sansaptak Dasgupta, Han Wui Then, Marko Radosavljevic
  • Patent number: 10992269
    Abstract: A compound semiconductor device includes a first compound semiconductor layer containing a p-type impurity, a second compound semiconductor layer disposed over the first compound semiconductor layer and containing InGaN, an electron transit layer disposed over the second compound semiconductor layer, and an electron supply layer disposed over the electron transit layer.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: April 27, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Tetsuro Ishiguro, Atsushi Yamada, Junji Kotani, Norikazu Nakamura, Kozo Makiyama
  • Patent number: 10971615
    Abstract: Certain aspects of the present disclosure provide a high electron mobility transistor (HEMT). The HEMT generally includes a gallium nitride (GaN) layer and an aluminum gallium nitride (AlGaN) layer disposed above the GaN layer. The HEMT also includes a source electrode, a gate electrode, and a drain electrode disposed above the AlGaN layer. The HEMT further includes n-doped protuberance(s) disposed above the AlGaN layer and disposed between at least one of: the gate electrode and the drain electrode; or the source electrode and the gate electrode. Each of the n-doped protuberances is separated from the gate electrode, the drain electrode, and the source electrode.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: April 6, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Gengming Tao, Bin Yang, Xia Li
  • Patent number: 10971614
    Abstract: A high electron mobility transistor (HEMT) made of primarily nitride semiconductor materials is disclosed. The HEMT, which is a type of reverse HEMT, includes, on a C-polar surface of a SiC substrate, a barrier layer and a channel layer each having N-polar surfaces in respective top surfaces thereof. The HEMT further includes an intermediate layer highly doped with impurities and a Schottky barrier layer on the channel layer. The Schottky barrier layer and a portion of the intermediate layer are removed in portions beneath non-rectifying electrodes but a gate electrode is provided on the Schottky barrier layer.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: April 6, 2021
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Ken Nakata
  • Patent number: 10957252
    Abstract: A pixel circuit includes a first transistor, a second transistor connected to a first source/drain of the first transistor, a circuit element connected to a gate of the first transistor and ground and configured to receive a select input and maintain the select input less than or equal to a potential of the ground, and a resistive element connected to an organic light emitting diode (OLED) and a first source/drain of the second transistor.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: March 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bahman Hekmatshoartabari, Ghavam G. Shahidi
  • Patent number: 10937878
    Abstract: A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: March 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Han-Chin Chiu, Chi-Ming Chen, Chung-Yi Yu, Chen-Hao Chiang
  • Patent number: 10916445
    Abstract: A method for preparing a p-type semiconductor layer, an enhanced device and a method for manufacturing the same disclosed relate to the technical field of microelectronics. The method for preparing a p-type semiconductor layer includes: preparing a p-type semiconductor layer; preparing a protective layer on the p-type semiconductor layer, in which the protective layer is made of AlN or AlGaN; and annealing the p-type semiconductor layer under protection of the protective layer. In this way, the protective layer can protect the p-type semiconductor layer from volatilization and to form high-quality surface morphology in the subsequent high-temperature annealing treatment of the p-type semiconductor layer.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: February 9, 2021
    Assignee: ENKRIS SEMICONDUCTOR, INC.
    Inventor: Kai Cheng
  • Patent number: 10916670
    Abstract: The present disclosure relates to a semiconductor device and a photoelectronic device, both including a transition-metal dichalcogenide thin-film, and to a method for producing a transition-metal dichalcogenide thin-film. The transition-metal dichalcogenide thin-film includes: a first region including a stack of N+M transition-metal dichalcogenide molecular layers; and a second region including a stack of N transition-metal dichalcogenide molecular layers, wherein the second region is horizontally adjacent to the first region, wherein the N transition-metal dichalcogenide molecular layers of the second region respectively horizontally extend from the N transition-metal dichalcogenide molecular layers of the first region.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: February 9, 2021
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Geun Young Yeom, Ki Seok Kim, Ki Hyun Kim, Jin Woo Park, Doo San Kim, You Jin Ji, Ji Young Byun, JiEun Kang
  • Patent number: 10903320
    Abstract: A transistor device includes a field plate that extends from a source runner layer and/or a source contact layer. The field plate can be coplanar with and/or below a gate runner layer. The gate runner layer is routed away from a region directly above the gate metal layer by a gate bridge, such that the field plate can extend directly above the gate metal layer without being interfered by the gate runner layer. Coplanar with the source runner layer or the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. By vertically overlapping the metal gate layer and the field plate, the disclosed HEMT device may achieve significant size efficiency without additional routings.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: January 26, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hiroyuki Tomomatsu, Sameer Pendharkar, Hiroshi Yamasaki
  • Patent number: 10892357
    Abstract: An HEMT device, comprising: a semiconductor body including a heterojunction structure; a dielectric layer on the semiconductor body; a gate electrode; a drain electrode, facing a first side of the gate electrode; and a source electrode, facing a second side opposite to the first side of the gate electrode; an auxiliary channel layer, which extends over the heterojunction structure between the gate electrode and the drain electrode, in electrical contact with the drain electrode and at a distance from the gate electrode, and forming an additional conductive path for charge carriers that flow between the source electrode and the drain electrode.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: January 12, 2021
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Ferdinando Iucolano, Alessandro Chini
  • Patent number: 10886392
    Abstract: A semiconductor structure for improving the thermal stability and Schottky behavior by engineering the stress in a III-nitride semiconductor, comprising a III-nitride semiconductor and a gate metal layer. The III-nitride semiconductor has a top surface on which a conductive area and a non-conductive area are defined. The gate metal layer is formed directly on the top surface of the III-nitride semiconductor and comprises a gate connection line and at least one gate contact extending from the gate connection line in a second direction perpendicular to the length of the gate connection line. The at least one gate contact forms a Schottky contact with the III-nitride semiconductor on the conductive area, and the gate connection line is in direct contact with the III-nitride semiconductor on the non-conductive area. The non-conductive area of the III-nitride semiconductor is at least partially covered by the gate connection line.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: January 5, 2021
    Assignee: Win Semiconductors Corp.
    Inventors: Jhih-Han Du, Yi Wei Lien, Che-Kai Lin, Wei-Chou Wang
  • Patent number: 10868134
    Abstract: A channel layer is grown over a substrate, and an active layer is grown over the channel layer, wherein the active layer has a band gap discontinuity with the channel layer. A dielectric layer is deposited over the active layer, and the dielectric layer is patterned to expose a portion of the active layer. A metal diffusion barrier is formed over the exposed portion of the active layer, and a gate is deposited over the metal diffusion barrier.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: King-Yuen Wong, Po-Chih Chen, Chen-Ju Yu, Fu-Chih Yang, Jiun-Lei Jerry Yu, Fu-Wei Yao, Ru-Yi Su, Yu-Syuan Lin
  • Patent number: 10861947
    Abstract: Methods for processing a semiconductor transistor are provided, where the semiconductor transistor includes a substrate, an epitaxial layer, and transistor components that are formed on the epitaxial layer. The method includes: removing a portion of the substrate that is disposed below a portion of the transistor components, to thereby expose a portion of a bottom surface of the epitaxial layer; forming an electrically insulating layer on the exposed portion of the bottom surface of the epitaxial layer; forming a via that extends from a bottom surface of the insulating layer to a bottom surface of one of the transistor components; depositing at least one metal layer on the bottom surface of the insulating layer, on a side wall of the via and on the bottom surface of one of the transistor components; and applying a solder paste to a bottom surface of the at least one metal layer.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: December 8, 2020
    Assignee: RFHIC CORPORATION
    Inventor: Won Sang Lee
  • Patent number: 10861970
    Abstract: A semiconductor epitaxial structure with reduced defects, including a substrate with a recess formed thereon, an island insulator on a bottom surface of the recess, spacers on sidewalls of the recess, a buffer layer in the recess and covering the island insulator, a channel layer in the recess and on the buffer layer, and a barrier layer in the recess and on the channel layer, wherein two-dimensional electron gas (2DEG) or two-dimensional hole gas (2DHG) is formed in the channel layer.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: December 8, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Ming Chang, Chun-Liang Hou, Wen-Jung Liao, Ming-Chang Lu
  • Patent number: 10861963
    Abstract: A gallium nitride based monolithic microwave integrated circuit includes a substrate, a channel layer on the substrate and a barrier layer on the channel layer. A recess is provided in a top surface of the barrier layer. First gate, source and drain electrodes are provided on the barrier layer opposite the channel layer, with a bottom surface of the first gate electrode in direct contact with the barrier layer. Second gate, source and drain electrodes are also provided on the barrier layer opposite the channel layer. A gate insulating layer is provided in the recess in the barrier layer, and the second gate electrode is on the gate insulating layer opposite the barrier layer and extending into the recess. The first gate, source and drain electrodes comprise the electrodes of a depletion mode transistor, and the second gate, source and drain electrodes comprise the electrodes of an enhancement mode transistor.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: December 8, 2020
    Assignee: Cree, Inc.
    Inventors: Saptharishi Sriram, Jennifer Qingzhu Gao, Jeremy Fisher, Scott Sheppard
  • Patent number: 10861943
    Abstract: In some examples, a transistor comprises a gallium nitride (GaN) layer; a first GaN-based alloy layer having a top side and disposed on the GaN layer; a second GaN-based alloy layer disposed on the first GaN-based alloy layer, wherein the second GaN-based alloy layer covers a first portion of the top side; and a source contact structure, a drain contact structure, and a gate contact structure, wherein the source, drain, and gate contact structures are supported by the first GaN-based alloy layer.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: December 8, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Dong Seup Lee, Jungwoo Joh, Pinghai Hao, Sameer Pendharkar
  • Patent number: 10854446
    Abstract: Methods and structures includes providing a substrate, forming a prelayer over a substrate, forming a barrier layer over the prelayer, and forming a channel layer over the barrier layer. Forming the prelayer may include growing the prelayer at a graded temperature. Forming the barrier layer is such that the barrier layer may include GaAs or InGaAs. Forming the channel layer is such that the channel layer may include InAs or an Sb-based heterostructure. Thereby structures are formed.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: December 1, 2020
    Assignees: Taiwan Semiconductor Manufacturing Company Limited, National Chiao-Tung University
    Inventors: Hung-Wei Yu, Yi Chang, Tsun-Ming Wang
  • Patent number: 10854741
    Abstract: An enhanced HFET, comprising a HFET device body.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: December 1, 2020
    Assignee: THE 13TH RESEARCH INSTITUTE OF CHINA ELECTRONICS
    Inventors: Yuangang Wang, Zhihong Feng, Yuanjie Lv, Xin Tan, Xubo Song, Xingye Zhou, Yulong Fang, Guodong Gu, Hongyu Guo, Shujun Cai
  • Patent number: 10854734
    Abstract: A manufacturing method of a semiconductor device includes the following steps. A substrate is provided. The substrate has a first side and a second side opposite to the first side. A first III-V compound layer is formed at the first side of the substrate. A drain trench and a contact trench are formed at the second side of the substrate. The drain trench extends from the second side of the substrate toward the first side of the substrate and penetrates the substrate. The contact trench extends from the second side of the substrate toward the first side of the substrate and penetrates the substrate. The drain trench and the contact trench are formed concurrently by the same process. A drain electrode is formed in the drain trench. A back contact structure is formed in the contact trench.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: December 1, 2020
    Assignee: GLC SEMICONDUCTOR GROUP (CQ) CO., LTD.
    Inventors: Yi-Chun Shih, Shun-Min Yeh
  • Patent number: 10847644
    Abstract: A gallium nitride transistor includes one or more P-type hole injection structures that are positioned between the gate and the drain. The P-type hole injection structures are configured to inject holes in the transistor channel to combine with trapped carriers (e.g., electrons) so the electrical conductivity of the channel is less susceptible to previous voltage potentials applied to the transistor.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: November 24, 2020
    Assignee: NAVITAS SEMICONDUCTOR LIMITED
    Inventors: Daniel M. Kinzer, Maher J. Hamdan
  • Patent number: 10840353
    Abstract: A semiconductor device includes a heterojunction semiconductor body including a first and second type III-V semiconductor layers with different bandgaps such that a first two-dimensional charge carrier gas forms at an interface between the two layers. The second type III-V semiconductor layer includes a thicker section and a thinner section. A first input-output electrode is on the thicker section and is in ohmic contact with the first two-dimensional charge carrier gas. A second input-output electrode is formed on the thinner section and is in ohmic contact with the first two-dimensional charge carrier gas. A gate structure is formed on the thinner section and is configured to control a conductive connection between the first and second input-output electrodes. The gate structure is laterally spaced apart from a transition between the thicker and thinner sections of the second type III-V semiconductor layer.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: November 17, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Gilberto Curatola, Oliver Haeberlen
  • Patent number: 10818787
    Abstract: An electronic device can include a HEMT. In an embodiment, a gate electrode, a drain electrode, and an access region including a first portion closer to the gate electrode and a second portion closer to the drain electrode. A lower dielectric film can overlie a portion of the access region, and an upper dielectric region can overlie another portion of the access region. In another embodiment, a dielectric film can have a relatively positive or negative charge and a varying thickness. In a further embodiment, the HEMT can include a gate electrode; a dielectric film overlying the gate electrode and defining openings to the gate electrode, wherein a portion of the dielectric film is disposed between the openings; and a gate interconnect extending into the openings of the dielectric film and contacting the gate electrode and the portion of the dielectric film.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: October 27, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Abhishek Banerjee, Peter Moens
  • Patent number: 10811527
    Abstract: An electronic device can include a drain electrode of a high electron mobility transistor overlying a channel layer; a source electrode overlying the channel layer, wherein a lowermost portion of the source electrode overlies at least a portion of the channel layer; and a gate electrode of the high electron mobility transistor overlying the channel layer; and a current limiting control structure that controls current passing between the drain and source electrodes. The current limiting control structure can be disposed between the source and gate electrodes, the current limiting control structure can be coupled to the source electrode and the first high electron mobility transistor, and the current limiting control structure has a threshold voltage. The current limiting control structure can be a Schottky-gated HEMT or a MISHEMT.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: October 20, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Peter Moens, Abhishek Banerjee, Piet Vanmeerbeek
  • Patent number: 10811407
    Abstract: A monolithic integration of enhancement mode (E-mode) and depletion mode (D-mode) field effect transistors (FETs) comprises a compound semiconductor substrate overlaid by an epitaxial structure overlaid by source and drain electrodes. The epitaxial structure includes from bottom to top sequentially a buffer layer, a channel layer, a Schottky barrier layer, a first etch stop layer, and a first cap layer. The respective first gate metal layers of the D-mode and E-mode FET are in contact with the first etch stop layer. The D-mode and E-mode gate-sinking regions are beneath the respective first gate metal layers of the D-mode and E-mode gate electrode at least within the first etch stop layer. The first gate metal layer material of the D-mode is the same as that of the E-mode, where the first gate metal layer thickness of the E-mode is greater than that of the D-mode.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: October 20, 2020
    Assignee: WIN SEMICONDUCTOR CORP.
    Inventors: Chia-Ming Chang, Jung-Tao Chung, Yan-Cheng Lin, Lung-Yi Tseng
  • Patent number: 10811526
    Abstract: A semiconductor device includes a silicon pillar disposed on a substrate, the silicon pillar has a sidewall. A group III-N semiconductor material is disposed on the sidewall of the silicon pillar. The group III-N semiconductor material has a sidewall. A doped source structure and a doped drain structure are disposed on the group III-N semiconductor material. A polarization charge inducing layer is disposed on the sidewall of the group III-N semiconductor material between the doped drain structure and the doped source structure. A plurality of portions of gate dielectric layer is disposed on the sidewalls of the group III-N semiconductor material and between the polarization charge inducing layer. A plurality of resistive gate electrodes separated by an interlayer dielectric layer are disposal adjacent to each of the plurality of portions of the gate dielectric layer. A source metal layer is disposed below and in contact with the doped source structure.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: October 20, 2020
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta
  • Patent number: 10804385
    Abstract: A semiconductor device includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a source/drain pair, a fluorinated region, and a gate. The channel layer is disposed over the substrate. The barrier layer is disposed over the channel layer. The compound semiconductor layer is disposed over the barrier layer. The source/drain pair is disposed over the substrate, wherein the source and the drain are located on opposite sides of the compound semiconductor layer. The fluorinated region is disposed in the compound semiconductor layer. The gate is disposed on the compound semiconductor layer.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: October 13, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventor: Chih-Yen Chen
  • Patent number: 10804228
    Abstract: A device includes a semiconductor substrate of a first conductivity type, and a deep well region in the semiconductor substrate, wherein the deep well region is of a second conductivity type opposite to the first conductivity type. The device further includes a well region of the first conductivity type over the deep well region. The semiconductor substrate has a top portion overlying the well region, and a bottom portion underlying the deep well region, wherein the top portion and the bottom portion are of the first conductivity type, and have a high resistivity. A gate dielectric is over the semiconductor substrate. A gate electrode is over the gate dielectric. A source region and a drain region extend into the top portion of the semiconductor substrate. The source region, the drain region, the gate dielectric, and the gate electrode form a Radio Frequency (RF) switch.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chung Chen, Chi-Feng Huang, Shu Fang Fu, Tzu-Jin Yeh, Chewn-Pu Jou
  • Patent number: 10804369
    Abstract: A nitride semiconductor layer (2,3,4) is provided on a Si substrate (1). A gate electrode (5), a source electrode (6) and a drain electrode (7) are provided on the nitride semiconductor layer (2,3,4). A P-type conductive layer (11) in contact with the nitride semiconductor layer (2,3,4) is provided on the Si substrate (1) below the drain electrode (7).
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: October 13, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventor: Toshiaki Kitano
  • Patent number: 10804384
    Abstract: A semiconductor device includes: a back barrier layer containing AlXGa(1-X)N (0<X?1); an electron transit layer containing AlaInbGa(1-a-b)N (0?a+b?1) and formed on the back barrier layer; a top barrier layer containing AlYGa(1-Y)N (0<Y?1) and formed on the electron transit layer; an electron supply layer containing AlZGa(1-Z)N (0<Z?1) and formed on the top barrier layer, the electron supply layer having an opening to expose the top barrier layer; a two-dimensional electron gas region formed in an area of a surface layer portion of the electron transit layer, the area opposing the electron supply layer with the top barrier layer interposed between the electron supply layer and the area; a gate insulating layer formed in the opening of the electron supply layer; and a gate electrode layer formed on the gate insulating layer and opposing the electron transit layer with the gate insulating layer interposed therebetween.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: October 13, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Kazuya Nagase, Shinya Takado, Minoru Akutsu