Doping On Side Of Heterojunction With Lower Carrier Affinity (e.g., High Electron Mobility Transistor (hemt)) Patents (Class 257/194)
  • Patent number: 10811527
    Abstract: An electronic device can include a drain electrode of a high electron mobility transistor overlying a channel layer; a source electrode overlying the channel layer, wherein a lowermost portion of the source electrode overlies at least a portion of the channel layer; and a gate electrode of the high electron mobility transistor overlying the channel layer; and a current limiting control structure that controls current passing between the drain and source electrodes. The current limiting control structure can be disposed between the source and gate electrodes, the current limiting control structure can be coupled to the source electrode and the first high electron mobility transistor, and the current limiting control structure has a threshold voltage. The current limiting control structure can be a Schottky-gated HEMT or a MISHEMT.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: October 20, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Peter Moens, Abhishek Banerjee, Piet Vanmeerbeek
  • Patent number: 10811526
    Abstract: A semiconductor device includes a silicon pillar disposed on a substrate, the silicon pillar has a sidewall. A group III-N semiconductor material is disposed on the sidewall of the silicon pillar. The group III-N semiconductor material has a sidewall. A doped source structure and a doped drain structure are disposed on the group III-N semiconductor material. A polarization charge inducing layer is disposed on the sidewall of the group III-N semiconductor material between the doped drain structure and the doped source structure. A plurality of portions of gate dielectric layer is disposed on the sidewalls of the group III-N semiconductor material and between the polarization charge inducing layer. A plurality of resistive gate electrodes separated by an interlayer dielectric layer are disposal adjacent to each of the plurality of portions of the gate dielectric layer. A source metal layer is disposed below and in contact with the doped source structure.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: October 20, 2020
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta
  • Patent number: 10811407
    Abstract: A monolithic integration of enhancement mode (E-mode) and depletion mode (D-mode) field effect transistors (FETs) comprises a compound semiconductor substrate overlaid by an epitaxial structure overlaid by source and drain electrodes. The epitaxial structure includes from bottom to top sequentially a buffer layer, a channel layer, a Schottky barrier layer, a first etch stop layer, and a first cap layer. The respective first gate metal layers of the D-mode and E-mode FET are in contact with the first etch stop layer. The D-mode and E-mode gate-sinking regions are beneath the respective first gate metal layers of the D-mode and E-mode gate electrode at least within the first etch stop layer. The first gate metal layer material of the D-mode is the same as that of the E-mode, where the first gate metal layer thickness of the E-mode is greater than that of the D-mode.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: October 20, 2020
    Assignee: WIN SEMICONDUCTOR CORP.
    Inventors: Chia-Ming Chang, Jung-Tao Chung, Yan-Cheng Lin, Lung-Yi Tseng
  • Patent number: 10804385
    Abstract: A semiconductor device includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a source/drain pair, a fluorinated region, and a gate. The channel layer is disposed over the substrate. The barrier layer is disposed over the channel layer. The compound semiconductor layer is disposed over the barrier layer. The source/drain pair is disposed over the substrate, wherein the source and the drain are located on opposite sides of the compound semiconductor layer. The fluorinated region is disposed in the compound semiconductor layer. The gate is disposed on the compound semiconductor layer.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: October 13, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventor: Chih-Yen Chen
  • Patent number: 10804384
    Abstract: A semiconductor device includes: a back barrier layer containing AlXGa(1-X)N (0<X?1); an electron transit layer containing AlaInbGa(1-a-b)N (0?a+b?1) and formed on the back barrier layer; a top barrier layer containing AlYGa(1-Y)N (0<Y?1) and formed on the electron transit layer; an electron supply layer containing AlZGa(1-Z)N (0<Z?1) and formed on the top barrier layer, the electron supply layer having an opening to expose the top barrier layer; a two-dimensional electron gas region formed in an area of a surface layer portion of the electron transit layer, the area opposing the electron supply layer with the top barrier layer interposed between the electron supply layer and the area; a gate insulating layer formed in the opening of the electron supply layer; and a gate electrode layer formed on the gate insulating layer and opposing the electron transit layer with the gate insulating layer interposed therebetween.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: October 13, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Kazuya Nagase, Shinya Takado, Minoru Akutsu
  • Patent number: 10804369
    Abstract: A nitride semiconductor layer (2,3,4) is provided on a Si substrate (1). A gate electrode (5), a source electrode (6) and a drain electrode (7) are provided on the nitride semiconductor layer (2,3,4). A P-type conductive layer (11) in contact with the nitride semiconductor layer (2,3,4) is provided on the Si substrate (1) below the drain electrode (7).
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: October 13, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventor: Toshiaki Kitano
  • Patent number: 10804228
    Abstract: A device includes a semiconductor substrate of a first conductivity type, and a deep well region in the semiconductor substrate, wherein the deep well region is of a second conductivity type opposite to the first conductivity type. The device further includes a well region of the first conductivity type over the deep well region. The semiconductor substrate has a top portion overlying the well region, and a bottom portion underlying the deep well region, wherein the top portion and the bottom portion are of the first conductivity type, and have a high resistivity. A gate dielectric is over the semiconductor substrate. A gate electrode is over the gate dielectric. A source region and a drain region extend into the top portion of the semiconductor substrate. The source region, the drain region, the gate dielectric, and the gate electrode form a Radio Frequency (RF) switch.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chung Chen, Chi-Feng Huang, Shu Fang Fu, Tzu-Jin Yeh, Chewn-Pu Jou
  • Patent number: 10804361
    Abstract: There is provided a nitride semiconductor device, including: a Si substrate including a front surface and a back surface; a buffer layer formed over the Si substrate; a first nitride semiconductor layer formed over the buffer layer; a second nitride semiconductor layer formed over the first nitride semiconductor layer; a gate electrode disposed over the second nitride semiconductor layer; a source electrode and a drain electrode electrically connected to the second nitride semiconductor layer, and disposed over the second nitride semiconductor layer to be spaced apart from the gate electrode that is interposed between the source electrode and the drain electrode; a back surface electrode pad formed over the back surface of the Si substrate; and a conductive path formed in the Si substrate, the buffer layer, the first nitride semiconductor layer, and the second nitride semiconductor layer.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: October 13, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Kenichi Yoshimochi
  • Patent number: 10790385
    Abstract: A high electron mobility transistor (HEMT) made of primarily nitride semiconductor materials is disclosed. The HEMT, which is a type of reverse HEMT, includes, on a C-polar surface of a SiC substrate, a barrier layer and a channel layer each having N-polar surfaces in respective top surfaces thereof. The HEMT further includes an intermediate layer highly doped with impurities and a Schottky barrier layer on the channel layer. The Schottky barrier layer and a portion of the intermediate layer are removed in portions beneath non-rectifying electrodes but a gate electrode is provided on the Schottky barrier layer.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: September 29, 2020
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Ken Nakata
  • Patent number: 10790375
    Abstract: A high electron mobility transistor (HEMT) includes a first compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A salicide source feature and a salicide drain feature are in contact with the first III-V compound layer through the second III-V compound layer. A gate electrode is disposed over a portion of the second compound layer between the salicide source feature and the salicide drain feature.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: September 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fu-Wei Yao, Chen-Ju Yu, King-Yuen Wong, Chun-Wei Hsu, Jiun-Lei Jerry Yu, Fu-Chih Yang, Chun Lin Tsai
  • Patent number: 10784366
    Abstract: The present invention provides an integrated enhancement/depletion mode HEMT and a method for manufacturing the same, by which method an enhancement mode transistor and a depletion mode transistor can be integrated together, which is beneficial for increasing the application of gallium nitride HEMT devices and improving the characteristics of circuits, and lay a foundation for realizing monolithic integration of high-speed digital/analog mixed signal radio frequency circuits. At the same time, by using a regrowth technology of a barrier layer, electrons generated by impurities are made part of a conductive channel, thus the concentration of the two-dimensional electron gas is increased, and the conductive performance is improved while preventing excessive electrons from interfering with the devices.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: September 22, 2020
    Inventors: Xianfeng Ni, Qian Fan, Wei He
  • Patent number: 10784361
    Abstract: A semiconductor device according to an embodiment includes a first GaN-based semiconductor layer, a second GaN-based semiconductor layer provided on the first GaN-based semiconductor layer and having a wider band gap than the first GaN-based semiconductor layer, a source electrode electrically connected to the second GaN-based semiconductor layer, a drain electrode electrically connected to the second GaN-based semiconductor layer, a gate electrode provided between the source electrode and the drain electrode, and a passivation film provided on the second GaN-based semiconductor layer between the source electrode and the gate electrode and between the gate electrode and the drain electrode, the passivation film including a first insulating film and a second insulating film, the first insulating film including nitrogen, the first insulating film having a thickness equal to or greater than 0.2 nm and less than 2 nm, the second insulating film including oxygen and provided on the first insulating film.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: September 22, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisashi Saito, Miki Yumoto
  • Patent number: 10784368
    Abstract: A semiconductor device includes a semiconductor substrate composed of a compound semiconductor, a first semiconductor region disposed over a surface of the semiconductor substrate so as to extend upward from the surface of the semiconductor substrate, the first semiconductor region including a semiconductor nanowire composed of a compound semiconductor, a second semiconductor region disposed over the periphery of a side surface of the first semiconductor region, a gate electrode disposed over the periphery of the second semiconductor region, a drain electrode coupled to one end of the first semiconductor region, and a source electrode coupled to another end of the first semiconductor region, the first and second semiconductor regions being composed of different semiconductor materials.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: September 22, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Tsuyoshi Takahashi, Kenichi Kawaguchi
  • Patent number: 10784170
    Abstract: Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: September 22, 2020
    Assignee: Intel Corporation
    Inventors: Marko Radosavljevic, Ravi Pillarisetty, Gilbert Dewey, Niloy Mukherjee, Jack Kavalieros, Willy Rachmady, Van Le, Benjamin Chu-Kung, Matthew Metz, Robert Chau
  • Patent number: 10777643
    Abstract: A semiconductor device includes: a semiconductor substrate; a buffer layer provided on the semiconductor substrate; a GaN channel layer provided on the buffer layer; an AlGaN electron travel layer provided on the GaN channel layer; a GaN cap layer provided on the AlGaN electron travel layer, having a nitrogen polarity, and on which a plurality of recesses are formed; and a gate electrode, a source electrode and a drain electrode provided in each of the plurality of recesses.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: September 15, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventor: Kohei Miki
  • Patent number: 10777669
    Abstract: A heterojunction bipolar transistor includes a collector layer, a base layer, and an emitter layer that are stacked on a substrate. The collector layer includes a graded semiconductor layer in which an electron affinity increases from a side closer to the base layer toward a side farther from the base layer. An electron affinity of the base layer at an interface closer to the collector layer is equal to an electron affinity of the graded semiconductor layer at an interface closer to the base layer.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: September 15, 2020
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari Umemoto, Shigeki Koya, Isao Obu
  • Patent number: 10763174
    Abstract: A method for recovering carbon-face-polarized silicon carbide substrates, including: providing an epitaxial structure, the epitaxial structure includes a carbon-face-polarized silicon carbide substrate to be recovered, as well as a nitrogen-face-polarized gallium nitride buffer layer, a barrier layer and a nitrogen-face-polarized gallium nitride channel layer that are sequentially deposited on the silicon carbide substrate; removing the nitrogen-face-polarized gallium nitride buffer layer, the barrier layer and the nitrogen-face-polarized gallium nitride channel layer by wet etching; and cleaning and blowing dry the carbon-face-polarized silicon carbide substrate.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: September 1, 2020
    Assignee: SUZHOU HAN HUA SEMICONDUCTOR CO., LTD.
    Inventors: Xianfeng Ni, Qian Fan, Wei He
  • Patent number: 10756207
    Abstract: A lateral III-N device has a vertical gate module with III-N material orientated in an N-polar or a group-III polar orientation. A III-N material structure has a III-N buffer layer, a III-N barrier layer, and a III-N channel layer. A compositional difference between the III-N barrier layer and the III-N channel layer causes a 2DEG channel to be induced in the III-N channel layer. A p-type III-N body layer is disposed over the III-N channel layer in a source side access region but not over a drain side access region. A n-type III-N capping layer over the p-type III-N body layer. A source electrode that contacts the n-type III-N capping layer is electrically connected to the p-type III-N body layer and is electrically isolated from the 2DEG channel when the gate electrode is biased relative to the source electrode at a voltage that is below a threshold voltage.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: August 25, 2020
    Assignee: Transphorm Technology, Inc.
    Inventors: Umesh Mishra, Davide Bisi, Geetak Gupta, Carl Joseph Neufeld, Brian L. Swenson, Rakesh K. Lal
  • Patent number: 10756084
    Abstract: The present invention discloses a group-III nitride semiconductor device, which comprises a substrate, a buffer layer, a semiconductor stack structure, and a passivation film. The buffer layer is disposed on the substrate. The semiconductor stack structure is disposed on the buffer layer and comprises a gate, a source, and a drain. In addition, a gate insulating layer is disposed between the gate and the semiconductor stack structure for forming a HEMT. The passivation film covers the HEMT and includes a plurality of openings corresponding to the gate, the source, and the drain, respectively. The material of the passivation film is silicon oxynitride.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: August 25, 2020
    Inventor: Wen-Jang Jiang
  • Patent number: 10749020
    Abstract: The invention relates to the group III-nitride semiconductor device and corresponding fabricating method. Specifically, a method to reduce RF dispersion in a group III-nitride high electron mobility transistor (HEMT), especially for reduced barrier thickness epi materials and scaled deices for higher frequency applications. Periodic n-type doping within barrier is used to screen surface state traps, which are responsible for the above-mentioned RF dispersion, without introducing additional gate leakage current path. Within the method, the barrier (typically AlGaN, AlInN) layer is periodically n-type doped with its composition (such as Al % within AlGaN) periodically modulated. The periodic structure is effective in both screening surface state traps and reducing the leakage current within the AlGaN/gate Schottky barrier.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: August 18, 2020
    Assignee: SUZHOU HAN HUA SEMICONDUCTOR CO., LTD.
    Inventors: Xian-Feng Ni, Qian Fan, Wei He
  • Patent number: 10749009
    Abstract: Fabricating high efficiency, high linearity N-polar gallium-nitride (GaN) transistors by selective area regrowth is disclosed. A demand for high efficiency components with highly linear performance characteristics for radio frequency (RF) systems has increased development of GaN transistors and, in particular, aluminum-gallium-nitride (AlGaN)/GaN high electron mobility transistor (HEMT) devices. A method of fabricating a high efficiency, high linearity N-polar HEMT device includes employing a selective area regrowth method for forming a HEMT structure on the Nitrogen-face (N-face) of a GaN buffer, a natural high composition AlGaN/AlN back barrier for carrier confinement, a thick undoped GaN layer on the access areas to eliminate surface dispersion, and a high access area width to channel width ratio for improved linearity. A problem of impurities on the GaN buffer surface prior to regrowth creating a leakage path is avoided by intentional silicon (Si) doping in the HEMT structure.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: August 18, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Xing Gu, Jinqiao Xie, Cathy Lee
  • Patent number: 10748776
    Abstract: In the present invention, a contact layer formed of a material having an electron concentration of less than 1×1022 cm?3 is directly provided on a surface of a semiconductor crystal having an n-type conductivity with a band gap of 1.2 eV or less at room temperature. Consequently, the wave function penetration from the contact layer side to the semiconductor surface side is reduced. As a result, the formation of the energy barrier height·?B due to the Fermi level pinning phenomenon is much suppressed. It is possible to achieve the contact with a lower resistivity and with high ohmic properties.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: August 18, 2020
    Assignee: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Akira Toriumi, Tomonori Nishimura
  • Patent number: 10749003
    Abstract: Provided is a manufacturing method of a semiconductor device including a vertical MOSFET having a planar gate. The manufacturing method of a semiconductor device includes forming a n-type gallium nitride layer on a gallium nitride monocrystalline substrate, and forming an impurity-implanted region that contains impurities at a uniform concentration in a direction parallel to a main surface of the gallium nitride monocrystalline substrate, by ion-implanting the impurities into the n-type gallium nitride layer, where the impurities include at least one type selected from among magnesium, beryllium, calcium and zinc. Here, at least part of the impurity-implanted region serves as a channel forming region of the vertical MOSFET.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: August 18, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Katsunori Ueno, Shinya Takashima
  • Patent number: 10741682
    Abstract: High-electron-mobility transistor (HEMT) devices are described in this patent application. In some implementations, the HEMT devices can include a back barrier hole injection structure. In some implementations, the HEMT devices include a conductive striped portion electrically coupled to a drain contact.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: August 11, 2020
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Woochul Jeon, Ali Salih, Llewellyn Vaughan-Edmunds
  • Patent number: 10741494
    Abstract: An electronic device can include a semiconductor layer and a contact structure forming an ohmic contact with the layer. In an embodiment, the semiconductor layer can include a III-N material, and the contact structure includes a first phase and a second phase, wherein the first phase includes Al, the second phase includes a metal, and the first phase contacts the semiconductor layer. In another embodiment, the semiconductor layer can be a monocrystalline layer having a surface along a crystal plane. The contact structure can include a polycrystalline material including crystals having surfaces that contact the surface of the monocrystalline layer, wherein a lattice mismatch between the surface of the monocrystalline layer and the surfaces of the crystals is at most 20%.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: August 11, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Aurore Constant, Peter Coppens, Joris Baele
  • Patent number: 10727328
    Abstract: A semiconductor device includes a substrate, a channel layer, an active layer, and a gate electrode. The channel layer has a fin portion over the substrate. The active layer is over at least the fin portion of the channel layer. The active layer is configured to cause a two-dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer. The gate electrode is in contact with a sidewall of the fin portion of the channel layer.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: July 28, 2020
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chao-Hsin Wu, Li-Cheng Chang, Cheng-Jia Dai, Shun-Cheng Yang
  • Patent number: 10727329
    Abstract: A semiconductor device includes a transistor, a semiconductor layer, an active region and a conductive layer. The active region is in the semiconductor layer. The conductive layer is configured to maintain a channel in the active region when the transistor is triggered to be conducted.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Syuan Lin, Jiun-Lei Yu, Ming-Cheng Lin, Chun Lin Tsai
  • Patent number: 10720497
    Abstract: A Field Effect Transistor (FET) having a source, drain, and gate disposed laterally along a surface of a semiconductor and a field plate structure: having one end connected to the source; and having a second end disposed between the gate and the drain and separated from the drain by a gap. A dielectric structure is disposed over the semiconductor, having: a first portion disposed under the second end of the field plate structure; and, a second, thinner portion under the gap.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: July 21, 2020
    Assignee: Raytheon Company
    Inventors: Christopher J. MacDonald, Kenneth A. Wilson, Kamal Tabatabaie Alavi, Adrian D. Williams
  • Patent number: 10720390
    Abstract: An ohmic metal for GaN device comprises a diffusion barrier seed metal layer and a plurality of metal layers. The diffusion barrier seed metal layer is formed on an epitaxial structure layer. The diffusion barrier seed metal layer is made of Pt. The epitaxial structure layer is made of AlGaN or GaN. The plurality of metal layers is formed on the diffusion barrier seed metal layer. The plurality of metal layers comprises a first metal layer and a second metal layer. The first metal layer is formed on the diffusion barrier seed metal layer. The first metal layer is made of Ti. The second metal layer is formed on the first metal layer. The second metal layer is made of Al. By the diffusion barrier seed metal layer, so as to suppress the diffusion of the plurality of metal layers into the epitaxial structure layer.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: July 21, 2020
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Chang-Hwang Hua, Yi-Wei Lien
  • Patent number: 10714605
    Abstract: A transistor includes a substrate, a channel layer coupled to the substrate, a source electrode coupled to the channel layer, a drain electrode coupled to the channel layer, and a gate electrode coupled to the channel layer between the source electrode and the drain electrode. The gate electrode has a length dimension of less than 50 nanometers near the channel layer, and the channel layer includes at least a first GaN layer and a first graded AlGaN layer on the first GaN layer.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: July 14, 2020
    Assignee: HRL Laboratories, LLC
    Inventors: Jeong-Sun Moon, Andrea Corrion, Joel C. Wong, Adam J. Williams
  • Patent number: 10714606
    Abstract: A semiconductor device includes a conductive substrate, a channel forming layer, a first electrode, and a second electrode. The channel forming layer is located above the conductive substrate and includes at least one hetero-junction structure. The hetero-junction structure includes a first GaN-type semiconductor layer providing a drift region and a second GaN-type semiconductor layer having a bandgap energy greater than the first GaN-type semiconductor layer. A total fixed charge quantity of charges in the first GaN-type layer and the second GaN-type layer is from 0.5×1013 to 1.5×1013 cm?2. The charges in the first GaN-type layer and the second GaN-type layer include charges generated by the polarization in the first GaN-type layer. Accordingly, the semiconductor device capable of improving a break-down voltage and decreasing an on-resistance is obtained.
    Type: Grant
    Filed: September 5, 2016
    Date of Patent: July 14, 2020
    Assignee: DENSO CORPORATION
    Inventors: Youngshin Eum, Kazuhiro Oyama, Yasushi Higuchi, Yoshinori Tsuchiya, Shinichi Hoshi
  • Patent number: 10707311
    Abstract: HEMT having a drain field plate is provided. The drain field plate is formed in the area between the gate and drain of a HEMT. The drain field plate includes a metal pad that has a larger projection area than the drain pad. The drain field plate and semiconductor layer disposed beneath the drain field plate form a metal-semiconductor (M-S) Schottky structure. The capacitance of the M-S Schottky structure generates capacitance in the semiconductor area, which increases the breakdown voltage of the transistor components of the HEMT. A portion of the substrate under the active area may be removed to thereby increase the heat conductivity and reduce the junction temperature of the transistor components of the HEMT.
    Type: Grant
    Filed: December 1, 2018
    Date of Patent: July 7, 2020
    Assignee: RFHIC CORPORATION
    Inventor: Won Sang Lee
  • Patent number: 10699896
    Abstract: A method of fabricating a semiconductor device structure includes: providing a substrate comprising a layer of compound semiconductor material; forming a seed layer of nano-crystalline diamond having a layer thickness in a range 5 to 50 nm on the layer of compound semiconductor material; and growing a layer of polycrystalline CVD diamond on the seed layer using a chemical vapour deposition (CVD) technique. An effective thermal boundary resistance (TBReff) at an interface between the layer of compound semiconductor material and the layer of polycrystalline CVD diamond material is no more than 50 m2K/GW.
    Type: Grant
    Filed: April 14, 2019
    Date of Patent: June 30, 2020
    Assignee: RFHIC CORPORATION
    Inventors: Firooz Nasser-Faili, Daniel Francis, Frank Yantis Lowe, Daniel James Twitchen
  • Patent number: 10693228
    Abstract: An antenna kit includes: main and auxiliary antenna units to be disposed respectively on first and second dielectric substrates; and two connecting units. The main antenna unit includes two main radiating modules which are symmetrical with respect to a first axis, and each of which includes a main feed point, a main radiating portion and an extending portion. The auxiliary antenna unit is symmetrical with respect to a second axis, and includes two auxiliary feed points, two auxiliary radiating portions and a connecting portion. Each connecting unit is capable of being assembled such that the main radiating portion of a respective main radiating module and a respective auxiliary radiating portion are connected via the assembled connecting unit.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: June 23, 2020
    Assignee: TRANS ELECTRIC CO., LTD.
    Inventor: Ching-Yuan Wang
  • Patent number: 10692984
    Abstract: A field effect transistor (FET) includes a III-nitride channel layer, a III-nitride barrier layer on the channel layer, a first dielectric on the barrier layer, a first gate trench extending through the first dielectric, and partially or entirely through the barrier layer, a second dielectric on a bottom and walls of the first gate trench, a source electrode on a first side of the first gate trench, a drain electrode on a second side of the first gate trench opposite the first side, a first gate electrode on the second dielectric and filling the first gate trench, a third dielectric between the first gate trench and the drain electrode, a second gate trench extending through the third dielectric and laterally located between the first gate trench and the drain electrode, and a second gate electrode filling the second gate trench.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: June 23, 2020
    Assignee: HRL Laboratories, LLC
    Inventor: Rongming Chu
  • Patent number: 10685007
    Abstract: A deployment infrastructure (DI) imports at least one object description artifact and at least one content data file associated with a database object to a design-time container. The DI deploys the database object in a runtime container based on the at least one object description artifact and the at least one content data file. The DI exports the at least one object description artifact in the design-time container and at least one updated content data file based on an updated database object in the runtime container, wherein the updated database object includes updated content of the database object generated at runtime of a database application.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: June 16, 2020
    Assignee: SAP SE
    Inventors: Peter Eberlein, Volker Driesen, Arne Harren
  • Patent number: 10686064
    Abstract: A nitride semiconductor device includes an electron transit layer (103) that is formed of a nitride semiconductor, an electron supply layer (104) that is formed on the electron transit layer (103), that is formed of a nitride semiconductor whose composition is different from the electron transit layer (103) and that has a recess (109) which reaches the electron transit layer (103) from a surface, a thermal oxide film (111) that is formed on the surface of the electron transit layer (103) exposed within the recess (109), a gate insulating film (110) that is embedded within the recess (109) so as to be in contact with the thermal oxide film (111), a gate electrode (108) that is formed on the gate insulating film (110) and that is opposite to the electron transit layer (103) across the thermal oxide film (111) and the gate insulating film (110), and a source electrode (106) and a drain electrode (107) that are provided on the electron supply layer (104) at an interval such that the gate electrode (108) intervene
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: June 16, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Kenji Yamamoto, Tetsuya Fujiwara, Minoru Akutsu, Ken Nakahara, Norikazu Ito
  • Patent number: 10680092
    Abstract: An electronic device can include a channel layer, a first carrier supply layer, a gate electrode of a HEMT, and a drain electrode of the HEMT. The HEMT can have a 2DEG along an interface between the channel and first carrier supply layers. In an aspect, the 2DEG can have a highest density that is the highest at a point between the drain and gate electrodes. In another aspect, the HEMT can further comprise first and second carrier supply layers, wherein the first carrier supply layer is disposed between the channel and second carrier supply layers. The second carrier supply layer be thicker at a location between the drain and gate electrodes. In a further aspect, a process of forming an electronic device can include the HEMT. In a particular embodiment, first and second carrier supply layers can be epitaxially grown from an underlying layer.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: June 9, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Peter Moens, Aurore Constant, Peter Coppens, Abhishek Banerjee
  • Patent number: 10658486
    Abstract: The present disclosure describes an exemplary replacement gate process that forms spacer layers in a gate stack to mitigate time dependent dielectric breakdown (TDDB) failures. For example, the method can include a partially fabricated gate structure with a first recess. A spacer layer is deposited into the first recess and etched with an anisotropic etchback (EB) process to form a second recess that has a smaller aperture than the first recess. A metal fill layer is deposited into the second recess.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacutring Co., Ltd.
    Inventors: Yi-Jyun Huang, Bao-Ru Young, Tung-Heng Hsieh
  • Patent number: 10658501
    Abstract: A high electron mobility transistor (HEMT) includes a channel semiconductor structure including a stack of layers arranged on top of each other in an order of magnitudes of the polarization of materials of the layers to form multiple carrier channels at heterojunctions formed by each pair of layers in the stack. The stack of layers includes a first layer and a second layer. The magnitude of polarization of the first layer is greater than the magnitude of polarization of the second layer arranged in the stack below the first layer, and the width of the first layer is less than the width of the second layer to form a staircase profile of the semiconductor structure. The HEMT includes a source semiconductor structure including a heavily doped semiconductor material, a drain semiconductor structure including the heavily doped semiconductor material. The HEMT includes a source, a drain, and a gate electrodes to modulate the conductivity of the carrier channels.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: May 19, 2020
    Assignee: Mitsubishi Electric Research Laboratories, Inc.
    Inventors: Koon Hoo Teo, Nadim Chowdhury
  • Patent number: 10651303
    Abstract: A device includes a first high electronic mobility transistor (HEMT) and a second HEMT. The first HEMT includes a first gate, a source coupled to the first gate, and a drain coupled to the first gate. The second HEMT includes a second gate coupled to the source and to the drain. The second HEMT has a lower threshold voltage than the first HEMT.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: May 12, 2020
    Assignee: Vishay Siliconix, LLC
    Inventors: Ayman Shibib, Kyle Terrill
  • Patent number: 10644107
    Abstract: The independent claims of this patent signify a concise description of embodiments. Disclosed herein is a normally-off, gallium oxide field-effect transistor. The field-effect transistor comprises a source, a source spacer, a first channel region, a second channel region, a drain spacer, and a drain. The source, the source spacer, the first channel region, the second channel region, the drain spacer, and the drain are of a first conductivity type. All the regions have the same type of doping. The field-effect transistor further includes a gate dielectric over the channel body and a gate over the gate dielectric. The first channel region has a cross-sectional area that is smaller than the second channel region.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: May 5, 2020
    Assignee: Synopsys, Inc.
    Inventors: Hiu Yung Wong, Nelson de Almeida Braga, Rimvydas Mickevicius
  • Patent number: 10629696
    Abstract: A method for forming a hexagonal boron nitride (h-BN) thin film is provided. According to the method, an alumina thin film including amorphous alumina or gamma-alumina is prepared. An h-BN thin film is synthesized at equal to or less than 750° C. on the alumina thin film. A mono-layer thickness of the h-BN film is equal to or less than 0.40 nm.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: April 21, 2020
    Assignee: Korea Institute of Science and Technology
    Inventors: Jaehyun Park, Yumin Sim, Jaikyeong Kim
  • Patent number: 10629718
    Abstract: An epitaxial structure includes a substrate, a buffer layer, a channel layer, an intermediate layer, and a barrier layer. The buffer layer is disposed on the substrate, the channel layer is disposed on the buffer layer, the barrier layer is disposed on the channel layer, and the intermediate layer is disposed between the channel layer and the barrier layer. The chemical composition of the barrier layer is Alx1Iny1Gaz1N, and the chemical composition of the intermediate layer is Alx2Iny2Gaz2N. The lattice constant of the barrier layer is greater than the lattice constant of the intermediate layer. The aluminum (Al) content of at least a portion of the intermediate layer is greater than the Al content of the barrier layer.
    Type: Grant
    Filed: November 22, 2018
    Date of Patent: April 21, 2020
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Jia-Zhe Liu, Yen-Lun Huang, Ying-Ru Shih
  • Patent number: 10629773
    Abstract: Disclosed is a light-emitting diode containing: first and second semiconductor layers respectively n-doped and p-doped, forming a p-n junction; an active zone placed between the first and second layers, including an InXGa1-XN emitting layer able to form a quantum well, and two InYGa1-YN, where 0<Y<X, barrier layers between which the emitting layer is placed; and an intermediate layer, which is placed either in the barrier layer located between the emitting layer and the first layer and portions of which are then on either side of the intermediate layer, or placed between the barrier layer and the emitting layer. The intermediate layer includes a III-N semiconductor of bandgap wider than that of the barrier layer. The second layer includes GaN or InWGa1-WN, where 0<W<Y, and the first layer includes InVGa1-VN, where V>W>0.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: April 21, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Armelle Even, Miryam Elouneg-Jamroz, Ivan-Christophe Robin
  • Patent number: 10600710
    Abstract: A semiconductor device includes a group III-semiconductor-nitride-based channel layer, a group III-semiconductor-nitride-based barrier layer formed on the channel layer, a two-dimensional electron gas channel formed in the channel layer, a first current electrode and a second current electrode formed on the barrier layer and laterally spaced from each other, and a gate structure formed on the barrier layer between the first and second current electrodes. The barrier layer has a symmetrically shaped recess between the first and second current electrodes, the symmetrically shaped recess including a first recess portion formed in a part of an upper surface of the barrier layer and a second recess portion formed within the first recess portion. The gate structure includes a group III-semiconductor-nitride-based doped layer that fills the symmetrically shaped recess and an electrically conductive gate electrode formed on an upper side of the doped layer that is opposite from the barrier layer.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: March 24, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Gerhard Prechtl, Clemens Ostermaier, Oliver Häberlen
  • Patent number: 10593610
    Abstract: A semiconductor power device including a base plate; an input lead; an output lead; a field effect transistor (FET) power die disposed over the base plate, wherein the FET power die includes a set of source fingers, a set of drain fingers, and a set of gate fingers disposed directly over an active region, wherein the gate fingers are configured to receive an input signal from the input lead, and wherein the FET power die is configured to process the input signal to generate an output signal at the drain fingers for routing to the output lead; and electrical conductors (wirebonds or ribbons) bonded to the source and/or drain directly over the active region of the FET power die. The electrical conductors produce additional thermal paths between the active region and the base plate for thermal management of the FET power die.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: March 17, 2020
    Assignee: Integra Technologies, Inc.
    Inventor: Gabriele Formicone
  • Patent number: 10592902
    Abstract: A computer-implemented method for modifying control parameters associated with a financial product that is linked to an account. The method includes receiving updated control parameters for the financial product, where the account provides financial backing for the financial product, and the updated control parameters define updated use restrictions for the financial product; and modifying the control parameters associated with the financial product to reflect the updated control parameters, where the financial product is configured to be used for one or more payment transactions in accordance with the updated use restrictions.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: March 17, 2020
    Assignee: VERIENT INC.
    Inventor: Rajesh G. Shakkarwar
  • Patent number: 10580922
    Abstract: Method of providing a boron doped region (8, 8a, 8b) in a silicon substrate (1), includes the steps of: (a) depositing a boron doping source (6) over a first surface (2) of the substrate (1); (b) annealing the substrate (1) for diffusing boron from the boron doping source (6) into the first surface (2), thereby yielding a boron doped region; (c) removing the boron doping source (6) from at least part of the first surface (2); (d) depositing undoped silicon oxide (10) over the first surface (2); and (e) annealing the substrate (1) for lowering a peak concentration of boron in the boron doped region (8, 8a) through boron absorption by the undoped silicon oxide. The silicon oxide (10) acts as a boron absorber to obtain the desired concentration of the boron doped region (8).
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: March 3, 2020
    Assignee: NEDERLANDSE ORGANISATIE VOOR TOEGEPAST-NATUURWETENSCHAPPELIJK ONDERZOEK TNO
    Inventors: Yuji Komatsu, John Anker, Paul Cornelis Barton, Ingrid Gerdina Romijn
  • Patent number: 10578708
    Abstract: A transmit/receive module having a switch, a load and a controller for coupling radar energy fed to switch to the load during a time interval subsequent to the controller producing a transmit enable signal to the transmit/receive module and prior to the controller producing a receive enable signal to the transmit/receive module.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: March 3, 2020
    Assignee: Raytheon Company
    Inventors: Steven C. Evangelista, Christopher M. Laighton, Anthony J. Silva