Combined With Diverse Type Device Patents (Class 257/195)
  • Patent number: 10083884
    Abstract: There are disclosed herein various implementations of a compact high-voltage semiconductor package. In one exemplary implementation, such a semiconductor package includes a power transistor, as well as a drain contact, a source contact, and a gate contact to provide external connections to the power transistor. The semiconductor package also includes a contour element formed between the drain contact and the source contact in the semiconductor package. The contour element increases a creepage distance between the drain contact and the source contact in the semiconductor package so as to increase a breakdown voltage of the semiconductor package.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: September 25, 2018
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Eung San Cho, Chuan Cheah
  • Patent number: 9911858
    Abstract: A miniaturized semiconductor device including a transistor in which a channel formation region is formed using an oxide semiconductor film and variation in electric characteristics due to a short-channel effect is suppressed is provided. In addition, a semiconductor device whose on-state current is improved is provided. A semiconductor device is provided with an oxide semiconductor film including a pair of second oxide semiconductor regions which are amorphous regions and a first oxide semiconductor region located between the pair of second oxide semiconductor regions, a gate insulating film, and a gate electrode provided over the first oxide semiconductor region with the gate insulating film interposed therebetween. One or more kinds of elements selected from Group 15 elements such as nitrogen, phosphorus, and arsenic are added to the second oxide semiconductor regions.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: March 6, 2018
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Shunpei Yamazaki
  • Patent number: 9837399
    Abstract: In accordance with an embodiment, semiconductor component having a compound semiconductor material based semiconductor device connected to a silicon based semiconductor device and a protection element, wherein the silicon based semiconductor device is a transistor. The protection element is coupled in parallel across the silicon based semiconductor device and may be a resistor, a diode, or a transistor. In accordance with another embodiment, the silicon based semiconductor device is a diode. The compound semiconductor material may be shorted to a source of potential such as, for example, ground, with a shorting element.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: December 5, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Balaji Padmanabhan, Prasad Venkatraman, Chun-Li Liu, Ali Salih
  • Patent number: 9799646
    Abstract: In accordance with an embodiment, semiconductor component includes a compound semiconductor material based semiconductor device coupled to a silicon based semiconductor device and a protection element, wherein the silicon based semiconductor device is a transistor. The protection element is coupled in parallel across the silicon based semiconductor device and may be a resistor, a diode, or a transistor. In accordance with another embodiment, the silicon based semiconductor device is a diode. The compound semiconductor material may be shorted to a source of potential such as, for example, ground, with a shorting element.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: October 24, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Chun-Li Liu, Ali Salih
  • Patent number: 9660109
    Abstract: A semiconductor device according to an embodiment includes a normally-off transistor having a first drain, a first source electrically connected to a source terminal, and a first gate electrically connected to a gate terminal, a normally-on transistor having a second source electrically connected to the first drain, a second drain electrically connected to a voltage terminal, and a second gate electrically connected to the first source, a coil component provided between the voltage terminal and the second drain, and a first diode having a first anode electrically connected to the first drain and the second source, and a first cathode electrically connected to the coil component and the voltage terminal.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: May 23, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kentaro Ikeda
  • Patent number: 9601483
    Abstract: A semiconductor device according to an embodiment includes a normally-off transistor having a first drain, a first source electrically connected to a source terminal, and a first gate electrically connected to a gate terminal, a normally-on transistor having a second gate, a second source electrically connected to the first drain, and a second drain electrically connected to a voltage terminal, a first capacitor provided between the gate terminal and the second gate, a first diode having a first anode electrically connected to the first capacitor and the second gate, and a first cathode electrically connected to the first source, a coil component provided between the voltage terminal and the second drain, and a second diode having a second anode electrically connected to the first drain and the second source, and a second cathode electrically connected to the coil component and the voltage terminal.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: March 21, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kentaro Ikeda
  • Patent number: 9502535
    Abstract: Semiconductor structures are disclosed for monolithically integrating multiple III-N transistors with different threshold voltages on a common substrate. A semiconductor structure includes a cap layer comprising a plurality of selectively etchable sublayers, wherein each sublayer is selectively etchable with respect to the sublayer immediately below, wherein each sublayer comprises a material AlxInyGazN (0?x, y, z?1), and wherein at least one selectively etchable sublayer has a non-zero Ga content (0<z?1). A gate recess is disposed in a number of adjacent sublayers of the cap layer to achieve a desired threshold voltage for a transistor. Also described are methods for fabricating such semiconductor structures, where gate recesses and/or ohmic recesses are formed by selectively removing adjacent sublayers of the cap layer. The performance of the resulting integrated circuits is improved, while providing design flexibility to reduce production cost and circuit footprint.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: November 22, 2016
    Assignee: Cambridge Electronics, Inc.
    Inventors: Ling Xia, Mohamed Azize, Bin Lu
  • Patent number: 9362267
    Abstract: In one implementation, a group III-V and group IV composite switch includes a group IV transistor in a lower active die, the group IV transistor having a source and a gate situated on a bottom side of the lower active die. The group III-V and group IV composite switch also includes a group III-V transistor in an upper active die stacked over the lower active die, the group III-V transistor having a drain, a source, and a gate situated on a top side of the upper active die. The source of the group III-V transistor is electrically coupled to a drain of the group IV transistor using a through-semiconductor via (TSV) of the upper active die.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: June 7, 2016
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Michael A. Briere, Tim McDonald
  • Patent number: 9343440
    Abstract: In one implementation, a stacked composite device comprises a group IV vertical transistor and a group III-V transistor stacked over the group IV vertical transistor. A drain of the group IV vertical transistor is in contact with a source of the group III-V transistor, a source of the group IV vertical transistor is coupled to a gate of the group III-V transistor to provide a composite source on a bottom side of the stacked composite device, and a drain of the group III-V transistor provides a composite drain on a top side of the stacked composite device. A gate of the group IV vertical transistor provides a composite gate on the top side of the stacked composite device.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: May 17, 2016
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Tim McDonald, Michael A. Briere
  • Patent number: 9306050
    Abstract: A semiconductor structure includes a semiconductor layer that is passivated with an aluminum-silicon nitride layer. When the semiconductor layer in particular comprises a III-V semiconductor material such as a group III nitride semiconductor material or a gallium nitride semiconductor material, the aluminum-silicon nitride material provides a superior passivation in comparison with a silicon nitride material.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: April 5, 2016
    Assignee: CORNELL UNIVERSITY
    Inventors: James R. Shealy, Richard Brown
  • Patent number: 9281388
    Abstract: There are disclosed herein various implementations of composite semiconductor devices. In one implementation, such a composite semiconductor device includes a semiconductor on insulator (SOI) substrate including a diode and an insulator layer. The composite semiconductor device also includes a transition body formed over the diode, and a transistor formed over the transition body. The diode is connected across the transistor using through-semiconductor vias, external electrical connectors, or a combination of the two.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: March 8, 2016
    Assignee: Infineon Technologies Americas Corp.
    Inventor: Michael A. Briere
  • Patent number: 9245738
    Abstract: According to example embodiments, a high electron mobility transistor (HEMT) includes a channel layer; a channel supply layer on the channel layer; a source electrode and a drain electrode spaced apart from each other on one of the channel layer and the channel supply layer; a gate electrode on a part of the channel supply layer between the source electrode and the drain electrode; a first depletion-forming layer between the gate electrode and the channel supply layer; and a at least one second depletion-forming layer on the channel supply layer between the gate electrode and the drain electrode. The at least one second depletion-forming layer is electrically connected to the source electrode.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: January 26, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-chul Jeon, Jong-seob Kim, Ki-yeol Park, Young-hwan Park, Jai-kwang Shin, Jae-joon Oh, Hyuk-soon Choi, In-jun Hwang
  • Patent number: 9184243
    Abstract: There are disclosed herein various implementations of a monolithically integrated component. In one exemplary implementation, such a monolithically integrated component includes an enhancement mode group IV transistor and two or more depletion mode III-Nitride transistors. The enhancement mode group IV transistor may be implemented as a group IV insulated gate bipolar transistor (group IV IGBT). One or more of the III-Nitride transistor(s) may be situated over a body layer of the group IV IGBT, or the III-Nitride transistor(s) may be situated over a collector layer of the IGBT.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: November 10, 2015
    Assignee: Infineon Technologies Americas Corp.
    Inventor: Michael A. Briere
  • Patent number: 9142550
    Abstract: An embodiment of a cascaded diode having a breakdown voltage exceeding 300V includes an HEMT and a Si Schottky diode. The HEMT includes a gate, a drain, a source, and a two-dimensional electron gas channel region connecting the source and the drain and controlled by the gate. The HEMT has a breakdown voltage exceeding 300V. The Si Schottky diode is monolithically integrated with the HEMT. The Si Schottky diode includes a cathode connected to the source of the HEMT and an anode connected to the gate of the HEMT. The Si Schottky diode has a breakdown voltage less than 300V and a forward voltage less than or equal to 0.4V. The anode of the Si Schottky diode forms the anode of the cascaded diode and the drain of the HEMT forms the cathode of the cascaded diode.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: September 22, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Gerhard Prechtl, Clemens Ostermaier, Oliver Häberlen
  • Patent number: 9136401
    Abstract: A compound semiconductor device includes a substrate, a p-type first semiconductor layer over the substrate and contains antimony, a p-type second semiconductor layer over the first semiconductor layer and contains antimony, an n-type third semiconductor layer over the second semiconductor layer, a fourth semiconductor layer between the first semiconductor layer and the second semiconductor layer, the fourth semiconductor layer containing phosphorus and having a thickness in which electrons tunnel between the first semiconductor layer and the second semiconductor layer, a first electrode in ohmic contact with the first semiconductor layer, and a second electrode in ohmic contact with the third semiconductor layer. The first semiconductor layer is made from a material whose contact resistance with the first electrode is lower than contact resistance of the second semiconductor layer.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: September 15, 2015
    Assignee: FUJITSU LIMITED
    Inventor: Tsuyoshi Takahashi
  • Patent number: 9105769
    Abstract: A method for fabricating a photovoltaic device includes forming a first contact on a crystalline substrate, by epitaxially growing a first doped layer having a doping concentration of 1019 cm?3 or greater, a dislocation density of 105 cm?2 or smaller, a hydrogen content of 0.1 atomic percent or smaller, and a thickness configured to reduce Auger recombination in the epitaxially grown doped layer. A first passivation layer is formed on the first doped layer. A second contact is formed on the crystalline substrate on a side opposite the first contact by epitaxially growing a second doped layer having a doping concentration of 1019 cm?3 or greater, a dislocation density of 105 cm?2 or smaller, a hydrogen content of 0.1 atomic percent or smaller and a thickness configured to reduce Auger recombination in the second epitaxially grown doped layer. A second passivation layer is formed on the second doped layer.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: August 11, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin K. Chan, Bahman Hekmatshoartabari, Tak H. Ning
  • Patent number: 9041067
    Abstract: There are disclosed herein various implementations of an integrated half-bridge circuit with low side and high side composite switches. In one exemplary implementation, such an integrated half-bridge circuit includes a III-N body including first and second III-N field-effect transistors (FETs) monolithically integrated with and situated over a first group IV FET. The integrated half-bridge circuit also includes a second group IV FET stacked over the III-N body. The first group IV FET is cascoded with the first III-N FET to provide one of the low side and the high side composite switches, and the second group IV FET is cascoded with the second III-N FET to provide the other of the low side and the high side composite switches.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: May 26, 2015
    Assignee: International Rectifier Corporation
    Inventor: Michael A. Briere
  • Patent number: 9041066
    Abstract: A transistor device includes a compound semiconductor body, a normally-on high electron mobility field effect transistor (HEMT) formed in the compound semiconductor body and a protection device monolithically integrated in the same compound semiconductor body as the normally-on HEMT. The normally-on HEMT has a source, a drain, a gate, and a threshold voltage. The protection device has a source and a drain each shared with the normally-on HEMT, a gate and a positive threshold voltage that is less than a difference of the threshold voltage of the normally-on HEMT and a gate voltage used to turn off the normally-on HEMT. The protection device is operable to conduct current in a reverse direction when the normally-on HEMT is switched off. A transistor device including a normally-off HEMT and a monolithically integrated protection device is also provided.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: May 26, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Walter Rieger, Oliver Häberlen
  • Publication number: 20150129929
    Abstract: A semiconductor device is provided that includes a composite semiconductor body including a high voltage depletion-mode transistor and a low voltage enhancement-mode transistor. The high voltage depletion-mode transistor is stacked on the low voltage enhancement-mode transistor so that an interface is formed between the high voltage depletion-mode transistor and the low voltage enhancement-mode transistor. The low voltage enhancement-mode transistor includes a current path coupled in series with a current path of the high voltage depletion-mode transistor, and a control electrode is arranged at the interface.
    Type: Application
    Filed: November 8, 2013
    Publication date: May 14, 2015
    Inventor: Franz Hirler
  • Patent number: 9012958
    Abstract: A semiconductor device of the invention includes an n-GaN layer provided on a substrate, a channel layer provided in contact with the upper surface of the n-GaN layer, an electron supply layer which is provided on the channel layer, and a gate electrode, a source electrode, and a drain electrode which are provided on the electron supply layer. The gate electrode is in contact with an underlying layer made from a nitride semiconductor. The semiconductor device has a ratio defined by the equation L/d1?7, where L is the width of the gate electrode in contact with the underlying layer in a direction between the source electrode and drain electrode; and d1 is the distance between a surface of the n-type gallium nitride layer and a boundary between the gate electrode and the underlying layer.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: April 21, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Kazutaka Inoue
  • Patent number: 9012959
    Abstract: A semiconductor device includes: a semiconductor substrate having an upper surface and a lower surface; a field effect transistor having a semiconductor layer on the upper surface of the semiconductor substrate, a gate electrode, a drain electrode, and a source electrode; a P-type diffusion region in the semiconductor substrate and extending to the upper surface of the semiconductor substrate; a first N-type diffusion region in the semiconductor substrate and extending t the upper surface of the semiconductor substrate; a first connection electrode connecting the P-type diffusion region to a grounding point; and a second connection electrode connecting the first N-type diffusion region to the gate electrode or the drain electrode. The P-type diffusion region and the first N-type diffusion region constitute a bidirectional lateral diode.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: April 21, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventor: Koichi Fujita
  • Patent number: 8987833
    Abstract: In one implementation, a stacked composite device comprises a group IV lateral transistor and a group III-V transistor stacked over the group IV lateral transistor. A drain of the group IV lateral transistor is in contact with a source of the group III-V transistor, a source of the group IV lateral transistor is coupled to a gate of the group III-V transistor to provide a composite source on a top side of the stacked composite device, and a drain of the group III-V transistor provides a composite drain on the top side of the stacked composite device. A gate of the group IV lateral transistor provides a composite gate on the top side of the stacked composite device, and a substrate of the group IV lateral transistor is on a bottom side of the stacked composite device.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: March 24, 2015
    Assignee: International Rectifier Corporation
    Inventors: Tim McDonald, Michael A. Briere
  • Publication number: 20150054036
    Abstract: A device includes a semiconductor die. The semiconductor die includes a plurality of semiconductor layers disposed on a GaAs substrate, including a first semiconductor layer having a first band-gap and a second semiconductor layer having a second band-gap. The semiconductor die further includes a contact layer disposed epitaxially upon the first semiconductor layer. The contact layer has a thickness that is less than a critical thickness. The second semiconductor layer is epitaxially disposed upon the contact layer. The contact layer has a third band-gap that is less than the first band-gap and the second band-gap. The semiconductor die further includes a conductive layer disposed upon the contact layer to form an ohmic contact. The conductive layer comprises one or more metal layers compatible with silicon processing techniques.
    Type: Application
    Filed: August 19, 2014
    Publication date: February 26, 2015
    Inventors: Yuefei Yang, Shing-Kuo Wang, Liping D. Hou
  • Patent number: 8963209
    Abstract: A circuit includes input drain, source and gate nodes. The circuit also includes a group III nitride enhancement-mode HFET having a source, drain and gate and a voltage shifter having a first terminal connected to the gate of the enhancement mode HFET at a common junction. The circuit also includes a load resistive element connected to the common junction. The drain of the enhancement-mode HFET serves as the input drain node, the source of the enhancement-mode HFET serves as the input source node and a second terminal of the voltage shifter serves as the input gate node.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: February 24, 2015
    Assignee: Power Integrations, Inc.
    Inventors: Xiaobin Xin, Milan Pophristic, Michael Shur
  • Patent number: 8957737
    Abstract: The various embodiments of the present invention provide improved methods and circuits for generating millimeter-wave oscillations. Generating millimeter-wave oscillations may involve providing a semiconductor device comprising at least two terminals and a polar heterojunction formed from two semiconductor materials. A voltage bias may be applied to at least two terminals of the device in which the voltage enhances a two-dimensional electron gas (2DEG) layer at the polar heterojunction and produces a sharply-peaked but spatially-localized electric field within the 2DEG with a large longitudinal component, wherein the longitudinal component of the electric field serves as a nucleation site for a plurality of propagating dipole domains observable as a plurality of self-sustaining millimeter-wave oscillations.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: February 17, 2015
    Assignee: Georgia Tech Research Corporation
    Inventors: Paul Douglas Yoder, Sriraaman Sridharan
  • Patent number: 8957454
    Abstract: There are disclosed herein various implementations of semiconductor structures including III-Nitride interlayer modules. One exemplary implementation comprises a substrate and a first transition body over the substrate. The first transition body has a first lattice parameter at a first surface and a second lattice parameter at a second surface opposite the first surface. The exemplary implementation further comprises a second transition body, such as a transition module, having a smaller lattice parameter at a lower surface overlying the second surface of the first transition body and a larger lattice parameter at an upper surface of the second transition body, as well as a III-Nitride semiconductor layer over the second transition body. The second transition body may consist of two or more transition modules, and each transition module may include two or more interlayers. The first and second transition bodies reduce strain for the semiconductor structure.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: February 17, 2015
    Assignee: International Rectifier Corporation
    Inventor: Michael A. Briere
  • Patent number: 8946779
    Abstract: A semiconductor device includes a substrate comprising a heterostructure configured to support formation of a channel during operation, first and second dielectric layers supported by the substrate, the second dielectric layer being disposed between the first dielectric layer and the substrate, a gate supported by the substrate, disposed in a first opening in the first dielectric layer, and to which a bias voltage is applied during operation to control current flow through the channel, the second dielectric layer being disposed between the gate and the substrate, and an electrode supported by the substrate, disposed in a second opening in the first and second dielectric layers, and configured to establish a Schottky junction with the substrate.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: February 3, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Bruce M. Green, James A. Teplik
  • Publication number: 20150028391
    Abstract: A compound semiconductor device includes a substrate, a p-type first semiconductor layer over the substrate and contains antimony, a p-type second semiconductor layer over the first semiconductor layer and contains antimony, an n-type third semiconductor layer over the second semiconductor layer, a fourth semiconductor layer between the first semiconductor layer and the second semiconductor layer, the fourth semiconductor layer containing phosphorus and having a thickness in which electrons tunnel between the first semiconductor layer and the second semiconductor layer, a first electrode in ohmic contact with the first semiconductor layer, and a second electrode in ohmic contact with the third semiconductor layer. The first semiconductor layer is made from a material whose contact resistance with the first electrode is lower than contact resistance of the second semiconductor layer.
    Type: Application
    Filed: June 23, 2014
    Publication date: January 29, 2015
    Inventor: Tsuyoshi Takahashi
  • Patent number: 8933486
    Abstract: A transistor with source and drain electrodes formed in contact with an active region and a gate between the source and drain electrodes and in contact with the active region. A first spacer layer is on at least part of the active region surface between the gate and drain electrodes and between the gate and source electrodes. The gate comprises a generally t-shaped top portion that extends toward the source and drain electrodes. A field plate is on the spacer layer and under the overhang of at least one section of the gate top portion. The field plate is at least partially covered by a second spacer layer that is on at least part of the first active layer surface and between the gate and drain and between the gate and source. At least one conductive path electrically connects the field plate to the source electrode or the gate.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: January 13, 2015
    Assignee: Cree, Inc.
    Inventor: Yifeng Wu
  • Publication number: 20140374801
    Abstract: A semiconductor device according to one embodiment is provided with a first metal substrate, a second metal substrate separated from the first metal substrate, a normally-off transistor of a silicon semiconductor provided on the first metal substrate, and a normally-on transistor of a nitride semiconductor provided on the second metal substrate.
    Type: Application
    Filed: March 12, 2014
    Publication date: December 25, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Kentaro IKEDA
  • Patent number: 8916909
    Abstract: A semiconductor device is disclosed. In one embodiment, the semiconductor device includes two different semiconductor materials. The two semiconductor materials are arranged adjacent one another in a common plane.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: December 23, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Andreas Meiser
  • Publication number: 20140367700
    Abstract: An embodiment of a cascaded diode having a breakdown voltage exceeding 300V includes an HEMT and a Si Schottky diode. The HEMT includes a gate, a drain, a source, and a two-dimensional electron gas channel region connecting the source and the drain and controlled by the gate. The HEMT has a breakdown voltage exceeding 300V. The Si Schottky diode is monolithically integrated with the HEMT. The Si Schottky diode includes a cathode connected to the source of the HEMT and an anode connected to the gate of the HEMT. The Si Schottky diode has a breakdown voltage less than 300V and a forward voltage less than or equal to 0.4V. The anode of the Si Schottky diode forms the anode of the cascaded diode and the drain of the HEMT forms the cathode of the cascaded diode.
    Type: Application
    Filed: June 18, 2013
    Publication date: December 18, 2014
    Inventors: Gerhard Prechtl, Clemens Ostermaier, Oliver Häberlen
  • Publication number: 20140367744
    Abstract: There are disclosed herein various implementations of a monolithic vertically integrated composite device. Such a composite device may include one or more group IV device fabricated in a group IV semiconductor body formed over a first side of a double sided substrate, and one or more group III-V device fabricated in a group III-V semiconductor body formed over a second side of the double sided substrate opposite the first side. In one implementation, the one or more group IV device may be a PN junction diode or a Schottky diode. In another implementation, the one or more group IV device may be a field-effect transistor (PET). In yet another implementation, such a composite device monolithically integrates one or more group III-V device and a group IV integrated circuit (IC). The one or more group III-V device and one or more group IV device and/or IC may be electrically coupled using one or more of a substrate via and a through-wafer via.
    Type: Application
    Filed: August 29, 2014
    Publication date: December 18, 2014
    Inventor: Michael A. Briere
  • Patent number: 8912573
    Abstract: A semiconductor structure with a MISFET and a HEMT region includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A third III-V compound layer is disposed on the second III-V compound layer is different from the second III-V compound layer in composition. A source feature and a drain feature are disposed in each of the MISFET and HEMT regions on the third III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A gate dielectric layer is disposed under the gate electrode in the MISFET region but above the top surface of the third III-V compound layer.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: December 16, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Yen Chou, Sheng-De Liu, Fu-Chih Yang, Shih-Chang Liu, Chia-Shiung Tsai
  • Patent number: 8907377
    Abstract: A higher electron mobility transistor (HEMT) and a method of manufacturing the same are disclosed. According to example embodiments, the HEMT may include a channel supply layer on a channel layer, a source electrode and a drain electrode that are on at least one of the channel layer and the channel supply layer, a gate electrode between the source electrode and the drain electrode, and a source pad and a drain pad. The source pad and a drain pad electrically contact the source electrode and the drain electrode, respectively. At least a portion of at least one of the source pad and the drain pad extends into a corresponding one of the source electrode and drain electrode that the at least one of the source pad and the drain pad is in electrical contact therewith.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: December 9, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-chul Jeon, Ki-yeol Park, Young-hwan Park, Jai-kwang Shin, Jae-joon Oh, Hyuk-soon Choi, Jong-bong Ha
  • Patent number: 8907378
    Abstract: A device includes a source and a drain for transmitting and receiving an electronic charge. The device also includes a first stack and a second stack for providing at least part of a conduction path between the source and the drain, wherein the first stack includes a first gallium nitride (GaN) layer of a first polarity, and the second stack includes a second gallium nitride (GaN) layer of the second polarity, and wherein the first polarity is different from the second polarity. At least one gate operatively connected to at least the first stack for controlling a conduction of the electronic charge, such that, during an operation of the device, the conduction path includes a first two-dimensional electron gas (2DEG) channel formed in the first GaN layer and a second 2DEG channel formed in the second GaN layer.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 9, 2014
    Assignee: Mitsubishi Electric Research Laboratories, Inc.
    Inventors: Koon Hoo Teo, Peijie Feng, Rui Ma
  • Publication number: 20140353724
    Abstract: A semiconductor device includes: a semiconductor substrate having an upper surface and a lower surface; a field effect transistor having a semiconductor layer on the upper surface of the semiconductor substrate, a gate electrode, a drain electrode, and a source electrode; a P-type diffusion region in the semiconductor substrate and extending to the upper surface of the semiconductor substrate; a first N-type diffusion region in the semiconductor substrate and extending t the upper surface of the semiconductor substrate; a first connection electrode connecting the P-type diffusion region to a grounding point; and a second connection electrode connecting the first N-type diffusion region to the gate electrode or the drain electrode. The P-type diffusion region and the first N-type diffusion region constitute a bidirectional lateral diode.
    Type: Application
    Filed: March 6, 2014
    Publication date: December 4, 2014
    Applicant: Mitsubishi Electric Corporation
    Inventor: Koichi Fujita
  • Publication number: 20140346570
    Abstract: A semiconductor device having high breakdown withstand voltage includes a first element which is a normally-on type transistor made of nitride compound semiconductor, a second element which is connected to the first element in series and is a transistor having withstand voltage between a source and a drain lower than withstand voltage of the first element, a first diode which is connected between a gate of the first element or a gate of the second element and a drain of the first element so that a cathode of the first diode is connected at the drain's side and has predetermined avalanche withstand voltage, and a first resistance connected to the gate to which the first diode is connected. The avalanche withstand voltage of the first diode is lower than breakdown voltage of the first element.
    Type: Application
    Filed: September 11, 2013
    Publication date: November 27, 2014
    Applicant: Advanced Power Device Research Association
    Inventor: Katsunori UENO
  • Publication number: 20140346569
    Abstract: A semiconductor die includes a III-nitride semiconductor substrate, a power HEMT (high-electron-mobility transistor) disposed in the III-nitride semiconductor substrate, and a first gate driver HEMT monolithically integrated with the power HEMT in the III-nitride semiconductor substrate. The power HEMT and the first gate driver HEMT each have a gate, a source and a drain. The first gate driver HEMT logically forms part of a driver, and is electrically connected to the gate of the power HEMT. The first gate driver HEMT is operable to turn the power HEMT off or on responsive to an externally-generated control signal received from the driver or other device. Additional embodiments of semiconductor dies and methods of manufacturing are also described.
    Type: Application
    Filed: May 23, 2013
    Publication date: November 27, 2014
    Inventors: Martin Vielemeyer, Walter Rieger, Martin Pölzl, Gerhard Nöbauer
  • Patent number: 8896026
    Abstract: Provided is a nitride semiconductor device including: a nitride semiconductor layer over a substrate wherein the nitride semiconductor has a two-dimensional electron gas (2DEG) channel inside; a drain electrode in ohmic contact with the nitride semiconductor layer; a source electrode in Schottky contact with the nitride semiconductor layer wherein the source electrode is spaced apart from the drain electrode; a dielectric layer formed on the nitride semiconductor layer between the drain electrode and the source electrode and on at least a portion of the source electrode; and a gate electrode disposed on the dielectric layer to be spaced apart from the drain electrode, wherein a portion of the gate electrode is formed over a drain-side edge portion of the source electrode with the dielectric layer interposed therebetween, and a manufacturing method thereof.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: November 25, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Woo Chul Jeon, Ki Yeol Park, Young Hwan Park
  • Patent number: 8896028
    Abstract: A semiconductor device includes: an epitaxial substrate formed by stacking a plurality of kinds of semiconductors over one semiconductor substrate by epitaxial growth; a field effect transistor of a first conductivity type formed in a first region; a field effect transistor of a second conductivity type formed in a second region; and a protective element formed in a third region. The protective element includes: a first stacking structure formed by etching the epitaxial substrate by vertical etching that proceeds in a stacking thickness direction; and a second stacking structure formed by etching the epitaxial substrate by vertical etching that proceeds in a stacking thickness direction. The protective element has two PN junctions on a current path formed between an upper end of the first stacking structure and an upper end of the second stacking structure via a base part of the first stacking structure and the second stacking structure.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: November 25, 2014
    Assignee: Sony Corporation
    Inventors: Masahiro Mitsunaga, Shinichi Tamari, Yuji Ibusuki
  • Publication number: 20140327049
    Abstract: Gallium nitride (GaN) based semiconductor devices and methods of manufacturing the same. The GaN-based semiconductor device may include a heterostructure field effect transistor (HFET) or a Schottky diode, arranged on a heat dissipation substrate. The HFET device may include a GaN-based multi-layer having a recess region; a gate arranged in the recess region; and a source and a drain that are arranged on portions of the GaN-based multi-layer at two opposite sides of the gate (or the recess region). The gate, the source, and the drain may be attached to the heat dissipation substrate. The recess region may have a double recess structure. While such a GaN-based semiconductor device is being manufactured, a wafer bonding process and a laser lift-off process may be used.
    Type: Application
    Filed: July 22, 2014
    Publication date: November 6, 2014
    Inventors: Jae-Hoon LEE, Ki-Se KIM
  • Publication number: 20140327048
    Abstract: A multi-gate Schottky depletion-mode field effect transistor (FET), at least one diode and two resistors comprise a compact electrostatic discharge (ESD) protection structure. This ESD protection structure can be laid out in a smaller area than typical multiple diode ESD devices. The multi-gate FET may comprise various types of high-electron-mobility transistor (HEMT) devices, e.g., (pseudomorphic) pHEMT, (metamorphic) mHEMT, induced HEMT. The multiple gates of the Schottky field effect device are used to form an ESD trigger and charge draining paths for protection of circuits following the ESD protection device. Both single and dual polarity ESD protection devices may be provided on an integrated circuit die for protection of input-output circuits thereof.
    Type: Application
    Filed: May 1, 2014
    Publication date: November 6, 2014
    Inventors: Pei-Ming Daniel Chow, Yon-Lin Kok, Jing Zhu, Steven Schell
  • Patent number: 8872235
    Abstract: An embodiment of a transistor device includes a compound semiconductor material on a semiconductor carrier and a source region and a drain region spaced apart from each other in the compound semiconductor material with a channel region interposed between the source and drain regions. A Schottky diode is integrated with the semiconductor carrier, and contacts extend from the source and drain regions through the compound semiconductor material. The contacts are in electrical contact with the Schottky diode so that the Schottky diode is connected in parallel between the source and drain regions. In another embodiment, the integrated Schottky diode is formed by a region of doped amorphous silicon or doped polycrystalline silicon disposed in a trench structure on the drain side of the device.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: October 28, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Gerhard Prechtl, Clemens Ostermaier, Oliver Häberlen
  • Patent number: 8872231
    Abstract: A semiconductor wafer includes a first semiconductor, and a second semiconductor formed directly or indirectly on the first semiconductor. The second semiconductor contains a first impurity atom exhibiting p-type or n-type conductivity, and a second impurity atom selected such that the Fermi level of the second semiconductor containing both the first and second impurity atoms is closer to the Fermi level of the second semiconductor containing neither the first impurity atom nor the second impurity atom, than the Fermi level of the second semiconductor containing the first impurity atom is. For example, the majority carrier of the second semiconductor is an electron, and the Fermi level of the second semiconductor containing the first and second impurity atoms is lower than the Fermi level of the second semiconductor containing the first impurity atom.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: October 28, 2014
    Assignee: Sumitomo Chemical Company, Limited
    Inventor: Osamu Ichikawa
  • Patent number: 8866193
    Abstract: According to one disclosed embodiment, a monolithic vertically integrated composite device comprises a double sided semiconductor substrate having first and second sides, a group IV semiconductor layer formed over the first side and comprising at least one group IV semiconductor device, and a group III-V semiconductor body formed over the second side and comprising at least one group III-V semiconductor device electrically coupled to the at least one group IV semiconductor device. The composite device may further comprise a substrate via and/or a through-wafer via providing electric coupling. In one embodiment, the group IV semiconductor layer may comprise an epitaxial silicon layer, and the at least one group IV semiconductor device may be a combined FET and Schottky diode (FETKY) fabricated on the epitaxial silicon layer. In one embodiment, the at least one group semiconductor device may be a III-nitride high electron mobility transistor (HEMT).
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: October 21, 2014
    Assignee: International Rectifier Corporation
    Inventor: Michael A. Briere
  • Patent number: 8866191
    Abstract: A transistor in which the electric field is reduced in critical areas using field plates, permitting the electric field to be more uniformly distributed along the component, is provided, wherein the electric field in the active region is smoothed and field peaks are reduced. The semiconductor component has a substrate with an active layer structure, a source contact and a drain contact located on said active layer structure. The source contact and the drain contact are mutually spaced and at least one part of a gate contact is provided on the active layer structure in the region between the source contact and the drain contact, a gate field plate being electrically connected to the gate contact. In addition, at least two separate field plates are placed directly on the active layer structure or directly on a passivation layer.
    Type: Grant
    Filed: February 21, 2008
    Date of Patent: October 21, 2014
    Assignee: Forschungsverbund Berlin E.V.
    Inventors: Eldat Bahat-Treidel, Victor Sidorov, Joachim Wuerfl
  • Patent number: 8860091
    Abstract: A device and a method of making said wherein the device wherein the device has a group III-nitride buffer deposited on a substrate; and a group III-nitride heterostructure disposed on a surface of the group III-nitride buffer, wherein the group III-nitride heterostructure has a group III-nitride channel and a group III-nitride barrier layer disposed on a surface of the group III-nitride channel, the group III-nitride barrier layer including Al as one of its constituent group III elements, the Al having a mole fraction which varies at least throughout a portion of said group III-nitride barrier layer.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: October 14, 2014
    Assignee: HRL Laboratories, LLC
    Inventors: David F. Brown, Miroslav Micovic
  • Patent number: 8860090
    Abstract: A nitride semiconductor device includes a first semiconductor layer, a second semiconductor layer, a conductive substrate, a first electrode, a second electrode, and a control electrode. The second semiconductor layer is directly bonded to the first semiconductor layer. The conductive substrate is provided on and electrically connected to the first semiconductor layer. The first electrode and the second electrode are provided on and electrically connected to a surface of the second semiconductor layer on a side opposite to the first semiconductor layer. The control electrode is provided on the surface of the second semiconductor layer between the first electrode and the second electrode. The first electrode is electrically connected to a drain electrode of a MOSFET formed of Si. The control electrode is electrically connected to a source electrode of the MOSFET. The conductive substrate is electrically connected to a gate electrode of the MOSFET.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: October 14, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Wataru Saito, Yasunobu Saito, Hidetoshi Fujimoto, Akira Yoshioka, Tetsuya Ohno
  • Patent number: 8860120
    Abstract: Consistent with various example embodiments, a field-controlling electrode applies a negative bias, relative to a source/drain electrode, increase voltage breakdown. The field-controlling electrode is located over a channel region and between source and drain electrodes, and adjacent a gate electrode. The field electrode shapes a field in a portion of the channel region laterally between the gate electrode and one of the source/drain electrodes, in response to a negative bias applied thereto.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: October 14, 2014
    Assignee: NXP, B.V.
    Inventors: Saad Kheder Murad, Ronaldus Johannus Martinus van Boxtel