Abstract: A transistor device includes a field plate that extends from a source runner layer and/or a source contact layer. The field plate can be coplanar with and/or below a gate runner layer. The gate runner layer is routed away from a region directly above the gate metal layer by a gate bridge, such that the field plate can extend directly above the gate metal layer without being interfered by the gate runner layer. Coplanar with the source runner layer or the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. By vertically overlapping the metal gate layer and the field plate, the disclosed HEMT device may achieve significant size efficiency without additional routings.

Abstract: An HEMT device, comprising: a semiconductor body including a heterojunction structure; a dielectric layer on the semiconductor body; a gate electrode; a drain electrode, facing a first side of the gate electrode; and a source electrode, facing a second side opposite to the first side of the gate electrode; an auxiliary channel layer, which extends over the heterojunction structure between the gate electrode and the drain electrode, in electrical contact with the drain electrode and at a distance from the gate electrode, and forming an additional conductive path for charge carriers that flow between the source electrode and the drain electrode.

Abstract: A semiconductor structure for improving the thermal stability and Schottky behavior by engineering the stress in a III-nitride semiconductor, comprising a III-nitride semiconductor and a gate metal layer. The III-nitride semiconductor has a top surface on which a conductive area and a non-conductive area are defined. The gate metal layer is formed directly on the top surface of the III-nitride semiconductor and comprises a gate connection line and at least one gate contact extending from the gate connection line in a second direction perpendicular to the length of the gate connection line. The at least one gate contact forms a Schottky contact with the III-nitride semiconductor on the conductive area, and the gate connection line is in direct contact with the III-nitride semiconductor on the non-conductive area. The non-conductive area of the III-nitride semiconductor is at least partially covered by the gate connection line.

Abstract: A channel layer is grown over a substrate, and an active layer is grown over the channel layer, wherein the active layer has a band gap discontinuity with the channel layer. A dielectric layer is deposited over the active layer, and the dielectric layer is patterned to expose a portion of the active layer. A metal diffusion barrier is formed over the exposed portion of the active layer, and a gate is deposited over the metal diffusion barrier.

Abstract: In some examples, a transistor comprises a gallium nitride (GaN) layer; a first GaN-based alloy layer having a top side and disposed on the GaN layer; a second GaN-based alloy layer disposed on the first GaN-based alloy layer, wherein the second GaN-based alloy layer covers a first portion of the top side; and a source contact structure, a drain contact structure, and a gate contact structure, wherein the source, drain, and gate contact structures are supported by the first GaN-based alloy layer.

Abstract: Methods for processing a semiconductor transistor are provided, where the semiconductor transistor includes a substrate, an epitaxial layer, and transistor components that are formed on the epitaxial layer. The method includes: removing a portion of the substrate that is disposed below a portion of the transistor components, to thereby expose a portion of a bottom surface of the epitaxial layer; forming an electrically insulating layer on the exposed portion of the bottom surface of the epitaxial layer; forming a via that extends from a bottom surface of the insulating layer to a bottom surface of one of the transistor components; depositing at least one metal layer on the bottom surface of the insulating layer, on a side wall of the via and on the bottom surface of one of the transistor components; and applying a solder paste to a bottom surface of the at least one metal layer.

Abstract: A gallium nitride based monolithic microwave integrated circuit includes a substrate, a channel layer on the substrate and a barrier layer on the channel layer. A recess is provided in a top surface of the barrier layer. First gate, source and drain electrodes are provided on the barrier layer opposite the channel layer, with a bottom surface of the first gate electrode in direct contact with the barrier layer. Second gate, source and drain electrodes are also provided on the barrier layer opposite the channel layer. A gate insulating layer is provided in the recess in the barrier layer, and the second gate electrode is on the gate insulating layer opposite the barrier layer and extending into the recess. The first gate, source and drain electrodes comprise the electrodes of a depletion mode transistor, and the second gate, source and drain electrodes comprise the electrodes of an enhancement mode transistor.

Abstract: A semiconductor epitaxial structure with reduced defects, including a substrate with a recess formed thereon, an island insulator on a bottom surface of the recess, spacers on sidewalls of the recess, a buffer layer in the recess and covering the island insulator, a channel layer in the recess and on the buffer layer, and a barrier layer in the recess and on the channel layer, wherein two-dimensional electron gas (2DEG) or two-dimensional hole gas (2DHG) is formed in the channel layer.

Abstract: Methods and structures includes providing a substrate, forming a prelayer over a substrate, forming a barrier layer over the prelayer, and forming a channel layer over the barrier layer. Forming the prelayer may include growing the prelayer at a graded temperature. Forming the barrier layer is such that the barrier layer may include GaAs or InGaAs. Forming the channel layer is such that the channel layer may include InAs or an Sb-based heterostructure. Thereby structures are formed.

Abstract: A manufacturing method of a semiconductor device includes the following steps. A substrate is provided. The substrate has a first side and a second side opposite to the first side. A first III-V compound layer is formed at the first side of the substrate. A drain trench and a contact trench are formed at the second side of the substrate. The drain trench extends from the second side of the substrate toward the first side of the substrate and penetrates the substrate. The contact trench extends from the second side of the substrate toward the first side of the substrate and penetrates the substrate. The drain trench and the contact trench are formed concurrently by the same process. A drain electrode is formed in the drain trench. A back contact structure is formed in the contact trench.

Abstract: An enhanced HFET, comprising a HFET device body.

Abstract: A gallium nitride transistor includes one or more P-type hole injection structures that are positioned between the gate and the drain. The P-type hole injection structures are configured to inject holes in the transistor channel to combine with trapped carriers (e.g., electrons) so the electrical conductivity of the channel is less susceptible to previous voltage potentials applied to the transistor.

Abstract: A semiconductor device includes a heterojunction semiconductor body including a first and second type III-V semiconductor layers with different bandgaps such that a first two-dimensional charge carrier gas forms at an interface between the two layers. The second type III-V semiconductor layer includes a thicker section and a thinner section. A first input-output electrode is on the thicker section and is in ohmic contact with the first two-dimensional charge carrier gas. A second input-output electrode is formed on the thinner section and is in ohmic contact with the first two-dimensional charge carrier gas. A gate structure is formed on the thinner section and is configured to control a conductive connection between the first and second input-output electrodes. The gate structure is laterally spaced apart from a transition between the thicker and thinner sections of the second type III-V semiconductor layer.

Abstract: An electronic device can include a HEMT. In an embodiment, a gate electrode, a drain electrode, and an access region including a first portion closer to the gate electrode and a second portion closer to the drain electrode. A lower dielectric film can overlie a portion of the access region, and an upper dielectric region can overlie another portion of the access region. In another embodiment, a dielectric film can have a relatively positive or negative charge and a varying thickness. In a further embodiment, the HEMT can include a gate electrode; a dielectric film overlying the gate electrode and defining openings to the gate electrode, wherein a portion of the dielectric film is disposed between the openings; and a gate interconnect extending into the openings of the dielectric film and contacting the gate electrode and the portion of the dielectric film.

Abstract: An electronic device can include a drain electrode of a high electron mobility transistor overlying a channel layer; a source electrode overlying the channel layer, wherein a lowermost portion of the source electrode overlies at least a portion of the channel layer; and a gate electrode of the high electron mobility transistor overlying the channel layer; and a current limiting control structure that controls current passing between the drain and source electrodes. The current limiting control structure can be disposed between the source and gate electrodes, the current limiting control structure can be coupled to the source electrode and the first high electron mobility transistor, and the current limiting control structure has a threshold voltage. The current limiting control structure can be a Schottky-gated HEMT or a MISHEMT.

Abstract: A monolithic integration of enhancement mode (E-mode) and depletion mode (D-mode) field effect transistors (FETs) comprises a compound semiconductor substrate overlaid by an epitaxial structure overlaid by source and drain electrodes. The epitaxial structure includes from bottom to top sequentially a buffer layer, a channel layer, a Schottky barrier layer, a first etch stop layer, and a first cap layer. The respective first gate metal layers of the D-mode and E-mode FET are in contact with the first etch stop layer. The D-mode and E-mode gate-sinking regions are beneath the respective first gate metal layers of the D-mode and E-mode gate electrode at least within the first etch stop layer. The first gate metal layer material of the D-mode is the same as that of the E-mode, where the first gate metal layer thickness of the E-mode is greater than that of the D-mode.

Abstract: A semiconductor device includes a silicon pillar disposed on a substrate, the silicon pillar has a sidewall. A group III-N semiconductor material is disposed on the sidewall of the silicon pillar. The group III-N semiconductor material has a sidewall. A doped source structure and a doped drain structure are disposed on the group III-N semiconductor material. A polarization charge inducing layer is disposed on the sidewall of the group III-N semiconductor material between the doped drain structure and the doped source structure. A plurality of portions of gate dielectric layer is disposed on the sidewalls of the group III-N semiconductor material and between the polarization charge inducing layer. A plurality of resistive gate electrodes separated by an interlayer dielectric layer are disposal adjacent to each of the plurality of portions of the gate dielectric layer. A source metal layer is disposed below and in contact with the doped source structure.

Abstract: A device includes a semiconductor substrate of a first conductivity type, and a deep well region in the semiconductor substrate, wherein the deep well region is of a second conductivity type opposite to the first conductivity type. The device further includes a well region of the first conductivity type over the deep well region. The semiconductor substrate has a top portion overlying the well region, and a bottom portion underlying the deep well region, wherein the top portion and the bottom portion are of the first conductivity type, and have a high resistivity. A gate dielectric is over the semiconductor substrate. A gate electrode is over the gate dielectric. A source region and a drain region extend into the top portion of the semiconductor substrate. The source region, the drain region, the gate dielectric, and the gate electrode form a Radio Frequency (RF) switch.

Abstract: A semiconductor device includes: a back barrier layer containing AlXGa(1-X)N (0<X?1); an electron transit layer containing AlaInbGa(1-a-b)N (0?a+b?1) and formed on the back barrier layer; a top barrier layer containing AlYGa(1-Y)N (0<Y?1) and formed on the electron transit layer; an electron supply layer containing AlZGa(1-Z)N (0<Z?1) and formed on the top barrier layer, the electron supply layer having an opening to expose the top barrier layer; a two-dimensional electron gas region formed in an area of a surface layer portion of the electron transit layer, the area opposing the electron supply layer with the top barrier layer interposed between the electron supply layer and the area; a gate insulating layer formed in the opening of the electron supply layer; and a gate electrode layer formed on the gate insulating layer and opposing the electron transit layer with the gate insulating layer interposed therebetween.

Abstract: A semiconductor device includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a source/drain pair, a fluorinated region, and a gate. The channel layer is disposed over the substrate. The barrier layer is disposed over the channel layer. The compound semiconductor layer is disposed over the barrier layer. The source/drain pair is disposed over the substrate, wherein the source and the drain are located on opposite sides of the compound semiconductor layer. The fluorinated region is disposed in the compound semiconductor layer. The gate is disposed on the compound semiconductor layer.

Abstract: There is provided a nitride semiconductor device, including: a Si substrate including a front surface and a back surface; a buffer layer formed over the Si substrate; a first nitride semiconductor layer formed over the buffer layer; a second nitride semiconductor layer formed over the first nitride semiconductor layer; a gate electrode disposed over the second nitride semiconductor layer; a source electrode and a drain electrode electrically connected to the second nitride semiconductor layer, and disposed over the second nitride semiconductor layer to be spaced apart from the gate electrode that is interposed between the source electrode and the drain electrode; a back surface electrode pad formed over the back surface of the Si substrate; and a conductive path formed in the Si substrate, the buffer layer, the first nitride semiconductor layer, and the second nitride semiconductor layer.

Abstract: A nitride semiconductor layer (2,3,4) is provided on a Si substrate (1). A gate electrode (5), a source electrode (6) and a drain electrode (7) are provided on the nitride semiconductor layer (2,3,4). A P-type conductive layer (11) in contact with the nitride semiconductor layer (2,3,4) is provided on the Si substrate (1) below the drain electrode (7).

Abstract: A high electron mobility transistor (HEMT) made of primarily nitride semiconductor materials is disclosed. The HEMT, which is a type of reverse HEMT, includes, on a C-polar surface of a SiC substrate, a barrier layer and a channel layer each having N-polar surfaces in respective top surfaces thereof. The HEMT further includes an intermediate layer highly doped with impurities and a Schottky barrier layer on the channel layer. The Schottky barrier layer and a portion of the intermediate layer are removed in portions beneath non-rectifying electrodes but a gate electrode is provided on the Schottky barrier layer.

Abstract: A high electron mobility transistor (HEMT) includes a first compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A salicide source feature and a salicide drain feature are in contact with the first III-V compound layer through the second III-V compound layer. A gate electrode is disposed over a portion of the second compound layer between the salicide source feature and the salicide drain feature.

Abstract: A semiconductor device includes a semiconductor substrate composed of a compound semiconductor, a first semiconductor region disposed over a surface of the semiconductor substrate so as to extend upward from the surface of the semiconductor substrate, the first semiconductor region including a semiconductor nanowire composed of a compound semiconductor, a second semiconductor region disposed over the periphery of a side surface of the first semiconductor region, a gate electrode disposed over the periphery of the second semiconductor region, a drain electrode coupled to one end of the first semiconductor region, and a source electrode coupled to another end of the first semiconductor region, the first and second semiconductor regions being composed of different semiconductor materials.

Abstract: The present invention provides an integrated enhancement/depletion mode HEMT and a method for manufacturing the same, by which method an enhancement mode transistor and a depletion mode transistor can be integrated together, which is beneficial for increasing the application of gallium nitride HEMT devices and improving the characteristics of circuits, and lay a foundation for realizing monolithic integration of high-speed digital/analog mixed signal radio frequency circuits. At the same time, by using a regrowth technology of a barrier layer, electrons generated by impurities are made part of a conductive channel, thus the concentration of the two-dimensional electron gas is increased, and the conductive performance is improved while preventing excessive electrons from interfering with the devices.

Abstract: A semiconductor device according to an embodiment includes a first GaN-based semiconductor layer, a second GaN-based semiconductor layer provided on the first GaN-based semiconductor layer and having a wider band gap than the first GaN-based semiconductor layer, a source electrode electrically connected to the second GaN-based semiconductor layer, a drain electrode electrically connected to the second GaN-based semiconductor layer, a gate electrode provided between the source electrode and the drain electrode, and a passivation film provided on the second GaN-based semiconductor layer between the source electrode and the gate electrode and between the gate electrode and the drain electrode, the passivation film including a first insulating film and a second insulating film, the first insulating film including nitrogen, the first insulating film having a thickness equal to or greater than 0.2 nm and less than 2 nm, the second insulating film including oxygen and provided on the first insulating film.

Abstract: Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.

Abstract: A semiconductor device includes: a semiconductor substrate; a buffer layer provided on the semiconductor substrate; a GaN channel layer provided on the buffer layer; an AlGaN electron travel layer provided on the GaN channel layer; a GaN cap layer provided on the AlGaN electron travel layer, having a nitrogen polarity, and on which a plurality of recesses are formed; and a gate electrode, a source electrode and a drain electrode provided in each of the plurality of recesses.

Abstract: A heterojunction bipolar transistor includes a collector layer, a base layer, and an emitter layer that are stacked on a substrate. The collector layer includes a graded semiconductor layer in which an electron affinity increases from a side closer to the base layer toward a side farther from the base layer. An electron affinity of the base layer at an interface closer to the collector layer is equal to an electron affinity of the graded semiconductor layer at an interface closer to the base layer.

Abstract: A method for recovering carbon-face-polarized silicon carbide substrates, including: providing an epitaxial structure, the epitaxial structure includes a carbon-face-polarized silicon carbide substrate to be recovered, as well as a nitrogen-face-polarized gallium nitride buffer layer, a barrier layer and a nitrogen-face-polarized gallium nitride channel layer that are sequentially deposited on the silicon carbide substrate; removing the nitrogen-face-polarized gallium nitride buffer layer, the barrier layer and the nitrogen-face-polarized gallium nitride channel layer by wet etching; and cleaning and blowing dry the carbon-face-polarized silicon carbide substrate.

Abstract: The present invention discloses a group-III nitride semiconductor device, which comprises a substrate, a buffer layer, a semiconductor stack structure, and a passivation film. The buffer layer is disposed on the substrate. The semiconductor stack structure is disposed on the buffer layer and comprises a gate, a source, and a drain. In addition, a gate insulating layer is disposed between the gate and the semiconductor stack structure for forming a HEMT. The passivation film covers the HEMT and includes a plurality of openings corresponding to the gate, the source, and the drain, respectively. The material of the passivation film is silicon oxynitride.

Abstract: A lateral III-N device has a vertical gate module with III-N material orientated in an N-polar or a group-III polar orientation. A III-N material structure has a III-N buffer layer, a III-N barrier layer, and a III-N channel layer. A compositional difference between the III-N barrier layer and the III-N channel layer causes a 2DEG channel to be induced in the III-N channel layer. A p-type III-N body layer is disposed over the III-N channel layer in a source side access region but not over a drain side access region. A n-type III-N capping layer over the p-type III-N body layer. A source electrode that contacts the n-type III-N capping layer is electrically connected to the p-type III-N body layer and is electrically isolated from the 2DEG channel when the gate electrode is biased relative to the source electrode at a voltage that is below a threshold voltage.

Abstract: The invention relates to the group III-nitride semiconductor device and corresponding fabricating method. Specifically, a method to reduce RF dispersion in a group III-nitride high electron mobility transistor (HEMT), especially for reduced barrier thickness epi materials and scaled deices for higher frequency applications. Periodic n-type doping within barrier is used to screen surface state traps, which are responsible for the above-mentioned RF dispersion, without introducing additional gate leakage current path. Within the method, the barrier (typically AlGaN, AlInN) layer is periodically n-type doped with its composition (such as Al % within AlGaN) periodically modulated. The periodic structure is effective in both screening surface state traps and reducing the leakage current within the AlGaN/gate Schottky barrier.

Abstract: Provided is a manufacturing method of a semiconductor device including a vertical MOSFET having a planar gate. The manufacturing method of a semiconductor device includes forming a n-type gallium nitride layer on a gallium nitride monocrystalline substrate, and forming an impurity-implanted region that contains impurities at a uniform concentration in a direction parallel to a main surface of the gallium nitride monocrystalline substrate, by ion-implanting the impurities into the n-type gallium nitride layer, where the impurities include at least one type selected from among magnesium, beryllium, calcium and zinc. Here, at least part of the impurity-implanted region serves as a channel forming region of the vertical MOSFET.

Abstract: Fabricating high efficiency, high linearity N-polar gallium-nitride (GaN) transistors by selective area regrowth is disclosed. A demand for high efficiency components with highly linear performance characteristics for radio frequency (RF) systems has increased development of GaN transistors and, in particular, aluminum-gallium-nitride (AlGaN)/GaN high electron mobility transistor (HEMT) devices. A method of fabricating a high efficiency, high linearity N-polar HEMT device includes employing a selective area regrowth method for forming a HEMT structure on the Nitrogen-face (N-face) of a GaN buffer, a natural high composition AlGaN/AlN back barrier for carrier confinement, a thick undoped GaN layer on the access areas to eliminate surface dispersion, and a high access area width to channel width ratio for improved linearity. A problem of impurities on the GaN buffer surface prior to regrowth creating a leakage path is avoided by intentional silicon (Si) doping in the HEMT structure.

Abstract: In the present invention, a contact layer formed of a material having an electron concentration of less than 1×1022 cm?3 is directly provided on a surface of a semiconductor crystal having an n-type conductivity with a band gap of 1.2 eV or less at room temperature. Consequently, the wave function penetration from the contact layer side to the semiconductor surface side is reduced. As a result, the formation of the energy barrier height·?B due to the Fermi level pinning phenomenon is much suppressed. It is possible to achieve the contact with a lower resistivity and with high ohmic properties.

Abstract: An electronic device can include a semiconductor layer and a contact structure forming an ohmic contact with the layer. In an embodiment, the semiconductor layer can include a III-N material, and the contact structure includes a first phase and a second phase, wherein the first phase includes Al, the second phase includes a metal, and the first phase contacts the semiconductor layer. In another embodiment, the semiconductor layer can be a monocrystalline layer having a surface along a crystal plane. The contact structure can include a polycrystalline material including crystals having surfaces that contact the surface of the monocrystalline layer, wherein a lattice mismatch between the surface of the monocrystalline layer and the surfaces of the crystals is at most 20%.

Abstract: High-electron-mobility transistor (HEMT) devices are described in this patent application. In some implementations, the HEMT devices can include a back barrier hole injection structure. In some implementations, the HEMT devices include a conductive striped portion electrically coupled to a drain contact.

Abstract: A semiconductor device includes a transistor, a semiconductor layer, an active region and a conductive layer. The active region is in the semiconductor layer. The conductive layer is configured to maintain a channel in the active region when the transistor is triggered to be conducted.

Abstract: A semiconductor device includes a substrate, a channel layer, an active layer, and a gate electrode. The channel layer has a fin portion over the substrate. The active layer is over at least the fin portion of the channel layer. The active layer is configured to cause a two-dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer. The gate electrode is in contact with a sidewall of the fin portion of the channel layer.

Abstract: A Field Effect Transistor (FET) having a source, drain, and gate disposed laterally along a surface of a semiconductor and a field plate structure: having one end connected to the source; and having a second end disposed between the gate and the drain and separated from the drain by a gap. A dielectric structure is disposed over the semiconductor, having: a first portion disposed under the second end of the field plate structure; and, a second, thinner portion under the gap.

Abstract: An ohmic metal for GaN device comprises a diffusion barrier seed metal layer and a plurality of metal layers. The diffusion barrier seed metal layer is formed on an epitaxial structure layer. The diffusion barrier seed metal layer is made of Pt. The epitaxial structure layer is made of AlGaN or GaN. The plurality of metal layers is formed on the diffusion barrier seed metal layer. The plurality of metal layers comprises a first metal layer and a second metal layer. The first metal layer is formed on the diffusion barrier seed metal layer. The first metal layer is made of Ti. The second metal layer is formed on the first metal layer. The second metal layer is made of Al. By the diffusion barrier seed metal layer, so as to suppress the diffusion of the plurality of metal layers into the epitaxial structure layer.

Abstract: A transistor includes a substrate, a channel layer coupled to the substrate, a source electrode coupled to the channel layer, a drain electrode coupled to the channel layer, and a gate electrode coupled to the channel layer between the source electrode and the drain electrode. The gate electrode has a length dimension of less than 50 nanometers near the channel layer, and the channel layer includes at least a first GaN layer and a first graded AlGaN layer on the first GaN layer.

Abstract: A semiconductor device includes a conductive substrate, a channel forming layer, a first electrode, and a second electrode. The channel forming layer is located above the conductive substrate and includes at least one hetero-junction structure. The hetero-junction structure includes a first GaN-type semiconductor layer providing a drift region and a second GaN-type semiconductor layer having a bandgap energy greater than the first GaN-type semiconductor layer. A total fixed charge quantity of charges in the first GaN-type layer and the second GaN-type layer is from 0.5×1013 to 1.5×1013 cm?2. The charges in the first GaN-type layer and the second GaN-type layer include charges generated by the polarization in the first GaN-type layer. Accordingly, the semiconductor device capable of improving a break-down voltage and decreasing an on-resistance is obtained.

Abstract: HEMT having a drain field plate is provided. The drain field plate is formed in the area between the gate and drain of a HEMT. The drain field plate includes a metal pad that has a larger projection area than the drain pad. The drain field plate and semiconductor layer disposed beneath the drain field plate form a metal-semiconductor (M-S) Schottky structure. The capacitance of the M-S Schottky structure generates capacitance in the semiconductor area, which increases the breakdown voltage of the transistor components of the HEMT. A portion of the substrate under the active area may be removed to thereby increase the heat conductivity and reduce the junction temperature of the transistor components of the HEMT.

Abstract: A method of fabricating a semiconductor device structure includes: providing a substrate comprising a layer of compound semiconductor material; forming a seed layer of nano-crystalline diamond having a layer thickness in a range 5 to 50 nm on the layer of compound semiconductor material; and growing a layer of polycrystalline CVD diamond on the seed layer using a chemical vapour deposition (CVD) technique. An effective thermal boundary resistance (TBReff) at an interface between the layer of compound semiconductor material and the layer of polycrystalline CVD diamond material is no more than 50 m2K/GW.

Abstract: An antenna kit includes: main and auxiliary antenna units to be disposed respectively on first and second dielectric substrates; and two connecting units. The main antenna unit includes two main radiating modules which are symmetrical with respect to a first axis, and each of which includes a main feed point, a main radiating portion and an extending portion. The auxiliary antenna unit is symmetrical with respect to a second axis, and includes two auxiliary feed points, two auxiliary radiating portions and a connecting portion. Each connecting unit is capable of being assembled such that the main radiating portion of a respective main radiating module and a respective auxiliary radiating portion are connected via the assembled connecting unit.

Abstract: A field effect transistor (FET) includes a III-nitride channel layer, a III-nitride barrier layer on the channel layer, a first dielectric on the barrier layer, a first gate trench extending through the first dielectric, and partially or entirely through the barrier layer, a second dielectric on a bottom and walls of the first gate trench, a source electrode on a first side of the first gate trench, a drain electrode on a second side of the first gate trench opposite the first side, a first gate electrode on the second dielectric and filling the first gate trench, a third dielectric between the first gate trench and the drain electrode, a second gate trench extending through the third dielectric and laterally located between the first gate trench and the drain electrode, and a second gate electrode filling the second gate trench.

Abstract: A nitride semiconductor device includes an electron transit layer (103) that is formed of a nitride semiconductor, an electron supply layer (104) that is formed on the electron transit layer (103), that is formed of a nitride semiconductor whose composition is different from the electron transit layer (103) and that has a recess (109) which reaches the electron transit layer (103) from a surface, a thermal oxide film (111) that is formed on the surface of the electron transit layer (103) exposed within the recess (109), a gate insulating film (110) that is embedded within the recess (109) so as to be in contact with the thermal oxide film (111), a gate electrode (108) that is formed on the gate insulating film (110) and that is opposite to the electron transit layer (103) across the thermal oxide film (111) and the gate insulating film (110), and a source electrode (106) and a drain electrode (107) that are provided on the electron supply layer (104) at an interval such that the gate electrode (108) intervene