Abstract: A semiconductor light-emitting transistor device, including: a bipolar pnp transistor structure having a p-type collector, an n-type base, and a p-type emitter; a first tunnel junction coupled with the collector, and a second tunnel junction coupled with the emitter; and a collector contact coupled with the first tunnel junction, an emitter contact coupled with the second tunnel junction, and a base contact coupled with the base; whereby, signals applied with respect to the collector, base, and emitter contacts causes light emission from the base by radiative recombination in the base.

Abstract: For the integration of an npn bipolar transistor with a hetero bipolar transistor, a placeholder layer is generated in a base region of the hetero bipolar transistor after structuring a collector structure for both types of transistors, wherein the placeholder layer is not present in a base region of the bipolar transistor. After generating the base of the bipolar transistor, the base of the bipolar transistor is covered, whereupon the placeholder layer is removed and the base of the hetero bipolar transistor is generated in the places where the placeholder layer has been removed. The emitter structure is again generated equally for both types of transistors so that an integrated circuit results which includes bipolar transistors and hetero bipolar transistors whose collector structures and/or whose emitter structures consist of identical production layers. Thus, space-saving and cost-effective integrated circuits may be produced benefiting from the advantages of both types of transistors.

Abstract: In a mesa type bipolar transistor or a thyristor, since carriers injected from an emitter layer or an anode layer to a base layer or a gate layer diffuse laterally and are recombined, reduction in the size and improvement for the switching frequency is difficult. In the invention, the emitter layer or the anode layer is formed of two high-doped and low-doped layers, a semiconductor region for suppressing recombination comprising an identical semiconductor having an impurity density identical with that of the low-doped layer is present being in contact with a base layer or a gate layer and a surface passivation layer, and the width of the semiconductor region for suppressing recombination is defined equal with or longer than the diffusion length of the carrier. This provides an effect of attaining reduction in the size of the bipolar transistor or improvement of the switching frequency of the thyristor without deteriorating the performance.

Abstract: According to one exemplary embodiment, a heterojunction bipolar transistor includes a base situated on a substrate. The heterojunction bipolar transistor can be an NPN silicon-germanium heterojunction bipolar transistor, for example. The heterojunction bipolar transistor further includes a cap layer situated on the base, where the cap layer includes a barrier region. The barrier region can comprises carbon and has a thickness, where the thickness of the barrier region determines a depth of an emitter-junction of the heterojunction bipolar transistor. An increase in the thickness of the barrier region can cause a decrease in the depth of the emitter-base junction. According to this exemplary embodiment, the heterojunction bipolar transistor further includes an emitter situated over the cap layer, where the emitter comprises an emitter dopant, which can be phosphorus. A diffusion retardant in the barrier region of the cap layer impedes diffusion of the emitter dopant.

Abstract: A heterobipolar transistor (HBT) for high-speed BiCMOS applications is provided in which the collector resistance, Rc, is lowered by providing a buried refractory metal silicide layer underneath the shallow trench isolation region on the subcollector of the device. Specifically, the HBT of the present invention includes a substrate including at least a subcollector; a buried refractory metal silicide layer located on the subcollector; and a shallow trench isolation region located on a surface of the buried refractory metal silicide layer. The present invention also provides a method of fabricating such a HBT. The method includes forming a buried refractory metal silicide underneath the shallow trench isolation region on the subcollector of the device.

Abstract: A semiconductor device is provided. In one example, a semiconductor device has a D-HBT structure which include a base layer formed from InGaAs and an emitter layer and a collector layer both formed from InGaP in such a way as to hold said base layer between them, wherein said InGaAs has a composition such that the content of In is smaller than 53% and said InGaP has a composition such that the content of In is just enough to make the lattice constant of said emitter layer and collector layer equal to the lattice constant of said base layer. This semiconductor device realizes a large current gain while keeping the high-speed operation owing to the base layer of InGaAs having good carrier mobility. In addition, it can be formed on a large wafer as the substrate.

Abstract: A bipolar transistor includes a Si single crystalline layer serving as a collector, a single crystalline Si/SiGeC layer and a polycrystalline Si/SiGeC layer which are formed on the Si single crystalline layer, an oxide film having an emitter opening portion, an emitter electrode, and an emitter layer. An intrinsic base layer is formed on the single crystalline Si/SiGeC layer, part of the single crystalline Si/SiGeC layer, the polycrystalline Si/SiGeC layer and the Co silicide layer together form an external base layer. The thickness of the emitter electrode is set so that boron ions implanted into the emitter electrode and diffused therein do not reach an emitter-base junction portion.

Abstract: A semiconductor device includes an emitter layer: a base layer; and a collector layer, wherein the collector layer and the emitter layer each include a heavily doped thin sublayer having a high impurity concentration, and each of the heavily doped thin sublayers has an impurity concentration higher than those of semiconductor layers adjacent to each heavily doped thin sublayer.

Abstract: An improved imaging array (and corresponding method of operation) includes a plurality of heterojunction thyristor-based pixel elements disposed within resonant cavities formed on a substrate. Each thyristor-based pixel element includes complementary n-type and p-type modulation doped quantum well interfaces that are spaced apart from one another. Incident radiation within a predetermined wavelength resonates within the cavity of a given pixel element for absorption therein that causes charge accumulation. The accumulated charge is related to the intensity of the incident radiation. The heterojunction-thyristor-based pixel element is suitable for many imaging applications, including CCD-based imaging arrays and active-pixel imaging arrays.

Abstract: A heterojunction bipolar transistor comprising a substrate; a collector on the substrate; a base layer on the collector; an emitter layer on the base layer; the emitter layer comprising an upper emitter layer and a lower emitter layer between the upper emitter layer and base; the collector, base and emitter layers being npn or pnp doped respectively; characterised in that the lower emitter layer has a larger bandgap than the base layer and is AlxIn1-xP or GaxAl1-xP, x being in the range 0+ to 1.

Abstract: A sophisticated semiconductor device capable of being fabricated without introducing a high-precision exposure apparatus is obtained. This semiconductor device includes a conductive layer formed on a first conductivity type collector layer, a first conductivity type emitter electrode formed on the conductive layer and a protruding portion protruding from an outer side toward an inner side of the emitter electrode along an interface between the emitter electrode and the conductive layer. The conductive layer has a first conductivity type emitter diffusion layer in contact with the emitter electrode through the protruding portion and a second conductivity type base layer.

Abstract: Group III-nitride quaternary and pentenary material systems and methods are disclosed for use in semiconductor structures, including laser diodes, transistors, and photodetectors, which reduce or eliminate phase separation and provide increased emission efficiency. In an exemplary embodiment the semiconductor structure includes a first ternary, quaternary or pentenary material layer using BInGaAlN material system of a first conduction type formed substantially without phase separation, and a quaternary or pentenary material active layer using BInGaAlN material system substantially without phase separation, and a third ternary, quaternary or pentenary material layer using BInGaAlN material system of an opposite conduction type formed substantially without phase separation.

Abstract: A bipolar transistor structure includes an intrinsic base layer formed over a collector layer, an emitter formed over the intrinsic base layer, and an extrinsic base layer formed over the intrinsic layer and adjacent the emitter. A ring shaped collector implant structure is formed within an upper portion of the collector layer, wherein the ring shaped collector implant structure is disposed so as to be aligned beneath a perimeter portion of the emitter.

Abstract: In a nitride semiconductor based bipolar transistor, a contact layer formed so as to contact an emitter layer is composed of n-type InAlGaN quaternary mixed crystals, the emitter layer and the contact layer are selectively removed so that the barrier height with the emitter formed thereon is small, and the ohmic electrode contact resistance can be lowered on the InAlGaN quaternary mixed crystals, for example, so that a WSi emitter electrode becomes an eave. A base electrode is formed by a self-aligned process using the emitter electrode as a mask. By such a configuration, the distance between the emitter and the edge of the base electrode is sufficiently shortened, and the base resistance can be lowered. As a result, a bipolar transistor having favorable high-frequency characteristics can be realized.

Abstract: A heterojunction bipolar transistor includes a first conductivity type subcollector layer, a first collector layer containing a first conductivity type impurity, a third collector layer containing a higher concentration of the first conductivity type impurity than the first collector layer, a second collector layer containing a lower concentration of the first conductivity type impurity than the first collector layer, a second conductivity type base layer, a first conductivity type emitter layer containing a semiconductor with a wider bandgap than the base layer, and a first conductivity type emitter cap layer.

Abstract: Low power double heterojunction bipolar transistors with low parasitics, and methods for making the same is presented. A transistor is fabricated such that the collector region underneath a base contact area is deactivated. This results in a drastic reduction of the base-collector parasitic capacitance, Cbc. An embodiment of the present invention provides a transistor architecture for which the base contact area can be decoupled from the collector and hence allows for dramatic reduction in the parasitics of transistors.

Abstract: Bipolar junction transistors (BJTs) and single or double heterojunction bipolar transistors with low parasitics, and methods for making the same is presented. A transistor is fabricated such that the collector region underneath a base contact area is deactivated. This results in a drastic reduction of the base-collector parasitic capacitance, Cbc. An embodiment of the present invention provides a transistor architecture for which the base contact area can be decoupled from the collector and hence allows for dramatic reduction in the parasitics of transistors.

Abstract: A heterojunction bipolar transistor is formed in a semiconductor substrate of a first conductivity type including a collector region. A base region is formed on the substrate and an emitter region is formed over the base region. At least one of the collector, base and emitter regions includes a first region doped with an impurity having a first concentration and a second region doped with the impurity having a second concentration. Noise performance and reliability of the heterojunction bipolar transistor is improved without degrading ac performance.

Abstract: A hetero-junction bipolar transistor is provided including emitter contact region, an emitter region made of a first semiconductor material, a base region made of a second semiconductor material having a smaller energy band gap than the first semiconductor material, a collector region made of the first semiconductor material, and a collector contact area, the regions being serially formed on a surface of a substrate in a direction parallel to the surface thereof. A buffer layer made of a third semiconductor material with an energy band gap larger than the first semiconductor material is provided between the emitter region, the base region, the collector region and the substrate surface. Emitter, base and collector electrodes are also provided, in contact with the emitter contact region, the base region, and the collector region, respectively.

Abstract: The present invention aims at providing a heterojunction bipolar transistor having improved breakdown voltage on operation for high power output, and includes: a GaAs semiconductor substrate 100; an n+-type GaAs sub-collector layer 110; an n-type GaAs collector layer 120; a p-type GaAs base layer 130; an emitter layer 140; an n-type GaAs emitter cap layer 150; and an n-type InGaAs emitter contact layer 160. The emitter layer 140 has a multilayer structure including an n-type or non-doped first emitter layer 141 and an n-type second emitter layer 142 which are laminated in sequence. The first emitter layer 141 is made of a semiconductor material including Al, while the second emitter layer 142 is made of InxGa1-xP (0<x<1).

Abstract: A bipolar transistor having a base electrode of an air bridge structure is simplified in structure and enhanced in the degree of freedom of a contact position of a base wiring line with the base electrode. The bipolar transistor has a semiconductor mesa portion having a base layer formed on an upper face thereof, and a base electrode contacts with the base layer and has a floating extension which extends from the semiconductor mesa portion to a space on the outer side with respect to the semiconductor mesa portion. The floating extension is used as a contact portion for a base wiring line to the base electrode.

Abstract: According to one exemplary embodiment, a heterojunction bipolar transistor includes a base situated on a substrate. The heterojunction bipolar transistor can be an NPN silicon-germanium heterojunction bipolar transistor, for example. The heterojunction bipolar transistor further includes a cap layer situated on the base, where the cap layer includes a barrier region. The barrier region can comprises carbon and has a thickness, where the thickness of the barrier region determines a depth of an emitter-junction of the heterojunction bipolar transistor. An increase in the thickness of the barrier region can cause a decrease in the depth of the emitter-base junction. According to this exemplary embodiment, the heterojunction bipolar transistor further includes an emitter situated over the cap layer, where the emitter comprises an emitter dopant, which can be phosphorus. A diffusion retardant in the barrier region of the cap layer impedes diffusion of the emitter dopant.

Abstract: Disclosed are an improved hetero-junction bipolar transistor (HBT) structure and a method of forming the structure that incorporates a silicon-germanium emitter layer with a graded germanium profile. The graded germanium concentration creates a quasi-drift field in the neutral region of the emitter layer. This quasi-drift field induces valence bandgap grading within the emitter layer so as to accelerate movement of holes from the base layer through the emitter layer. Accelerated movement of the holes from the base layer through the emitter layer reduces emitter delay time and thereby, increases the cut-off frequency (fT) and the maximum oscillation frequency (fMAX) of the resultant HBT.

Abstract: The semiconductor device of this invention includes an active region formed from a group III nitride semiconductor grown on a substrate and an insulating oxide film formed in a peripheral portion of the active region by oxidizing the group III nitride semiconductor. On the active region, a gate electrode in Schottky contact with the active region extending onto the insulating oxide film and having an extended portion on the insulating oxide film is formed, and ohmic electrodes respectively serving as a source electrode and a drain electrode are formed with space from side edges along the gate length direction of the gate electrode.

Abstract: In a nitride semiconductor device according to one embodiment of the invention, a p-type gallium nitride (GaN) layer electrically connected to a source electrode and extending and projecting to a drain electrode side with respect to a gate electrode is formed on an undoped or n-type aluminum gallium nitride (AlGaN) layer serving as a barrier layer.

Abstract: A method of manufacturing a field emission device (FED), which reduces the number of photomask patterning processes and improves the manufacturing yield of the FED, is provided.

Abstract: An improved imaging array (and corresponding method of operation) includes a plurality of heterojunction thyristor-based pixel elements disposed within resonant cavities formed on a substrate. Each thyristor-based pixel element includes complementary n-type and p-type modulation doped quantum well interfaces that are spaced apart from one another. Incident radiation within a predetermined wavelength resonates within the cavity of a given pixel element for absorption therein that causes charge accumulation. The accumulated charge is related to the intensity of the incident radiation. The heterojunction-thyristor-based pixel element is suitable for many imaging applications, including CCD-based imaging arrays and active-pixel imaging arrays.

Abstract: A plasma display panel (PDP) may include a first substrate having first discharge electrodes and a first separation border where the first substrate was separated from a first base substrate and a second substrate having second discharge electrodes and a second separation border where the second substrate was separated from a second base substrate.

Abstract: An n-type InP sub collector layer 2 heavily doped with silicon (Si), an InP collector layer 3, a p-type GaAs(0.51)Sb(0.49) base layer 4 heavily doped with carbon (C), an n-type In(1-y)Al(y)P emitter layer 7 doped with Si, an n-type InP cap layer 8 heavily doped with Si, and an n-type In(0.53)Ga(0.47)As contact layer 9 heavily doped with Si are stacked on a substrate 1.

Abstract: Disclosed are apparatus and methods for designing electrical contact for a bipolar emitter structure. The area of an emitter structure (106, 306, 400, 404) and the required current density throughput of an electrical contact structure (108, 308, 402, 406) are determined. A required electrical contact area is determined based on the required current density, and the electrical contact structure is then designed to minimize the required electrical contact area with respect to the emitter structure area.

Abstract: A material made by arranging layers of gallium-arsenide-antimonide (GaAsxSb1-x, 0.0?x?1.0) and/or indium-gallium-arsenic-nitride (InyGa1-yAszN1-z, 0.0?y, z?1.0) in a specific order is used to form the transistor base of a heterojunction bipolar transistor. By controlling the compositions of the materials indium-gallium-arsenic-nitride and gallium-arsenide-antimonide, and by changing the thickness and order of the layers, the new material would possess a specific energy gap, which in turn determines the base-emitter turn-on voltage of the heterojunction bipolar transistor.

Abstract: A semiconductor material which has a high carbon dopant concentration and is composed of gallium, indium, arsenic and nitrogen is disclosed. The material is useful in forming the base layer of gallium arsenide based heterojunction bipolar transistors because it can be lattice matched to gallium arsenide by controlling the concentration of indium and nitrogen. The disclosed semiconductor materials have a low sheet resistivity because of the high carbon dopant concentration obtained.

Abstract: A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique in the range from 350° C. to 750° C. is described for incorporating carbon epitaxially in Si and SiGe films with very abrupt and well defined junctions, but without any associated oxygen background contamination. Preferably, these epitakial SiC and SiGeC films are in-situ doped p- or n-type and with the presence of low concentration of carbon <1020 cm?3, the as-grown p- or n-type dopant profile can withstand furnace anneals to temperatures of 850° C. and rapid thermal anneal temperatures to 1000° C.

Abstract: A bipolar transistor structure and process technology is described incorporating a emitter, a base, and a collector, with most of the intrinsic base adjacent the collector having a graded energy bandgap and a layer of the intrinsic base adjacent the emitter having a substantially constant energy bandgap. The invention has a smaller base transit time than a conventional graded-base-bandgap bipolar transistor.

Abstract: A silicon semiconductor die comprises a heavily doped silicon substrate and an upper layer comprising doped silicon of a first conduction type disposed on the substrate. The upper layer comprises a well region of a second, opposite conduction type adjacent an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon. Both the well region and adjacent edge termination zone are disposed at an upper surface of the upper layer, and an oxide layer overlies the upper layer and the edge termination zone. A process for forming a silicon die having improved edge termination. The process comprises forming an upper layer comprising doped silicon of a first conduction type on a heavily doped silicon substrate, and forming an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon at an upper surface of the upper layer.

Abstract: There is provided and manufactured, at a low cost and with high yields, a semiconductor light emitting device which allows extraction of light produced in an emitter layer not only from its top surface but also from its side surfaces and which has high luminance. An AlGaInP-based semiconductor light emitting device having a contact layer 8 made of (AlyGa1?y)zIn1?zP (0?y?1, 0<z<1) disposed between an emitter layer 3 and a transparent substrate 2 which is transparent to emission wavelengths from the emitter layer 3.

Abstract: A bipolar transistor includes: a first semiconductor layer having an intrinsic base region and an extrinsic base region; and a second semiconductor layer having a portion located on the intrinsic base region to be an emitter region or a collector region. A capacitive film is provided on the extrinsic base region using the same semiconductor material as that for the second semiconductor layer. A base electrode is formed on the first semiconductor layer to cover the capacitive film and the extrinsic base region.

Abstract: The bipolar transistor of the present invention includes a Si collector buried layer, a first base region made of a SiGeC layer having a high C content, a second base region made of a SiGeC layer having a low C content or a SiGe layer, and a Si cap layer 14 including an emitter region. The C content is less than 0.8% in at least the emitter-side boundary portion of the second base region. This suppresses formation of recombination centers due to a high C content in a depletion layer at the emitter-base junction, and improves electric characteristics such as the gain thanks to reduction in recombination current, while low-voltage driving is maintained.

Abstract: Provided is a process for forming a contact for a compound semiconductor device without electrically shorting the device. In one embodiment, a highly doped compound semiconductor material is electrically connected to a compound semiconductor material of the same conductivity type through an opening in a compound semiconductor material of the opposite conductivity type. Another embodiment discloses a transistor including multiple compound semiconductor layers where a highly doped compound semiconductor material is electrically connected to a compound semiconductor layer of the same conductivity type through an opening in a compound semiconductor layer of the opposite conductivity type. Embodiments further include metal contacts electrically connected to the highly doped compound semiconductor material. A substantially planar semiconductor device is disclosed. In embodiments, the compound semiconductor material may be silicon carbide.

Abstract: A bipolar transistor of the present invention comprises a collector layer made of an n-type semiconductor and an emitter layer made of an n-type semiconductor provided on this collector layer. A gate layer for injecting p-type carriers (holes) into the emitter layer is provided on the emitter layer. A p-type carrier retaining layer is formed between the collector layer and the emitter layer. The p-type carrier retaining layer temporarily retains the p-type carriers that are injected from the gate layer into the emitter layer and diffused in the emitter layer and reach the p-type carrier retaining layer. The bipolar transistor has a structure whose performance is not influenced by sheet resistance of the base layer, and is able to exhibit a high current gain even in a high-frequency region.

Abstract: The present invention realizes a heterobipolar transistor using a SiGeC base layer in order to improve its electric characteristics. Specifically, the distribution of carbon and boron within the base layer is controlled so that the concentration of boron is higher than the concentration of carbon on the side bordering on the emitter layer, and upon the formation of the emitter layer, both boron and carbon are dispersed into a portion of the emitter layer that comes into contact with the base layer.

Abstract: An indium phosphide based double hetero-junction bipolar transistor with an increased collector-base breakdown voltage and a reduced operational knee voltage is provided by manipulating the conductivity in the collector region. The collector is formed using layers of different conductivities, with a region of the collector relatively close to the base being unintentionally or low doped. A voltage drop across the unintentionally doped region reduces the maximum value of the electric field and the velocity of carriers injected into the collector region at the base-collector junction. The conductivity throughout the collector region may be graded such that the highest conductivity occurs near the sub-collector and lowest conductivity occurs near the base region.

Abstract: The invention relates to a semiconductor device with a heterojunction bipolar, in particular npn, transistor with an emitter region (1), a base region (2), and a collector region (3), which are provided with respectively a first, a second, and a third connection conductor (4, 5, 6), while the bandgap of the base region (2) is lower than that of the collector region (3) or of the emitter region (1), for example owing to the use of a silicon-germanium alloy instead of pure silicon. Such a device is very fast, but its transistor shows a relatively low BVceo. In a device according to the invention, the emitter region (1) or the base region (2) comprises a sub-region (1B, 2B) with a reduced doping concentration, which sub-region (1B, 2B) is provided with a further connection conductor (4B, 5B) which forms a Schottky junction with the sub-region (1B, 2B). Such a device results in a transistor with a particularly high cut-off frequency fT but with no or hardly any reduction of the BVceo.

Abstract: A semiconductor device is provided having an improved breakdown voltage on high power output, the semiconductor device comprising a n-type GaAs subcollector layer, a n-type GaAs intermediate collector layer formed between a collector layer and the subcollector layer, the n-type GaAs collector layer, a p-type GaAs base layer, a n-type InGaP second emitter layer, a n-type GaAs first emitter layer, and a n-type InGaAs emitter contact layer, and a concentration of impurities in the intermediate collector layer is higher than a concentration of impurities in the collector layer and is lower than a concentration of impurities in the subcollector layer.

Abstract: A semiconductor integrated circuit including a plurality of bipolar transistors that are produced by forming, in a plurality of transistor-producing regions, a first conductive type emitter layer on the front surface side of a second conductive type base layer that is formed on the surface side of a first conductive collector layer and contains germanium, the first conductive type emitter layer being formed from a semiconductor material having a band gap larger than the base layer. The concentrations of impurities contained in the emitter layers vary among the plurality of transistor-producing regions, and the germanium concentrations differ in the base-emitter junction interfaces of at least two of the transistor-producing regions, such that the ON-state voltages required for turning the plurality of bipolar transistors into an ON state differ from each other.

Abstract: A transistor having minimized parasitics is provided including an emitter having a recessed extrinsic emitter portion atop an intrinsic emitter portion; a base including an intrinsic base portion in electrical contact with the intrinsic emitter portion and an extrinsic base portion in electrical contact with the intrinsic base portion and electrically isolated from the recessed extrinsic emitter portion by a set of emitter/base spacers; and a collector in electrical contact with the intrinsic base portion. The transistor may further include extrinsic base having top surfaces entirely silicided to the emitter/base spacer. Additionally, the transistor may include a base window opening within the transistor's active area. Methods of forming the above-described transistor are also provided.

Abstract: The gist of the present invention is as follows: In a monolithic microwave integrate circuit (MMIC) using a heterojunction bipolar transistor (HBT), via holes are respectively formed from the bottom of the MMIC for the emitter, base and collector. Of the via holes, one is located so as to face the HBT. The respective topside electrodes for the other via holes located so as not to face the HBT are provided in contact with the MMIC substrate.

Abstract: A heterojunction bipolar transistor (HBT) with improved characteristics is provided. A III–V compound semiconductor having Bi added thereto is used for a base layer of a GaAs-based or InP-based HBT. For example, a GaAs-based HBT is formed by successively stacking a subcollector layer made of n+-GaAs, a collector layer made of n?-GaAs, a base layer made of p+-GaAsBi, an emitter layer made of n-InGaP, a first cap layer made of n-GaAs, and a second cap layer made of n+-InGaAs on a substrate 1 made of single crystal GaAs.

Abstract: According to one exemplary embodiment, an NPN bipolar transistor comprises a base layer situated over a collector, where the base layer comprises an intrinsic base region and an extrinsic base region. The NPN bipolar transistor may be, for example, an NPN silicon-germanium heterojunction bipolar transistor. The base layer can be, for example, silicon-germanium. According to this exemplary embodiment, the NPN bipolar transistor further comprises a cap layer situated over the base layer, where a portion of the cap layer is situated over the extrinsic base region, and where the portion of the cap layer situated over the extrinsic base region comprises an indium dopant. The cap layer may be, for example, polycrystalline silicon. According to this exemplary embodiment, the NPN bipolar transistor may further comprise an emitter situated over the intrinsic base region. The emitter may be, for example, polycrystalline silicon.

Abstract: According to the present invention, there is a provided a semiconductor device having, a collector contact layer made of an n-type GaAs layer; a first collector layer formed on the collector contact layer and made of an n-type GaAs layer; a second collector layer formed on the first collector layer and made of a p-type GaAs layer; a third collector layer formed on the second collector layer and made of an n-type InGaP layer; a fourth collector layer formed on the third collector layer and made of an n-type InGaP layer having an impurity concentration higher than that of the third collector layer; a fifth collector layer formed on the fourth collector layer and made of an n-type GaAs layer; a base layer formed on the fifth collector layer and made of a p-type GaAs layer; and an emitter layer formed on the base layer and made of an n-type InGaP layer.