Abstract: This invention provides a double hetero-junction bipolar transistor (DHBT) in which a probability of the impact ionization at the interface between the base and the collector is reduced, thereby enhancing the break down voltage. In the present DHBT, a plurality of transition layers is inserted between the base layer and the collector layer. Each transition layers has an energy band gap gradually increasing from the base to the collector, and comprises a doped layer close to the base and an un-doped layer. Transition layers thus configured may bring both characteristics of the high break down voltage by the reduction of the average doping concentration and the capability of the high-speed operation by the reduction of the junction capacitance.

Abstract: A double heterojunction bipolar transistor structure having desirable properties of a low base-emitter turn-on voltage and no electron blocking discontinuities in the base-collector junction. These properties are achieved by selecting base, emitter and collector materials to provide a bandgap profile that exhibits abrupt transitions at the heterojunctions, such that both abrupt transitions are due to transitions in the valence band edge of the bandgap, but not in the conductive band edge of the bandgap.

Abstract: A Heterojunction Bipolar Transistor, HBT, (100) containing a collector layer (104), a base layer (105) and an emitter layer (106) is constructed such that the collector layer (104), the base layer (105) and the emitter layer (106) have different lattice constants of ac, ab and ae respectively, and a value of ab between values of ac and ae (in other words, the values of ac, ab and ae satisfy a relationship of ac>ab>ae or ac<ab<ae). According to the present invention, the HBT having a high reliability can be realized without altering the existing apparatus and steps for producing the HBT extensively.

Abstract: According to one exemplary embodiment, a gallium arsenide heterojunction bipolar transistor comprises a collector layer and a first spacer layer situated over the collector layer, where the first spacer layer is a high-doped P+ layer. For example, the first spacer layer may comprise GaAs doped with carbon. The gallium arsenide heterojunction bipolar transistor further comprises a base layer situated over the first spacer layer. The base layer may comprise, for example, a concentration of indium, where the concentration of indium is linearly graded in the base layer. The base layer may comprise InGaAsN, for example. The gallium arsenide heterojunction bipolar transistor further comprises an emitter layer situated over the base layer. The emitter layer may comprise, for example, InGaP.

Abstract: The safe-operating area (SOA) in a heterojunction bipolar transistor (HBT) is improved by providing a collector region in the transistor having a graded (uniformly or stepped) doping between the base region and the underlying subcollector region with the collector doping being lower near the base and higher near the subcollector and with the collector doping being less than the doping of the subcollector. The non-uniformly doped collector reduces Kirk effect induced breakdown when collector current increases.

Abstract: A heterojunction bipolar transistor (HBT) with improved characteristics is provided. A III–V compound semiconductor having Bi added thereto is used for a base layer of a GaAs-based or InP-based HBT. For example, a GaAs-based HBT is formed by successively stacking a subcollector layer made of n+-GaAs, a collector layer made of n?-GaAs, a base layer made of p+-GaAsBi, an emitter layer made of n-InGaP, a first cap layer made of n-GaAs, and a second cap layer made of n+-InGaAs on a substrate 1 made of single crystal GaAs.

Abstract: A heterobipolar transistor (HBT) for high-speed BiCMOS applications is provided in which the collector resistance, Rc, is lowered by providing a buried refractory metal silicide layer underneath the shallow trench isolation region on the subcollector of the device. Specifically, the HBT of the present invention includes a substrate including at least a subcollector; a buried refractory metal silicide layer located on the subcollector; and a shallow trench isolation region located on a surface of the buried refractory metal silicide layer. The present invention also provides a method of fabricating such a HBT. The method includes forming a buried refractory metal silicide underneath the shallow trench isolation region on the subcollector of the device.

Abstract: A heterojunction bipolar transistor (HBT) and method of making an HBT are provided. The HBT includes a collector, and an intrinsic base overlying the collector. The intrinsic base includes a layer of a single-crystal semiconductor alloy. The HBT further includes a raised extrinsic base having a first semiconductive layer overlying the intrinsic base and a second semiconductive layer formed on the first semiconductive layer. An emitter overlies the intrinsic base, and is disposed in an opening of the first and second semiconductive layers, such that the raised extrinsic base is self-aligned to the emitter.

Abstract: A method for manufacturing a heterojunction bipolar transistor is provided. An intrinsic collector structure is formed on a substrate. An extrinsic base structure partially overlaps the intrinsic collector structure. An intrinsic base structure is formed adjacent the intrinsic collector structure and under the extrinsic base structure. An emitter structure is formed adjacent the intrinsic base structure. An extrinsic collector structure is formed adjacent the intrinsic collector structure. A plurality of contacts is formed through an interlevel dielectric layer to the extrinsic collector structure, the extrinsic base structure, and the emitter structure.

Abstract: A bipolar transistor is provided which includes a collector region, an intrinsic base layer including a single-crystal semiconductor overlying the collector region, and an emitter disposed within a first opening overlying the intrinsic base layer. The bipolar transistor includes a raised extrinsic base, which in turn includes a raised extrinsic base layer and a link-up region which electrically connects the raised extrinsic base layer to the intrinsic base layer. The link-up region also self-aligns the raised extrinsic base to the emitter. The link-up region is disposed in a second opening separate from the first opening and in an undercut region extending from the second opening below the raised extrinsic base layer.

Abstract: In a semiconductor device using an emitter top heterojunction bipolar transistor having a planar shape in a ring-like shape, a structure is provided in which a base electrode is present only on an inner side of a ring-like emitter-base junction region. This allows reduction of base/collector junction capacitance per unit emitter area, whereby a semiconductor device having high power adding efficiency and high power gain suitable for a power amplifier can be realized. Further, in a multistage power amplifier including first and second amplifier circuits each having one or more of bipolar transistors, a bipolar transistor in the first amplifier circuit uses an emitter having a planar shape in a rectangular shape, and a bipolar transistor in the second amplifier circuit uses an emitter having a ring-like shape and a base electrode only on the inner side of the emitter.

Abstract: A heterojunction bipolar transistor (HBT) with improved characteristics is provided. A III-V compound semiconductor having Bi added thereto is used for a base layer of a GaAs-based or InP-based HBT. For example, a GaAs-based HBT is formed by successively stacking a subcollector layer made of n+-GaAs, a collector layer made of n?-GaAs, a base layer made of p+-GaAsBi, an emitter layer made of n-InGaP, a first cap layer made of n-GaAs, and a second cap layer made of n+-InGaAs on a substrate 1 made of single crystal GaAs.

Abstract: A semiconductor device which IGBT (Z1) and a control circuit (B1) for driving the IGBT (Z1) are formed on the same semiconductor substrate by using a junction isolation technology, includes an input terminal (P1) for inputting a drive signal of the IGBT (Z1), a Schottky barrier diode (D2) having an anode connected to the input terminal (P1) and a cathode connected to an input terminal (B11) of the control circuit (B1), and a p-channel MOSFET (T1) for shorting both ends of the Schottky barrier diode (D2) when the voltage of the drive signal input to the input terminal (P1) is higher than a predetermined voltage, thereby latch-up of the parasitic element is prevented and a transmission loss of the input signal can be reduced.

Abstract: A heterojunction bipolar transistor is provided that has a reduced turn-on voltage threshold. A base spacer layer is provided and alternately an emitter layer is provided that has a lowered energy gap. The lowered energy gap of the base spacer or the emitter spacer allow the heterojunction bipolar transistor to realize a lower turn-on voltage threshold. The thickness of the emitter layer if utilized is kept to a minimum to reduce the associated space charge recombination current in the heterojunction bipolar transistor.

Abstract: A hetero-junction bipolar transistor that satisfies high resistance required to avoid a potential breakdown includes: an n-type sub-collector layer 110 that is made of GaAs; an n-type first collector 121 that is made of a semiconductor material with a smaller avalanche coefficient than that of the sub-collector 110 and is formed on the sub-collector layer 110; a second collector layer 132 that is made of n-type or i-type GaAs with lower dopant concentration than that of the sub-collector layer 110 and is formed on the first collector layer 121; a p-type base layer 133 that is made of GaAs and is formed on the second collector layer 132; and emitter layer 134 that is made of a semiconductor material with a larger band gap than that of the base layer 133 and is formed on the base layer 133.

Abstract: A semiconductor device having a heterojunction bipolar transistor capable of suppressing the deterioration of basic transistor characteristics, such as a decline of an injection efficiency from an emitter layer to a base layer due to the rising of emitter resistance, a decline of breakdown strength between the base layer and a collector layer, or a decline of reliability due to an introduction of a defect; configured to comprise a heterojunction bipolar transistor having an emitter layer, base layer and a collector layer, wherein an electron affinity of the base layer is smaller than that of the emitter layer and that of the collector layer, an interlayer is formed at least either between the emitter layer and the base layer or between the base layer and the collector layer, and the electron affinity of the interlayer has a value between the electron affinities of the two layers sandwiching the interlayer.

Abstract: This invention provides a hetero-junction bipolar transistor (HBT) in which both a base resistance and a base-collector parasitic capacitance are decreased. The HBT has a collector (C) 18, a base (B) 20 and an emitter (E) 26. The collector comprises an outer collector region and an inner collector region, a thickness of the outer collector region is greater than that of the inner region. The base comprises an intrinsic region and an extrinsic region on the outer collector region, while the intrinsic base disposed on the inner collector region. The emitter is disposed on both the intrinsic base and the extrinsic base, and has a band gap energy greater than that of the base.

Abstract: A heterojunction bipolar transistor has a raised breakdown voltage and restrains the rising characteristic of IC-VCE characteristic from degrading. The collector region includes first, second, and third collector layers of semiconductor. The first collector layer is made of a doped or undoped semiconductor in such a way as to contact the sub-collector region. The second collector layer is made of a doped or undoped semiconductor having a narrower band gap than the first collector layer in such a way as to contact the base region. The third collector layer has a higher doping concentration than the second collector layer in such a way as to be located between or sandwiched by the first collector layer and the second collector layer.

Abstract: Selectively implanting carbon in a transistor lowers the collector-to-emitter breakdown (BVCEO) of the transistor. This transistor, with the lowered BVCEO, is then used as a “trigger” device in an Electrostatic Discharge (ESD) power clamp comprising a first low breakdown trigger device and a second high breakdown clamp device. ESD power clamps are constructed using epitaxial base pseudomorphic Silicon Germanium heterojunction transistors in a common-collector Darlington configuration.

Abstract: A compound semiconductor multilayer structure comprising a carbon-containing p-type gallium arsenide (GaAs)-system crystal layer, wherein the carbon-containing p-type GaAs-system crystal layer exhibits a predominant photoluminescence peak measured at 20K within a range of 828 nm to 845 nm, and wherein the ratio of hydrogen atom concentration to carbon atom concentration in the carbon-containing p-type GaAs crystal layer is 1/5 or less. Furthermore, in a photoluminescence measurement at 10K, the carbon-containing GaAs-system p-type crystal layer exhibits a first predominant photoluminescence peak and a second predominant photoluminescence peak due to band gap transitions of GaAs and wherein the second predominant luminescence wavelength has a longer wavelength than the first predominant photoluminescence wavelength and the intensity ratio of the second luminescence peak to the first luminescence peak is within a range from 0.5 to 3.

Abstract: The present invention provides a Hetero-Bipolar Transistor that suppresses a recombination current between electrons in the conduction band of an emitter and holes in the valence band of a base, which results on an enhancement of the current gain of the transistor. The HBT according to the present invention comprises a semi-insulating semiconductor substrate and a series of semiconductor layers on the substrate. The semiconductor layers are a buffer layer, a sub-collector layer a collector layer, a base layer, an emitter layer, an emitter contact layer, and an intermediate layer between the emitter layer and the emitter contact layer. The emitter layer has a carrier concentation of 1.0×1019 cm?3.

Abstract: A bipolar transistor includes a collector that is selected from the group SiC and SiC polytypes (4H, 6H, 15R, 3C . . . ), a base that is selected from the group Si, Ge and SiGe, at least a first emitter that is selected from the group Si, SiGe, SiC, amorphous-Si, amorphous-SiC and diamond-like carbon, and at least a second emitter that is selected from the group Si, SiGe, SiC, amorphous-Si, amorphous-SiC and diamond-like carbon. Direct-wafer-bonding is used to assemble the bipolar transistor. In an embodiment the bandgap of the collector, the bandgap of the at least a first emitter and the bandgap of the at least a second emitter are larger than the bandgap of the base.

Abstract: In one embodiment, a transistor is fabricated by forming a sacrificial emitter over a base, forming an oxide layer over the sacrificial emitter, removing a portion of the oxide layer, and then removing the sacrificial emitter. An emitter is later formed in the space formerly occupied by the sacrificial emitter. The sacrificial emitter allows a base implant step to be performed early in the process using a single masking step. The base may comprise epitaxial silicon-germanium or silicon.

Abstract: According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a sacrificial post situated on the top surface of the base. The bipolar transistor also comprises a conformal layer situated on a first and a second side of the sacrificial post, where the conformal layer is not separated from the first and second sides of the sacrificial post by spacers. According to this exemplary embodiment, the bipolar transistor further comprises a sacrificial planarizing layer situated over the conformal layer, the sacrificial post, and the base. The sacrificial planarizing layer has a first thickness in a first region between the first and second sides of the sacrificial post and a second thickness in a second region outside of the first and second sides of the sacrificial post, where the second thickness is greater than the first thickness.

Abstract: An underlayer made of a III-V semiconductor compound is formed on a given substrate, and a CrSb compound is epitaxially grown on the underlayer by means of MBE method to fabricate a zinc blend type CrSb compound.

Abstract: A family of high speed transistors and optoelectronic devices are obtained on a monolithic substrate by adding two sheets of planar doping together with a wideband cladding layer to the top of a pseudomorphic high electron mobility transistor (PHEMT) structure. The two sheets are of the same polarity which is opposite to the modulation doping of the PHEMT and they are separated by a lightly doped layer of specific thickness. The combination is separated from the PHEMT modulation doping by a specific thickness of undoped material. The charge sheets are thin and highly doped. The top charge sheet achieves low gate contact resistance and the bottom charge sheet defines the capacitance of the field-effect transistor (FET) with respect to the modulation doping layer of the PHEMT. The structure produces a pnp bipolar transistor, enhancement and depletion type FETs, a vertical cavity surface emitting laser, and a resonant cavity detector.

Abstract: A semiconductor material which has a high carbon dopant concentration includes gallium, indium, arsenic and nitrogen. The disclosed semiconductor materials have a low sheet resistivity because of the high carbon dopant concentrations obtained. The material can be the base layer of gallium arsenide-based heterojunction bipolar transistors and can be lattice-matched to gallium arsenide emitter and/or collector layers by controlling concentrations of indium and nitrogen in the base layer. The base layer can have a graded band gap that is formed by changing the flow rates during deposition of III and V additive elements employed to reduce band gap relative to different III-V elements that represent the bulk of the layer. The flow rates of the III and V additive elements maintain an essentially constant doping-mobility product value during deposition and can be regulated to obtain pre-selected base-emitter voltages at junctions within a resulting transistor.

Abstract: In a semiconductor device functioning as a SiGeC-HBT, an emitter/base stacked portion 20 is formed on a Si epitaxially grown layer 2. The emitter/base stacked portion 20 includes: a SiGeC spacer layer 21; a SiGeC core base layer 22 containing boron at a high concentration, a SiGe cap layer 23; a Si cap layer 24, and an emitter layer 25 formed by introducing phosphorus into the Si cap layer 24 and the SiGe cap layer 23.

Abstract: In a semiconductor device acting as an HBT, an emitter/base laminate portion is provided on a Si epitaxially grown layer in the SiGeC-HBT. The emitter/base laminate portion includes a SiGeC spacer layer, a SiGeC core base layer containing the boron, a Si cap layer, and an emitter layer formed by introducing phosphorous into the Si cap layer. The C content of the SiGeC spacer layer is equal to or lower than that of the SiGeC core base layer.

Abstract: An optical transistor is disclosed that provides a fast switching time, an amplified gain, and isolation. The optical transistor receives a small optical input signal at an optical base port, generates an amplified replica at an optical emitter port, and generates an inverted replica on a vertical light at an collector port. One embodiment of the optical transistor is implemented with a vertical lasing semiconductor optical amplifiers (VLSOA), wherein the ballast light is used a signal for the collector port.

Abstract: The invention relates to the protection of devices in a monolithic chip fabricated from an epitaxial wafer, such as a wafer for a Group III-V compound semiconductor or a wafer for a Group IV compound semiconductor. Devices fabricated from Group III-V compound semiconductors offer higher speed and better isolation than comparable devices from silicon semiconductors. Semiconductor devices can be permanently damaged when exposed to an undesired voltage transient such as electrostatic discharge (ESD). However, conventional techniques developed for silicon devices are not compatible with processing techniques for Group III-V compound semiconductors, such as gallium arsenide (GaAs). Embodiments of the invention advantageously include transient voltage protection circuits that are relatively efficiently and reliably manufactured to protect sensitive devices from undesired voltage transients.

Abstract: A hetero-bipolar transistor according to the present invention enhances reliability that relates to the breaking of wiring metal. The transistor comprises a semiconductor substrate, a sub-collector layer formed on a (100) surface of the substrate, a collector mesa formed on the sub-collector layer, and an emitter contact layer. The transistor further includes a collector electrode and wiring metal connected to the collector electrode. The edge of the sub-collector layer forms a step S, the angle of which is in obtuse relative to the substrate. Therefore, the wiring metal traversing the step S bends in obtuse angle at the step S, thus reducing the breaking of the wiring metal.

Abstract: As the top electrode material of a thin-film electron emitter, a material having a bandgap wider than that of Si and electrical conductivity is used. In particular, a conductive oxide such as an SnO2 or ITO film and a wide-bandgap semiconductor such as GaN or SiC are employed. The electron energy loss in a top electrode through which hot electrons pass can be reduced so as to enhance the electron emission efficiency. A high emission current can be obtained in the case of the same diode current as a prior art. In addition, in the case of the same emission current density as a prior art, a small driving current is enough. A bus line and driving circuits can be simplified.

Abstract: Bipolar junction transistor (BJT) devices, particularly heterojunction bipolar transistor (HBT) devices, and methods of making same are described. A combination of InPSb and &rgr;-type InAs is used to create extremely high speed bipolar devices which, due to reduced turn-on voltages, lend themselves to circuits having drastically reduced power dissipation. The described HBTs are fabricated on InAs or GaSb substrates, and include an InPSb emitter. The base includes In and As, in the form of InAs when on an InAs substrate, and as InAsSb when on a GaSb substrate. The collector may be the same as the base to form a single heterojunction bipolar transistor (SHBT) or may be the same as the emitter to form a double heterojunction bipolar transistor (DHBT). Heterojunctions preferably include a grading layer, which may be implemented by continuously changing the bulk material composition, or by forming a chirped superlattice of alternating materials.

Abstract: The safe operating area (SOA) in a heterojunction bipolar transistor is improved by inserting a material between the collector and subcollector of the transistor with the insertion layer being a material having a wider energy bandgap than the material of the collector. The insertion layer increases the breakdown field at the collector-subcollector junction and thereby increases the Kirk effect induced breakdown voltage.

Abstract: A method in the fabrication of a silicon-germanium mesa transistor in a semiconductor process flow comprises the steps of providing a p-type doped silicon bulk substrate (10) having an n+-type doped surface region (31) being a subcollector; depositing epitaxially thereon a silicon layer (41) comprising n-type dopant; depositing epitaxially thereon a silicon layer (174) comprising germanium and p-type dopant; forming in the epitaxial layers (41, 174) field isolation areas (81) around, in a horizontal plane, a portion of the epitaxial layers (41, 174) to simultaneously define an n-type doped collector region (41) on the subcollector (31); a p-type doped base region (174) thereon; and an n-type doped collector plug on the subcollector (31), but separated from the n-type doped collector region (41) and the p-type doped base region (174); and forming in the p-type doped base region (174) an n-type doped emitter region.

Abstract: Novel heterojunction bipolar transistors (HBT's) with high current gain and extremely low offset voltage are disclosed. Owing to the insertion of spacer/&dgr;-doped sheet/spacer at base-emitter (B-E) heterojunction in this invention, the potential spike at B-E junction can be eliminated and the confinement effect for holes are enhanced. The potential spike is not observed under large B-E bias, and the offset voltage is still relatively small with small increase. In particular, for the HBT's with large conduction band discontinuity, the method of the invention is more efficient for completely eliminating the potential spike. For the example of InP/GaInAs HBT, a maximum common-emitter current gain of 455 and above 320 at IB=5 &mgr;A, and a low offset voltage less 60 mV are achieved.

Abstract: A silicon-germanium hetero bipolar transistor comprising a silicon collector layer, a boron-doped silicon-germanium base layer, a silicon emitter layer and an emitter contact area. The transistor is fabricated using an epitaxy process on a surface of pure silicon. An electrically inert material is incorporated into the epitaxial layers in order to link the defects in the semiconductor structure and to reduce the outdiffusion of the dopant. Thus, a transistor for high-frequency applications can be fabricated in two ways: to increase the dopant dose of the base region or to reduce the thickness of the base layer. In particular, an implantation or doped region having a T-shaped cross section profile is provided between the emitter layer and the emitter contact area.

Abstract: The safe-operating area (SOA) in a heterojunction bipolar transistor (HBT) is improved by providing a collector region in the transistor having a graded (continuous or stepped) doping between the base region and the underlying subcollector region with the collector doping being lowest near the base and highest near the subcollector and with the collector doping being less than the doping of the subcollector. The non-uniformly doped collector reduces Kirk effect induced breakdown when collector current increases.

Abstract: A compound semiconductor device includes an emitter layer, a base layer which is in contact with the emitter layer and formed of a first compound semiconductor, a collector layer which is in contact with the base layer and formed of a second compound semiconductor having a wider bandgap than that of the first compound semiconductor. In the device, a delta doped layer having a higher concentration of an impurity than that of the collector layer is formed at the heterojunction interface between the collector layer and the base layer or in a region of the collector layer located at about 10 nm or less from the heterojunction interface with the base layer.

Abstract: A thin InGaAs contact layer is provided for the collector of a heterojunction bipolar transistor (HBT) above an InP sub-collector. The contact layer provides a low resistance contact mechanism and a high thermal conductivity path for removing device heat though the sub-collector, and also serves as an etch stop to protect the sub-collector during device fabrication. A portion of the sub-collector lateral to the remainder of the HBT is rendered electrically insulative, preferably by an ion implant, to provide electrical isolation for the device and improve its planarity by avoiding etching through the sub-collector.

Abstract: The speed at which optical networking devices operate is increased with the present invention with integrated circuits that provide both optical and electronic functions. The present invention provides highly integrated p-i-n or p-i-n-i-p photodetectors and heterojunction bipolar transistors for amplifying photodetector signals formed from a single semiconductor layer stack. The techniques are applicable for the integration of all InP-based and GaAs-based single-heterojunction bipolar transistors and double-heterojunction bipolar transistors. The photodetectors and transistors are formed from common layers, allowing them to be manufactured simultaneously during a processing of the stack. Integrating these components on a single circuit has the potential to greatly increase the speed (in excess of 40 Gb/s) and to decrease the cost of high-speed networking components through the development of compact optical circuits for optical networking.

Abstract: The heterojunction transistor comprises III-V semiconductor materials with a broad forbidden band material and a narrow forbidden band material. The narrow forbidden band material is an III-V compound containing gallium as one of its III elements and both arsenic and nitrogen as V elements, the nitrogen content being less than about 5%, and the narrow forbidden band material includes at least a fourth III or V element. Adding this fourth element makes it possible to adjust the width of the forbidden band, the conduction band discontinuity &Dgr;Ec, and the valance band discontinuity &Dgr;Ev of the heterojunction. The invention is applicable to making field effect transistors of the HEMT type having a very small forbidden band, and thus having high drain current. It also applies to making heterojunction bipolar transistors of small VBE, and thus capable of operating with power supply voltages that are very low.

Abstract: There is provided a compound semiconductor device that comprises a substrate formed of a first compound semiconductor, a graded channel layer formed on the substrate and formed of a second compound semiconductor layer, that lowers mostly an energy band gap in its inside by continuously changing a mixed-crystal ratio in a thickness direction such that a peak of the mixed-crystal ratio of one constituent element is positioned in its inside, and containing an impurity, a barrier layer formed on the graded channel layer, a gate electrode formed on the barrier layer, and source/drain electrodes for flowing a current into the graded channel layer. Accordingly, the compound semiconductor device having MESFET, that has the maximum mutual conductance and can make the change in the mutual conductance gentle in response to the gate voltage, can be obtained.

Abstract: In the present invention, a semiconductor device is formed which includes an MIM capacitor located on the upper surface of a heterostructure from which the emitter, base and collector sections of a nearby HBT are defined. In this way the capacitor and HBT share a substantially common structure, with the base and emitter electrodes of the HBT fashioned from the same metal layers as the upper and lower capacitor plates, respectively. Furthermore, as the insulator region of the capacitor is formed prior to definition of the HBT structure, the dielectric material used can be deposited by means of a plasma enhanced process, without damaging the HBT structure.

Abstract: This invention provides a double hetero-junction bipolar transistor (DHBT) in which a probability of the impact ionization at the interface between the base and the collector is reduced, thereby enhancing the break down voltage. In the present DHBT, a plurality of transition layers is inserted between the base layer and the collector layer. Each transition layers has an energy band gap gradually increasing from the base to the collector, and comprises a doped layer close to the base and an un-doped layer. Transition layers thus configured may bring both characteristics of the high break down voltage by the reduction of the average doping concentration and the capability of the high-speed operation by the reduction of the junction capacitance.

Abstract: A heterojunction bipolar transistor is provided having an improved current gain cutoff frequency. The heterojunction bipolar transistor includes a graded base layer formed from antimony. The graded base allows the heterojunction bipolar transistor to establish a quasi-electric field to yield an improved cutoff frequency.

Abstract: An AlN film as an underlayer is epitaxially grown on a substrate having a dislocation density of 1011/cm2 or below and a crystallinity of 90 seconds or below in full width at half maximum (FWHM) of an X-ray rocking curve at (002) reflection. Then, on the AlN film an n-GaN film is epitaxially grown as a conductive layer having a dislocation density of 1010/cm2 or below and a crystallinity of 150 seconds or below in full width at half maximum (FWHM) of an X-ray rocking curve at (002) reflection, to fabricate a semiconductor element.

Abstract: A heterojunction bipolar transistor (HBT), including an emitter formed from a first semiconductor material, a base formed from a second semiconductor material, and a grading structure between the emitter and the base is disclosed. The grading structure comprises a semiconductor material containing at least one element not present in the first and second semiconductor materials, where the grading structure has a conduction band energy substantially equal to a conduction band energy of the base at an interface between the base and the grading structure, and where the grading structure has a conduction band energy substantially equal to a conduction band energy of the emitter at an interface between the emitter and the grading structure.

Abstract: According to one exemplary embodiment, a heterojunction bipolar transistor comprises a base having a top surface. The heterojunction bipolar transistor further comprises a first spacer and a second spacer situated on the top surface of the base. The heterojunction bipolar transistor further comprises an intermediate oxide layer situated on the first and second oxide spacers. The heterojunction bipolar transistor further comprises an amorphous layer situated on the intermediate oxide layer. The heterojunction bipolar transistor further comprises an antireflective coating layer on the amorphous layer. The heterojunction bipolar transistor further comprises an emitter window opening situated between the first and second spacers, where the emitter window opening is defined by the top surface of the base, the first and second spacers, the intermediate oxide layer, the amorphous layer, and the antireflective coating layer.