Abstract: An NPN double heterostructure bipolar transistor (DHBT) is disclosed with a base region comprising a layer of p-type-doped indium gallium arsenide nitride (InGaAsN) sandwiched between n-type-doped collector and emitter regions. The use of InGaAsN for the base region lowers the transistor turn-on voltage, Von, thereby reducing power dissipation within the device. The NPN transistor, which has applications for forming low-power electronic circuitry, is formed on a gallium arsenide (GaAs) substrate and can be fabricated at commercial GaAs foundries. Methods for fabricating the NPN transistor are also disclosed.

Abstract: A phototransistor structure is disclosed. A sidewall is grown on the collector side and under the base. The surface of the sidewall is formed with a sidewall contact. When the contact is connected to an external voltage, the holes accumulated at the junction of the base and emitter can be quickly removed. This solves the problem in the prior art that using a bias between the base and the emitter to remove holes usually results in a large dark current (bias current), power consumption, and diminishing optoelectronic conversion gain.

Abstract: A composite Pt/Ti/WSi/Ni Ohmic contact has been fabricated by a physical deposition process which uses electron beam evaporation and dc-sputter deposition. The Ni based composite Ohmic contact on n-SiC is rapid thermally annealed (RTA) at 950° C. to 1000° C. for 30s to provide excellent current-voltage characteristics, an abrupt, void free contact-SiC interface, retention of the as-deposited contact layer width, smooth surface morphology and an absence of residual carbon within the contact layer and/or at the Ohmic contact-SiC interface. The annealed produced Ni2Si interfacial phase is responsible for the superior electrical integrity of the Ohmic contact to n-SiC. The effects of contact delamination due to stress associated with interfacial voiding has been eliminated. Wire bonding failure, non-uniform current flow and SiC polytype alteration due to extreme surface roughness have also been abolished.

Abstract: A bipolar junction transistor (BJT) includes a dielectric layer formed on a predetermined region of a substrate, an opening formed in the dielectric layer and a portion of the substrate being exposed, a heavily doped polysilicon layer formed on a sidewall of the opening to define a self-aligned base region in the opening, an intrinsic base doped region formed within the substrate and in a bottom of the opening by implanting through the self-aligned base region, a spacer formed on the heavily doped polysilicon layer to define a self-aligned emitter region in the opening, and an emitter conductivity layer being filled with the self-aligned emitter region and a PN junction being formed between the emitter conductivity layer and the intrinsic base doped region.

Abstract: A heterojunction bipolar transistor comprises, an emitter made of a first compound semiconductor of a first conductivity type; a base made of a second compound semiconductor of a second conductivity type and having a bandgap smaller than the first compound semiconductor; and a collector made of a third compound semiconductor of a first conductivity type and having a bandgap wider than the second compound semiconductor. The emitter and the base form a heterojunction of type I. The base and the collector form a heterojunction of type II. Further, the base includes impurities by a concentration equal to or more than 5×1019 cm−3.

Abstract: A structure is provided that ensures a low on-resistance and a better blocking effect. In a lateral type SIT (Static Induction Transistor) in which a first region is used as a p+ gate and a gate electrode is formed on the bottom of the first region, the structure is built such that the p+ gate and an n+ source are contiguous. An insulating film is formed on the surface of an n− channel, and an auxiliary gate electrode is formed on the insulating film. In addition, the auxiliary gate electrode and the source electrode are shorted.

Abstract: A silicon-germanium hetero bipolar transistor comprising a silicon collector layer, a boron-doped silicon-germanium base layer, a silicon emitter layer and an emitter contact area. The transistor is fabricated using an epitaxy process on a surface of pure silicon. An electrically inert material is incorporated into the epitaxial layers in order to link the defects in the semiconductor structure and to reduce the outdiffusion of the dopant. Thus, a transistor for high-frequency applications can be fabricated in two ways: to increase the dopant dose of the base region or to reduce the thickness of the base layer. In particular, carbon is incorporated in the base layer and in the collector layer and/or emitter layer.

Abstract: A silicon-germanium bipolar transistor includes a silicon substrate in which a first n-doped emitter region, a second p-doped base region adjoining the latter and a third n-doped collector region adjoining the latter, are formed. A first space charge zone is formed between the emitter region and the base region and a second space charge zone is formed between the base region and the collector region. The base region and an edge zone of the adjoining emitter region are alloyed with germanium. The germanium concentration in the emitter region rises toward the base region. The germanium concentration in a junction region containing the first space charge zone rises less sharply than in the emitter region or decreases and, in the base region, it initially again rises more sharply than in the junction region.

Abstract: A thin film crystal wafer with pn-junction comprising a first layer of a first conductivity type which is a 3-5 group compound semiconductor represented by a general formula: InxGayAlzP (0≦x≦1, 0≦y≦1, 0≦z≦, x+y+z=1), and the second layer of a first conductivity type which is a 3-5 group compound semiconductor represented by a general formula: InxGayAlZ,As (0≦x≦1, 0≦y≦1, 0≦z≦1, x+y+z=1), said second layer being made above said first layer, and at a heterojunction interface formed between said first layer and said second layer, further comprising a charge compensation layer of a first conductivity type with an impurity concentration higher than that of said first and second layers.

Abstract: A semiconductor device and method of fabricating the device. An emitter region is formed self centered and self aligned symmetrically with a base region. Using frontside processing techniques, a collector is formed symmetrically self-aligned with the base region and the emitter region. The collector region may be further formed self-centered with the base region using backside processing techniques. The self-aligned and self-centered symmetric structure virtually eliminates parasitic elements in the device significantly improving the device performance. The device is scalable on the order of approximately 0.1 microns. The method also provides reproduceability and repeatability of device characteristics necessary for commercial manufacture of the symmetric device.

Abstract: The speed at which optical networking devices operate is increased with the present invention with integrated circuits that provide both optical and electronic functions. The present invention provides highly integrated p-i-n or p-i-n-i-p photodetectors and heterojunction bipolar transistors for amplifying photodetector signals formed from a single semiconductor layer stack. The techniques are applicable for the integration of all InP-based and GaAs-based single-heterojunction bipolar transistors and double-heterojunction bipolar transistors. The photodetectors and transistors are formed from common layers, allowing them to be manufactured simultaneously during a processing of the stack. Integrating these components on a single circuit has the potential to greatly increase the speed (in excess of 40 Gb/s) and to decrease the cost of high-speed networking components through the development of compact optical circuits for optical networking.

Abstract: A semiconductor structure and a method of forming same is disclosed. The method includes forming, on a substrate, an n-doped collector structure of InAs/AlSb materials; forming a base structure on said collector structure which base structure comprises p-doped GaSb; and forming, on said base structure, an n-doped emitter structure of InAs/AlSb materials. The collector and emitter structure are preferably superlattices each comprising a plurality of periods of InAs and AlSb sublayers. A heterojunction bipolar transistor manufactured using the method is disclosed.

Abstract: A semiconductor device comprising a bipolar transistor having an emitter layer consisting of a semiconductor containing indium, and a protective insulating film containing silicon and oxygen which is formed on the surface of the guard ring of the emitter layer, wherein the protective insulating film has a density of oxygen of less than 7×1022 cm−3. This semiconductor device prevents performance deterioration and ensures high performance in a power amplifier.

Abstract: A transistor includes a base, a collector, and an emitter comprising a group III/VI semiconductor. Microcircuits having at least one metal oxide semiconductor (MOS) transistor and the previously described transistor are provided. Processes for manufacturing a transistor and a BiMOS microcircuit are also provided.

Abstract: A Pt alloyed reaction layer is formed under a base ohmic electrode. This alloyed reaction layer extends through a base protective layer so as to reach a base layer. Besides, a Pt alloyed reaction layer is formed under an emitter ohmic electrode. This alloyed reaction layer is formed only within a second emitter contact layer. With this constitution, the manufacturing cost for the HBT can be reduced and successful contact characteristics for the HBT can be obtained.

Abstract: Reduction in the base to collector capacitance of a heterojunction bipolar transistor, and, improved high frequency performance is achieved using existing materials and processes by undercutting the collector (5) under the base (7) along two parallel sides of the base mesa (7—FIG. 4), and providing a sloped collector edge (5—FIG. 6) along the remaining two parallel sides of the base. The foregoing is accomplished by selective etching and with the four sides of the mesa regions oriented as a non-rectangular parallelogram (7, 9—FIG. 4) in which one pair of sides is in parallel with one of the said [0 0 1] and [0 0 {overscore (1)}] planes of the crystalline structure and the other pair of sides in parallel with one of the [0 1 1] and [0 {overscore (1)} {overscore (1)}] planes of the crystalline structure.

Abstract: Disclosed are apparatus and methods for designing electrical contact for a bipolar emitter structure. The area of an emitter structure (106, 306, 400, 404) and the required current density throughput of an electrical contact structure (108, 308, 402, 406) are determined. A required electrical contact area is determined based on the required current density, and the electrical contact structure is then designed to minimize the required electrical contact area with respect to the emitter structure area.

Abstract: The invention provides a bipolar transistor attaining large MSG and a method of fabricating the same. The bipolar transistor of this invention includes a collector layer; abase layer deposited on the collector layer; and a semiconductor layer deposited on the base layer in the shape of a ring along the outer circumference of the base layer, the semiconductor layer includes a ring-shaped emitter region functioning as an emitter, and the outer edge of the emitter region and the outer edge of the base layer are disposed in substantially the same plane position.

Abstract: A bipolar transistor having base and collector regions of narrow bandgap semiconductor material and a minority-carrier excluding base contact has a base doping level greater than 1017 cm−3. The transistor has a greater dynamic range, greater AC voltage and power gain-bandwidth products and a lower base access resistance than prior art narrow band-gap bipolar transistors.

Abstract: It is to be made possible to eliminate unevenness of the inductances of bonding wires and to reduce the size of semiconductor devices. Over the surface of a semiconductor device in whose MISFET formation area a MISFET comprising a plurality of unit MISFETs connected in parallel, gate electrode pads electrically connected to the gate electrode of the MISFET and drain electrode pads electrically connected to the drain electrode of the same are arranged in a row each. The intervals of the gate electrode pads become gradually shorter from the end areas towards the central area of the electrode array of the gate electrode pads. The intervals of the drain electrode pads also become gradually shorter from the end areas towards the central area of the electrode array of the drain electrode pads.

Abstract: A silicon germanium heterojunction bipolar transistor device having a semiconductor region, and a diffusion region in the semiconductor region, wherein the diffusion region is boron-doped, wherein the semiconductor region comprises a carbon dopant therein to minimize boron diffusion, and wherein a combination of an amount of the dopant, an amount of the boron, and a size of the semiconductor region are such that the diffusion region has a sheet resistance of less than approximately 4 Kohms/cm2. Also, the diffusion region is boron-doped at a concentration of 1×1020/cm3 to 1×1021/cm3. Additionally, the semiconductor region comprises 5-25% germanium and 0-3% carbon. By adding carbon to the semiconductor region, the device achieves an electrostatic discharge robustness, which further causes a tighter distribution of a power-to-failure of the device, and increases a critical thickness and reduces the thermal strain of the semiconductor region.

Abstract: A Double Heterojunction Bipolar Transistor (DHBT) is disclosed employing a collector of InP, an emitter of InP or other material such as InAlAs, and a base of either a selected InxGa1−xAsySb1−y compound, which preferably is lattice-matched to InP or may be somewhat compressively strained thereto, or of a superlattice which mimics the selected InGaAsSb compound. When an emitter having a conduction band non-aligned with that of the base is used, such as InAlAs, the base-emitter junction is preferably graded using either continuous or stepped changes in bulk material, or using a chirped superlattice. Doping of the junction may include one or more delta doping layer to improve the shift of conduction band discontinuities provided by a grading layer, or to permit a wider depletion region.

Abstract: A transistor includes a base, a collector, and an emitter comprising a group III/VI semiconductor. Microcircuits having at least one metal oxide semiconductor (MOS) transistor and the previously described transistor are provided. Processes for manufacturing a transistor and a BiMOS microcircuit are also provided.

Abstract: A semiconductor component (100) includes a semiconductor substrate (16) that is formed with trench (27). A semiconductor layer (20) is formed in the trench for coupling a control signal (VB) through a sidewall (25) of the trench to route a current (Ic) through a bottom surface (23) of the trench.

Abstract: This invention provides a new configuration and manufacturing method of the hetero-junction bipolar transistor. According to the invention, the HBT comprises a semi-insulating InP substrate, a buffer layer on the substrate, a sub-collector layer, a collector layer, a base layer, an emitter layer, and an emitter contact layer These layers are sequentially grown on the buffer layer. Since a pre-processing of forming two depressions in the sub-collector layer before growing the collector layer, the top surface of the emitter layer becomes planar surface. This results on the reduction of pits induced in the etching of the emitter contact layer, thus enhances the reliability and the high frequency performance of the HBT.

Abstract: A semiconductor device including a semiconductive body having formed therein an active region and a termination feature which includes spaced field rings disposed around the active region and diffusion rings of the same conductivity type as, but different conductivity than the semiconductive body formed between each pair of field rings.

Abstract: A semiconductor device of the present invention includes a systematic structure layer of first conductivity type and having a systematically arranged structure. The systematic structure layer is formed on a collector contact layer of first conductivity type, which is connected to collector electrodes. A compensation layer of first conductivity type is formed on the systematic structure layer. A collector layer of first conductivity type is formed on the compensation layer. A base layer is formed on the collector layer and connected to base electrodes. An emitter layer is formed on the base electrode and connected to an emitter electrode. The semiconductor device reduces collector resistance and thereby improves reliability.

Abstract: A heterojunction bipolar transistor is provided having an improved current gain cutoff frequency. The heterojunction bipolar transistor includes a contact region formed from InGaAsSb. The contact region allows an emitter region of the heterojunction bipolar transistor to realize a lower contact resistance value to yield an improved cutoff frequency (fT).

Abstract: A hetero-bipolar transistor according to the present invention enhances reliability that relates to the breaking of wiring metal. The transistor comprises a semiconductor substrate, a sub-collector layer formed on a (100) surface of the substrate, a collector mesa formed on the sub-collector layer, and an emitter contact layer. The transistor further includes a collector electrode and wiring metal connected to the collector electrode. The edge of the sub-collector layer forms a step S, the angle of which is in obtuse relative to the substrate. Therefore, the wiring metal traversing the step S bends in obtuse angle at the step S, thus reducing the breaking of the wiring metal.

Abstract: A heterojunction bipolar transistor of the present invention is produced from a wafer including a substrate and a collector layer of a first conductivity type, a base layer of a second conductivity type and an emitter layer of the first conductivity type sequentially laminated on the substrate in this order. First, the wafer is etched up to a preselected depth of the collector layer via a first photoresist, which is formed at a preselected position on the emitter layer, serving as a mask. Subsequently, the collector layer etched with at least the sidewalls of the base layer and collector layer, which are exposed by the first etching step, and a second photoresist covering part of the surface of the collector layer contiguous with the sidewalls serving as a mask.

Abstract: The invention relates to a bipolar transistor and a method for producing same. The aim of the invention is to provide a bipolar transistor and a method for producing same, which during the use of a single-process poly-silicon technology with differential epitaxis for the production of bases overcomes the disadvantages of conventional systems, so as notably further to improve the high-speed properties of a bipolar transistor, provide the most conductive connections possible between the metal contacts and the active (internal) transistor region as well as a minimized passive transistor surface, while at the same time avoiding greater process complexity and increased contact resistances. To this end a surface relief is produced in the active emitter region by a wet-chemical process. A single-process poly-silicon bipolar transistor having a base produced by epitaxis in accordance with the invention permits a reduction in external base resistance without causing a deterioration in emitter properties.

Abstract: The present invention realizes a heterobipolar transistor using a SiGeC base layer in order to improve its electric characteristics. Specifically, the distribution of carbon and boron within the base layer is controlled so that the concentration of boron is higher than the concentration of carbon on the side bordering on the emitter layer, and upon the formation of the emitter layer, both boron and carbon are dispersed into a portion of the emitter layer that comes into contact with the base layer.

Abstract: A bipolar transistor device with a large current capacity is formed by connecting a plurality of transistor elements to each other in parallel, each transistor element having a collector layer, a base layer, and an emitter layer formed respectively in a semiconductor substrate. In the bipolar transistor device, the base layers of a plurality of the transistor elements are extended in parallel to each other and those base layers are separated from each other. In each separated base layer, a first base electrode is formed on a part of the base layer which is separated from an emitter junction with the emitter layer, and a second base electrode is formed on another portion of the base layer closer to the emitter junction than the first base electrode. To dispose the base electrodes of a plurality of the transistor elements in parallel to each other, a base wiring is connected to the first base electrodes of those elements electrically.

Abstract: A heterojunction bipolar transistor has a stack comprised of a base layer, an emitter layer and a ballast layer made of AlGaAs. The emitter layer is comprised of a single layer or a multiplicity of layers, and at least one of which is comprised of a material that prevents hole injection from the base layer into the ballast layer. Thus, the hole injection from the base layer into the emitter layer is prevented. Accordingly, it is able to prevent the conductivity modulation of the ballast layer that is the cause of a deterioration in temperature characteristics.

Abstract: A structure includes an etch stop layer and a cap layer. The etch stop layer is situated over a first oxide isolation region and a second oxide isolation region in a wafer. A window is situated in the cap layer and the etch stop layer. The window exposes a surface of the wafer situated between the first oxide isolation region and the second oxide isolation region. The surface is cleaned for epitaxially growing a semiconductor. The etch stop layer can comprise, for example, silicon. The cap layer can comprise, for example, silicon nitride, amorphous silicon or polycrystalline silicon. According to one embodiment, the structure can further comprise an epitaxially grown silicon-germanium structure on the surface. According to one embodiment, the surface includes a single crystal silicon collector and a base grown on the single crystal silicon collector, where the base is an epitaxially grown silicon-germanium structure.

Abstract: An emitter of a heterojunction bipolar transistor has a double-layer protrusion formed of a first emitter layer and a second emitter layer and protruded outside an external base region. The protrusion of 50 nm in total thickness is enough to prevent damage during formation of the protrusion by etching or during later fabricating processes. Penetration of moisture through damaged places is eliminated. A base ohmic electrode is continuously formed on the first and second emitter layers on the external base region up to the protrusion. Thus, the protrusion is reinforced so as to be further hard to damage. By ensuring a large area for the base ohmic electrode, an alignment margin can be taken during formation of a base lead electrode.

Abstract: The formation of routing traces on an external surface of a semiconductor device, such as a flip-chip, which has a plurality of ball or bump sites patterned in specific locations, wherein the ball or bump sites are in electrical communication with external communication traces which are used to route signals from the flip-chip integrated circuitry. Such external communication traces generally result in unused space on the exterior surface of the flip-chip. This unused space can be utilized for forming routing traces to connect portions of the internal circuitry of the flip-chip rather than forming such routing traces internally, for forming routing traces to connect two or more semiconductor dice, or for forming routing traces for use as repair mechanisms.

Abstract: A method and structure for a bipolar transistor with a semiconductor substrate having a surface and a shallow trench isolation (STI) in the surface. The STI has an edge, a crevice region in the STI adjacent the STI edge, a base region above the STI, a silicide above the base region, an emitter structure on the surface adjacent the base region, and a crevice cover between the emitter structure and the silicide. The crevice cover maintains spacing between the emitter structure and the silicide.

Abstract: Various embodiments of a novel transistor layout having improved electrical and heat dissipation characteristics are disclosed. Several embodiments include various intrinsic components contoured to the shape of the emitter. The various intrinsic components may include a collector layer center portion, a collector contact, a base pedestal, and/or a base contact. Additional embodiments include improved heat dissipation within single transistors. Still further embodiments include improved heat dissipation across a plurality of transistors.

Abstract: A semiconductor device including a bipolar transistor having an emitter layer consisting of a semiconductor containing indium, and a protective insulating film containing silicon and oxygen which is formed on the surface of the guard ring of the emitter layer, wherein the protective insulating film has a density of oxygen of less than 7×1022 cm−3. This semiconductor device prevents performance deterioration and ensures high performance in a power amplifier.

Abstract: In the present invention, a semiconductor device is formed which includes an MIM capacitor located on the upper surface of a heterostructure from which the emitter, base and collector sections of a nearby HBT are defined. In this way the capacitor and HBT share a substantially common structure, with the base and emitter electrodes of the HBT fashioned from the same metal layers as the upper and lower capacitor plates, respectively. Furthermore, as the insulator region of the capacitor is formed prior to definition of the HBT structure, the dielectric material used can be deposited by means of a plasma enhanced process, without damaging the HBT structure.

Abstract: A III-N compound semiconductor bipolar transistor structure and method of manufacture. An epitaxial layer structure is formed over a substrate. The epitaxial layer structure includes a nucleation layer, a buffer layer, an emitter layer containing first type dopants (conductive type) and a base layer containing second type dopants (conductive type). Ion implantation is conducted to form a first conductive region within the base layer for forming a collector terminal. A portion of the emitter layer is etched for forming an emitter terminal. In addition, two ion-implantation regions may form inside the base layer. The ion-implantation regions serve separately as the collector terminal and the emitter terminal of the bipolar transistor, respectively, so that a more planar transistor structure is formed.

Abstract: The present invention relates to a heterojunction bipolar transistor, and comprises a collector region, and a graded profile SiGe base layer overlying the collector region. The transistor further comprises a diffusion blocking layer overlying the graded profile SiGe base layer, and an emitter layer overlying the diffusion blocking layer. The diffusion blocking layer is operable to retard a diffusion of dopants therethrough from the emitter layer to the graded profile SiGe base layer, thereby allowing for a reduction in the thickness of the layer comprising a graded profile SiGe layer and a buffer layer. The thickness reduction allows increased Ge concentration in the base layer and the emitter/base doping profile is improved, each leading to improved transistor performance.

Abstract: The invention relates to a silicon germanium hetero bipolar transistor and a method of fabricating the epitaxial individual layers of a silicon germanium hetero bipolar transistor.

Abstract: The present invention relates to a hetero-bipolar transistor. This transistor comprises a semi-insulating InP substrate, a buffer layer on the substrate, a sub-collector layer on the buffer layer, a collector layer on the sub-collector layer, a base layer on the collector layer, a wide-gap emitter layer on the base layer and a emitter contact layer on the emitter layer. The emitter layer extends the emitter contact layer, so the edge of the emitter layer is apart from the emitter contact layer and entirely covers the region where the collector layer and the sub-collector layer are overlapped to each other. According to this configuration, the transistor shows the enhanced reliability and the improved high frequency performance.

Abstract: A method for forming a heterojunction bipolar transistor includes forming two sets of spacers on the sides of an emitter pedestal. After the first set of spacers is formed, first extrinsic base regions are implanted on either side of an intrinsic base. The second set of spacers is formed on the first set of spacers. Second extrinsic base regions are then implanted on respective sides of the intrinsic base. By using two sets of spacers, the first and second extrinsic base regions have different widths. This advantageously brings the combined extrinsic base structure closer to the emitter of the transistor but not closer to the collector. As a result, the base parasitic resistance is reduced along with collector-to-extrinsic base parasitic capacitance. The performance of the transistor is further enhanced as a result of the extrinsic base regions being self-aligned to the emitter and collector.

Abstract: A semiconductor component (100) includes a semiconductor substrate (16) that is formed with trench(27). A semiconductor layer (20) is formed in the trench for coupling a control signal (VB) through a sidewall (25) of the trench to route a current (Ic) through a bottom surface (23) of the trench.

Abstract: A differential negative resistance element includes a heavily doped GaAs layer interposed between a collector layer of lightly doped GaAs and an emitter layer of heavily doped AlGaAs, is shared between a base region between the collector layer and the emitter layer, a base contact region and a channel region between the base region and the base contact region, and a depletion layer is developed into the channel region together with the collector voltage so as to exhibit a differential negative resistance characteristics, wherein the channel region is formed through an epitaxial growth and etching so that the manufacturer easily imparts target differential negative resistance characteristics to the channel region.

Abstract: An edge illuminated epilayer waveguide phototransistor including a subcollector layer formed from an epitaxially grown quaternary semiconductor material, such as heavily doped InGaAsP. A collector region of undoped InGaAs is epitaxially grown on the subcollector layer. A base region of moderately doped InGaAs is epitaxially grown on the collector layer. An emitter region, including a doped InGaAsP layer, a doped InP layer, and a heavily doped InGaAs emitter contact layer, is epitaxially grown on the base layer. The various layers and regions are formed so as to define an edge-illuminated facet for receiving incident light. Also, the base does not have an ohmic contact so that the base thickness can be minimized. Finally, the base doping concentration is minimized so that the gain-bandwidth product can be maximized.

Abstract: A heterojunction bipolar transistor (HBT), having a substrate formed of indium phosphide (InP), and having emitter, base and collector layers formed over the substrate such that the base layer is disposed between the emitter and collector layers. The collector layer formed from InGaAs, and the collector layer being doped n-type. The emitter layer formed from InP, and the emitter layer being doped n-type. The base layer formed of indium gallium arsenide (InGaAs) and grown by MOCVD, the base layer being tensile strained and graded, and the base layer being doped p-type with carbon. A lattice mismatch, for at least a portion of the base layer, between the substrate and the base material is greater than 0.2%.