Abstract: An integrated circuit with at least one transistor is formed using a buffer structure on the substrate. The buffer structure includes one or more layers of buffer material and comprises indium, gallium, and phosphorous. A ratio of indium to gallium in the buffer structure increases from a lower value to a higher value such that the buffer structure has small changes in lattice constant to control relaxation and defects. A source and a drain are on top of the buffer structure and a body of Group III-V semiconductor material extends between and connects the source and the drain. A gate structure wrapped around the body, the gate structure including a gate electrode and a gate dielectric, wherein the gate dielectric is between the body and the gate electrode.

Abstract: An optoelectronic semiconductor device includes a semiconductor layer sequence having an active zone that generates radiation, a first electrode that supplies current directly to a bottom side of the semiconductor layer sequence, and a second electrode that supplies current and extends from the bottom side to a top side of the semiconductor layer sequence opposite the bottom side, wherein the second electrode includes at least one current distribution structure on the top side, and the current distribution structure is impermeable to the generated radiation and electrically connected in a plurality of contact regions to at least one further component of the second electrode and configured for lateral current distribution starting from the contact regions.

Abstract: A display unit includes multiple pixels, a first electrode, a partition wall, a light emission layer, and a second electrode. The multiple pixels each have a light emission region and a non-light emission region along a first direction. The first electrode is provided in the light emission region in each of the multiple pixels. The partition wall is provided between each two of the pixels that are adjacent to each other in a second direction. The second direction intersects the first direction. The light emission layer covers the first electrode and is provided in the light emission region and the non-light emission region in a continuous manner. The second electrode faces the first electrode across the light emission layer.

Abstract: A method of forming a semiconductor structure for a III-N semiconductor channel device and a device produced by the method are disclosed. The method includes: (i) forming a buffer structure on a Si-substrate, wherein forming the buffer structure includes: forming a superlattice including at least one superlattice block, each superlattice block including a repetitive sequence of superlattice units, each superlattice unit including a first layer and a second layer formed on the first layer, wherein the first layer is a carbon-doped AlxGa1-xN layer and the second layer is a carbon-doped AlyGa1-yN layer, wherein x and y differ from each other and 0?x?1, 0?y?1, and wherein said at least first and second layers are epitaxially grown at a temperature of 980° C. or lower, and (ii) forming a III-N semiconductor channel layer above the buffer structure wherein the channel layer is epitaxially grown at a temperature of 1040° C. or lower and is grown to a thickness of 1 ?m or smaller.

Abstract: The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.

Abstract: A bonded substrate for epitaxial growth and a method for forming the same are disclosed. The method includes steps of providing a first substrate, which has a first dopant concentration; providing a second substrate, which has a second dopant concentration, wherein the second dopant concentration is lower than the first dopant concentration; directly bonding a first surface of the first substrate with a second surface of the second substrate to form a bonded substrate; annealing the bonded substrate to form a high impedance layer in the bonded substrate; and removing part of the second substrate to expose the high impedance layer depending on the requirements whereby, the bonded substrate formed by the method could have a heavily doped substrate which includes a stronger strength and the impedance layer formed thereon, which could effectively increase the substrate strength, reduce the leakage current, and sustains a higher breakdown voltage.

Abstract: A semiconductor device including conductive lines is disclosed. First conductive lines each comprise a first portion, a second portion, and an enlarged portion, the enlarged portion connecting the first portion and the second portion of the first conductive line. The semiconductor device includes second conductive lines, at least some of the second conductive lines disposed between a pair of the first conductive lines, each second conductive line including a larger cross-sectional area at an end portion of the second conductive line than at other portions thereof. The semiconductor device includes a pad on each of the first conductive lines and the second conductive lines, wherein the pad on each of the second conductive lines is on the end portion thereof and the pad on each of the first conductive lines is on the enlarged portion thereof.

Abstract: This invention relates to identification of organic or nonorganic molecules dissolved in liquid solutions based on their internal dipole moment. These molecules include and are not limited to viruses, microbes, bacteria, and in general pathogens. The liquid solution provides a specific dielectric constant, which is directly related to the internal dipole moment of the dissolved pathogen. An electronic device namely PtSi-Porous Si schottky junction is proposed as the pathogen detector. This device, which is made of PtSi alloy covering the pores of an n-type Silicon substrate, is a sensitive indicator of the dielectric constant of the material filling its pores. In particular, such a device has a unique reverse biased current-voltage (IV) relation that is sensitive to changes in electric fields around its surface, which change its breakdown voltage.

Abstract: Exemplary embodiments provide materials and methods of forming high-quality semiconductor devices using lattice-mismatched materials. In one embodiment, a composite film including one or more substantially-single-particle-thick nanoparticle layers can be deposited over a substrate as a nanoscale selective growth mask for epitaxially growing lattice-mismatched materials over the substrate.

Abstract: A semiconductor die includes a substrate and a semiconductor body supported by the substrate and having a periphery which is devoid of active devices and terminates at an edge face of the semiconductor die. The semiconductor body includes a first III-nitride semiconductor layer and a plurality of second III-nitride semiconductor layers below the first III-nitride semiconductor layer. An uninsulated connection structure extends vertically in the periphery of the semiconductor body and provides a vertical leakage path for at least some of the second III-nitride semiconductor layers to the substrate, to a metallization layer disposed above the substrate, or to both. A corresponding method of manufacturing the semiconductor die is also described.

Abstract: An optical device includes an optical waveguide provided on a principal surface of a substrate. The optical waveguide includes a core and a cladding provided around the core. The cladding is configured by a substance having a refractive index smaller than 71.4% of the refractive index of the core. The core has constituent atoms substantially forming a diamond lattice structure. The optical waveguide has a light input/output part through which a light beam is input and/or output. The light input/output part decreases stepwise in thickness towards an output end while tapering down in its width. The core is provided in the light input/output part to have a (111) plane or an equivalent plane to the (111) plane exposed on a face of a riser of the stepwise thickness of the light input/output part.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate and a plurality of devices on the substrate, wherein a first device of the devices includes a first nitride semiconductor layer on the substrate, a second nitride semiconductor layer brought together with the first nitride semiconductor layer to form a first heterojunction interface, between the substrate and the first nitride semiconductor layer, a third nitride semiconductor layer brought together with the second nitride semiconductor layer to form a second heterojunction interface, between the substrate and the second nitride semiconductor layer, and a first contact electrically connected to the first and second heterojunction interfaces.

Abstract: A semiconductor device including a low conducting field-controlling element is provided. The device can include a semiconductor including an active region (e.g., a channel), and a set of contacts to the active region. The field-controlling element can be coupled to one or more of the contacts in the set of contacts. The field-controlling element can be formed of a low conducting layer of material and have a lateral resistance that is both larger than an inverse of a minimal operating frequency of the device and smaller than an inverse of a maximum control frequency of the device.

Abstract: According to one exemplary embodiment, a group III-V semiconductor device includes at least one transition layer situated over a substrate. The group III-V semiconductor device further includes a first strain-relieving interlayer situated over the at least one transition layer and a second strain-relieving interlayer situated over the first strain-relieving interlayer. The group III-V semiconductor device further includes a first group III-V semiconductor body situated over the second strain-relieving interlayer. The first and second strain-relieving interlayers comprise different semiconductor materials so as to reduce a strain in the first group III-V semiconductor body. The second strain-relieving interlayer can be substantially thinner than the first strain-relieving interlayer.

Abstract: An electronic device can include a substrate having a primary surface; a monocrystalline semiconductor film overlying the primary surface of the substrate; and a polycrystalline compound semiconductor layer adjacent to the monocrystalline semiconductor film. In an embodiment, the polycrystalline compound semiconductor layer has a dopant concentration at most 1×1016 atoms/cm3, a donor concentration of greater than 1×1017 donors/cm3, and is part of a contact of an electrode of a transistor. In another embodiment, the electronic device can further include an interconnect over the polycrystalline compound semiconductor layer, wherein a combination of the interconnect and polycrystalline compound semiconductor layer form an ohmic contact. In a further embodiment, a polycrystalline compound semiconductor layer can be adjacent to the monocrystalline semiconductor film, wherein an energy level of a conduction band of the polycrystalline compound semiconductor layer is lower than its Fermi energy level.

Abstract: Embodiments of the invention include a III-nitride light emitting layer disposed between an n-type region and a p-type region, a III-nitride layer including a nanopipe defect, and a nanopipe terminating layer disposed between the III-nitride light emitting layer and the III-nitride layer comprising a nanopipe defect. The nanopipe terminates in the nanopipe terminating layer.

Abstract: To provide an oxide composition, represented by: ZnO1?xSx+? (0<x?0.5, ?>0), where part of O sites of ZnO is substituted with an S atom, and another S atom is provided to an interstitial site by doping, and wherein the oxide composition is p-type.

Abstract: A nitride-based semiconductor diode includes a substrate, a first semiconductor layer disposed on the substrate, and a second semiconductor layer disposed on the first semiconductor layer. The first and second semiconductor layers include a nitride-based semiconductor. A first portion of the second semiconductor layer may have a thickness thinner than a second portion of the second semiconductor layer. The diode may further include an insulating layer disposed on the second semiconductor layer, a first electrode covering the first portion of the second semiconductor layer and forming an ohmic contact with the first semiconductor layer and the second semiconductor layer, and a second electrode separated from the first electrode, the second electrode forming an ohmic contact with the first semiconductor layer and the second semiconductor layer.

Abstract: Provided is a method for forming a two-dimensional array of semiconductor quantum confined structures. The method includes providing a layer that has first atoms and second atoms, the first atoms having a different size than the second atoms; providing an indenter template that includes at least one indenter structure extending from a surface of the indenter template; contacting the layer and the at least one indenter structure together with a pressure sufficient to generate an elastic deformation in the layer but without generating plastic deformation of the layer; annealing the layer; and forming at least one quantum confined structure in a region of the layer in a region of the layer not pressed by the at least one indenter structure.

Abstract: In a method of manufacturing an optical device including an optical waveguide having a core, a cladding and a light input/output part through which a light beam is input or output, a substrate is prepared which is provided with a uniform thickness of single-crystalline film having its constituent atoms forming a diamond lattice structure and its surface being neither the (111) plane nor its equivalent planes. In the single-crystalline film, a precursor structure is formed which has a precursor of light input/output part. A mask is formed such as to expose the precursor with the remaining part covered. The structure is immersed into an alkaline solution for wet etching with the (111) planes used as etch-stop planes.

Abstract: Boron carbide polymers prepared from orthocarborane icosahedra cross-linked with a moiety A wherein A is selected from the group consisting of benzene, pyridine. 1,4-diaminobenzene and mixtures thereof give positive magnetoresistance effects of 30%-80% at room temperature. The novel polymers may be doped with transitional metals to improve electronic and spin performance. These polymers may be deposited by any of a variety of techniques, and may be used in a wide variety of devices including magnetic tunnel junctions, spin-memristors and non-local spin valves.

Abstract: A field effect transistor (FET) disclosed herein comprising a substrate, a C-doped semiconductor layer disposed on the substrate, a channel layer disposed on the C-doped semiconductor layer, and an electron supply layer disposed on the channel layer. The FET further comprises a diffusion barrier layer disposed between the C-doped semiconductor layer and the channel layer, wherein the diffusion barrier layer contacts the channel layer directly.

Abstract: A monolithic multiple solar cell includes at least three partial cells, with a semiconductor mirror placed between two partial cells. The aim of the invention is to improve the radiation stability of said solar cell. For this purpose, the semiconductor mirror has a high degree of reflection in at least one part of a spectral absorption area of the partial cell which is arranged above the semiconductor mirror and a high degree of transmission within the spectral absorption range of the partial cell arranged below the semiconductor mirror.

Abstract: A power switching device includes a channel forming layer on a substrate which includes a 2-dimensional electron gas (2DEG), and a channel supply layer which corresponds to the 2DEG at the channel forming layer. A cathode is coupled to a first end of the channel supply layer and an anode is coupled to a second end of the channel supply layer. The channel forming layer further includes a plurality of depletion areas arranged in a pattern, and portions of the channel forming layer between the plurality of depletion areas are non-depletion areas.

Abstract: A semiconductor wafer comprises, on a semiconductor crystal layer forming wafer, a first semiconductor crystal layer, a second semiconductor crystal layer, and a third semiconductor crystal layer in this order, wherein both the etching rates of the first semiconductor crystal layer and the third semiconductor crystal layer by a first etching agent are higher than the etching rate of the second semiconductor crystal layer by the first etching agent, and both the etching rates of the first semiconductor crystal layer and the third semiconductor crystal layer by a second etching agent are lower than the etching rate of the second semiconductor crystal layer by the second etching agent.

Abstract: A method for manufacturing a compound semiconductor device so as to separate a first substrate from a compound semiconductor laminated structure which includes forming a first compound semiconductor layer over a first substrate containing AlxGa1-xN (0?x<1) and having a first band gap; forming a second compound semiconductor layer over the first compound semiconductor layer containing AlyInzGa1-y-zN (0<y<1, 0<y+z?1) and having a second band gap larger than the first band gap; forming a compound semiconductor laminated structure over the second compound semiconductor layer; and removing the first compound semiconductor layer while irradiating the first compound semiconductor layer with light having an energy between the first band gap and the second band gap, and thereby separating the first substrate from the compound semiconductor laminated structure.

Abstract: A semiconductor device includes an electron transit layer formed on a substrate; an electron supply layer formed on the electron transit layer; a doping layer formed on the electron supply layer, the doping layer being formed with a nitride semiconductor in which an impurity element to become p-type and C are doped; a p-type layer formed on the doping layer, the p-type layer being formed with a nitride semiconductor in which the impurity element to become p-type is doped; a gate electrode formed on the p-type layer; and a source electrode and a drain electrode formed on the doping layer or the electron supply layer. The p-type layer is formed in an area immediately below the gate electrode, and a density of the C doped in the doping layer is greater than or equal to 1×1017 cm?3 and less than or equal to 1×1019 cm?3.

Abstract: A semiconductor device includes a first compound semiconductor material and a second compound semiconductor material on the first compound semiconductor material. The second compound semiconductor material comprises a different material than the first compound semiconductor material such that the first compound semiconductor material has a two-dimensional electron gas (2DEG). The semiconductor device further includes a buried field plate disposed in the first compound semiconductor material and electrically connected to a terminal of the semiconductor device. The 2DEG is interposed between the buried field plate and the second compound semiconductor material.

Abstract: A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A carrier channel depleting layer is disposed on the second III-V compound layer. The carrier channel depleting layer is deposited using plasma and a portion of the carrier channel depleting layer is under at least a portion of the gate electrode.

Abstract: The present invention concerns a method for forming a Semiconductor-On-Insulator structure that includes a semiconductor layer of III/V material by growing a relaxed germanium layer on a donor substrate; growing at least one layer of III/V material on the layer of germanium; forming a cleaving plane in the relaxed germanium layer; transferring a cleaved part of the donor substrate to a support substrate, with the cleaved part being a part of the donor substrate cleaved at the cleaving plane that includes the at least one layer of III/V material. The present invention also concerns a germanium on III/V-On-Insulator structure, an N Field-Effect Transistor (NFET), a method for manufacturing an NFET, a P Field-Effect Transistor (PFET), and a method for manufacturing a PFET.

Abstract: According to one embodiment a nitride semiconductor device includes a first, a second and a third semiconductor layer, a first and a second main electrode and a control electrode. The first layer made of a nitride semiconductor of a first conductivity type is provided on a substrate. The second layer made of a nitride semiconductor of a second conductivity type is provided on the first layer. The third layer made of a nitride semiconductor is provided on the second layer. The first electrode is electrically connected with the second layer. The second electrode is provided at a distance from the first electrode and electrically connected with the second layer. The control electrode is provided within a first trench via an insulating film. The first trench is disposed between the first and the second main electrodes, penetrates the third and the second layers, and reaches the first layer.

Abstract: First and second template epitaxial semiconductor material portions including different semiconductor materials are formed within a dielectric template material layer on a single crystalline substrate. Heteroepitaxy is performed to form first and second epitaxial semiconductor portions on the first and second template epitaxial semiconductor material portions, respectively. At least one dielectric bonding material layer is deposited, and a handle substrate is bonded to the at least one dielectric bonding material layer. The single crystalline substrate, the dielectric template material layer, and the first and second template epitaxial semiconductor material portions are subsequently removed. Elemental semiconductor devices and compound semiconductor devices can be formed on the first and second semiconductor portions, which are embedded within the at least one dielectric bonding material layer on the handle substrate.

Abstract: An improved heterostructure for an optoelectronic device is provided. The heterostructure includes an active region, an electron blocking layer, and a p-type contact layer. The p-type contact layer and electron blocking layer can be doped with a p-type dopant. The dopant concentration for the electron blocking layer can be at most ten percent the dopant concentration of the p-type contact layer. A method of designing such a heterostructure is also described.

Abstract: A semiconductor film composition includes an oxide semiconductor material. At least one polyatomic ion is incorporated into the oxide semiconductor material.

Abstract: A semiconductor device is provided with: a GaN layer; an anode electrode that forms a Schottky junction with a Ga face of the GaN layer; and an InGaN layer positioned between at least a part of the anode electrode and the GaN layer.

Abstract: A transistor includes a substrate, a channel layer over the substrate and an active layer over the channel layer. The active layer includes a gradient having a first concentration of a first material at an interface with the channel layer and a second concentration of the first material at a surface opposite the channel layer, and the first concentration is higher than the second concentration.

Abstract: A photovoltaic device comprises an interface (8) between a layer of Group III-V material (3) and a layer of Group IV material (1) with a thin silicon diffusion barrier (6) provided at or near the interface. The silicon barrier controls the diffusion of Group V atoms into the Group IV material, which is doped n-type thereby. The n-type doped region can provide the p-n junction of a solar cell in the Group IV material with superior solar cell properties. It can also provide a tunnel diode in contact with a p-type region of the III-V material, which tunnel diode is also useful in solar cells. In another aspect, a multijunction photovoltaic device is provided in which there are at least a first light-absorbing layer (111) of SiGe or SiGeSn and a second light-absorbing layer (112) of SiGeSn, both layers being lattice-matched to GaAs.

Abstract: A diode is described with a III-N material structure, an electrically conductive channel in the III-N material structure, two terminals, wherein a first terminal is an anode adjacent to the III-N material structure and a second terminal is a cathode in ohmic contact with the electrically conductive channel, and a dielectric layer over at least a portion of the anode. The anode comprises a first metal layer adjacent to the III-N material structure, a second metal layer, and an intermediary electrically conductive structure between the first metal layer and the second metal layer. The intermediary electrically conductive structure reduces a shift in an on-voltage or reduces a shift in reverse bias current of the diode resulting from the inclusion of the dielectric layer. The diode can be a high voltage device and can have low reverse bias currents.

Abstract: A semiconductor device includes a substrate, a buffer layer on the substrate, and a plurality of nitride semiconductor layers on the buffer layer. The semiconductor device further includes at least one masking layer and at least one inter layer between the plurality of nitride semiconductor layers. The at least one inter layer is on the at least one masking layer.

Abstract: An epitaxial substrate for electronic devices, in which current flows in a lateral direction and of which warpage configuration is properly controlled, and a method of producing the same. The epitaxial substrate for electronic devices is produced by forming a bonded substrate by bonding a low-resistance Si single crystal substrate and a high-resistance Si single crystal substrate together; forming a buffer as an insulating layer on a surface of the bonded substrate on the high-resistance Si single crystal substrate side; and producing an epitaxial substrate by epitaxially growing a plurality of III-nitride layers on the buffer to form a main laminate. The resistivity of the low-resistance Si single crystal substrate is 100 ?·cm or less, and the resistivity of the high-resistance Si single crystal substrate is 1000 ?·cm or more.

Abstract: A semiconductor device includes a first layer and a second layer over the first layer. The first and second layers are configured to form an electron gas layer at an interface of the first and second layers. The semiconductor device also includes an Ohmic contact and multiple conductive vias through the second layer. The conductive vias are configured to electrically couple the Ohmic contact to the electron gas layer. The conductive vias could have substantially vertical sidewalls or substantially sloped sidewalls, or the conductive vias could form a nano-textured surface on the Ohmic contact. The first layer could include Group III-nitride nucleation, buffer, and channel layers, and the second layer could include a Group III-nitride barrier layer.

Abstract: Si(1-v-w-x)CwAlxNv crystals in a mixed crystal state are formed. A method for manufacturing an easily processable Si(1-v-w-x)CwAlxNv substrate, a method for manufacturing an epitaxial wafer, a Si(1-v-w-x)CwAlxNv substrate, and an epitaxial wafer are provided. A method for manufacturing a Si(1-v-w-x)CwAlxNv substrate 10a includes the following steps. First, a Si substrate 11 is prepared. A Si(1-v-w-x)CwAlxNv layer 12 (0<v<1, 0?w<1, 0<x<1, and 0<v+w+x<1) is then grown on the Si substrate 11 by a pulsed laser deposition method.

Abstract: In accordance with one or more embodiments, an apparatus and method involves a channel region, barrier layers separated by the channel region and a dielectric on one of the barrier layers. The barrier layers have band gaps that are different than a band gap of the channel region, and confine both electrons and holes in the channel region. A gate electrode applies electric field to the channel region via the dielectric. In various contexts, the apparatus and method are amenable to implementation for both electron-based and hole-based implementations, such as for nmos, pmos, and cmos applications.

Abstract: In one embodiment, a method of forming a semiconductor device is provided that may include forming a semiconductor device including a gate structure on a channel portion of III-V semiconductor substrate. The III-V semiconductor substrate including a III-V base substrate layer, an aluminum containing III-V semiconductor layer that is present on the III-V base substrate layer, and a III-V channel layer. Oxidizing a portion of the aluminum containing III-V semiconductor layer on opposing sides of the gate structure. Forming a raised source region and a raised drain region over the portion of the aluminum containing III-V semiconductor layer that has been oxidized. Forming interconnects to the raised source region and the raised drain region.

Abstract: The invention relates to light-emitting devices; in particular, to highly effective light-emitting diodes on the base of nitrides of III group elements of the periodic system. The light-emitting device includes a substrate, a buffer layer formed on the substrate, a first layer from n-type semiconductor formed on the buffer layer, a second layer from p-type semiconductor and an active layer arranged between the first and second layers. The first, second and active layers form interlacing of the layers with zinc blend phase structure and layers with wurtzite phase structure forming heterophase boundaries therebetween. Technical result of the invention is increasing the effectiveness (efficiency) of the light-emitting device at the expense of heterophase boundaries available in the light-emitting device which allow to eliminate formation of the potential wells for holes, to increase the uniformity of the hole distribution in the active layer and to ensure suppression of nonradiative Auger recombination.

Abstract: The disclosure relates to multiple quantum well (MQW) structures for intrinsic regions of monolithic photovoltaic junctions within solar cells which are substantially lattice matched to GaAs or Ge. The disclosed MQW structures incorporate quantum wells formed of quaternary InGaAsP, between barriers of InGaP.

Abstract: A III nitride structure includes a film 108 having a surface composed of a metal formed in a predetermined region on the surface of a substrate 102, and a fine columnar crystal 110 composed of at least a III nitride semiconductor formed on the surface of the substrate 102, wherein the spatial occupancy ratio of the fine columnar crystal 110 is higher on the surface of the substrate 102 where the film 108 is not formed than that on the film.

Abstract: Heterojunction bipolar transistors are provided that include at least one contact (e.g., collector, and/or emitter, and/or base) formed by a heterojunction between a crystalline semiconductor material and a doped non-crystalline semiconductor material layer. A highly doped epitaxial semiconductor layer comprising a highly doped hydrogenated crystalline semiconductor material layer portion is present at the heterojunction between the crystalline semiconductor material and the doped non-crystalline semiconductor material layer. Minority carriers within the highly doped epitaxial semiconductor layer have a diffusion length that is larger than a thickness of the highly doped epitaxial semiconductor layer.

Abstract: In one embodiment, a method of forming a semiconductor device is provided that may include forming a semiconductor device including a gate structure on a channel portion of III-V semiconductor substrate. The III-V semiconductor substrate including a III-V base substrate layer, an aluminum containing III-V semiconductor layer that is present on the III-V base substrate layer, and a III-V channel layer. Oxidizing a portion of the aluminum containing III-V semiconductor layer on opposing sides of the gate structure. Forming a raised source region and a raised drain region over the portion of the aluminum containing III-V semiconductor layer that has been oxidized. Forming interconnects to the raised source region and the raised drain region.

Abstract: In one embodiment, a method of forming a semiconductor device is provided that may include forming a semiconductor device including a gate structure on a channel portion of III-V semiconductor substrate. The III-V semiconductor substrate including a III-V base substrate layer, an aluminum containing III-V semiconductor layer that is present on the III-V base substrate layer, and a III-V channel layer. Oxidizing a portion of the aluminum containing III-V semiconductor layer on opposing sides of the gate structure. Forming a raised source region and a raised drain region over the portion of the aluminum containing III-V semiconductor layer that has been oxidized. Forming interconnects to the raised source region and the raised drain region.