Between Different Group Iv-vi Or Ii-vi Or Iii-v Compounds Other Than Gaas/gaalas Patents (Class 257/201)
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Patent number: 8872231Abstract: A semiconductor wafer includes a first semiconductor, and a second semiconductor formed directly or indirectly on the first semiconductor. The second semiconductor contains a first impurity atom exhibiting p-type or n-type conductivity, and a second impurity atom selected such that the Fermi level of the second semiconductor containing both the first and second impurity atoms is closer to the Fermi level of the second semiconductor containing neither the first impurity atom nor the second impurity atom, than the Fermi level of the second semiconductor containing the first impurity atom is. For example, the majority carrier of the second semiconductor is an electron, and the Fermi level of the second semiconductor containing the first and second impurity atoms is lower than the Fermi level of the second semiconductor containing the first impurity atom.Type: GrantFiled: November 21, 2011Date of Patent: October 28, 2014Assignee: Sumitomo Chemical Company, LimitedInventor: Osamu Ichikawa
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Patent number: 8872238Abstract: The present invention is related to a method for manufacturing a low defect interface between a dielectric material and an III-V compound. More specifically, the present invention relates to a method for manufacturing a passivated interface between a dielectric material and an III-V compound. The present invention is also directed to a device comprising a low defect interface between a dielectric material and an III-V compound that has improved performance.Type: GrantFiled: October 17, 2012Date of Patent: October 28, 2014Assignee: IMECInventor: Clement Merckling
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Patent number: 8866193Abstract: According to one disclosed embodiment, a monolithic vertically integrated composite device comprises a double sided semiconductor substrate having first and second sides, a group IV semiconductor layer formed over the first side and comprising at least one group IV semiconductor device, and a group III-V semiconductor body formed over the second side and comprising at least one group III-V semiconductor device electrically coupled to the at least one group IV semiconductor device. The composite device may further comprise a substrate via and/or a through-wafer via providing electric coupling. In one embodiment, the group IV semiconductor layer may comprise an epitaxial silicon layer, and the at least one group IV semiconductor device may be a combined FET and Schottky diode (FETKY) fabricated on the epitaxial silicon layer. In one embodiment, the at least one group semiconductor device may be a III-nitride high electron mobility transistor (HEMT).Type: GrantFiled: October 9, 2013Date of Patent: October 21, 2014Assignee: International Rectifier CorporationInventor: Michael A. Briere
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Patent number: 8866195Abstract: A semiconductor device comprises a semiconductor substrate; a channel layer of at least a first III-V semiconductor compound above the semiconductor substrate; a gate stack structure above a first portion of the channel layer; a source region and a drain region comprising at least a second III-V semiconductor compound above a second portion of the channel layer; and a first metal contact structure above the S/D regions comprising a first metallic contact layer contacting the S/D regions. The first metallic contact layer comprises at least one metal-III-V semiconductor compound.Type: GrantFiled: July 6, 2012Date of Patent: October 21, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Richard Kenneth Oxland
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Publication number: 20140307997Abstract: Photonic passivation layers, III-V semiconductor die with offcut edges, and NiGe contact metallization for silicon-based photonic integrated circuits (PICs). In embodiments, a non-sacrificial passivation layer is formed on a silicon photonic element, such as a waveguide for protection of the waveguide surfaces. In embodiments, a III-V semiconductor film is transferred from a III-V growth substrate that is singulated along streets that are misaligned from cleave planes to avoid crystallographic etch artifacts in a layer transfer process. In embodiments, a NiGe contact metallization is employed for both p-type and n-type contacts on a device formed in the transferred III-V semiconductor layer to provide low specific contact resistance and compatibility with MOS processes.Type: ApplicationFiled: December 20, 2011Publication date: October 16, 2014Inventors: Hanan Bar, John Heck, Avi Feshali, Ran Feldesh
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Patent number: 8860038Abstract: Provided is a nitride semiconductor device comprising a base substrate; a buffer layer formed above the base substrate; an active layer formed on the buffer layer; and at least two electrodes formed above the active layer. The buffer layer includes one or more composite layers that each have a plurality of nitride semiconductor layers with different lattice constants, and at least one of the one or more composite layers is doped with carbon atoms and oxygen atoms in at least a portion of a carrier region of the nitride semiconductor having the largest lattice constant among the plurality of nitride semiconductor layers, the carrier region being a region in which carriers are generated due to the difference in lattice constants between this nitride semiconductor layer and the nitride semiconductor layer formed directly thereon.Type: GrantFiled: September 14, 2012Date of Patent: October 14, 2014Assignee: Furukawa Electric Co., Ltd.Inventors: Masayuki Iwami, Takuya Kokawa
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Publication number: 20140264408Abstract: Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising InwGa1-wN, and at least one barrier layer comprising InbGa1-bN proximate the at least one well layer. In some embodiments, the value of w in the InwGa1-wN of the well layer may be greater than or equal to about 0.10 and less than or equal to about 0.40 in some embodiments, and the value of b in the InbGa1-bN of the at least one barrier layer may be greater than or equal to about 0.01 and less than or equal to about 0.10. Methods of forming semiconductor structures include growing such layers of InGaN to form an active region of a light emitting device, such as an LED. Luminary devices include such LEDs.Type: ApplicationFiled: March 14, 2014Publication date: September 18, 2014Applicant: SoitecInventors: Jean-Philippe Debray, Chantal Arena, Heather McFavilen, Ding Ding, Li Huang
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Publication number: 20140264459Abstract: An electronic device includes a trigonal crystal substrate defining a (0001) C-plane. The substrate may comprise Sapphire or other suitable material. A plurality of rhomhohedrally aligned SiGe (111)-oriented crystals are disposed on the (0001) C-plane of the crystal substrate. A first region of material is disposed on the rhombohedrally aligned SiGe layer. The first region comprises an intrinsic or doped Si, Ge, or SiGe layer. The first region can be layered between two secondary regions comprising n+doped SiGe or n+doped Ge, whereby the first region collects electrons from the two secondary regions.Type: ApplicationFiled: March 10, 2014Publication date: September 18, 2014Applicant: U.S.A. as represented by the National Aeronautics and Space AdministrationInventors: Sang Hyouk Choi, Yeonjoon Park, Glen C. King, Hyun-Jung Kim, Kunik Lee
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Patent number: 8829488Abstract: Provided is a laminate containing a first compound semiconductor layer; and a second compound semiconductor layer integrally bonded to the first compound semiconductor layer via a bonding layer. A plane A is in the second compound semiconductor layer bonded to a surface where a plane B is in the first compound semiconductor layer, or a surface where a plane B is in the second compound semiconductor layer bonded to a surface where a plane A in the first compound semiconductor layer. The impurity concentration of the bonding layer is 2×1018 cm3 or more.Type: GrantFiled: August 27, 2012Date of Patent: September 9, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kazuyoshi Furukawa, Yasuhiko Akaike, Shunji Yoshitake
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Patent number: 8829569Abstract: A semiconductor apparatus includes a first semiconductor layer formed on a substrate, a second semiconductor layer formed on the first semiconductor layer, a gate recess formed by removing at least a portion of the second semiconductor layer, an insulation film formed on the gate recess and the second semiconductor layer, a gate electrode formed on the gate recess via the insulation film, source and drain electrodes formed on one of the first and the second semiconductor layers, and a fluorine containing region formed in at least one of a part of the first semiconductor layer corresponding to a region in which the gate recess is formed and a part of the second semiconductor layer corresponding to the region in which the gate recess is formed.Type: GrantFiled: November 7, 2011Date of Patent: September 9, 2014Assignee: Fujitsu LimitedInventors: Toshihiro Ohki, Hiroshi Endo
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Patent number: 8829566Abstract: A semiconductor waveguide based optical receiver is disclosed. An apparatus according to aspects of the present invention includes an absorption region including a first type of semiconductor region proximate to a second type of semiconductor region. The first type of semiconductor is to absorb light in a first range of wavelengths and the second type of semiconductor to absorb light in a second range of wavelengths. A multiplication region is defined proximate to and separate from the absorption region. The multiplication region includes an intrinsic semiconductor region in which there is an electric field to multiply the electrons created in the absorption region.Type: GrantFiled: March 15, 2007Date of Patent: September 9, 2014Assignee: Intel CorporationInventors: Michael T. Morse, Olufemi I. Dosunmu, Ansheng Liu, Mario J. Paniccia
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Patent number: 8815688Abstract: A method of manufacturing a power device includes forming a first drift region on a substrate. A trench is formed by patterning the first drift region. A second drift region is formed by growing n-gallium nitride (GaN) in the trench, and alternately disposing the first drift region and the second drift region. A source electrode contact layer is formed on the second drift region. A source electrode and a gate electrode are formed on the source electrode contact layer. A drain electrode is formed on one side of the substrate which is an opposite side of the first drift region.Type: GrantFiled: July 17, 2012Date of Patent: August 26, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jae Hoon Lee, Ki Se Kim, Jung Hee Lee, Ki Sik Im, Dong Seok Kim
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Patent number: 8803158Abstract: A High Electron Mobility Transistor (HEMT) includes a first III-V compound layer having a first band gap, and a second III-V compound layer having a second band gap over the first III-V compound layer. The second band gap is greater than the first band gap. A crystalline interfacial layer is overlying and in contact with the second III-V compound layer. A gate dielectric is over the crystalline interfacial layer. A gate electrode is over the gate dielectric. A source region and a drain region are over the second III-V compound layer, and are on opposite sides of the gate electrode.Type: GrantFiled: February 18, 2013Date of Patent: August 12, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Han-Chin Chiu, Po-Chun Liu, Chi-Ming Chen, Chung-Yi Yu, King-Yuen Wong
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Patent number: 8779435Abstract: A semiconductor wafer has a plurality of optical semiconductor devices (namely, semiconductor lasers) which are formed from epitaxially grown layers and arranged across the surface of the semiconductor wafer. The InGaAs epitaxial layer of the semiconductor wafer has an opening (or groove) which continuously extends along and between the plurality of optical semiconductor devices, and which exposes the layer underlying the InGaAs epitaxial layer to at least the layer overlying the InGaAs epitaxial layer. The semiconductor wafer may be scribed along this opening to form a vertically extending crack therein.Type: GrantFiled: October 12, 2011Date of Patent: July 15, 2014Assignee: Mitsubishi Electric CorporationInventor: Masato Negishi
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Patent number: 8772832Abstract: The present invention reduces the dynamic on resistance in the channel layer of a GaN device by etching a void in the nucleation and buffer layers between the gate and the drain. This void and the underside of the device substrate may be plated to form a back gate metal layer. The present invention increases the device breakdown voltage by reducing the electric field strength from the gate to the drain of a HEMT. This electric field strength is reduced by placing a back gate metal layer below the active region of the channel. The back gate metal layer may be in electrical contact with the source or drain.Type: GrantFiled: May 17, 2011Date of Patent: July 8, 2014Assignee: HRL Laboratories, LLCInventor: Karim S Boutros
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Patent number: 8772826Abstract: It is an object to provide a photoelectric conversion device with high photoelectric conversion efficiency. The photoelectric conversion device includes an electrode layer, and a light absorbing layer located on the electrode layer. The light absorbing layer is comprised of a plurality of stacked semiconductor layers containing a chalcopyrite-based compound semiconductor. The semiconductor layers contain oxygen. A molar concentration of the oxygen in surfaces and their vicinities of the semiconductor layers where the semiconductor layers are stacked on each other is higher than average molar concentrations of the oxygen in the semiconductor layers.Type: GrantFiled: May 30, 2011Date of Patent: July 8, 2014Assignee: KYOCERA CorporationInventors: Hideaki Asao, Rui Kamada, Shuichi Kasai, Seiji Oguri, Isamu Tanaka, Nobuyuki Horiuchi, Kazumasa Umesato
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Patent number: 8772623Abstract: Low bandgap, monolithic, multi-bandgap, optoelectronic devices (10), including PV converters, photodetectors, and LED's, have lattice-matched (LM), double-heterostructure (DH), low-bandgap GaInAs(P) subcells (22, 24) including those that are lattice-mismatched (LMM) to InP, grown on an InP substrate (26) by use of at least one graded lattice constant transition layer (20) of InAsP positioned somewhere between the InP substrate (26) and the LMM subcell(s) (22, 24). These devices are monofacial (10) or bifacial (80) and include monolithic, integrated, modules (MIMs) (190) with a plurality of voltage-matched subcell circuits (262, 264, 266, 270, 272) as well as other variations and embodiments.Type: GrantFiled: October 30, 2012Date of Patent: July 8, 2014Assignee: Alliance for Sustainable Energy, LLCInventors: Mark W. Wanlass, Jeffrey J. Carapella
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Patent number: 8759881Abstract: A heterostructure that includes, successively, a support substrate of a material having an electrical resistivity of less than 10?3 ohm·cm and a thermal conductivity of greater than 100 W·m?1·K?1, a bonding layer, a first seed layer of a monocrystalline material of composition AlxInyGa(1-x-y)N, a second seed layer of a monocrystalline material of composition AlxInyGa(1-x-y)N, and an active layer of a monocrystalline material of composition AlxInyGa(1-x-y)N, and being present in a thickness of between 3 and 100 micrometers. The materials of the support substrate, the bonding layer and the first seed layer are refractory at a temperature of greater than 750° C., the active layer and second seed layer have a difference in lattice parameter of less than 0.005 ?, the active layer is crack-free, and the heterostructure has a specific contact resistance between the bonding layer and the first seed layer that is less than or equal to 0.1 ohm·cm2.Type: GrantFiled: December 1, 2010Date of Patent: June 24, 2014Assignee: SoitecInventors: Jean-Marc Bethoux, Fabrice Letertre, Chris Werkhoven, Ionut Radu, Oleg Kononchuck
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Patent number: 8754421Abstract: Forming an alignment mark on a semiconductor structure using an optical lithography to form a metal alignment mark on a substrate of the structure, using the formed metal alignment mark to form a first feature of a semiconductor device being formed on the substrate using optical lithography, and using the formed metal alignment mark to form a second, different feature for the semiconductor using electron beam lithography. In one embodiment, the first feature is an ohmic contact, the second feature is a Schottky contact, the metal alignment mark is a refractory metal or a refractory metal compound having an atomic weight greater than 60 such as TaN and the semiconductor device is a GaN semiconductor device. A semiconductor structure having a metal alignment mark on a zero layer of the structure, the metal alignment mark is a TaN and the semiconductor is GaN.Type: GrantFiled: February 24, 2012Date of Patent: June 17, 2014Assignee: Raytheon CompanyInventors: Paul J. Duval, Kamal Tabatabaie, William J. Davis
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Patent number: 8736061Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, an integrated circuit includes a standard cell having a first boundary, a second boundary opposite the first boundary, a third boundary interconnecting the first and second boundaries, and a fourth boundary opposite the third boundary and interconnecting the first and second boundaries. The standard cell further includes parallel active areas extending from the first boundary to the second boundary. Also, the standard cell has parallel gate strips extending from the third boundary to the fourth boundary and over the active areas. A cut mask overlies the gate strips. An interconnect is positioned overlying the cut mask and forms an electrical connection with a selected gate strip.Type: GrantFiled: June 7, 2012Date of Patent: May 27, 2014Assignees: GLOBALFOUNDRIES, Inc., International Business Machines, STMicroelectronics, Inc.Inventors: Frank Johnson, Olivier Menut, Marc Tarabbia, Gregory A. Northrop
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Publication number: 20140138698Abstract: A semiconductor device includes a substrate, a first active layer disposed over the substrate and a second active layer disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. A first electrode has a first portion disposed in a recess in the second active layer and a second portion disposed on the second active layer such that a Schottky junction is formed therewith. The first portion of the first electrode has a lower Schottky potential barrier than the second portion of the first electrode. A second electrode is in contact with the first active layer.Type: ApplicationFiled: November 16, 2012Publication date: May 22, 2014Applicant: Vishay General Semiconductor LLCInventor: Yih-Yin Lin
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Publication number: 20140138697Abstract: A semiconductor device such as a Schottky diode is provided which includes a substrate, a first active layer disposed over the substrate and a second active layer disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. A first electrode has a first portion disposed in a recess in the second active layer and a second portion disposed on the second active layer such that a Schottky junction is formed therewith. A second electrode is in contact with the first active layer. The second electrode establishes an ohmic junction with the first active layer.Type: ApplicationFiled: November 16, 2012Publication date: May 22, 2014Applicant: Vishay General Semiconductor LLCInventor: Yih-Yin Lin
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Patent number: 8710551Abstract: The present invention discloses a high electron mobility transistor (HEMT) and a manufacturing method thereof. The HEMT includes a semiconductor layer, a barrier layer on the semiconductor layer, a piezoelectric layer on the barrier layer, a gate on the piezoelectric layer, and a source and a drain at two sides of the gate respectively, wherein each bandgap of the semiconductor layer, the barrier layer, and the piezoelectric layer partially but not entirely overlaps the other two bandgaps. The gate is formed for receiving a gate voltage. A two dimensional electron gas (2DEG) is formed in a portion of a junction between the semiconductor layer and the barrier layer but not below at least a portion of the piezoelectric layer, wherein the 2DEG is electrically connected to the source and the drain.Type: GrantFiled: August 29, 2012Date of Patent: April 29, 2014Assignee: Richtek Technology Corporation, R.O.C.Inventors: Chih-Fang Huang, Chien-Wei Chiu, Ting-Fu Chang, Tsung-Yu Yang, Tsung-Yi Huang
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Publication number: 20140097433Abstract: A semiconductor device includes a substrate; a carrier traveling layer formed on the substrate, made of first group III nitride semiconductor, and containing carriers traveling in a direction along a principal surface of the substrate; a barrier layer formed on the carrier traveling layer and made of second group III nitride semiconductor having a wider band gap than the first group III nitride semiconductor; and an electrode formed on the barrier layer. The device further includes a cap layer formed on the barrier layer at a side of the electrode, and made of third group III nitride semiconductor containing a mixture of single crystals and polycrystals.Type: ApplicationFiled: December 11, 2013Publication date: April 10, 2014Applicant: Panasonic CorporationInventors: Noboru NEGORO, Hidekazu UMEDA, Nanako HIRASHITA, Tetsuzo UEDA
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Publication number: 20140097473Abstract: A semiconductor device includes: an electron transit layer formed on a substrate and of a group III nitride-based compound semiconductor; an electron supply layer formed on the electron transit layer and of a group III nitride-based compound semiconductor having a higher band gap energy than the transit layer; a field plate layer formed on the supply layer, formed of a non-p-type group III nitride-based compound semiconductor, and having a lower band gap energy than the supply layer; a first electrode forming an ohmic contact with a two-dimensional electron gas layer in the transit layer at an interface thereof with the supply layer; and a second electrode forming a Schottky contact with the electron gas layer. The second electrode forms an ohmic contact, at a side wall of the field plate layer, with two-dimensional hole gas in the field plate layer at an interface thereof with the supply layer.Type: ApplicationFiled: July 9, 2013Publication date: April 10, 2014Inventor: Yoshihiro IKURA
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Patent number: 8692294Abstract: A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.Type: GrantFiled: January 24, 2013Date of Patent: April 8, 2014Assignee: Transphorm Inc.Inventors: Rongming Chu, Robert Coffie
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Patent number: 8680581Abstract: The present invention provides a method for producing a Group III nitride semiconductor. The method includes forming a groove in a surface of a growth substrate through etching; forming a buffer film on the groove-formed surface of the growth substrate through sputtering; heating, in an atmosphere containing hydrogen and ammonia, the substrate to a temperature at which a Group III nitride semiconductor of interest is grown; and epitaxially growing the Group III nitride semiconductor on side surfaces of the groove at the growth temperature. The thickness of the buffer film or the growth temperature is regulated so that the Group III nitride semiconductor is grown primarily on the side surfaces of the groove in a direction parallel to the main surface of the growth substrate.Type: GrantFiled: December 23, 2009Date of Patent: March 25, 2014Assignee: Toyoda Gosei Co., Ltd.Inventors: Naoyuki Nakada, Koji Okuno, Yasuhisa Ushida
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Patent number: 8674398Abstract: There are provided a group III nitride semiconductor light emitting device which is constituted of a substrate, an intermediate layer formed thereon having a favorable level of orientation properties, and a group III nitride semiconductor formed thereon having a favorable level of crystallinity, and having excellent levels of light emitting properties and productivity; a production method thereof; and a lamp, the group III nitride semiconductor light emitting device configured so that at least an intermediate layer 12 composed of a group III nitride compound is laminated on a substrate 11, and an n-type semiconductor layer 14 having a base layer 14a, a light emitting layer 15 and a p-type semiconductor layer 16 are sequentially laminated on the intermediate layer 12, wherein when components are separated, based on a peak separation technique using an X-ray rocking curve of the intermediate layer 12, into a broad component having the full width at half maximum of 720 arcsec or more and a narrow component,Type: GrantFiled: July 3, 2008Date of Patent: March 18, 2014Assignee: Toyoda Gosei Co., Ltd.Inventors: Hiroaki Kaji, Hisayuki Miki
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Patent number: 8674382Abstract: A semiconductor light emitting device (10) comprises a semiconductor structure (12) comprising a first body (14) of a first semiconductor material (in this case Ge) comprising a first region of a first doping kind (in this case n) and a second body (18) of a second semiconductor material (in this case Si) comprising a first region of a second doping kind (in this case p). The structure comprises a junction region (15) comprising a first heterojunction (16) formed between the first body (14) and the second body (18) and a pn junction (17) formed between regions of the structure of the first and second doping kinds respectively. A biasing arrangement (20) is connected to the structure for, in use, reverse biasing the pn junction, thereby to cause emission of light.Type: GrantFiled: January 30, 2009Date of Patent: March 18, 2014Assignee: Insiava (Pty) LimitedInventors: Lukas Willem Snyman, Monuko Du Plessis
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Patent number: 8664696Abstract: According to one embodiment, a nitride semiconductor device includes a first, a second and a third semiconductor layer, a first and a second main electrode and a control electrode. The first layer made of a nitride semiconductor of a first conductivity type is provided on a substrate. The second layer made of a nitride semiconductor of a second conductivity type is provided on the first layer. The third layer made of a nitride semiconductor is provided on the second layer. The first electrode is electrically connected with the second layer. The second electrode is provided at a distance from the first electrode and electrically connected with the second layer. The control electrode is provided within a first trench via an insulating film. The first trench is disposed between the first and the second main electrodes, penetrates the third and the second layers, and reaches the first layer.Type: GrantFiled: March 21, 2011Date of Patent: March 4, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Akira Yoshioka, Wataru Saito, Yasunobu Saito, Hidetoshi Fujimoto, Tetsuya Ohno
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Publication number: 20140054603Abstract: Planar Schottky diodes for which the semiconductor material includes a heterojunction which induces a 2DEG in at least one of the semiconductor layers. A metal anode contact is on top of the upper semiconductor layer and forms a Schottky contact with that layer. A metal cathode contact is connected to the 2DEG, forming an ohmic contact with the layer containing the 2DEG.Type: ApplicationFiled: August 22, 2013Publication date: February 27, 2014Applicant: Transphorm Inc.Inventors: Yifeng Wu, Umesh Mishra, Primit Parikh, Rongming Chu, Ilan Ben-Yaacov, Likun Shen
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Patent number: 8659053Abstract: A semiconductor light detecting element includes: an InP substrate; and a semiconductor stacked structure on the InP substrate and including at least a light absorbing layer, wherein the light absorbing layer includes an InGaAsBi layer lattice-matched to the InP substrate.Type: GrantFiled: August 28, 2012Date of Patent: February 25, 2014Assignee: Mitsubishi Electric CorporationInventors: Yoshifumi Sasahata, Eitaro Ishimura
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Publication number: 20140048851Abstract: The present invention relates to a substrate (5) comprising a Si-base (1) and an InAs-layer (4) provided on said Si-base where said InAs-layer (4) has a thickness between 100 and 500 nanometers and root-mean-square roughness of the upper surface of said InAs-layer (4) is below 1 nanometer. The invention further relates to a method for forming said substrate. The invention also relates to growing InAs-nanowires (7) as well as a GaSb-layer (17) on said substrate (5).Type: ApplicationFiled: April 27, 2012Publication date: February 20, 2014Applicant: QUNANO ABInventors: Lars-Erik Wernersson, Sepideh Ghalamestani
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Patent number: 8653563Abstract: A semiconductor device includes: a substrate comprised of gallium nitride; an active layer provided on the substrate; a first buffer layer that is provided between the substrate and the active layer and is comprised of indium aluminum nitride (InxAl1?xN, 0.15?x?0.2); and a spacer layer that is provided between the first buffer layer and the active layer and is comprised of aluminum nitride having a thickness of 1 nm or more to 10 nm or less.Type: GrantFiled: September 27, 2012Date of Patent: February 18, 2014Assignee: Sumitomo Electric Industries, Ltd.Inventors: Fumio Yamada, Takeshi Araya
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Patent number: 8647901Abstract: There is provided a method of forming a nitride semiconductor layer, including the steps of firstly providing a substrate on which a patterned epitaxy layer with a pier structure is formed. A protective layer is then formed on the patterned epitaxy layer, exposing a top surface of the pier structure. Next, a nitride semiconductor layer is formed over the patterned epitaxy layer connected to the nitride semiconductor layer through the pier structure, wherein the nitride semiconductor layer, the pier structure, and the patterned epitaxy layer together form a space exposing a bottom surface of the nitride semiconductor layer. Thereafter, a weakening process is performed to remove a portion of the bottom surface of the nitride semiconductor layer and to weaken a connection point between the top surface of the pier structure and the nitride semiconductor layer. Finally, the substrate is separated from the nitride semiconductor layer through the connection point.Type: GrantFiled: June 11, 2008Date of Patent: February 11, 2014Assignee: Industrial Technology Research InstituteInventors: Yih-Der Guo, Chih-Ming Lai, Jenq-Dar Tsay, Po-Chun Liu
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Publication number: 20140021512Abstract: Gallium nitride (GaN) based semiconductor devices and methods of manufacturing the same. The GaN-based semiconductor device may include a heterostructure field effect transistor (HFET) or a Schottky diode, arranged on a heat dissipation substrate. The HFET device may include a GaN-based multi-layer having a recess region; a gate arranged in the recess region; and a source and a drain that are arranged on portions of the GaN-based multi-layer at two opposite sides of the gate (or the recess region). The gate, the source, and the drain may be attached to the heat dissipation substrate. The recess region may have a double recess structure. While such a GaN-based semiconductor device is being manufactured, a wafer bonding process and a laser lift-off process may be used.Type: ApplicationFiled: September 19, 2013Publication date: January 23, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-hoon LEE, Ki-se KIM
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Patent number: 8633519Abstract: Provided is an HEMT exhibiting a normally-off characteristic and low on-state resistance, which includes a first carrier transport layer; two separate second carrier transport layers formed of undoped GaN and provided on two separate regions of the first carrier transport layer; and carrier supply layers formed of AlGaN and respectively provided on the two separate second carrier transport layers. The second carrier transport layers and the carrier supply layers are respectively formed through crystal growth on the first carrier transport layer. The heterojunction interface between the second carrier transport layer and the carrier supply layer exhibits high flatness, and virtually no growth-associated impurities are incorporated in the vicinity of the heterojunction interface. Therefore, reduction in mobility of 2DEG is prevented, and on-state resistance is reduced.Type: GrantFiled: September 20, 2010Date of Patent: January 21, 2014Assignee: Toyoda Gosei Co., Ltd.Inventor: Toru Oka
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Patent number: 8617945Abstract: A stacking fault and twin blocking barrier for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1×108 cm?2 to be formed on silicon substrates. In an embodiment of the present invention, a buffer layer is positioned between a III-V device layer and a silicon substrate to glide dislocations. In an embodiment of the present invention, GaSb buffer layer is selected on the basis of lattice constant, band gap, and melting point to prevent many lattice defects from propagating out of the buffer into the III-V device layer. In a specific embodiment, a III-V InSb device layer is formed directly on the GaSb buffer.Type: GrantFiled: February 3, 2012Date of Patent: December 31, 2013Assignee: Intel CorporationInventors: Mantu K. Hudait, Mohamad A. Shaheen, Loren A. Chow, Peter G. Tolchinsky, Joel M. Fastenau, Dmitri Loubychev, Amy W. K. Liu
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Publication number: 20130341682Abstract: A nitride semiconductor device includes a semiconductor substrate and a nitride semiconductor layer disposed on the semiconductor substrate. The semiconductor substrate includes a normal region, a carrier supplying region, and an interface current blocking region. The interface current blocking region surrounds the normal region and the carrier supplying region. The interface current blocking region and the carrier supplying region include impurities. The carrier supplying region has a conductivity type allowing the carrier supplying region to serve as a source of carriers supplied to or a destination of carriers supplied from a carrier layer generated at an interface between the nitride semiconductor layer and the semiconductor substrate. The interface current blocking region has a conductivity type allowing the interface current blocking region to serve as a potential barrier to the carriers.Type: ApplicationFiled: August 23, 2013Publication date: December 26, 2013Applicant: PANASONIC CORPORATIONInventors: Hidekazu UMEDA, Tetsuzo UEDA, Daisuke UEDA
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Patent number: 8610175Abstract: This invention relates to a semiconductor device and a manufacturing method thereof for reducing stacking faults caused by high content of Ge in an embedded SiGe structure. The semiconductor device comprises a Si substrate with a recess formed therein. A first SiGe layer having a Ge content gradually increased from bottom to top is formed on the recess bottom, a SiGe seed layer is formed on sidewalls of the recess and a second SiGe layer having a constant content of Ge is formed on the first SiGe layer. The thickness of the first SiGe layer is less than the depth of the recess. The Ge content in the SiGe seed layer is less than the Ge content in the second SiGe layer and the Ge content at the upper surface of the first SiGe layer is less than or equal to the Ge content in the second SiGe layer.Type: GrantFiled: December 9, 2011Date of Patent: December 17, 2013Assignee: Semiconductor Manufacturing International (Beijing) CorporationInventors: Zhongshan Hong, Huojin Tu
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Patent number: 8604519Abstract: Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations are defined on a layered semiconductor wafer. The layered semiconductor wafer preferably includes a III-V semiconductor surface layer, e.g., Gallium Arsenide (GaAs), and a buried layer, e.g., Aluminum Arsenide (AlAs). Portions of the buried layer are converted to dielectric material, e.g., Aluminum Oxide (AlO), at least beneath FET source/drain regions. The converted dielectric material may extend completely under the FET. Source/drain contacts are formed to FETs above the dielectric material in the buried layer.Type: GrantFiled: June 4, 2012Date of Patent: December 10, 2013Assignee: International Business Machines CorporationInventors: Cheng-Wei Cheng, Shu-Jen Han, Kuen-Ting Shiu
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Patent number: 8598594Abstract: In a semiconductor device including a stack structure having heterojunction units formed by alternately stacking GaN (gallium nitride) films and barrier films which are different in forbidden band width, a first electrode formed in a Schottky barrier contact with one sidewall of the stack structure, and a second electrode formed in contact with the other sidewall, an oxide film is interposed between the first electrode and the barrier films. Therefore, the reverse leakage current is prevented from flowing through defects remaining in the barrier films due to processing of the barrier films, so that a reverse leakage current of a Schottky barrier diode is reduced.Type: GrantFiled: February 4, 2012Date of Patent: December 3, 2013Assignee: Hitachi, Ltd.Inventors: Kazuhiro Mochizuki, Takashi Ishigaki, Akihisa Terano, Tomonobu Tsuchiya
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Publication number: 20130313579Abstract: Detectors based on such Ge(Sn) alloys of the formula Ge1-xSnx (e.g., 0<x<0.01) have increased responsivity while keeping alloy scattering to a minimum. Such small amounts of Sn are also useful for improving the performance of the recently demonstrated Ge-on-Si laser structures, since the addition of Sn monotonically reduces the separation between the direct and indirect minima in the conduction band of Ge. Thus, provided herein are Ge(Sn) alloys of the formula Ge1xSnx, wherein x is less than 0.01, wherein the alloy is optionally n-doped or p-doped; and assemblies and photodiodes comprising the same, and methods for their formation.Type: ApplicationFiled: November 18, 2011Publication date: November 28, 2013Inventors: John Kouvetakis, Richard Beeler, Jose Menendez, Radek Roucka
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Patent number: 8586859Abstract: A method of forming a plurality of discrete, interconnected solar cells mounted on a carrier by providing a first semiconductor substrate; depositing on the first substrate a sequence of layers of semiconductor material forming a solar cell structure; forming a metal back contact layer over the solar cell structure; mounting a carrier on top of the metal back contact; removing the first substrate; and lithographically patterning and etching the solar cell structure to form a plurality of discrete solar cells mounted on the carrier.Type: GrantFiled: July 27, 2012Date of Patent: November 19, 2013Assignee: Emcore Solar Power, Inc.Inventor: Tansen Varghese
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Patent number: 8575660Abstract: According to one exemplary embodiment, a group III-V semiconductor device includes at least one transition layer situated over a substrate. The group III-V semiconductor device further includes a first strain-relieving interlayer situated over the at least one transition layer and a second strain-relieving interlayer situated over the first strain-relieving interlayer. The group III-V semiconductor device further includes a first group III-V semiconductor body situated over the second strain-relieving interlayer. The first and second strain-relieving interlayers comprise different semiconductor materials so as to reduce a strain in the first group III-V semiconductor body. The second strain-relieving interlayer can be substantially thinner than the first strain-relieving interlayer.Type: GrantFiled: October 14, 2009Date of Patent: November 5, 2013Assignee: International Rectifier CorporationInventors: Scott Nelson, Ronald Birkhahn, Brett Hughes
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Patent number: 8575656Abstract: According to one embodiment, a semiconductor device having a semiconductor substrate, first to fourth semiconductor layers of nitride, first to third electrodes and a gate electrode is provided. The first semiconductor layer is provided directly on the semiconductor substrate or on the same via a buffer layer. The second semiconductor layer is provided so as to be spaced apart from the first semiconductor layer. The third semiconductor layer is provided on the second semiconductor layer and has a band gap wider than that of the second semiconductor layer. The fourth semiconductor layer insulates the first and second semiconductor layers. The first electrode forms an ohmic junction with the first to the third semiconductor layers. The second electrode is provided on the third semiconductor layer. The gate electrode is provided between the first and the second electrodes. The third electrode forms a Schottky junction with the first semiconductor layer.Type: GrantFiled: September 6, 2012Date of Patent: November 5, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Akira Yoshioka, Yasunobu Saito, Wataru Saito
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Patent number: 8575471Abstract: Methods of fabricating a semiconductor layer or device and said devices are disclosed. The methods include but are not limited to providing a metal or metal alloy substrate having a crystalline surface with a known lattice parameter (a). The methods further include growing a crystalline semiconductor alloy layer on the crystalline substrate surface by coincident site lattice matched epitaxy. The semiconductor layer may be grown without any buffer layer between the alloy and the crystalline surface of the substrate. The semiconductor alloy may be prepared to have a lattice parameter (a?) that is related to the lattice parameter (a). The semiconductor alloy may further be prepared to have a selected band gap.Type: GrantFiled: August 31, 2009Date of Patent: November 5, 2013Assignee: Alliance for Sustainable Energy, LLCInventors: Andrew G. Norman, Aaron J. Ptak, William E. McMahon
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Patent number: 8575655Abstract: Various techniques for changing the workfunction of the substrate by using a SiGe channel which, in turn, changes the bandgap favorably for a p-type metal oxide semiconductor field effect transistors (pMOSFETs) are disclosed. In the various techniques, a SiGe film that includes a low doped SiGe region above a more highly doped SiGe region to allow the appropriate threshold voltage (Vt) for pMOSFET devices while preventing pitting, roughness and thinning of the SiGe film during subsequent cleans and processing is provided.Type: GrantFiled: March 27, 2012Date of Patent: November 5, 2013Assignee: International Business Machines CorporationInventors: Stephen W. Bedell, Ashima B. Chakravarti, Michael P. Chudzik, Judson R. Holt, Dominic J. Schepis
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Patent number: 8569800Abstract: A field effect transistor includes: a buffer layer that is formed on a substrate; a high resistance layer or a foundation layer that is formed on the buffer layer; a carbon-containing carrier concentration controlling layer that is formed on the high resistance layer or the foundation layer; a carrier traveling layer that is formed on the carrier concentration controlling layer; a carrier supplying layer that is formed on the carrier traveling layer; a recess that is formed from the carrier supplying layer up to a predetermined depth; source/drain electrodes that are formed on the carrier supplying layer with the recess intervening therebetween; a gate insulating film that is formed on the carrier supplying layer so as to cover the recess; and a gate electrode that is formed on the gate insulating film in the recess.Type: GrantFiled: March 31, 2011Date of Patent: October 29, 2013Assignee: Furukawa Electric Co., Ltd.Inventors: Nariaki Ikeda, Takuya Kokawa, Masayuki Iwami, Sadahiro Kato
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Publication number: 20130277715Abstract: A semiconductor heterostructure having: a substrate (SS); a buffer layer (h); a spacer layer (d, e, f); a barrier layer (b, c); and which may also include a cover layer (a) is provided. The barrier layer is doped (DS); and the barrier and spacer layers are made of one or more semiconductors having wider bandgaps than the one or more materials forming the buffer layer, the heterostructure being characterized in that: the barrier layer comprises a first barrier sublayer (c) in contact with the spacer layer, and a second barrier sublayer (b), distant from the spacer layer; and in that the second barrier sublayer has a wider bandgap than the first barrier sublayer. The invention also relates to a HEMT transistor produced using such a heterostructure and to the use of such a transistor at cryogenic temperatures.Type: ApplicationFiled: October 7, 2011Publication date: October 24, 2013Applicant: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUEInventors: Yong Jin, Ulf Gennser, Antonella Cavanna