With Particular Chip Input/output Means Patents (Class 257/203)
  • Patent number: 11211279
    Abstract: A method for processing a 3D integrated circuit, the method including: providing a first level including a first wafer, the first wafer including a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers, where the first copper interconnecting layers at least interconnect the plurality of first transistors; processing a second level including a second wafer, the second wafer including a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers, where the second copper interconnecting layers at least interconnect the plurality of second transistors; then forming a bonded structure by bonding the second level to the first level, where the bonding includes metal to metal bonding, where the bonding includes oxide to oxide bonding; and then performing a lithography process to define dice lines for the bonded structure; and etching the dice lines.
    Type: Grant
    Filed: January 3, 2021
    Date of Patent: December 28, 2021
    Assignee: MONOLITHIC 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
  • Patent number: 11158566
    Abstract: Methods, systems, and apparatus, including an integrated circuit (IC) with a ring-shaped hot spot area. In one aspect, an IC includes a first area along an outside perimeter of a surface of the IC. The first area defines a first inner perimeter. The IC includes a second area that includes a center of the IC and that includes a first set of components. The second area defines a first outer. The IC includes a ring-shaped hot spot area between the first area and the second area. The ring-shaped hot spot area defines a ring outer perimeter that is juxtaposed with the first inner perimeter. The ring-shaped hot spot area defines a ring inner perimeter that is juxtaposed with the first outer perimeter. The ring-shaped hot spot area includes a second set of components that produce more heat than the first set of components.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: October 26, 2021
    Assignee: Google LLC
    Inventors: Madhusudan Krishnan Iyengar, Norman Paul Jouppi, Jorge Padilla, Christopher Gregory Malone
  • Patent number: 11157676
    Abstract: Systems and methods to translate or convert a desired circuit into a database that instructs a place and route or wire bonding machine where on a substrate to place components and also where to place bond wires on the pads of a connection matrix on a substrate. During the assembly process, the pads of the connection matrix are populated with bond wires using the database.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: October 26, 2021
    Assignee: OCTAVO SYSTEMS LLC
    Inventors: Neeraj Kumar Reddy Dantu, Masood Murtuza, Gene Alan Frantz
  • Patent number: 11133256
    Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate; a bridge, embedded in the package substrate, wherein the bridge includes an integral passive component, and wherein a surface of the bridge include first contacts in a first interconnect area and second contacts in a second interconnect area; a first die coupled to the passive component via the first contacts in the first interconnect area; and a second die coupled to the second contacts in the second interconnect area.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: September 28, 2021
    Assignee: Intel Corporation
    Inventors: Amit Kumar Jain, Sameer Shekhar, Chin Lee Kuan, Kevin Joseph Doran, Dong-Ho Han
  • Patent number: 11121049
    Abstract: A semiconductor package includes a lead frame having a die attach pad and a plurality of leads. A die is attached to the die attach pad and the electrically connected to the plurality of leads. The die includes a plurality of bond pads along a periphery of the die and a bond pad strip surrounding a circuit in the die. A first plurality of bond wires is bonded between first opposite sides of the bond pad strip. The first plurality of bond wires is aligned in a first direction. A second plurality of bond wires is bonded between second opposite sides of the bond pad strip. The second plurality of bond wires is aligned in a second direction. Mold compound covers portions of the lead frame, the die, the bond pad strip, the first plurality of bond wires and the second plurality of bond wires.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: September 14, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Siva Prakash Gurrum, Amit Sureshkumar Nangia
  • Patent number: 11094693
    Abstract: A semiconductor device includes circuit active fin lines and circuit gate lines intersecting each other in a circuit active region, dummy active fin lines and dummy gate lines intersecting each other in a dummy active region, the active fin lines and the dummy active fin lines having same width and pitch, and the circuit gate lines and the dummy gate lines having same width and pitch, wherein at least some of the dummy active fin lines are aligned with and collinear with respective circuit active fin lines, and at least some of the dummy gate lines are aligned with and collinear with respective circuit gate lines.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: August 17, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: In Wook Oh, Jae Seok Yang, Jong Hyun Lee, Hyun Jae Lee, Sung Wook Hwang
  • Patent number: 11087696
    Abstract: A display device including: a pixel connected to a scan line and a data line intersecting the scan line. The pixel includes a light emitting element and a driving transistor which controls a driving current supplied to the light emitting element according to a data voltage applied from the data line. The driving transistor includes a first active layer including an oxide semiconductor doped with a metal.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: August 10, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Myoung Hwa Kim, Masataka Kano, Yeon Keon Moon, Joon Seok Park, Jun Hyung Lim, Hye Lim Choi
  • Patent number: 11031378
    Abstract: A semiconductor device is disclosed including a controller die and a memory module. The controller die may be a heterogeneous integrated controller die having ASIC logic circuits, memory array logic circuits and a cache structure. In examples, the memory module may have continuously formed through silicon vias in a face-up or face-down configuration.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: June 8, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Yazhou Zhang, Chin-Tien Chiu, Zengyu Zhou
  • Patent number: 11030231
    Abstract: An embodiment of a semiconductor package apparatus may include a substrate, and logic coupled to the substrate, wherein the logic is at least partly implemented in one or more of configurable logic and fixed-functionality hardware logic, the logic coupled to the substrate to determine an angular distance between a data object and a group of data objects, and assign the data object to the group of data objects based on the determined angular distance. In some embodiments, the logic may also be to determine one or more of an upper bound and a lower bound for the group of data objects based on triangle inequality. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventor: Piotr Tylenda
  • Patent number: 11009758
    Abstract: A display panel displaying an image includes a first substrate, a second substrate disposed opposite the first substrate, electric optical substance sealed between the first substrate and the second substrate, a transistor disposed on the first substrate and supplying an electric signal to the electric optical substance and including an oxide semiconductor film as an activating layer, and a light blocking film disposed on the second substrate and blocking visible light from transmitting therethrough, the light blocking film having a hole in a position overlapping the transistor in a plan view.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: May 18, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yoshimasa Chikama, Jun Nishimura, Yoshiharu Hirata
  • Patent number: 10991635
    Abstract: The present invention includes a bridge connector with one or more semiconductor layers in a bridge connector shape. The shape has one or more edges, one or more bridge connector contacts on a surface of the shape, and one or more bridge connectors. The bridge connectors run through one or more of the semiconductor layers and connect two or more of the bridge connector contacts. The bridge connector contacts are with a tolerance distance from one of the edges. In some embodiments the bridge connector is a central bridge connector that connects two or more chips disposed on the substrate of a multi-chip module (MCM). The chips have chip contacts that are on an interior corner of the chip. The interior corners face one another. The central bridge connector overlaps the interior corners so that each of one or more of the bridge contacts is in electrical contact with each of one or more of the chip contacts. In some embodiments, overlap is minimized to permit more access to the surface of the chips.
    Type: Grant
    Filed: July 20, 2019
    Date of Patent: April 27, 2021
    Assignee: International Business Machines Corporation
    Inventors: Dale Curtis McHerron, Kamal K. Sikka, Joshua M. Rubin, Ravi K. Bonam, Ramachandra Divakaruni, William J. Starke, Maryse Cournoyer
  • Patent number: 10879164
    Abstract: An integrated circuit ESD bus structure includes a circuit area; a plurality of electrostatic discharge (ESD) buses; a plurality of pad groups adjacent and connected to the plurality of ESD buses; a common ESD bus; and a plurality of bonding wires configured to connect the plurality of pad groups to the common ESD bus.
    Type: Grant
    Filed: December 2, 2018
    Date of Patent: December 29, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventor: Zhiguo Li
  • Patent number: 10868008
    Abstract: Exemplary embodiments for an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: December 15, 2020
    Inventors: Shih-Wei Peng, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Li-Chun Tien, Pin-Dai Sue, Wei-Cheng Lin
  • Patent number: 10847433
    Abstract: Apparatuses and methods for coupling contact pads to a circuit in a semiconductor device is described. An example apparatus includes a first pad, a first wiring coupled to the first pad, a second pad, a second wiring, a circuit coupled to the second pad, and a switch circuit. The switch circuit includes first, second, and third connections, and includes first and second control gates. The first wiring is coupled to the first and third connections and second wiring is coupled to the second connection. The switch circuit is configured to couple the first wiring with the second wiring when the first and second control gates are activated and to decouple the first wiring from the second wiring when the first and second control gates are not activated.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: November 24, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Masahiko Igeta, Yoshimi Terui
  • Patent number: 10825807
    Abstract: An electrostatic protection circuit, an array substrate, a display panel and a display device are disclosed. The electrostatic protection circuit is located within a peripheral region of an array substrate and includes: a first ground wire provided in a same layer as a source electrode and a drain electrode of a thin film transistor located within a display region of the array substrate; and a second ground wire provided in a same layer as a gate electrode of the thin film transistor, wherein, the first ground wire forms a first loop with a printed circuit board provided within the peripheral region, the first loop surrounds the display region; the second ground wire forms a second loop with the printed circuit board, and the second loop surrounds the display region.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: November 3, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Yanwei Ren, Jingyi Xu, Kunpeng Zhang, Yu Liu, Min Liu, Ruiying Tian
  • Patent number: 10809789
    Abstract: Logic on the baseboard can be used to provide backfeed protection by determining the condition of the peripheral component before enabling communication over a data cable to the peripheral component. By determining the condition of the peripheral component prior to beginning communications, the baseboard can reduce the likelihood that the baseboard asserts a wire on the data cable before the peripheral component receives power. With such information available to the baseboard, the baseboard avoids supplying a data signal over a wire of the data cable that would cause the destination circuitry of the peripheral component from exceeding its safety specification. When a bias voltage exists on the wire of the data connector corresponding to the peripheral component, the peripheral component is considered powered-on and data can be communicated to the peripheral component.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: October 20, 2020
    Assignee: Dell Products L.P.
    Inventors: Timothy M. Lambert, Jeffrey Leighton Kennedy
  • Patent number: 10811106
    Abstract: A data reading method, a low voltage detection logic circuit, an integrated circuit and a chip are provided. The data reading method includes that: under the condition that a request for reading data from a NonVolatile Memory (NVM) is received, a pre-burnt region return value is read from a preset pre-burnt region of the NVM (S101); whether the pre-burnt region return value is equal to a target pre-burnt value or not is determined (S102); and under the condition that the pre-burnt region return value is equal to the target pre-burnt value, a first control signal is generated, and the first control signal is sent to an NVM controller and the first control signal is used for controlling the VNM controller to read the data from the NVM (S103).
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: October 20, 2020
    Assignee: Gree Electric Appliances, Inc. of Zhuhai
    Inventors: Langming Wen, Heng Chen, Dongbai Yi, Li Fang
  • Patent number: 10796994
    Abstract: According to an aspect, a semiconductor device and an IO-cell include a plurality of first power supply lines and a plurality of second power supply lines alternately arranged in a first direction, the first and second power supply lines each being supplied with electric power in which the voltage of the electric power supplied to the first power supply is different from that supplied to the second power supply, and a third power supply line formed in a wiring layer different from a wiring layer in which the first and second power supply lines are arranged, the third power supply line being connected to adjacent first power supply lines among the plurality of first power supply lines through a via, in which all of the first, second and third power supply lines are formed so as to extend in a second direction perpendicular to the first direction.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: October 6, 2020
    Assignee: Renesas Electronics Corporation
    Inventor: Keisuke Nakayama
  • Patent number: 10741516
    Abstract: Disclosed are a drive integrated circuit (IC) capable of being applied to all of a chip on film (COF) type and a chip on glass (COG) type and a display device including the drive IC. The drive IC includes an input pad part including a plurality of input bumps and an output pad part including a plurality of first diode parts, a plurality of second diode parts, and a plurality of output bumps. At least two of the plurality of output bumps overlap the plurality of first diode parts and the plurality of second diode parts, and a first output bump of the at least two output bumps is connected to at least one of the plurality of first diode parts and at least one of the plurality of second diode parts.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: August 11, 2020
    Assignee: SILICON WORKS CO., LTD.
    Inventors: Myeong Woo Oh, Yong Nam Choi, Dong Geon Lee, Dong Wook Kim, Jae Sup Han, Eun Ji Jo
  • Patent number: 10723895
    Abstract: A single-walled carbon nanotube composition includes single-walled carbon nanotubes substantially enriched in semiconducting single-walled carbon nanotubes in association with a polymer having one or more oligoether side groups. The oligoether side groups render the composition dispersable in polar organic solvents, for example alkyl carbitols, permitting formulation of ink compositions containing single-walled carbon nanotubes substantially enriched in semiconducting single-walled carbon nanotubes. Such ink compositions may be readily printed using common printing methods, such as inkjet, flexography and gravure printing.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: July 28, 2020
    Inventors: Jianfu Ding, Zhao Li, Patrick Malenfant
  • Patent number: 10714484
    Abstract: An SRAM structure is provided. The SRAM structure includes a plurality of first well regions with a first doping type, a plurality of second well regions with a second doping type, a third well region with the second doping type, a plurality of first well pick-up regions, a plurality of second well pick-up regions, and a plurality of memory cells. The first well regions, the second well regions, and the third well region are formed in a semiconductor substrate. The third well region is adjacent to the second well regions. The first well pick-up regions are formed in the first well regions. The second well pick-up regions are formed in the third well region. The second well pick-up regions are shared by the third well region and the second well regions. The memory cells are formed on the first and second well regions.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: July 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Feng-Ming Chang, Chia-Hao Pao, Lien-Jung Hung, Ping-Wei Wang
  • Patent number: 10685949
    Abstract: Generally discussed herein are systems and apparatuses that can include apparatuses, systems, or method for a flexible, wire bonded device. According to an example an apparatus can include (1) a first rigid circuit comprising a first plurality of bond pads proximate to a first edge of the first rigid circuit, (2) a second rigid circuit comprising a second plurality of bond pads proximate to a first edge of the second rigid circuit, the second rigid circuit adjacent the first rigid circuit and the first edge of the second rigid circuit facing the first edge of the first rigid circuit, or (3) a first plurality of wire bonded wires, each wire bonded wire of the first plurality of wire bonded wires electrically and mechanically connected to a bond pad of the first plurality of bond pads and a bond pad of the second plurality of bond pads.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Mauro Kobrinsky, Johanna Swan, Rajendra C. Dias
  • Patent number: 10580462
    Abstract: A memory device includes a memory cell array that a plurality of memory cells, an edge buffer circuit that is placed in a first region adjacent to one side of the memory cell array and receives an external signal from the outside through a pad, and a middle buffer circuit that is placed in a second region adjacent to an opposite side of the memory cell array and receives a differential small-swing signal corresponding to the external signal from the edge buffer circuit through first and second signal lines above the memory cell array. The edge buffer circuit drives the first and second signal lines based on the external signal such that the differential small-swing signal is transmitted to the middle buffer circuit.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: March 3, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Chankyung Kim
  • Patent number: 10573262
    Abstract: The disclosure discloses a data voltage storage circuit, a method for driving the same, a liquid crystal display, and a display device, and the data voltage storage circuit includes a voltage input subcircuit, a storage control subcircuit, and an output control subcircuit; and the storage control subcircuit stores a data signal input to the first node, so that the data signal can be stored for a long period of time. The three subcircuits above cooperate with each other so that a signal output end can be provided with a signal of a second reference voltage signal end or a common voltage signal end using the simple structure to thereby lower the difficulty of a fabrication process thereof, narrow a space to be occupied by the circuit, and improve a pixel aperture ratio.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: February 25, 2020
    Assignees: BOE Technology Group Co., Ltd., Hefei BOE Optoelectronics Technology Co., Ltd.
    Inventors: Yimin Chen, Xianjie Shao, Xiujuan Wang, Zhangmeng Wang
  • Patent number: 10553508
    Abstract: Embodiments are disclosed for semiconductor manufacturing using disposable test circuitry formed within scribe lanes. The manufacturing steps can include forming device circuitry within a semiconductor die and forming test circuitry within a scribe lane. One or more electrical connection route lines are also formed that connect the device circuitry and test circuitry blocks. Further, each die can be connected to a single test circuitry block, or multiple dice can share common test circuitry blocks. After testing, the electrical connection route line(s) are sealed, and the test circuitry is discarded when the device dice are singulated. For certain embodiments, the edge of the devices dice are encapsulated with a protective metal layer, and certain other embodiments include protective sealrings through which the connection route lines pass to enter the dice from the test circuitry blocks within the scribe lanes.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: February 4, 2020
    Assignee: NXP USA, INC.
    Inventors: Douglas M. Reber, Sergio A. Ajuria, Phuc M. Nguyen
  • Patent number: 10529834
    Abstract: Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: January 7, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Yongjun Jeff Hu
  • Patent number: 10522516
    Abstract: A system comprising a die stack having at least a first die and a second die; one or more Redistribution Layer(s); one or more Through Silicon Via(s); one or more Serial I/O(s); one or more contact pad(s); and a substrate. The die stack is configured to communicate through said one or more Redistribution Layer(s) and said Through Silicon Via(s). The first die and/or said second die is/are configured to communicate through said one or more Redistribution Layer(s) and said Through Silicon Via(s). The one or more Serial I/O(s) is/are configured to communicate through said one or more Redistribution Layer(s) and said Through Silicon Via(s).
    Type: Grant
    Filed: March 16, 2019
    Date of Patent: December 31, 2019
    Assignee: BroadPak Corporation
    Inventor: Farhang Yazdani
  • Patent number: 10522530
    Abstract: An electrostatic discharge (ESD) shielding semiconductor device and an ESD testing method thereof, the ESD shielding semiconductor device includes an integrated circuit, a seal ring and a conductive layer. The integrated circuit is disposed on a die, and the integrated circuit has a first region and a second region. The seal ring is disposed on the die to surround the integrated circuit. The conductive layer at least covers the first region, and which is electrically connected to the seal ring.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: December 31, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun Chiang, Ying-Wei Tseng, Ping-Chen Chang, Tien-Hao Tang
  • Patent number: 10467165
    Abstract: One example of a system includes a Universal Serial Bus Type-C (USB-C) port, a set of logic circuits, a multiplexer, and an embedded controller. The set of logic circuits includes a first logic circuit providing a first utility and a second logic circuit providing a second utility different from the first utility. The multiplexer is communicatively coupled between the set of logic circuits and the USB-C port. The embedded controller controls the multiplexer to connect the first logic circuit or the second logic circuit to the USB-C port based on a value of a multi-level strap received from a device connected to the USB-C port.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: November 5, 2019
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Connor Jam Watkins, Christopher Ritchie Tabarez, Amol Subhash Pandit, Peter Andrew Seiler
  • Patent number: 10438890
    Abstract: Disclosed herein is an integrated circuit (IC) including a first metal layer running in a first direction, a second metal layer running in a second direction perpendicular to the first direction, the second metal layer above the first metal layer and a third metal layer running in the first direction above the second metal layer. A viabar electrically connects the first metal layer to the third metal layer, the viabar running in the first direction wherein the viabar vertically extends from the first metal layer to the third metal layer. A method of manufacturing the IC is provided.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: October 8, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Erdem Kaltalioglu, Atsushi Ogino
  • Patent number: 10425030
    Abstract: A semiconductor device disclosed in the present specification has a structure that includes: a first terminal that is to be externally connected to a power source line; a second terminal that is to be externally connected to a ground line; a third terminal that is internally connected to the first terminal and to be externally connected to a first terminal of a bypass capacitor; and a fourth terminal that is internally connected to the second terminal and to be externally connected to a second terminal of the bypass capacitor.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: September 24, 2019
    Assignee: Rohm Co., Ltd.
    Inventor: Masashi Nagasato
  • Patent number: 10418550
    Abstract: A high temperature resistant memristor comprises a bottom electrode, a dielectric and a top electrode, wherein the dielectric is a two-dimensional covalent crystal material or a two-dimensional covalent crystal material doped with oxygen or sulfur which has (1) the two-dimensional covalent crystal material or the two-dimensional covalent crystal material doped with oxygen or sulfur is adopted as the dielectric; (2) a memristor prepared by utilizing relatively high thermal stability of a lattice structure of two-dimensional transition metal; and (3) the high temperature resistant memristor.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: September 17, 2019
    Assignee: Nanjing University
    Inventors: Feng Miao, Miao Wang
  • Patent number: 10338421
    Abstract: The invention provides a display device, which employs ultra-thin flexible substrate with WOA disposed on both sides of the flexible substrate, wherein the WOA on the front side is directly connected to the active area, and the WOA on the back side passes through the holes in the flexible substrate to extend to the front side to connect to the active area. As such, the circuit area utilization is improved so that the same size of substrate area can carry almost twice the circuit structure to reduce the border width of the non-active area to achieve borderless or ultra-narrow borders.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: July 2, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Gang Wang, Lixuan Chen
  • Patent number: 10186486
    Abstract: A wiring board includes conductor layers, core layers including a first core layer and a second core layer formed such that each of the first and second core layers includes a core material, an intermediate insulating layer formed between the first core layer and second core layer such that the intermediate insulating layer does not contain a core material, and an electronic component positioned between the first core layer and second core layer such that the electronic component is embedded in the intermediate insulating layer. At least one of the first and second core layers has a multilayer structure including a resin layer and an adhesive layer laminated on the resin layer such that the resin layer includes the core material and that the adhesive layer does not contain a core material, and the conductor layers include a conductor layer laminated on the adhesive layer of the multilayer structure.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: January 22, 2019
    Assignee: IBIDEN CO., LTD.
    Inventors: Hajime Sakamoto, Keisuke Shimizu
  • Patent number: 10102893
    Abstract: Systems and methods for performing word line pulse techniques in magnetoelectric junctions in accordance with embodiments of the invention are disclosed. In one embodiment, a magnetoelectric random access memory (MeRAM) circuit, including, a plurality of voltage controlled magnetic tunnel junction bits (MEJs) each magnetoelectric junction connected to the drain of an MOS transistor, the combination including three terminals, each connected to a bit, source, and at least one word line, in an array, and a driver circuit, including a bit line driver, and a word line driver the bit line driver, the driver circuit generates voltage pulses for application to the magnetoelectric junction bit, the output of the driver circuit is connected to the word line, which in turn is connected to the gate of the MOS access transistor in each MeRAM cell, thereby generating a square voltage pulse across the magnetoelectric junction bit.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: October 16, 2018
    Assignee: Inston Inc.
    Inventor: Hochul Lee
  • Patent number: 10032804
    Abstract: An electro-optic apparatus includes an element substrate, a pixel region including a first and second pixel formed on the element substrate, a first terminal formed on the element substrate, a second terminal formed on the element substrate, located opposite of the pixel region with the first terminal being interposed between the pixel region and the second terminal, a first wiring extending from the first terminal included in a path for transmitting to the first pixel, a first signal having been input to the first terminal and a second wiring extending from the second terminal included in a path for transmitting to the second pixel, a second signal having been input to the second terminal. Further, a difference between a resistance of the path for transmitting the first and second signal is made smaller than a resistance difference due to a difference between a length of the first and second wiring.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: July 24, 2018
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Nariya Takahashi, Hiroyuki Hosaka, Suguru Uchiyama
  • Patent number: 9978682
    Abstract: Complementary metal oxide semiconductor (MOS) (CMOS) standard cell circuits employing metal lines in a first metal layer used for routing, and related methods are disclosed. In one aspect, a CMOS standard cell circuit includes first supply rail, second supply rail, and metal lines disposed in the first metal layer. One or more of the metal lines are dynamically cut corresponding to a first cell boundary and a second cell boundary of the CMOS standard cell such that the metal lines have cut edges corresponding to the first and second cell boundaries. Metal lines not cut corresponding to the first and second cell boundaries can be used to interconnect nodes of the CMOS standard cell circuit. Dynamically cutting the metal lines allows the first metal layer to be used for routing, reducing routing in other metal layers such that fewer vias and metal lines are disposed above the first metal layer.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: May 22, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Anthony Correale, Jr., William Goodall, III, Philip Michael Iles
  • Patent number: 9941247
    Abstract: A memory device including a stack semiconductor device including; an upper substrate vertically stacked on a lower substrate, the upper substrate including N upper through-silicon vias (UTSV) and upper driving circuits, and the lower substrate including N lower through-silicon vias (LTSV) and lower driving circuits, wherein each one of the upper driving circuits is stagger-connected between a Kth UTSV and a (K+1)th LTSV, where ‘N’ is a natural number greater than 1, and ‘K’ is a natural number ranging from 1 to (N?1).
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: April 10, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hae-Suk Lee, Kyo-Min Sohn, Ho-Young Song, Sang-Hoon Shin, Han-Vit Jung
  • Patent number: 9929095
    Abstract: A MOS device includes an IO pad ring. The MOS device includes a first IO pad located on a first side of the IO pad ring, and a second IO pad located on a second side of the IO pad ring. The first IO pad includes a metal x layer power interconnect extending in a first direction. The first metal x layer power interconnect is of a metal x layer. The second side is 90° from the first side. The second IO pad includes a second metal x layer power interconnect extending in the first direction. The second metal x layer power interconnect is of the metal x layer. The second IO pad may further include at least one of a metal x+1 layer power interconnect or a metal x?1 layer power interconnect that extends orthogonal to the second metal x layer power interconnect of the second IO pad.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: March 27, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Rohit Vinod Singewar, Roshan Thonse Shetty
  • Patent number: 9899415
    Abstract: A radio frequency fully depleted silicon on insulator (RF-FDSOI) device and method of fabrication are provided. A silicon wafer for digital circuits is constructed using fully depleted silicon on insulator technology having a thin buried oxide layer. Localized areas of the silicon wafer are constructed for radio frequency circuits and/or passive devices. The silicon wafer has a silicon substrate having a resistivity greater than 1 K?·cm. The localized areas of the silicon wafer may include a trap rich layer implanted underneath a thin buried oxide layer. The localized areas of the silicon wafer may include a buried oxide layer that is thicker than the thin buried oxide layer. The thicker oxide layer is between 20 and 2000 nm thick. The localized areas of the silicon wafer may include a trap rich layer implanted underneath the thicker buried oxide layer.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: February 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Jean-Olivier Plouchart
  • Patent number: 9893054
    Abstract: A protection cell for a cell library. The protection cell defines a protection circuit for an IC having a driving device with a first supply voltage Vdd1 and an output, and a driven device having an input and a second supply voltage Vdd2. The protection circuit includes a first device from the group consisting of a P-diode and a gate-Vdd PMOS. The first device is coupled between a first power bus connected to Vdd2 and the input of the driven device. The input of the driven device is coupled by way of a resistor to the output of the driving device. A second device corresponding to the first device is provided, from the group consisting of an N-diode and a grounded gate NMOS. The second device is coupled between the input of the driven device and a ground bus.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: February 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Bo-Ting Chen
  • Patent number: 9882567
    Abstract: A programmable semiconductor device includes a user programmable switch comprising a configurable element positioned above a transistor material layer deposited on a substrate layer.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: January 30, 2018
    Assignee: CALLAHAN CELLULAR L.L.C.
    Inventor: Raminda Udaya Madurawe
  • Patent number: 9869910
    Abstract: A liquid crystal display device includes a display region, a plurality of lead-out lines led from the display region, and an application circuit that applies a voltage to liquid crystal in the display region through each of the lead-out lines. Each of the lead-out lines has a tilt portion wired with a directional component parallel to a peripheral direction enclosing the display region in a plan view, and when a difference between a voltage applied to one of the lead-out lines and a voltage applied to another one of the lead-out lines is specified as an applied voltage difference, each of the lead-out lines is wired such that, in a plan view, the taper portion of one of the lead-out lines is overlapped with the taper portion of another one of the lead-out lines having the applied voltage difference lower than a difference with adjacent one of the lead-out lines.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: January 16, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventor: Shohei Yasuda
  • Patent number: 9859263
    Abstract: A semiconductor package includes a package base substrate including bonding pads and a connection pads respectively on an upper surface and a lower surface of the package base substrate, four semiconductor chips attached onto the package base substrate, including a 1A semiconductor chip, a 1B semiconductor chip, a 2A semiconductor chip, and a 2B semiconductor chip, and each including a plurality of chip pads that are adjacent to a first edge of an upper surface of each of the 1A semiconductor chip, the 1B semiconductor chip, the 2A semiconductor chip, and the 2B semiconductor chip, and a bonding wire electrically connecting the chip pad and the bonding pad to each other, wherein the four semiconductor chips are disposed on the package base substrate such that first edges of the four semiconductor chips respectively face edges of the package base substrate that are different from each other.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: January 2, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-hong Kwon, Sang-nam Jeong, Sun-won Kang, Hee-jin Lee
  • Patent number: 9847339
    Abstract: Various embodiments provide a self-merged profile (SMP) method for fabricating a semiconductor device and a device fabricated using an SMP method. In an example embodiment, a semiconductor device is provided. The example semiconductor device comprises (a) a plurality of conductive lines; (b) a plurality of conductive pads; (c) a plurality of dummy tails; and (d) a plurality of closed loops. Each of the plurality of conductive pads is associated with one of the plurality of conductive lines, one of the plurality of dummy tails, and one of the plurality of closed loops. In example embodiments, the plurality of dummy tails and the plurality of closed loops are formed as residuals of the process used to create the plurality of conductive lines and the plurality of conductive pads.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: December 19, 2017
    Assignee: Macronix International Co., Ltd.
    Inventors: Yu-Min Hung, Chien-Ying Lee, Tzung-Ting Han
  • Patent number: 9837437
    Abstract: An integrated circuit (IC) may include at least one cell including a plurality of conductive lines that extend in a first direction and are in parallel to each other in a second direction that is perpendicular to the first direction, first contacts respectively disposed at two sides of at least one conductive line from among the plurality of conductive lines, and a second contact disposed on the at least one conductive line and the first contacts and forming a single node by being electrically connected to the at least one conductive line and the first contacts.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: December 5, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-hoon Baek, Sang-kyu Oh, Jung-Ho Do, Sun-young Park, Seung-young Lee, Hyo-sig Won
  • Patent number: 9818656
    Abstract: A method of testing includes attaching a first and second die to first and second die sites of a lead frame and forming a plurality of wire bonds coupling a plurality of pins of the first die site to the first die and a plurality of pins of the second die site to the second die. The first and second die are encapsulated. An isolation cut is performed to isolate the plurality of pins of the first die site from the plurality of pins of the second die site, while maintaining electrical connection between the first tie bar of the first die site and the first tie bar of the second die site. The first and second die are tested while providing a first power supply source to the first and second die via the first tie bars. After testing, the dies sites are fully singulated to result in packaged IC device.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: November 14, 2017
    Assignee: NXP USA, Inc.
    Inventors: Mark Edward Schlarmann, Dwight Lee Daniels, Stephen Ryan Hooper, Chad Dawson, Fengyuan Li
  • Patent number: 9812960
    Abstract: Methods and apparatus for DC-DC power controller with low standby current and fast transient response. In an example arrangement, an apparatus includes a voltage converter outputting a direct current output voltage, configured to increase the output voltage responsive to an enable control signal; at least one feedback comparator configured to output a first control signal, the feedback comparator being active responsive to an edge at a clock signal input; an adjustable frequency oscillator for outputting a first clock signal; and a fast transient detect circuit configured to output a second signal asynchronously upon detecting a rapid change greater than a voltage threshold in the output voltage; the voltage converter receiving the enable control signal when either the first clock signal is active, or the second signal is active and the output voltage is less than a reference voltage. Additional apparatus and methods are disclosed.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: November 7, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Keith Edmund Kunz, Vipul Kumar Singhal, Rajat Chauhan, Per Torstein Røine, Danielle Griffith
  • Patent number: 9812441
    Abstract: In a semiconductor integrated circuit device, a plurality of electrode pads for external connection are arranged in a zigzag pattern. Some electrode pads of the electrode pads of the plurality of I/O cells which are closer to a side of the semiconductor chip, each have an end portion closer to the side of the semiconductor chip, the end portion being set at the same position as that of an end portion of the corresponding I/O cell. A power source-side protective circuit and a ground-side protective circuit against discharge of static electricity are provided with the power source-side protective circuit being closer to the scribe region. A distance between a center position of one of the electrode pads and the ground-side protective circuit of the corresponding I/O cell and a distance between a center position of the other one electrode pad and the ground-side protective circuit of the corresponding I/O cell are both short and are substantially equal between each I/O cell.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: November 7, 2017
    Assignee: SOCIONEXT INC.
    Inventors: Koichi Taniguchi, Masato Maede
  • Patent number: 9780051
    Abstract: A method for forming a semiconductor structure includes forming a bond pad over a last metal layer of the semiconductor structure wherein the bond pad includes a wire bond region; and recessing the wire bond region such that the wire bond region has a first thickness and a region of the bond pad outside the wire bond region has a second thickness that is greater than the first thickness.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: October 3, 2017
    Assignee: NXP USA, Inc.
    Inventors: Tu-Anh N. Tran, Kurt H. Junker