With Particular Chip Input/output Means Patents (Class 257/203)
  • Patent number: 10438890
    Abstract: Disclosed herein is an integrated circuit (IC) including a first metal layer running in a first direction, a second metal layer running in a second direction perpendicular to the first direction, the second metal layer above the first metal layer and a third metal layer running in the first direction above the second metal layer. A viabar electrically connects the first metal layer to the third metal layer, the viabar running in the first direction wherein the viabar vertically extends from the first metal layer to the third metal layer. A method of manufacturing the IC is provided.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: October 8, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Erdem Kaltalioglu, Atsushi Ogino
  • Patent number: 10425030
    Abstract: A semiconductor device disclosed in the present specification has a structure that includes: a first terminal that is to be externally connected to a power source line; a second terminal that is to be externally connected to a ground line; a third terminal that is internally connected to the first terminal and to be externally connected to a first terminal of a bypass capacitor; and a fourth terminal that is internally connected to the second terminal and to be externally connected to a second terminal of the bypass capacitor.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: September 24, 2019
    Assignee: Rohm Co., Ltd.
    Inventor: Masashi Nagasato
  • Patent number: 10418550
    Abstract: A high temperature resistant memristor comprises a bottom electrode, a dielectric and a top electrode, wherein the dielectric is a two-dimensional covalent crystal material or a two-dimensional covalent crystal material doped with oxygen or sulfur which has (1) the two-dimensional covalent crystal material or the two-dimensional covalent crystal material doped with oxygen or sulfur is adopted as the dielectric; (2) a memristor prepared by utilizing relatively high thermal stability of a lattice structure of two-dimensional transition metal; and (3) the high temperature resistant memristor.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: September 17, 2019
    Assignee: Nanjing University
    Inventors: Feng Miao, Miao Wang
  • Patent number: 10338421
    Abstract: The invention provides a display device, which employs ultra-thin flexible substrate with WOA disposed on both sides of the flexible substrate, wherein the WOA on the front side is directly connected to the active area, and the WOA on the back side passes through the holes in the flexible substrate to extend to the front side to connect to the active area. As such, the circuit area utilization is improved so that the same size of substrate area can carry almost twice the circuit structure to reduce the border width of the non-active area to achieve borderless or ultra-narrow borders.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: July 2, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Gang Wang, Lixuan Chen
  • Patent number: 10186486
    Abstract: A wiring board includes conductor layers, core layers including a first core layer and a second core layer formed such that each of the first and second core layers includes a core material, an intermediate insulating layer formed between the first core layer and second core layer such that the intermediate insulating layer does not contain a core material, and an electronic component positioned between the first core layer and second core layer such that the electronic component is embedded in the intermediate insulating layer. At least one of the first and second core layers has a multilayer structure including a resin layer and an adhesive layer laminated on the resin layer such that the resin layer includes the core material and that the adhesive layer does not contain a core material, and the conductor layers include a conductor layer laminated on the adhesive layer of the multilayer structure.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: January 22, 2019
    Assignee: IBIDEN CO., LTD.
    Inventors: Hajime Sakamoto, Keisuke Shimizu
  • Patent number: 10102893
    Abstract: Systems and methods for performing word line pulse techniques in magnetoelectric junctions in accordance with embodiments of the invention are disclosed. In one embodiment, a magnetoelectric random access memory (MeRAM) circuit, including, a plurality of voltage controlled magnetic tunnel junction bits (MEJs) each magnetoelectric junction connected to the drain of an MOS transistor, the combination including three terminals, each connected to a bit, source, and at least one word line, in an array, and a driver circuit, including a bit line driver, and a word line driver the bit line driver, the driver circuit generates voltage pulses for application to the magnetoelectric junction bit, the output of the driver circuit is connected to the word line, which in turn is connected to the gate of the MOS access transistor in each MeRAM cell, thereby generating a square voltage pulse across the magnetoelectric junction bit.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: October 16, 2018
    Assignee: Inston Inc.
    Inventor: Hochul Lee
  • Patent number: 10032804
    Abstract: An electro-optic apparatus includes an element substrate, a pixel region including a first and second pixel formed on the element substrate, a first terminal formed on the element substrate, a second terminal formed on the element substrate, located opposite of the pixel region with the first terminal being interposed between the pixel region and the second terminal, a first wiring extending from the first terminal included in a path for transmitting to the first pixel, a first signal having been input to the first terminal and a second wiring extending from the second terminal included in a path for transmitting to the second pixel, a second signal having been input to the second terminal. Further, a difference between a resistance of the path for transmitting the first and second signal is made smaller than a resistance difference due to a difference between a length of the first and second wiring.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: July 24, 2018
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Nariya Takahashi, Hiroyuki Hosaka, Suguru Uchiyama
  • Patent number: 9978682
    Abstract: Complementary metal oxide semiconductor (MOS) (CMOS) standard cell circuits employing metal lines in a first metal layer used for routing, and related methods are disclosed. In one aspect, a CMOS standard cell circuit includes first supply rail, second supply rail, and metal lines disposed in the first metal layer. One or more of the metal lines are dynamically cut corresponding to a first cell boundary and a second cell boundary of the CMOS standard cell such that the metal lines have cut edges corresponding to the first and second cell boundaries. Metal lines not cut corresponding to the first and second cell boundaries can be used to interconnect nodes of the CMOS standard cell circuit. Dynamically cutting the metal lines allows the first metal layer to be used for routing, reducing routing in other metal layers such that fewer vias and metal lines are disposed above the first metal layer.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: May 22, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Anthony Correale, Jr., William Goodall, III, Philip Michael Iles
  • Patent number: 9941247
    Abstract: A memory device including a stack semiconductor device including; an upper substrate vertically stacked on a lower substrate, the upper substrate including N upper through-silicon vias (UTSV) and upper driving circuits, and the lower substrate including N lower through-silicon vias (LTSV) and lower driving circuits, wherein each one of the upper driving circuits is stagger-connected between a Kth UTSV and a (K+1)th LTSV, where ‘N’ is a natural number greater than 1, and ‘K’ is a natural number ranging from 1 to (N?1).
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: April 10, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hae-Suk Lee, Kyo-Min Sohn, Ho-Young Song, Sang-Hoon Shin, Han-Vit Jung
  • Patent number: 9929095
    Abstract: A MOS device includes an IO pad ring. The MOS device includes a first IO pad located on a first side of the IO pad ring, and a second IO pad located on a second side of the IO pad ring. The first IO pad includes a metal x layer power interconnect extending in a first direction. The first metal x layer power interconnect is of a metal x layer. The second side is 90° from the first side. The second IO pad includes a second metal x layer power interconnect extending in the first direction. The second metal x layer power interconnect is of the metal x layer. The second IO pad may further include at least one of a metal x+1 layer power interconnect or a metal x?1 layer power interconnect that extends orthogonal to the second metal x layer power interconnect of the second IO pad.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: March 27, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Rohit Vinod Singewar, Roshan Thonse Shetty
  • Patent number: 9899415
    Abstract: A radio frequency fully depleted silicon on insulator (RF-FDSOI) device and method of fabrication are provided. A silicon wafer for digital circuits is constructed using fully depleted silicon on insulator technology having a thin buried oxide layer. Localized areas of the silicon wafer are constructed for radio frequency circuits and/or passive devices. The silicon wafer has a silicon substrate having a resistivity greater than 1 K?·cm. The localized areas of the silicon wafer may include a trap rich layer implanted underneath a thin buried oxide layer. The localized areas of the silicon wafer may include a buried oxide layer that is thicker than the thin buried oxide layer. The thicker oxide layer is between 20 and 2000 nm thick. The localized areas of the silicon wafer may include a trap rich layer implanted underneath the thicker buried oxide layer.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: February 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Jean-Olivier Plouchart
  • Patent number: 9893054
    Abstract: A protection cell for a cell library. The protection cell defines a protection circuit for an IC having a driving device with a first supply voltage Vdd1 and an output, and a driven device having an input and a second supply voltage Vdd2. The protection circuit includes a first device from the group consisting of a P-diode and a gate-Vdd PMOS. The first device is coupled between a first power bus connected to Vdd2 and the input of the driven device. The input of the driven device is coupled by way of a resistor to the output of the driving device. A second device corresponding to the first device is provided, from the group consisting of an N-diode and a grounded gate NMOS. The second device is coupled between the input of the driven device and a ground bus.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: February 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Bo-Ting Chen
  • Patent number: 9882567
    Abstract: A programmable semiconductor device includes a user programmable switch comprising a configurable element positioned above a transistor material layer deposited on a substrate layer.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: January 30, 2018
    Assignee: CALLAHAN CELLULAR L.L.C.
    Inventor: Raminda Udaya Madurawe
  • Patent number: 9869910
    Abstract: A liquid crystal display device includes a display region, a plurality of lead-out lines led from the display region, and an application circuit that applies a voltage to liquid crystal in the display region through each of the lead-out lines. Each of the lead-out lines has a tilt portion wired with a directional component parallel to a peripheral direction enclosing the display region in a plan view, and when a difference between a voltage applied to one of the lead-out lines and a voltage applied to another one of the lead-out lines is specified as an applied voltage difference, each of the lead-out lines is wired such that, in a plan view, the taper portion of one of the lead-out lines is overlapped with the taper portion of another one of the lead-out lines having the applied voltage difference lower than a difference with adjacent one of the lead-out lines.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: January 16, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventor: Shohei Yasuda
  • Patent number: 9859263
    Abstract: A semiconductor package includes a package base substrate including bonding pads and a connection pads respectively on an upper surface and a lower surface of the package base substrate, four semiconductor chips attached onto the package base substrate, including a 1A semiconductor chip, a 1B semiconductor chip, a 2A semiconductor chip, and a 2B semiconductor chip, and each including a plurality of chip pads that are adjacent to a first edge of an upper surface of each of the 1A semiconductor chip, the 1B semiconductor chip, the 2A semiconductor chip, and the 2B semiconductor chip, and a bonding wire electrically connecting the chip pad and the bonding pad to each other, wherein the four semiconductor chips are disposed on the package base substrate such that first edges of the four semiconductor chips respectively face edges of the package base substrate that are different from each other.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: January 2, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-hong Kwon, Sang-nam Jeong, Sun-won Kang, Hee-jin Lee
  • Patent number: 9847339
    Abstract: Various embodiments provide a self-merged profile (SMP) method for fabricating a semiconductor device and a device fabricated using an SMP method. In an example embodiment, a semiconductor device is provided. The example semiconductor device comprises (a) a plurality of conductive lines; (b) a plurality of conductive pads; (c) a plurality of dummy tails; and (d) a plurality of closed loops. Each of the plurality of conductive pads is associated with one of the plurality of conductive lines, one of the plurality of dummy tails, and one of the plurality of closed loops. In example embodiments, the plurality of dummy tails and the plurality of closed loops are formed as residuals of the process used to create the plurality of conductive lines and the plurality of conductive pads.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: December 19, 2017
    Assignee: Macronix International Co., Ltd.
    Inventors: Yu-Min Hung, Chien-Ying Lee, Tzung-Ting Han
  • Patent number: 9837437
    Abstract: An integrated circuit (IC) may include at least one cell including a plurality of conductive lines that extend in a first direction and are in parallel to each other in a second direction that is perpendicular to the first direction, first contacts respectively disposed at two sides of at least one conductive line from among the plurality of conductive lines, and a second contact disposed on the at least one conductive line and the first contacts and forming a single node by being electrically connected to the at least one conductive line and the first contacts.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: December 5, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-hoon Baek, Sang-kyu Oh, Jung-Ho Do, Sun-young Park, Seung-young Lee, Hyo-sig Won
  • Patent number: 9818656
    Abstract: A method of testing includes attaching a first and second die to first and second die sites of a lead frame and forming a plurality of wire bonds coupling a plurality of pins of the first die site to the first die and a plurality of pins of the second die site to the second die. The first and second die are encapsulated. An isolation cut is performed to isolate the plurality of pins of the first die site from the plurality of pins of the second die site, while maintaining electrical connection between the first tie bar of the first die site and the first tie bar of the second die site. The first and second die are tested while providing a first power supply source to the first and second die via the first tie bars. After testing, the dies sites are fully singulated to result in packaged IC device.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: November 14, 2017
    Assignee: NXP USA, Inc.
    Inventors: Mark Edward Schlarmann, Dwight Lee Daniels, Stephen Ryan Hooper, Chad Dawson, Fengyuan Li
  • Patent number: 9812441
    Abstract: In a semiconductor integrated circuit device, a plurality of electrode pads for external connection are arranged in a zigzag pattern. Some electrode pads of the electrode pads of the plurality of I/O cells which are closer to a side of the semiconductor chip, each have an end portion closer to the side of the semiconductor chip, the end portion being set at the same position as that of an end portion of the corresponding I/O cell. A power source-side protective circuit and a ground-side protective circuit against discharge of static electricity are provided with the power source-side protective circuit being closer to the scribe region. A distance between a center position of one of the electrode pads and the ground-side protective circuit of the corresponding I/O cell and a distance between a center position of the other one electrode pad and the ground-side protective circuit of the corresponding I/O cell are both short and are substantially equal between each I/O cell.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: November 7, 2017
    Assignee: SOCIONEXT INC.
    Inventors: Koichi Taniguchi, Masato Maede
  • Patent number: 9812960
    Abstract: Methods and apparatus for DC-DC power controller with low standby current and fast transient response. In an example arrangement, an apparatus includes a voltage converter outputting a direct current output voltage, configured to increase the output voltage responsive to an enable control signal; at least one feedback comparator configured to output a first control signal, the feedback comparator being active responsive to an edge at a clock signal input; an adjustable frequency oscillator for outputting a first clock signal; and a fast transient detect circuit configured to output a second signal asynchronously upon detecting a rapid change greater than a voltage threshold in the output voltage; the voltage converter receiving the enable control signal when either the first clock signal is active, or the second signal is active and the output voltage is less than a reference voltage. Additional apparatus and methods are disclosed.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: November 7, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Keith Edmund Kunz, Vipul Kumar Singhal, Rajat Chauhan, Per Torstein Røine, Danielle Griffith
  • Patent number: 9780051
    Abstract: A method for forming a semiconductor structure includes forming a bond pad over a last metal layer of the semiconductor structure wherein the bond pad includes a wire bond region; and recessing the wire bond region such that the wire bond region has a first thickness and a region of the bond pad outside the wire bond region has a second thickness that is greater than the first thickness.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: October 3, 2017
    Assignee: NXP USA, Inc.
    Inventors: Tu-Anh N. Tran, Kurt H. Junker
  • Patent number: 9735157
    Abstract: A semiconductor device includes a first active area, a second active area and a first gate line. The second active area is spaced apart from the first active area. The first gate line includes a first gate part crossing the first active area along a first imaginary line, a second gate part crossing the second active area along a second imaginary line, and a third gate part connecting the first gate part and the second gate part and extending along a third imaginary line crossing the first imaginary line and the second imaginary line. The first gate part, the second gate part and the third gate part are arranged so that the first gate line has a shape of 180° rotational symmetry. A point of the rotational symmetry is located on the first gate part.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: August 15, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwan-Young Chun, Yoon-Moon Park, Kang-Ill Seo, Wouns Yang
  • Patent number: 9659887
    Abstract: A semiconductor device includes a pad group including pads provided on a semiconductor substrate and arranged in a row to form a pad row as a whole. The pad group includes at least one first pad provided with a first via-connection part electrically connected therewith and extending in a first direction perpendicular to a row direction of the pad row, and at least one second pad provided with a second via-connection part electrically connected therewith and extending in a second direction opposite to the first direction. The at least one second pad is formed at a position moved in the first direction from the row direction of the pad row passing through a center of the at least one first pad.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: May 23, 2017
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Nobutaka Nasu
  • Patent number: 9640494
    Abstract: An integrated circuit (IC) structure for radio frequency circuits having a grounded die seal that mitigates the effects of parasitic coupling through the die seal. Embodiments include conductive grounding ties that each electrically couple one or more of the internal grounding pads on an IC die within the magnetic loop formed by the die seal ring to an adjacent extent of an IC die seal. Induced parasitic energy within the die seal ring is quickly coupled to ground through the corresponding grounding ties and grounding pads. Accordingly, very little, if any, induced parasitic energy is propagated around the die seal ring.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: May 2, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Vikas Sharma
  • Patent number: 9639651
    Abstract: A routing method is illustrated. One exemplary embodiment of the routing method includes: determining a signal path between a signal source and a corresponding receiving terminal according to a routing structure of a system power mesh; determining a routing structure of an independent power mesh that is independent from the system power mesh according to the signal path; and performing a routing process according to the determined routing structure of the independent power mesh and the signal path. The system power mesh and the independent power mesh are respectively coupled to different voltage sources.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: May 2, 2017
    Assignee: ALI Corporation
    Inventors: Liang-Hsin Chen, Yi-Hsien Cheng
  • Patent number: 9633959
    Abstract: An integrated circuit (IC) die has side input/output (IO) pads located along each side of the die interior. Each die corner has a corner IO pad. The side IO pads adjacent to the corner IO pads have shortened passivation regions in the top metal layer (TML) that define TML access regions. TML traces run through the TML access regions to connect the corner IO pads to the die interior. Providing corner IO pads enables an IC die to have up to four more IO pads than a comparable conventional IC die that does not have any corner IO pads, or an IC die to have the same number of IO pads within a smaller overall footprint.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: April 25, 2017
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Shailesh Kumar, Vikas Garg, Meng Kong Lye
  • Patent number: 9607962
    Abstract: A semiconductor device includes a corner constituted by a first side and a second side being perpendicular to the first side; and a plurality of pads including a first pad, arranged along the second side and formed over a semiconductor substrate. The first pad is arranged nearer the corner than other pads of the plurality of pads. The first pad includes a third side, a fourth side being perpendicular to the third side, a fifth side being parallel to the third side and a sixth side being perpendicular to a fifth side. The third side and the fourth side are nearer to the corner than the fifth side and sixth side. A first dummy wiring is formed along the first side. A second dummy wiring is formed along the second side. The first dummy wiring and the second dummy wiring are formed integrally with each other.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: March 28, 2017
    Assignee: Renesas Electronics Corporation
    Inventor: Kentaro Saito
  • Patent number: 9589902
    Abstract: A semiconductor wafer has formed thereon various types of semiconductor chips and enables different types of semiconductor chips having the same chip size to be easily distinguished. An excluded region is formed on an outer periphery of the semiconductor wafer, and a region inside the excluded region is divided into different types of regions by boundaries. Mark chips are respectively arranged in the vicinity of both ends of the boundaries.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: March 7, 2017
    Assignee: SII Semiconductor Corporation
    Inventors: Yasunobu Matsumoto, Masaki Suzuki, Makoto Asou, Hiroshi Morita
  • Patent number: 9576947
    Abstract: In a semiconductor integrated circuit device, a plurality of electrode pads for external connection are arranged in a zigzag pattern. Some electrode pads of the electrode pads of the plurality of I/O cells which are closer to a side of the semiconductor chip, each have an end portion closer to the side of the semiconductor chip, the end portion being set at the same position as that of an end portion of the corresponding I/O cell. A power source-side protective circuit and a ground-side protective circuit against discharge of static electricity are provided with the power source-side protective circuit being closer to the scribe region. A distance between a center position of one of the electrode pads and the ground-side protective circuit of the corresponding I/O cell and a distance between a center position of the other one electrode pad and the ground-side protective circuit of the corresponding I/O cell are both short and are substantially equal between each I/O cell.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: February 21, 2017
    Assignee: SOCIONEXT INC.
    Inventors: Koichi Taniguchi, Masato Maede
  • Patent number: 9564903
    Abstract: A semiconductor die having: a logic unit having a plurality of inputs/outputs; a plurality of pads whereby electrical connections can be made to the die; and a multiplexer arranged between the inputs/outputs and the pads, the multiplexer being operable in a first mode in which it maps a first number of the inputs/outputs to a first number of the pads with a first mean spacing between those pads, and a second mode in which it maps a second number of the inputs/outputs to a first number of the pads with a second mean spacing between those pads, wherein the first number is larger than the second number and the first spacing is smaller than the second spacing.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: February 7, 2017
    Assignee: QUALCOMM TECHNOLOGIES INTERNATIONAL, LTD.
    Inventor: Paul Simon Hoayun
  • Patent number: 9558312
    Abstract: A standard cell semiconductor integrated circuit device design provides a standard cell semiconductor device that includes first standard cells and user-defined target standard cells which consume more power or include other operational characteristics that differ from the operational characteristics of the first standard cells. The standard cells are routed to ground and power wires using one power rail and the target cells are routed to the ground and power lines using the first power rail and a second power rail to alleviate electromigration in either of the power rails. The two power rails include an upper power rail and a lower power rail. An intermediate conductive layer may be disposed between the upper and lower power rails to provide for signal routing by lateral interconnection between cells.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: January 31, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lee-Chung Lu, Wen-Hao Chen, Yuan-Te Hou, Shen-Feng Chen, Meng-Fu You
  • Patent number: 9449936
    Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: September 20, 2016
    Assignee: INTEL CORPORATION
    Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charan K. Gurumurthy, Tamil Selvy Selvamuniandy
  • Patent number: 9418960
    Abstract: The driver semiconductor package includes a base substrate. The semiconductor package includes a semiconductor chip mounted on the base substrate. The semiconductor chip includes a core region disposed in a center part of the semiconductor chip, an internal circuit being provided in the core region. The semiconductor chip includes a plurality of IO cell regions disposed in a line along a side of the semiconductor chip, a differential circuit being provided in each of the plurality of IO cell regions. The semiconductor chip includes a non-inverting pad electrode disposed above each of the IO cell regions and electrically connected to a non-inverting terminal of the differential circuit. The semiconductor chip includes an inverting pad electrode disposed above each of the IO cell regions and connected to an inverting terminal of the differential circuit.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: August 16, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shohei Fukuda
  • Patent number: 9385714
    Abstract: Various implementations include circuits, devices and/or methods that provide closed-loop feedback crowbar current limiting for logic level-shifting between circuits with different voltage supplies. Some implementations include a level-shift circuit assembly including an input buffer and a current limiter. The input buffer is configured to receive an incoming logic signal that is set relative to a first electrical level, and in response, provide a level-shifted logic signal that is set relative to a second electrical level and is logically consistent with the incoming logic signal. The current limiter is configured to suppress the generation of current associated with the input buffer by providing a bias modification condition to the input buffer, in order to adjust the operation of the input buffer, in response to sensing a voltage difference between the first electrical level and the second electrical level.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: July 5, 2016
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventor: Gary S Bechman
  • Patent number: 9384991
    Abstract: A system and method for manufacturing a carbon layer is provided. An embodiment comprises depositing a first metal layer on a substrate, the substrate comprising carbon. A silicide is eptiaxially grown on the substrate, the epitaxially growing the silicide also forming a layer of carbon over the silicide. In an embodiment the carbon layer is graphene, and may be transferred to a semiconductor substrate for further processing to form a channel within the graphene.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: July 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Mark van Dal
  • Patent number: 9379101
    Abstract: In a semiconductor integrated circuit device, a plurality of electrode pads for external connection are arranged in a zigzag pattern. Some electrode pads of the electrode pads of the plurality of I/O cells which are closer to a side of the semiconductor chip, each have an end portion closer to the side of the semiconductor chip, the end portion being set at the same position as that of an end portion of the corresponding I/O cell. A power source-side protective circuit and a ground-side protective circuit against discharge of static electricity are provided with the power source-side protective circuit being closer to the scribe region. A distance between a center position of one of the electrode pads and the ground-side protective circuit of the corresponding I/O cell and a distance between a center position of the other one electrode pad and the ground-side protective circuit of the corresponding I/O cell are both short and are substantially equal between each I/O cell.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: June 28, 2016
    Assignee: SOCIONEXT INC
    Inventors: Koichi Taniguchi, Masato Maede
  • Patent number: 9269732
    Abstract: A chip package is provided. The chip package includes a chip, having a plurality of conductive pads disposed along a periphery of the chip, wherein the conductive pads have a width. A seal ring includes a plurality of metal strips disposed within a space between the two adjacent conductive pads. Each metal strip is electrically connected to at most one of the two adjacent conductive pads.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: February 23, 2016
    Assignee: XINTEC INC.
    Inventor: Chia-Lun Tsai
  • Patent number: 9213795
    Abstract: Among other things, one or more techniques and/or systems for performing design layout are provided. In an example, a design layout corresponds to a layout of a standard cell whose connectivity is described by a netlist. For example, the netlist specifies net types for respective vias of the standard cell. One or more connectivity rings are formed within the design layout to provide connectivity for one or more vias of the design layout. For example, a first connectivity ring is generated, such as from mandrel, to connect one or more ring one vias. A second connectivity ring is generated, such as from passive pattern, to connect one or more ring two vias. One or more cuts are generated within the design layout to isolate vias having different net types. In this way, the design layout is self-aligned double patterning (SADP) compliant.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: December 15, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chin-Hsiung Hsu, Huang-Yu Chen, Li-Chun Tien, Lee-Chung Lu, Hui-Zhong Zhuang, Cheng-I Huang, Chung-Hsing Wang, Yi-Kan Cheng
  • Patent number: 9183795
    Abstract: The present invention relates to a liquid crystal display device which can reduce a chip size and improves an electrostatic discharge capability. The liquid crystal display device includes a liquid crystal panel for displaying a picture, and a driving circuit unit for driving the liquid crystal panel, wherein the driving circuit unit includes an input/output unit having a plurality of input units for receiving signals from an outside and a plurality of output units for forwarding signals to an outside, a logic unit having a plurality of logical cells each having a plurality of digital logical devices for receiving or forwarding a signal through the input/output unit, and an electrostatic shielding unit for protecting the digital logical devices from an external static electricity, wherein some of elements of the electrostatic shielding unit are formed in spaces among the logical cells.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: November 10, 2015
    Assignee: LG Display Co., Ltd.
    Inventor: Jae-hun Jun
  • Patent number: 9041460
    Abstract: A power package is provided comprising a packaged transistor and a driving unit connected to the transistor and adapted to drive the transistor. A control terminal of the transistor is connected to a middle terminal pin of the housing of the transistor and outer terminal pins of the housing are connected to the driving unit and to a voltage level, respectively, wherein the connections are crossing free.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: May 26, 2015
    Assignee: Infineon Technologies AG
    Inventor: Ingo Voss
  • Patent number: 9029917
    Abstract: In a semiconductor integrated circuit device, a plurality of electrode pads for external connection are arranged in a zigzag pattern. Some electrode pads of the electrode pads of the plurality of I/O cells which are closer to a side of the semiconductor chip, each have an end portion closer to the side of the semiconductor chip, the end portion being set at the same position as that of an end portion of the corresponding I/O cell. A power source-side protective circuit and a ground-side protective circuit against discharge of static electricity are provided with the power source-side protective circuit being closer to the scribe region. A distance between a center position of one of the electrode pads and the ground-side protective circuit of the corresponding I/O cell and a distance between a center position of the other one electrode pad and the ground-side protective circuit of the corresponding I/O cell are both short and are substantially equal between each I/O cell.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: May 12, 2015
    Assignee: Socionext Inc.
    Inventors: Koichi Taniguchi, Masato Maede
  • Patent number: 9006794
    Abstract: An integrated circuit with electrically programmable fuse circuitry coupled to a programming transistor is provided. The programming transistor may be a metal-oxide-semiconductor transistor that is separated from other circuitry in an integrated circuit substrate with shallow trench isolation. The electrically programmable fuse circuitry may be formed in a second layer above the integrated circuit substrate using a conductive material which may be tungsten-based. This second layer may further include interconnect wires made from the same conductive material. The electrically programmable fuse may be coupled to the programming transistor through vias and routing paths in a fourth layer above the integrated circuit substrate. The routing paths in the fourth layer may be made from a conductive material which may be different than the fuse conductive material used to form the programmable fuse circuitry.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: April 14, 2015
    Assignee: Altera Corporation
    Inventors: Shuang Xie, Shankar Sinha, Cheng-Hsiung Huang
  • Patent number: 9000489
    Abstract: A multi-field effect transistor (FET) device includes a first FET device arranged on a substrate, the first FET device including a first active region and a second active region, a second FET device arranged on the substrate, the second FET device including a first active region and a second active region, and a first conductive interconnect electrically connecting the first active region of the first FET device to the first active region of the second FET device, the first conductive interconnect having a first cross sectional area proximate to the first active region of the first FET device that is greater than a second cross sectional area proximate to the first active region of the second FET device.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventor: Ning Lu
  • Patent number: 8957457
    Abstract: A method for manufacturing a semiconductor chip stack device is provided. The method includes forming a first connecting element array on a surface of a first semiconductor chip; forming a second connecting element array on a surface of a second semiconductor chip, the second array comprising more connecting elements than the first array and the pitch of the first array being a multiple of the pitch of the second array; applying the first chip against the second chip; and setting up test signals between the first and second chips to determine the matching between the connecting elements of the first array and the connecting elements of the second array.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: February 17, 2015
    Assignee: STMicroelectronics SA
    Inventors: Richard Fournel, Pierre Dautriche
  • Patent number: 8941150
    Abstract: An integrated circuit created from a cell library of compact cells. The cell library includes cells having a metal trace routed along the boundary of the cells for carrying a power supply voltage. The cells also include another metal trace routed along the interior of the cells for carrying another power supply voltage. A cell pin carrying an input signal or output signal of the cell is located outside of the region between the two power rails. By routing the power supply voltages and cell pins of the cell in this manner, the integrated circuit created from the cell is extremely compact while still complying with various design rules.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: January 27, 2015
    Assignee: Synopsys, Inc.
    Inventors: Deepak D. Sherlekar, Vahe Hovsepyan
  • Patent number: 8937351
    Abstract: A power metal-oxide-semiconductor (MOS) field effect transistor (FET) has a plurality of transistor cells, each cell having a source region and a drain region to be contacted through a surface of a silicon wafer die, A first dielectric layer is disposed on the surface of the silicon wafer die and a plurality of grooves are formed in the first dielectric layer above the source regions and drain regions, respectively and filled with a conductive material, A second dielectric layer is disposed on a surface of the first dielectric layer and has openings to expose contact areas to the grooves. A metal layer is disposed on a surface of the second dielectric layer and filling the openings, wherein the metal layer is patterned and etched to form separate metal wires connecting each drain region and each source region of the plurality of transistor cells, respectively through the grooves.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: January 20, 2015
    Assignee: Microchip Technology Incorporated
    Inventors: Gregory Dix, Harold Kline, Dan Grimm, Roger Melcher, Jacob L. Williams
  • Publication number: 20140353727
    Abstract: An integrated circuit including an ESD network including a portion located in ESD subareas of a plurality of I/O cells where the ESD subareas are arranged in a row traversing the plurality of I/O cells. The ESD network includes ESD clamp cells and ESD trigger circuit cells wherein a portion of the network is located in the row. In some examples, the row includes an ESD trigger circuit cell with a portion in one subarea of one ESD subarea of one I/O cell and a second portion in a second ESD subarea of another I/O cell. Also described herein is a method for producing an integrated circuit layout with an ESD network.
    Type: Application
    Filed: May 30, 2013
    Publication date: December 4, 2014
    Inventors: MELANIE ETHERTON, ALEXEY GILBUR, JAMES W. MILLER, JONATHAN M. PHILLIPPE, ROBERT S. RUTH
  • Patent number: 8890215
    Abstract: The present invention provides for a multiprocessor device on either a chip or a stack of chips. The multiprocessor device includes a plurality of processing entities and a memory system. The multiprocessor device further includes at least one interface unit to at least one of an external memory and one or more peripherals. The multiprocessor device includes a bus system interconnecting the processing entities, the memory system and the at least one interface unit. Wherein, the memory system includes a plurality of cache segments, and the plurality of segments are located on a plurality of memory cores, each having a connection to the bus system.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: November 18, 2014
    Assignee: Pact XPP Technologies AG
    Inventor: Martin Vorbach
  • Patent number: 8884337
    Abstract: An output buffer includes an input/output end, a voltage source, a first transistor and a second transistor. The first transistor includes a first end coupled to the input/output end, a second end coupled to the voltage source, and a control end coupled to the voltage source. The second transistor includes a first end coupled to the input/output end, a second end coupled to the voltage source, and a control end coupled to the voltage source. The control end of the first transistor and the control end of the second transistor are substantially perpendicular to each other, and the punch through voltage of the first transistor is higher than the punch through voltage of the second transistor.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: November 11, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chang-Tzu Wang, Ping-Chen Chang, Tien-Hao Tang
  • Patent number: 8841187
    Abstract: Disclosed is a semiconductor device and a method for fabricating the semiconductor device. The method for fabricating the semiconductor device comprises steps of: forming a side cliff in a substrate in accordance with a gate mask pattern, the side cliff being substantially vertical to a substrate surface; forming a dielectric layer on the substrate that comprises the side cliff; etching the dielectric layer to have the dielectric layer left only on the side cliff, as a dielectric wall; and burying the side cliff by a substrate growth, the burying is performed up to a level higher than the upper end of the dielectric wall.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: September 23, 2014
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Meng Zhao