With Particular Chip Input/output Means Patents (Class 257/203)
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Patent number: 7728361Abstract: In the present invention, a method of testing an unpackaged integrated circuit die is disclosed. The die has a plurality of first input/output pads. A serial electrical connection is fabricated in the die between all of the input/output pads of the die which are not of the first plurality (hereinafter: “second plurality”). The second plurality has a start input and an end output. The start input of the second plurality is connected to the output of one selected input buffer of the input pad of the first plurality and the end output of the second plurality is also connected to the input of one selected output pad of the first plurality. The second plurality of input/output pads are tested through selected input pad and selected output pad of the first plurality without electrical probes making contact during the wafer sort. The present invention also relates to an integrated circuit die so fabricated as to facilitate testing.Type: GrantFiled: May 1, 2008Date of Patent: June 1, 2010Assignee: Silicon Storage Technology, Inc.Inventors: Kangping Zhang, Fong-Long Lin
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Patent number: 7725865Abstract: A method for a computer setting up a terminal layer of a semiconductor circuit having plural wiring layers including obtaining various kinds of information such as placement information relating to a plurality of cells or macros of the semiconductor circuit and being mounted onto a circuit board from a storage unit of the computer; comparing a driving capacity of a subject cell or macro, which is contained in the obtained information, and a resistance of wiring for connecting the subject cell or macro with the cell or macro at a connecting destination; and setting up a terminal layer based on a result of the comparing.Type: GrantFiled: September 28, 2005Date of Patent: May 25, 2010Assignee: Fujitsu Microelectronics LimitedInventor: Hisayoshi Oba
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Patent number: 7714362Abstract: A semiconductor device including a plurality of input/output cells and having a first bond pad and at least one second bond pad coupled to each input/output cell. The first bond pads comprise a first pattern, and the at least second bond pads comprise at least one second pattern, wherein the at least one second pattern is different from or the same as the first pattern. Either the first bond pads, the at least second bond pads, or both, may be used to electrically couple the input/output cells of the semiconductor device to leads of an integrated circuit package or other circuit component.Type: GrantFiled: May 12, 2006Date of Patent: May 11, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Ker-Min Chen
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Publication number: 20100109053Abstract: The present invention discloses a semiconductor device. The semiconductor device includes an integrated circuit and a connecting component. The integrated circuit includes a first pad; a second pad; a first current guiding circuit, coupled to the first pad and a first reference voltage, for selectively guiding a first specific electrical signal received from the first pad to the first reference voltage; and a second current guiding circuit, coupled to the second pad and a second reference voltage, for selectively guiding a second specific electrical signal received from the second pad to the second reference voltage; and the connecting component is external to the integrated circuit for coupling the first pad and the second pad.Type: ApplicationFiled: November 4, 2008Publication date: May 6, 2010Inventors: Ching-Han Jan, Yu-Hsin Lin
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Patent number: 7709861Abstract: Various systems and methods for implementing multi-mode semiconductor devices are discussed herein. For example, a multi-mode semiconductor device is disclosed that includes a device package with a number of package pins. In addition, the device includes a semiconductor die or substrate with at least two IO buffers. One of the IO buffers is located a distance from a package pin and another of the IO buffers is located another distance from the package pin. One of the IO buffers includes first bond pad electrically coupled to a circuit implementing a first interface type and a floating bond pad, and the other IO buffer includes a second bond pad electrically coupled to a circuit implementing a second interface type. In some cases, the floating bond pad is electrically coupled to the circuit implementing the second interface type via a conductive interconnect, and the floating bond pad is electrically coupled to the package pin.Type: GrantFiled: March 12, 2007Date of Patent: May 4, 2010Assignee: Agere Systems Inc.Inventors: Parag Madhani, Paul F. Barnes, Donald E. Hawk, Jr., Kandaswamy Prabakaran
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Patent number: 7704837Abstract: A unit cell for an integrated circuit includes a first conductive type active region and a second conductive type active region which extend in a first direction. Each of the active regions has first and second ends. The first end of the second conductive type active region opposes the second end of the first conductive type active region. A poly-silicon pattern extends in the first direction across the first conductive type active region and second conductive type active region. A first contact region is adjacent the first end of the first conductive type active region in the first direction. A second contact region is adjacent the second end of the second conductive type active region in the first direction.Type: GrantFiled: August 7, 2008Date of Patent: April 27, 2010Assignee: Oki Semiconductor Co., Ltd.Inventors: Hirohisa Masuda, Hirokazu Ishikawa
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Publication number: 20100096670Abstract: Methods and devices yielding an improved semiconductor device with interface circuit are disclosed. Configuring a semiconductor with parallel device features reduces process variation (e.g., lithographically-induced process variation or other defects). Embodiments of the present invention provide semiconductor devices with I/O cell device features (e.g., I/O gates or core gates) laid out in parallel. Additionally, embodiments of the present invention can allow patterning devices to be made to more exacting tolerances because some patterning devices may have a higher capability along one axis than another. Embodiments of the present invention also include a semiconductor device having like-functioned I/O cells arranged such that their layouts and rotational orientations with respect to their corresponding core remain constant.Type: ApplicationFiled: December 18, 2009Publication date: April 22, 2010Applicant: Kabushiki Kaisha ToshibaInventor: Eiichi Hosomi
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Publication number: 20100090252Abstract: To provide a semiconductor integrated circuit device advantageous against EM and ESD. A plurality of I/O cells; a power wire formed of a plurality of interconnect layers over the above-described I/O cells; a bonding pad formed in an upper layer of the power wire and in a position corresponding to the I/O cell; and lead-out areas capable of electrically coupling the I/O cell to the bonding pad are provided. The above-described power wire includes a first power wire and a second power wire, and the above-described I/O cell includes first elements coupled to the first power wire and second elements coupled to the second power wire. The first element is placed on the first power wire side, and the second element is placed on the second power wire side. The first power wire and the second power wire can allow for a high current due to the interconnect layers over the I/O cells, thus having robustness against EM and ESD.Type: ApplicationFiled: December 10, 2009Publication date: April 15, 2010Inventors: Shunsuke TOYOSHIMA, Kazuo TANAKA, Masaru IWABUCHI
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Patent number: 7683403Abstract: A design method for an integrated circuit adds spare cells in a System-on-Chip to allow for Engineering Change Orders (ECOs) to be performed at a later stage in the design. This method can be used to provide a second version of the chip having minimal alterations performed in a short cycle time. The spare cells can be divided into combinational and sequential cells. There is an optimum spread of combinational cells in the design for post placement repairs of the chip with just metal layer changes. The method takes into account the drive strength of the spare cells as the main factor in their placement on the chip.Type: GrantFiled: March 28, 2008Date of Patent: March 23, 2010Assignee: STMicroelectronics, Inc.Inventor: Anshuman Tripathi
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Patent number: 7671384Abstract: An integrated circuit device comprises a memory cell well formed with a flash memory device, first and second well of opposite conductivity types for formation of high voltage transistors, and third and fourth wells of opposite conductivity types for low voltage transistors, wherein at least one of the first and second wells and at least one of the third and fourth wells have an impurity distribution profile steeper than the memory cell well.Type: GrantFiled: August 24, 2005Date of Patent: March 2, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Taiji Ema, Hideyuki Kojima, Toru Anezaki
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Patent number: 7667330Abstract: A semiconductor device includes an input/output pad, an input line of an internal circuit, and a plurality of metal lines formed on a lower portion of the input/output pad to have a buffer area overlapping with a plane area of the input/output pad, wherein one of an entirety and a portion of the plurality of metal lines included in the buffer area forms protective resistance interconnecting the input/output pad to the input line.Type: GrantFiled: September 10, 2008Date of Patent: February 23, 2010Assignee: Hynix Semiconductor, Inc.Inventor: Si Woo Lee
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Patent number: 7663247Abstract: A semiconductor integrated circuit device includes a semiconductor chip, a memory cell array arranged on the semiconductor chip and first and second decoder strings arranged along both ends of the memory cell array. The arrangement position of the first decoder string is deviated from the arrangement position of the second decoder string and a space caused by the deviation is arranged in the corner of the semiconductor chip.Type: GrantFiled: July 11, 2008Date of Patent: February 16, 2010Assignee: Kabuhsiki Kaisha ToshibaInventor: Takahiko Hara
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Patent number: 7663163Abstract: A semiconductor device includes a first pad, a second pad and a third pad. The first pad and the third pad are electrically connected to each other. The first pad and the second pad are used for bonding. The second pad and the third pad are used for probing. According to this structure, Small size semiconductor device having high reliability even after a probing test can be provided.Type: GrantFiled: July 12, 2007Date of Patent: February 16, 2010Assignee: NEC Electronics CorporationInventor: Tsukasa Ojiro
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Publication number: 20100012979Abstract: Disclosed is a substrate for an electro-optical device including: a substrate; a plurality of data lines and a plurality of scanning lines which intersect with other on the substrate; a pixel electrode formed in each of a plurality of pixels which configure a display region on the substrate and are defined in correspondence with intersections between the plurality of data lines and the plurality of scanning lines; a transistor provided in each of non-opening regions which discriminate between opening regions of the plurality of pixels and including a semiconductor layer including a channel region having a channel length in one direction of the display region, a data line side source/drain region electrically connected to the data line, a pixel electrode side source/drain region electrically connected to the pixel electrode, a first junction region formed between the channel region and the data line side source/drain region, and a second junction region formed between the channel region and the pixel electrodeType: ApplicationFiled: September 25, 2009Publication date: January 21, 2010Applicant: SEIKO EPSON CORPORATIONInventor: Tatsuya ISHII
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Patent number: 7642551Abstract: A wafer-level package includes a semiconductor wafer having at least one semiconductor chip circuit forming region each including a semiconductor chip circuit each provided with test chip terminals and non test chip terminals, at least one external connection terminal, at least one redistribution trace provided on the semiconductor wafer, at least one testing member, and an insulating material. A first end of the redistribution trace is connected to one of the test chip terminals and a second end of said redistribution trace is extended out to a position offset from the chip terminals. The testing member is provided in an outer region of the semiconductor chip circuit forming region, and the second end of the redistribution trace is connected to the testing member.Type: GrantFiled: June 10, 2008Date of Patent: January 5, 2010Assignee: Fujitsu Microelectronics LimitedInventor: Shigeyuki Maruyama
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Publication number: 20090321721Abstract: The present invention is directed toward field effect transistors (FETs) and thin film transistors (TFTs) comprising carbon nanotubes (CNTs) and to methods of making such devices using solution-based processing techniques, wherein the CNTs within such devices have been fractionated so as to be concentrated in semiconducting CNTs. Additionally, the relatively low-temperature solution-based processing achievable with the methods of the present invention permit the use of plastics in the fabricated devices.Type: ApplicationFiled: April 25, 2007Publication date: December 31, 2009Applicant: General Electric CompanyInventors: Patrick Roland Lucien Malenfant, Ji-Ung Lee, Yun Li, Walter Vladimir Cicha
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Publication number: 20090273007Abstract: In the present invention, a method of testing an unpackaged integrated circuit die is disclosed. The die has a plurality of first input/output pads. A serial electrical connection is fabricated in the die between all of the input/output pads of the die which are not of the first plurality (hereinafter: “second plurality”). The second plurality has a start input and an end output. The start input of the second plurality is connected to the output of one selected input buffer of the input pad of the first plurality and the end output of the second plurality is also connected to the input of one selected output pad of the first plurality. The second plurality of input/output pads are tested through selected input pad and selected output pad of the first plurality without electrical probes making contact during the wafer sort. The present invention also relates to an integrated circuit die so fabricated as to facilitate testing.Type: ApplicationFiled: May 1, 2008Publication date: November 5, 2009Inventors: Kangping Zhang, Fong-Long Lin
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Patent number: 7592710Abstract: A bond pad structure of an integrated circuit is provided. The bond pad structure includes a conductive bond pad, a first dielectric layer underlying the bond pad, and an Mtop plate located in the first dielectric layer and underlying the bond pad. The Mtop plate is a solid conductive plate and is electrically coupled to the bond pad. The bond pad structure further includes a first passivation layer over the first dielectric layer wherein the first passivation layer has at least a portion under a middle portion of the bond pad. At least part of an active circuit is located under the bond pad.Type: GrantFiled: April 21, 2006Date of Patent: September 22, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Chiu Hsia, Chih-Hsiang Yao, Tai-Chun Huang, Chih-Tang Peng
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Patent number: 7582921Abstract: In a masking pattern (a) for patterning word and data lines, length is changed between adjacent word lines so as to be shifted from each other at their tips, and furthermore, the tip of each word line is cut obliquely. It is thus possible to prevent the resist pattern from separation and contact of adjacent patterns. Consequently, it is also possible to prevent break failures of patterned lines and short failures between those patterned lines.Type: GrantFiled: August 16, 2006Date of Patent: September 1, 2009Assignee: Hitachi, Ltd.Inventors: Tomonori Sekiguchi, Toshihiko Tanaka, Toshiaki Yamanaka, Takeshi Sakata, Katsutaka Kimura
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Patent number: 7576440Abstract: A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region. The bond pad-wiring pattern is formed substantially in a center region of the semiconductor substrate. Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced and an MCP can be fabricated without the problems mentioned above.Type: GrantFiled: November 2, 2006Date of Patent: August 18, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Hee Song, Il-Heung Choi, Jeong-Jin Kim, Hae-Jeong Sohn, Chung-Woo Lee
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Patent number: 7573135Abstract: The present invention includes the steps of forming a first resin film uncured on a wiring substrate including a wiring pattern, burying an electronic parts having a connection terminal on an element formation surface in the first resin film uncured in a state where the connection terminal is directed upward, forming a second resin film for covering the electronic parts, obtaining an insulation film by curing the first and second resin films by heat treatment, forming a via hole in a predetermined portion of the insulation film on the wiring pattern and the connection terminal, and forming an upper wiring pattern connected to the wiring pattern and the connection terminal through the via hole, on the insulation film.Type: GrantFiled: May 17, 2007Date of Patent: August 11, 2009Assignee: Shinko Electric Industries Co., Ltd.Inventors: Masahiro Sunohara, Kei Murayama, Mitsutoshi Higashi, Toshinori Koyama
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Patent number: 7573066Abstract: A semiconductor substrate inspection method includes: generating a charged particle beam, and irradiating the charged particle beam to a semiconductor substrate in which contact wiring lines are formed on a surface thereof, the contact wiring lines of the semiconductor substrate being designed to alternately repeat in a plane view so that one of the adjacent contact wiring lines is grounded to the semiconductor substrate and the other of the adjacent contact wiring lines is insulated from the semiconductor substrate; detecting at least one of a secondary charged particle, a reflected charged particle and a back scattering charged particle generated from the surface of the semiconductor substrate to acquire a signal; generating an inspection image with the signal, the inspection image showing a state of the surface of the semiconductor substrate; and judging whether the semiconductor substrate is good or bad from a difference of brightness in the inspection image obtained from the surfaces of the adjacent contType: GrantFiled: April 4, 2007Date of Patent: August 11, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyuki Hayashi, Takamitsu Nagai, Tomonobu Noda, Kenichi Kadota, Hisaki Kozaki
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Publication number: 20090189194Abstract: Semiconductor devices, methods of manufacturing thereof, and methods of arranging circuit components of an integrated circuit are disclosed. In one embodiment, a semiconductor device includes an array of a plurality of devices arranged in a plurality of rows. At least one electrostatic discharge (ESD) protection circuit or a portion thereof is disposed in at least one of the plurality of rows of the array of the plurality of devices.Type: ApplicationFiled: January 28, 2008Publication date: July 30, 2009Inventors: Uwe Paul Schroeder, David Alvarez
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Publication number: 20090189195Abstract: Semiconductor devices, methods of manufacturing thereof, and methods of arranging circuit components of an integrated circuit are disclosed. In one embodiment, a semiconductor device includes an array of a plurality of devices arranged in a plurality of rows. At least one radio frequency (RF) circuit or a portion thereof is disposed in at least one of the plurality of rows of the array of the plurality of devices.Type: ApplicationFiled: January 29, 2008Publication date: July 30, 2009Inventors: Uwe Paul Schroeder, Chu-Hsin Liang
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Publication number: 20090166620Abstract: In a semiconductor chip in which external connection pads are arranged in three or more rows in a staggered configuration at the peripheral portion thereof, a first pad which is arranged in the outermost row is used as a power supply pad or a ground pad for an internal core circuit. To the first pad, a second pad which is arranged in the second outermost row is connected with a metal in the same layer as a pad metal. The resistance of a power supply line to the internal core circuit has a value of the parallel resistance of a resistance from the first pad and a resistance from the second pad, which is by far lower than the resistance from the first pad. Therefore, it is possible to prevent circuit misoperation resulting from an IR drop in the power supply of the internal core circuit.Type: ApplicationFiled: November 11, 2008Publication date: July 2, 2009Inventor: Masato MAEDE
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Publication number: 20090166679Abstract: An integrated circuit (IC) having a selectively-designated electromagnetic compatibility (EMC) performance characteristic. The IC includes an IC die having an input or output (I/O) node. A first I/O cell of a first type associated with the I/O node provides a first EMC performance characteristic, and a second I/O cell of a second type associated with the I/O node provides a second EMC performance characteristic different from the first EMC performance characteristic. A first bonding pad is electrically coupled with the first I/O cell, and a second bonding pad is electrically coupled with the second I/O cell. The IC die can be packaged into a packaged IC having an I/O pin corresponding to the I/O node. The I/O pin is wired to one of either the first bonding pad or the second bonding pad, but not to the other, such that a pinout for the I/O node is preferentially provided having one of either the first EMC performance characteristic or the second EMC performance characteristic.Type: ApplicationFiled: December 31, 2007Publication date: July 2, 2009Inventors: Paul Paternoster, Vaibhavi Sabharanjak, Po-Shen Lai
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Patent number: 7554133Abstract: An integrated circuit with a monolithic semiconducting substrate formed in a chip, where the chip has a peripheral edge, a backside, and an opposing top on which circuitry is formed. A first ring of bonding pads is formed along at least a portion of the peripheral edge. At least one of the bonding pads is configured as a power pad, and at least one of the bonding pads is configured as a ground pad. An intermediate power bus is disposed interior to the first ring of bonding pads on the chip, and forms no direct electrical connections to any core devices. An intermediate ground bus is also disposed interior to the first ring of bonding pads on the chip, and forms no direct electrical connections to any core devices. A power pad wire forms an exclusive electrical connection between the power pad and the intermediate power bus. A ground pad wire forms an exclusive electrical connection between the ground pad and the intermediate ground bus.Type: GrantFiled: May 13, 2008Date of Patent: June 30, 2009Assignee: LSI CorporationInventors: Anwar Ali, Nenad Miladinovic, Kalyan Doddapaneni
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Patent number: 7550790Abstract: A D/A conversion circuit with a small area is provided. In the D/A conversion circuit, according to a digital signal transmitted from address lines of an address decoder, one of four gradation voltage lines is selected. A circuit including two N-channel TFTs is connected in series to a circuit including two P-channel TFT, and a circuit including the circuits connected in series to each other is connected in parallel to each of the gradation voltage lines. Further, an arrangement of the circuit including the two N-channel TFTs and the circuit including the two P-channel TFTs is reversed for every gradation voltage line. By this, the crossings of wiring lines in the D/A conversion circuit becomes small and the area can be made small.Type: GrantFiled: February 22, 2007Date of Patent: June 23, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Jun Koyama, Mitsuaki Osame, Yukio Tanaka, Munehiro Azami, Naoko Yano, Shou Nagao
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Design Structure for an On-Demand Power Supply Current Modification System for an Integrated Circuit
Publication number: 20090152591Abstract: A design structure for a circuit that selectively connects an integrated circuit to elements external to the integrated circuits. The circuit includes and input/output element that selectively connects an input/output pin as a function of a power requirement or a signal bandwidth requirement of the integrated circuit. The input/output element includes one or more switching devices that connect the input/output pin to an external element, such as a power supply or external signal path. The input/output element also includes one or more switching devices that connect the input/output pin to an internal element, such as a power network or internal signal line.Type: ApplicationFiled: December 17, 2007Publication date: June 18, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Corey K. Barrows, Kenneth J. Goodnow, Stephen G. Shuma, Peter A. Twombly, Paul S. Zuchowski -
Publication number: 20090152592Abstract: A design structure including: an I/O cell and an ESD protection circuit in a region of an integrated circuit chip containing logic circuits; an electrically conductive through via extending from a bottom surface of the substrate toward a top surface of the substrate between the I/O cell and an ESD protection circuit and at least one of the logic circuits.Type: ApplicationFiled: March 6, 2008Publication date: June 18, 2009Inventors: Phillip Francis Chapman, David S. Collins, Steven H. Voldman
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Publication number: 20090146189Abstract: A three dimensional semiconductor device, comprising: a substrate including a plurality of circuits; a plurality of pads, each pad coupled to a said circuit; and a memory array positioned above or below the substrate coupled to a said circuit to program the memory array.Type: ApplicationFiled: November 19, 2007Publication date: June 11, 2009Inventor: Raminda Udaya Madurawe
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Patent number: 7531852Abstract: In an electronic unit with a substrate, a control circuit is mounted on the substrate and is configured to execute an operation related to a load. A package encapsulates the control circuit and the substrate. The package has sides around a periphery of the substrate. At least one input terminal for input of a signal externally sent to the electronic unit is disposed on at least one of the plurality of surfaces. At least one output terminal for output of a control signal for controlling the load is disposed on at least another one of the plurality of surfaces. At least one check terminal for input/output of a signal for checking at least the control circuit is disposed on at least another one of the plurality of surfaces.Type: GrantFiled: June 14, 2005Date of Patent: May 12, 2009Assignee: DENSO CORPORATIONInventors: Nobumasa Ueda, Hirokazu Kasuya, Koji Numazaki, Yutaka Fukuda, Mitsuhiro Saitou
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Patent number: 7525132Abstract: The facility of operation in a manufacturing process and the reliability of the finished product can be improved by making a design based on two basic wiring pattern layers in which wiring traces are formed with regularity, and a basic via array layer inserted between the two basic wiring pattern layers, in which vias are formed with regularity.Type: GrantFiled: February 2, 2007Date of Patent: April 28, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Shinji Kitabayashi, Yukihiro Urakawa
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Patent number: 7522405Abstract: A method and system are disclosed for a high current electrical switch. The switch may be suitable for switching, rectifying or blocking direct current in the range of one to a thousand amperes per module or assembly. It does so with such high efficiency that it produces relatively insignificant heat; such that it requires little or no cooling by convection or radiation. The relatively low heat that is generated in the process is conducted away quite effectively by the electric cables connected to the device.Type: GrantFiled: May 23, 2005Date of Patent: April 21, 2009Assignee: Perfect Switch, LLCInventor: H. Frank Fogleman
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Patent number: 7521735Abstract: A semiconductor on insulator substrate and a method of fabricating the substrate. The substrate including: a first crystalline semiconductor layer and a second crystalline semiconductor layer; and an insulating layer bonding a bottom surface of the first crystalline semiconductor layer to a top surface of the second crystalline semiconductor layer, a first crystal direction of the first crystalline semiconductor layer aligned relative to a second crystal direction of the second crystalline semiconductor layer, the first crystal direction different from the second crystal direction.Type: GrantFiled: January 4, 2008Date of Patent: April 21, 2009Assignee: International Business Machines CorporationInventors: Toshiharu Furukawa, David V. Horak, Charles W. Koburger, III, Leathen Shi
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Patent number: 7514728Abstract: In a semiconductor substrate of a first conductivity type, a first well region of the first conductivity type, second well regions of a second conductivity type, and a third well region of the second conductivity type are formed. The second well regions are formed in the semiconductor substrate excluding the region where the first well region has been formed. The third well region is formed under the first and second well regions in the semiconductor substrate in such a manner that a part of the third well region under the first well region is removed, thereby connecting the second well regions to one another electrically.Type: GrantFiled: November 30, 2007Date of Patent: April 7, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Takeshi Sugahara, Yasuhito Itaka
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Patent number: 7514796Abstract: To prevent short-circuit due to contact of bonding wires each other and to make a semiconductor device compact. A semiconductor chip with a rectangular main surface may comprise: a first side composing the main surface; a second side opposed to the first side; a main electrode pad group composed of a plurality of main electrode pads, which plurality of main electrode pads is arranged on the main surface along the first side; a first electrode pad group composed of a plurality of first electrode pads, which plurality of first electrode pads is arranged between the first side and the main electrode pad group; a second electrode pad group composed of a plurality of second electrode pads, which plurality of second electrode pads is arranged on the main surface along the second side; a first interconnection connecting the main electrode pad with the first electrode pad; and a second interconnection connecting the main electrode pad with the second electrode pad.Type: GrantFiled: November 3, 2006Date of Patent: April 7, 2009Assignee: Oki Semiconductor Co., Ltd.Inventor: Yoshihiro Saeki
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Publication number: 20090078967Abstract: The present invention comprises a semiconductor chip, and a semiconductor device having a plurality of semiconductor chips, that enables ESD protection from another semiconductor chip without increasing the chip area in case the semiconductor chip is Multi-Chip-Packaged, without wasting chip area in case the semiconductor chip is not Multi-Chip-Packaged. The exemplary semiconductor chip of the present invention includes an internal circuit and a first electrode pad electrically connected to a ground bus line of the first semiconductor chip in a region where an electrode pad, which gives and receives electric signals required for an operation of the internal circuit, cannot be provided.Type: ApplicationFiled: August 19, 2008Publication date: March 26, 2009Inventor: Katsuhiro Kato
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Patent number: 7508238Abstract: A semiconductor integrated circuit device includes a main region on which a main circuit is formed and a spare cell region for logic modification of the circuit formed on the main region. The spare cell region includes a P-channel transistor region, an N-channel transistor region, a plurality of gate electrodes provided above the P-channel transistor region and the N-channel transistor region, a main wire layer that is a different layer from the gate electrodes, and a plurality of bypass wires that are formed at a different layer from the main wire layer. Each of the plurality of bypass wires has a structure that can be connected to the main wire layer at more than one point through contact holes formed in a dielectric layer intervening between the main wire layer and the bypass wires.Type: GrantFiled: August 2, 2005Date of Patent: March 24, 2009Assignee: Elpida Memory, Inc.Inventor: Minoru Yamagami
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Patent number: 7499340Abstract: A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The first memory arrays are formed in the first rectangle region. The second memory arrays are formed in the second rectangle region. The voltage generator and first bonding pads are arranged in the third rectangle region. The first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the second memory arrays.Type: GrantFiled: January 9, 2008Date of Patent: March 3, 2009Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata
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Publication number: 20090050940Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.Type: ApplicationFiled: October 17, 2008Publication date: February 26, 2009Inventors: Takahiro Hayashi, Shunsuke Toyoshima, Kazuo Sakamoto, Naozumi Morino, Kazuo Tanaka
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Patent number: 7495269Abstract: A semiconductor device contains a semiconductor chip, and includes first and second circuits, a control signal line and a terminal. The first circuit is arranged in a center of the semiconductor chip and is configured to operate at a first voltage. The second circuit is arranged in an input/output circuit area around the first circuit on the semiconductor chip, and is configured to operate at the first voltage and a second voltage and to transfer a signal between an external unit outside the semiconductor chip and the first circuit. The control signal line is provided for the input/output circuit area on the semiconductor chip. The terminal is connected with the control signal line and supplied with a control signal. The second circuit stops a transfer of the signal between the external unit and the first circuit in response to the control signal which is transferred on the control signal line.Type: GrantFiled: August 16, 2005Date of Patent: February 24, 2009Assignee: NEC Electronics CorporationInventor: Tetsuya Katoh
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Patent number: 7492013Abstract: Systems and arrangements to interconnect cells and structures within cells of an integrated circuit to enhance cell density. Embodiments comprise an adjusted polysilicon gate pitch to metal wire pitch relationship to improve area scalars while increasing ACLV tolerance with a fixed polysilicon gate pitch. In some embodiments, the wire pitch for at least one metallization layer is adjusted to match the pitch for the polysilicon gate. In one embodiment, the next to the lowest metallization layer running in the same orientation as the polysilicon gate, utilized to access the input or output of the interconnected cell structures is relaxed to match the minimum contacted gate pitch and the metal is aligned above each polysilicon gate. In another embodiment, the polysilicon gate pitch may be relaxed to attain a smaller lowest common multiple with the wire pitch for an integrated circuit to reduce the minimum step off.Type: GrantFiled: June 27, 2005Date of Patent: February 17, 2009Assignee: International Business Machines CorporationInventor: Anthony Correale, Jr.
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Patent number: 7491986Abstract: A different electric power supply electric power source cell is proposed which includes paths by which electric power source voltages, the electric potentials of which are different from each other, are respectively taken in from the area pad and the probing pad and by which the voltages are supplied to the blocks requiring these electric power source voltages.Type: GrantFiled: December 22, 2003Date of Patent: February 17, 2009Assignee: Panasonic CorporationInventors: Takaaki Kumagae, Yasuyuki Okada, Masumi Nobata
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Patent number: 7488994Abstract: A coiled circuit device is produced by forming a circuit layer on a substrate. Optional insulator layers may be disposed above and below the circuit layer. The circuit layer, which may be memory, control, or other circuitry, is released from the substrate such that it coils into a dense, coiled device. A stressed coiling layer may be included which effects coiling when the circuit layer is released.Type: GrantFiled: June 7, 2004Date of Patent: February 10, 2009Assignee: Northrop Grumman CorporationInventors: Harvey C. Nathanson, Robert S. Howell, Garrett A. Storaska
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Patent number: 7488995Abstract: In a semiconductor integrated circuit device in which a plurality of I/O cells having level shift circuits are placed in an I/O region, two input/output cells respectively have four level shift circuits 11, 12a to 12c. A power supply cell, originally including only wiring for supply of a power supply voltage or a ground voltage, is additionally provided with three level shift circuits, which should originally be placed in the two input/output cells. The level shift circuits in the power supply cell are circuits asked for no high-speed operation and shared by the two input/output cells. This reduces the size of the two input/output cells and reduces the pitch of the I/O cells, permitting a larger number of required pins in a smaller area.Type: GrantFiled: March 9, 2006Date of Patent: February 10, 2009Assignee: Panasonic CorporationInventors: Shiro Usami, Daisuke Matsuoka
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Patent number: 7465971Abstract: A configuration memory cell (“CRAM”) for a field programmable gate array (“FPGA”) integrated circuit (“IC”) device is given increased resistance to single event upset (“SEU”). A portion of the gate structure of the input node of the CRAM is increased in size relative to the nominal size of the remainder of the gate structure. Part of the enlarged gate structure is located capacitively adjacent to an N-well region of the IC, and another part is located capacitively adjacent to a P-well region of the IC. This arrangement gives the input node increased capacitance to resist SEU, regardless of the logical level of the input node. The invention is also applicable to any node of any type of memory cell for which increased resistance to SEU is desired.Type: GrantFiled: December 5, 2007Date of Patent: December 16, 2008Assignee: Altera CorporationInventors: Lakhbeer S. Sidhu, Irfan Rahim, Jeffrey Watt, John Turner
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Patent number: 7459779Abstract: Output pads on an integrated circuit (IC) chip are arranged along a first longer side and are arranged along a second longer side with input pads. The output pads are connected to respective output patterns formed on top and bottom surfaces of a base film. All the output patterns may pass over the first longer side. Alternatively, the output patterns connected to the output pads at the second longer side may pass over a shorter side. These pattern structures establish an effective pad arrangement without increasing the size of a TAB package, yet allowing reduced the chip size.Type: GrantFiled: November 7, 2005Date of Patent: December 2, 2008Assignee: Samsung Electric Co., Ltd.Inventors: Ye-Chung Chung, Si-Hoon Lee
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Publication number: 20080290375Abstract: The present invention provides an integrated circuit suitable for various packaging modes. This integrated circuit includes: a core circuit, a plurality of pads, and a selection circuit. The selection circuit is coupled between the core circuit and the pads for determining the connection state between the core circuit and the pads based on a control signal. When the control signal provides a first value, the core circuit and the pads will be in a first connection state, and the integrated circuit will be applied with a single-die package. However, when the control signal provides a second value, the core circuit and the pads will be in the second connection state, and the integrated circuit will be applied with a multi-die package.Type: ApplicationFiled: May 27, 2008Publication date: November 27, 2008Applicant: REALTEK SEMICONDUCTOR CORP.Inventors: Hsien Chun Chang, Chia Lung Hung, Tsung Chi Lin, Tzuo Bo Lin
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Patent number: 7453105Abstract: An integrated circuit including an assembly of functional blocks and an interconnection network formed of at least N levels of conductive tracks separated by conductive via levels, the interconnection network including a power supply network comprising a first assembly of substantially parallel rails placed at the N-th track level, and a second assembly of substantially parallel rails placed at the (N?1)-th track level under the first rail assembly, the rails of the first assembly being non-parallel to those of the second assembly, the power supply network further including, for each functional block, a third assembly of power supply rails placed at the (N?2)-th track level above the elements of the considered block, and in which the rails of the second assembly form an acute angle smaller than 80° with the rails of each third rail assembly.Type: GrantFiled: June 30, 2006Date of Patent: November 18, 2008Assignee: STMicroelectronics S.A.Inventor: Jean-Pierre Schoellkopf