Having Specific Type Of Active Device (e.g., Cmos) Patents (Class 257/204)
  • Patent number: 10804302
    Abstract: The present disclosure provides a pixel structure for a CMOS image sensor and a manufacturing method therefor, the pixel structure comprising a photo diode and a source follow transistor, and an isolation strip is provided between the photo diode and the source follow transistor, and a contact hole is provided in a drain terminal of the source follow transistor, with the width of a part, corresponding to the contact hole portion, of a drain terminal active area of the source follow transistor being smaller than the width of the rest of the drain terminal active area, so that the width of a part, corresponding to the contact hole portion, of the isolation strip is greater than the width of a part, corresponding to the rest of the drain terminal active area, of the isolation strip.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: October 13, 2020
    Inventor: Zhi Tian
  • Patent number: 10783311
    Abstract: A DRC tool optimized for analyzing early-stage (“dirty”) IC layout designs by performing one or more of (a) automatically selectively focusing DRC processing to selected regions (i.e., layers and/or cells) of a dirty IC layout design that are most likely to provide useful error information to a user, (b) automatically selectively ordering and/or limiting rule checks performed during DRC processing to provide the user with a manageable amount of error data in a predetermined reasonable amount of time, and (c) automatically providing error data in a graphical manner using a contrasting dot to indicate the location of each rule violation, whereby relevant problem areas of the dirty IC layout design are easily identified for correction by a human user, and non-relevant areas (e.g., missing block regions) can be efficiently identified and ignored, thereby facilitating efficient modification of the IC layout design.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: September 22, 2020
    Assignee: Synopsys, Inc.
    Inventor: John R. Studders
  • Patent number: 10783832
    Abstract: A scan driver, includes a plurality of stage circuits, each of which includes a driving circuit unit providing an output signal and an inverter inverting the output signal of the driving circuit unit and generating a scan signal, in which the inverter includes a first transistor and a second transistor, which are complementarily operated, the first transistor is a P-type polysilicon transistor, and the second transistor is an N-type oxide semiconductor transistor. A display device may include the scan driver.
    Type: Grant
    Filed: December 17, 2017
    Date of Patent: September 22, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Kyoung Ju Shin, Cheol Gon Lee, Sang Uk Lim, Chang Yong Jeong
  • Patent number: 10777546
    Abstract: An electrostatic discharge (ESD) protection device having a source region coupled to a first electrical node, a first drain region coupled to a second electrical node different from the first electrical node, and an extended drain region between the source region and the first drain region. The extended drain region includes a number N of electrically floating doped regions and a number M of gate regions coupled to the second electrical node, where N and M are integers greater than 1 and N is equal to M. Each electrically floating doped region of the N number of floating doped regions alternates with each gate region of the M number of gate regions.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: September 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Lin Peng, Han-Jen Yang, Jam-Wem Lee, Li-Wei Chu
  • Patent number: 10756217
    Abstract: Systems, apparatuses and methods related to access devices formed with conductive contacts are described. An example apparatus may include an access device that includes a field-effect transistor (FET). A vertical pillar may be formed to include a channel of the FET, with a portion of the vertical pillar formed between at least two gates of the FET (i.e., a multi-gate Fin-FET). A conductive contact may be coupled to a body region of the vertical pillar.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: August 25, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Haitao Liu, Yunfei Gao, Kamal M. Karda, Deepak Chandra Pandey, Sanh D. Tang, Litao Yang
  • Patent number: 10748893
    Abstract: Electrostatic discharge (ESD) devices and methods of manufacture are provided. The method includes forming a plurality of fin structures and a mesa structure from semiconductor material. The method further includes forming an epitaxial material with doped regions on the mesa structure and forming gate material over at least the plurality of fin structures. The method further includes planarizing at least the gate material such that the gate material and the epitaxial material are of a same height. The method further includes forming contacts in electrical connection with respective ones of the doped regions of the epitaxial material.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: August 18, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Huiming Bu, Junjun Li, Theodorus E. Standaert, Tenko Yamashita
  • Patent number: 10700095
    Abstract: A semiconductor integrated circuit device including standard cells including fin transistors includes, at a cell row end, a cell-row-terminating cell that does not contribute to a logical function of a circuit block. The cell-row-terminating cell includes a plurality of fins extending in an X direction. Ends of the plurality of fins on the inner side of the circuit block are near a gate structure placed at a cell end and do not overlap with the gate structure in a plan view, and ends of the plurality of fins on an outer side of the circuit block overlap with any one of a gate structure in a plan view.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: June 30, 2020
    Assignee: SOCIONEXT INC.
    Inventors: Toshio Hino, Junji Iwahori
  • Patent number: 10685982
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a first standard cell; and a second standard cell; wherein a cell width of the first standard cell along a first direction is substantially the same as a cell width of the second standard cell along the first direction, and a cell height of the first standard cell along a second direction perpendicular to the first direction is substantially greater than a cell height of the second standard cell along the second direction.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsueh-Chih Chou, Chia Hao Tu, Sang Hoo Dhong, Lee-Chung Lu, Li-Chun Tien, Ting-Wei Chiang, Hui-Zhong Zhuang
  • Patent number: 10672885
    Abstract: A silicon-on-insulator (SOI) CMOS transistor structure includes a plurality of series-connected SOI CMOS transistors, including a plurality of parallel source/drain regions, a plurality of channel/body regions located between the plurality of source/drain regions, and a polysilicon gate structure located over the plurality of channel regions. The polysilicon gate structure includes a plurality of polysilicon gate fingers, wherein each polysilicon gate finger extends over a corresponding one of the channel/body regions. A silicide blocking structure is formed over portions of the polysilicon gate fingers, wherein channel/body contact regions, which extend at least partially under the silicide blocking structure, provide electrical connections to the parallel channel/body regions.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: June 2, 2020
    Assignee: Newport Fab, LLC
    Inventor: Roda Kanawati
  • Patent number: 10672826
    Abstract: An imaging system includes a focal plane array comprising a first row of photodetectors, a second row of photodetectors adjacent to the first row of photodetectors, and a segmented isolation grid including portions disposed between photodetectors in the first row of photodetectors and photodetectors in the second row of photodetectors.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: June 2, 2020
    Assignee: RAYTHEON COMPANY
    Inventors: Sean P. Kilcoyne, John L. Vampola, George Paloczi
  • Patent number: 10665450
    Abstract: Methods and apparatus for forming a semiconductor structure, including depositing a doping stack having a first surface atop a high-k dielectric layer, wherein the doping stack includes at least one first metal layer having a first surface, at least one second metal layer comprising a first aluminum dopant and a first surface, wherein the second metal layer is atop the first surface of the first metal layer, and at least one third metal layer atop the first surface of the second metal layer; depositing an anneal layer atop the first surface of the doping stack; annealing the structure to diffuse at least the first aluminum dopant into the high-k dielectric layer; removing the anneal layer; and depositing at least one work function layer atop the first surface of the doping stack.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: May 26, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Yixiong Yang, Paul F. Ma, Wei V. Tang, Wenyu Zhang, Shih Chung Chen, Chen Han Lin, Chi-Chou Lin, Yi Xu, Yu Lei, Naomi Yoshida, Lin Dong, Siddarth Krishnan
  • Patent number: 10658385
    Abstract: A first PMOS transistor is defined by a gate electrode extending along a first gate electrode track. A second PMOS transistor is defined by a gate electrode extending along a second gate electrode track. A first NMOS transistor is defined by a gate electrode extending along a third gate electrode track. A second NMOS transistor is defined by a gate electrode extending along a fourth gate electrode track. The gate electrodes of the first PMOS transistor and the first NMOS transistor are electrically connected to a first gate node. The gate electrodes of the second PMOS transistor and the second NMOS transistor are electrically connected to a second gate node. Each of the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, and the second NMOS transistor has a respective diffusion terminal electrically connected to a common output node.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 19, 2020
    Assignee: Tela Innovations, Inc.
    Inventors: Scott T. Becker, Jim Mali, Carole Lambert
  • Patent number: 10658361
    Abstract: Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: May 19, 2020
    Assignee: Intel Corporation
    Inventors: Curtis Tsai, Chia-Hong Jan, Jeng-Ya David Yeh, Joodong Park, Walid M. Hafez
  • Patent number: 10600807
    Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within the conductive levels, an insulative material over the stack and a select gate material over the insulative material. An opening extends through the select gate material, through the insulative material, and through the stack of alternating dielectric and conductive levels. A first region of the opening within the insulative material is wider along a cross-section than a second region of the opening within the select gate material, and is wider along the cross-section than a third region of the opening within the stack of alternating dielectric levels and conductive levels. Channel material is within the opening and adjacent the insulative material, the select gate material and the memory cells. Some embodiments include methods of forming vertically-stacked memory cells.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: March 24, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Jie Sun, Fatma Arzum Simsek-Ege
  • Patent number: 10600785
    Abstract: A CMOS device with a plurality of PMOS transistors and a plurality of NMOS transistors includes a first interconnect and a second interconnect on an interconnect level connecting a first subset and a second subset of PMOS drains together, respectively. The first and second subsets are different and the first and second interconnect are disconnected on the interconnect level. A third interconnect and a fourth interconnect on the interconnect level connect a first subset and a second subset of the NMOS drains together, respectively. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, fourth interconnects are coupled together through at least one other interconnect level. Additional interconnects on the interconnect level connect the first and third interconnects together, and the second and fourth interconnects together, to provide parallel current paths with a current path through the at least one other interconnect level.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: March 24, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Seid Hadi Rasouli, Michael Joseph Brunolli, Christine Sung-An Hau-Riege, Mickael Malabry, Sucheta Kumar Harish, Prathiba Balasubramanian, Kamesh Medisetti, Nikolay Bomshtein, Animesh Datta, Ohsang Kwon
  • Patent number: 10588506
    Abstract: The present invention relates to a device and to a method for the quantitative detection of disorders in the field of vision of an eye of a test subject, in particular in the case of eye diseases which are associated with macular edema, wherein a square grid is displayed on a display device whose grid lines which are perceived by the test subject as curved can be modified by the subject in such a way that the subject can view an orthogonal reticule again. Such lines perceived as curved can be modified by input signals which modify the boundary curves defined by the boundary functions in such a way that the originally displayed linear reticule is perceived again, wherein the geometric deviations caused by transformation of the regions of the square reticule perceived as curved from the originally present squares are determined quantitatively as the sum of the absolute values of the horizontal deviations and as the sum of the absolute values of the vertical deviations.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: March 17, 2020
    Inventors: Daniela Claessens, Ronald V. Krüger
  • Patent number: 10546811
    Abstract: Some embodiments include an assembly having bitlines extending along a first direction. Semiconductor pillars are over the bitlines and are arranged in an array. The array includes columns along the first direction and rows along a second direction which crosses the first direction. Each of the semiconductor pillars extends vertically. The semiconductor pillars are over the bitlines. The semiconductor pillars are spaced from one another along the first direction by first gaps, and are spaced from one another along the second direction by second gaps. Wordlines extend along the second direction, and are elevationally above the semiconductor pillars. The wordlines are directly over the first gaps and are not directly over the semiconductor pillars. Gate electrodes are beneath the wordlines and are coupled with the wordlines. Each of the gate electrodes is within one of the second gaps. Shield lines may be within the first gaps.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: January 28, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Mitsunari Sukekawa
  • Patent number: 10541330
    Abstract: A method of making a vertical transistor device includes forming a front gate and a back gate opposite a major surface of a substrate. The front gate and the back gate are symmetric and arranged on opposing sides of a channel between the front gate and the back gate. The channel extends from a drain to a source. The method includes disposing a mask to cover the front gate and removing the back gate. The method further includes replacing the back gate with a layer of insulator and another back gate stack. The another back gate stack only covers a junction between the channel and the source, and remaining portions of the back gate are the layer of insulator.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: January 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Xin Miao, Peng Xu, Chen Zhang
  • Patent number: 10541007
    Abstract: A device includes a memory array. The memory array includes a first sub-bank, a second sub-bank, a strap cell and a continuous data line. The strap cell is arranged between the first sub-bank and the second sub-bank. The continuous data line includes a first portion coupled to the first sub-bank and a second portion disposed across the second sub-bank. The first portion of the continuous data line and the second portion of the continuous data line are disposed at separate layers above the strap cell.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: January 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jonathan Tsung-Yung Chang, Cheng-Hung Lee, Chi-Ting Cheng, Hung-Jen Liao, Jhon-Jhy Liaw, Yen-Huei Chen
  • Patent number: 10535670
    Abstract: A method of manufacturing a non-volatile memory is described. A substrate including a first region and a second region located at periphery of the first region is provided. A plurality of stacked structures are formed on the first region of the substrate. A wall structure is formed on the second region of the substrate. A conductive layer is formed over the substrate. A bottom anti-reflective coating is formed over the conductive layer. The bottom anti-reflective coating and the conductive layer are etched back. The conductive layer is patterned.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Hsuan Liu, Chiang-Ming Chuang, Chih-Ming Lee, Kun-Tsang Chuang, Hung-Che Liao, Chia-Ming Pan, Hsin-Chi Chen
  • Patent number: 10529724
    Abstract: A vertical SRAM cell includes a first (1st) inverter having a 1st common gate structure operatively connecting channels of a 1st pull-up (PU) and a 1st pull-down (PD) transistor. A 1st metal contact electrically connects bottom source/drain (S/D) regions of the 1st PU and 1st PD transistors. A second (2nd) inverter has a 2nd common gate structure operatively connecting channels of a 2nd PU and a 2nd PD transistor. A 2nd metal contact electrically connects bottom S/D regions of the 2nd PU and 2nd PD transistors. A 1st cross-coupled contact electrically connects the 2nd common gate structure to the 1st metal contact. The 2nd common gate structure entirely surrounds a perimeter of the 1st cross-coupled contact. A 2nd cross-coupled contact electrically connects the 1st common gate structure to the 2nd metal contact. The 1st common gate structure entirely surrounds a perimeter of the 2nd cross-coupled contact.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: January 7, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Manfred Eller, Kwan-Yong Lim
  • Patent number: 10510548
    Abstract: Semiconductor structures are provided. The semiconductor structure includes a base including first, second, third, and fourth regions, used for first, second, third, and fourth transistors, respectively. A gate dielectric layer is on the first, second, third and fourth regions of the base. A first material layer is on the gate dielectric layer. A second material layer is on the first material layer above the fourth region. A third material layer is on the first material layer above the third region and on the second material layer above the fourth region. A fourth material layer is on the third material layer above the third and fourth regions and on the first material layer on the second region. The first material layer above the first region is used as a first work function layer for the first transistor.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: December 17, 2019
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Xin He
  • Patent number: 10431576
    Abstract: A memory cell array includes a first memory cell arranged in a first row in a first direction and a second memory cell arranged in a second row in the first direction. The first memory cell or the second memory cell includes a set of active regions, a set of gates and a first set of conductive structures. Each of the active regions of the set of active regions is separated from an adjacent active region in the first direction by a first pitch. The set of active regions extends in a second direction. The set of active regions includes a first active region adjacent to a first side of the first memory cell, and a second active region adjacent to a second side of the first memory cell. A length of the first active region is different from a length of the second active region.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: October 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Shih-Lien Linus Lu
  • Patent number: 10319709
    Abstract: The present invention provides an integrated circuit with a standard cell of an inverter standard cell. The integrated circuit includes: a first metal line and a second metal line stretching along a first direction; a first dummy gate and a second dummy gate stretching along a second direction; Plural fin structures stretching along the first direction; A gate structure disposed on the fin structures and stretching along the second direction; Two long contact plugs disposed at one side of the gate structure; two short contact plugs disposed at the other side of the gate structure; a gate contact plug disposed on the gate structure; Plural via plugs disposed on the long contact plugs, the short contact plugs and the gate contact plugs; A metal layer includes the first metal line, the second metal line, a third metal line and a fourth metal line.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: June 11, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chen-Hsien Hsu, Chien-Fu Chen, Cheng-Yang Tsai, Wei-Jen Wang, Chao-Wei Lin, Zhi-Hong Huang, Cheng-Tsung Ku, Chin-Sheng Yang
  • Patent number: 10283526
    Abstract: Standard cell circuits employing voltage rails electrically coupled to metal shunts for reducing or avoiding increases in voltage drop are disclosed. In one aspect, a standard cell circuit is provided that employs active devices that include corresponding gates disposed with a gate pitch. First and second voltage rails having a line width are disposed in a first metal layer. Employing the first and second voltage rails having substantially a same line width reduces the height of the standard cell circuit as compared to conventional standard cell circuits. Metal lines are disposed in a second metal layer with a metal pitch less than the gate pitch such that the number of metal lines exceeds the number of gates. Electrically coupling the first and second voltage rails to the metal shunts increases the conductive area of each voltage rail, which reduces a voltage drop across each voltage rail.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: May 7, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: John Jianhong Zhu, Jeffrey Junhao Xu, Mustafa Badaroglu
  • Patent number: 10269730
    Abstract: Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 ?m, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Puu Jeng, Clinton Chao, Szu-Wei Lu
  • Patent number: 10236886
    Abstract: A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mx layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second Mx layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second Mx layer interconnects are parallel. The MOS device further includes a first Mx+1 layer interconnect extending in a second direction orthogonal to the first direction. The first Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The MOS device further includes a second Mx+1 layer interconnect extending in the second direction. The second Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The second Mx+1 layer interconnect is parallel to the first Mx+1 layer interconnect.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: March 19, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Satyanarayana Sahu, Xiangdong Chen, Venugopal Boynapalli, Hyeokjin Lim, Mickael Malabry, Mukul Gupta
  • Patent number: 10224416
    Abstract: The present disclosure provides a method for manufacturing an LTPS TFT, including steps of: forming patterns of a p-Si layer and a protection layer on a base substrate, the protection layer covering the p-Si layer; performing a first ion injection operation so as to inject ions through the protection layer into the p-Si layer, thereby to form a heavily-drain-doped region; and performing an ashing operation and performing a second ion injection operation, to form a pattern of an LTPS active layer including a heavily-drain-doped region, a lightly-drain-doped region and an undoped region.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: March 5, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Kui Gong
  • Patent number: 10163922
    Abstract: In a MONOS memory, withstand voltage is increased between a control gate electrode over an ONO film having a charge accumulating part and a semiconductor substrate. When a silicon film is processed to form a control gate electrode, dry etching is performed for a relatively long time, thereby a recess is formed in a sidewall of the control gate electrode. Subsequently, the control gate electrode is subjected to dry oxidation treatment to form an insulating film on the sidewall of the control gate electrode including the recess, thereby an end of the bottom of the control gate electrode is separated from an end of the top of the ONO film.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: December 25, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Shinichiro Abe, Masaaki Shinohara
  • Patent number: 10158100
    Abstract: A method for manufacturing a flexible display panel includes: binding a flexible substrate with a supporting column matrix on a supporting plate, and fixing the flexible substrate with the supporting plate by a sealant in vacuum, wherein the sealant is disposed at an edge of the supporting column matrix, such that the supporting column matrix is surrounded in a sealed space formed by the sealant, the supporting plate and the flexible substrate; forming a flexible display panel on the flexible substrate; and cutting the supporting plate and the flexible display panel along the inner side of the sealant, such that the flexible display panel separating with the supporting plate. Thus, the flexible substrate can be separated from the supporting plate without damaging devices disposed on the flexible substrate.
    Type: Grant
    Filed: November 25, 2017
    Date of Patent: December 18, 2018
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Wei Yu
  • Patent number: 10109619
    Abstract: In an aspect of the disclosure, a MOS device for reducing routing congestion caused by using split n-well cells in a merged n-well circuit block is provided. The MOS device may include a first set of cells adjacent to each other in a first direction. The MOS device may include a second set of cells adjacent to each other in the first direction and adjacent to the first set of cells in a second direction. The second set of cells each may include a first n-well, a second n-well, and a third n-well separated from each other. The MOS device may include an interconnect extending in the first direction in the second set of cells. The interconnect may provide a voltage source to the first n-well of each of the second set of cells.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: October 23, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Harshat Pant, Mohammed Yousuff Shariff, Parissa Najdesamii, Ramaprasath Vilangudipitchai, Divjyot Bhan
  • Patent number: 10096705
    Abstract: An integrated high side gate driver structure for driving a power transistor. The structure includes a semiconductor substrate having a first polarity semiconductor material in which a first well diffusion including a second polarity semiconductor material is formed. An outer wall of the first well diffusion is abutted to the substrate. A second well diffusion, having first polarity semiconductor material, is arranged inside the first well diffusion such that an outer wall of the second well diffusion abuts an inner wall of the first well diffusion. The structure includes a gate driver having high side positive and negative supply voltage ports, and a driver input and output. The gate driver includes a transistor driver in the second well diffusion such that control and output terminals of the transistor driver are coupled to the driver input and output, respectively.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: October 9, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Allan Nogueras Nielsen, Mikkel Høyerby
  • Patent number: 10090412
    Abstract: A method of making a vertical transistor device includes forming a front gate and a back gate opposite a major surface of a substrate. The front gate and the back gate are symmetric and arranged on opposing sides of a channel between the front gate and the back gate. The channel extends from a drain to a source. The method includes disposing a mask to cover the front gate and removing the back gate. The method further includes replacing the back gate with a layer of insulator and another back gate stack. The another back gate stack only covers a junction between the channel and the source, and remaining portions of the back gate are the layer of insulator.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: October 2, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Xin Miao, Peng Xu, Chen Zhang
  • Patent number: 10083992
    Abstract: A display device includes a first substrate having an active area, a circuit area extending outwardly from the active area, and a cell seal area extending outwardly from the circuit area, a second substrate covering the first substrate, a sealing part between the first substrate and the second substrate, the sealing part covering at least a portion of the circuit area, a wiring part in the circuit area of the first substrate and electrically connected to elements in the active area of the first substrate, the wiring part including at least one level-difference compensation part, and a stepped part between the sealing part and at least a portion of the wiring part, the at least one level-difference compensation part of the wiring part being adjacent to the stepped part.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: September 25, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jaekyung Go, Eunjae Na, Minjun Jo, Hyunjun Choi
  • Patent number: 10074653
    Abstract: Asymmetric, semiconductor memory cells, arrays, devices and methods are described. Among these, an asymmetric, bi-stable semiconductor memory cell is described that includes: a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with the floating body region; a second region in electrical contact with the floating body region and spaced apart from the first region; and a gate positioned between the first and second regions, such that the first region is on a first side of the memory cell relative to the gate and the second region is on a second side of the memory cell relative to the gate; wherein performance characteristics of the first side are different from performance characteristics of the second side.
    Type: Grant
    Filed: November 19, 2016
    Date of Patent: September 11, 2018
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 10073728
    Abstract: Exemplary systems, methods and computer-accessible mediums can be provided that can, for example, determine a camouflaging location(s) of the logic gate(s) using a fault analysis procedure, and can camouflage the logic gate(s) at the location(s) based on the determination. The camouflaging procedure can be performed by replacing the logic gate(s) at the camouflaging location(s) with a further camouflaged gate, which can have a dummy contact(s) or a vias.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: September 11, 2018
    Assignee: New York University
    Inventors: Jeyavijayan Rajendran, Ozgur Sinanoglu, Ramesh Karri
  • Patent number: 10043887
    Abstract: A semiconductor device includes a metal gate stack. The metal gate stack includes a high-k gate dielectric and a metal gate electrode over the high-k gate dielectric. The metal gate electrode includes a first top surface and a second bottom surface substantially diametrically opposite the first top surface. The first top surface includes a first surface length and the second bottom surface includes a second surface length. The first surface length is larger than the second surface length. A method of forming a semiconductor device is provided.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: August 7, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Che-Cheng Chang, Yi-Jen Chen, Chang-Yin Chen, Yung Jung Chang
  • Patent number: 10032763
    Abstract: In an aspect of the disclosure, a MOS device for using bulk cross-coupled thin-oxide decoupling capacitor is provided. The MOS device may include a pMOS transistor and an nMOS transistor. The MOS device may include a first set of transistor body connections adjacent the pMOS transistor and the nMOS transistor. The first set of transistor body connections may couple a first voltage source to the pMOS transistor body. The first set of transistor body connections may further couple a second voltage source to the nMOS transistor body. The MOS device may include a second set of transistor body connections adjacent the pMOS transistor and the nMOS transistor. The second set of transistor body connections may couple the nMOS transistor gate to the pMOS transistor body. The second set of transistor body connections may further couple the pMOS transistor gate to the nMOS transistor body.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: July 24, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Albert Kumar, Hai Dang, Sreeker Dundigal, Vasisht Vadi
  • Patent number: 10020356
    Abstract: Provided is an organic light-emitting display device. An organic light-emitting display device (OLED) includes: a substrate including at least three pixel regions arranged in a horizontal direction, a first electrode in each pixel region on the substrate, a bank surrounding each pixel region, and a power line in the horizontal portion at a lower side of each pixel region on the substrate, the power line being configured to supply a driving voltage to each pixel region.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: July 10, 2018
    Assignee: LG Display Co., Ltd.
    Inventors: A-Ryoung Lee, Ki-Soub Yang, Da-Hye Shim
  • Patent number: 9972626
    Abstract: Provided is a dynamic random access memory. A plurality of isolation structures is disposed in a substrate to define a plurality of active regions arranged along a first direction. The substrate has a trench extended along the first direction and passing through the plurality of isolation structures and the plurality of active regions. A buried word line is disposed in the trench. A plurality of gate dielectric layers is disposed in the trench of the plurality of active regions to surround and cover the buried word line. A cap layer covers the buried word line. The height of the top surface of the second side of the buried word line is lower than the height of the top surface of the first side of the buried word line passing through the plurality of active regions and the plurality of isolation structures.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: May 15, 2018
    Assignee: Winbond Electronics Corp.
    Inventors: Kazuaki Takesako, Kazutaka Manabe, Noriaki Ikeda, Wei-Che Chang
  • Patent number: 9947724
    Abstract: A method of fabricating a CMOS logic device with SWCNTs includes forming a plurality of local metallic gate structures on a substrate by depositing a metal on the substrate; forming a plurality of contacts on the substrate; and depositing the SWCNTs on the substrate, and doping a certain area of the SWCNTs to form the CMOS logic device having at least one NMOS transistor and at least one PMOS transistor. Each of the NMOS and PMOS transistors has a gate formed by one of the local metallic gate structures, and a source and a drain formed by two of the contacts respectively. The gate of each PMOS transistor and the gate of each NMOS transistor are configured to alternatively receive at least one input voltage. At least one of the drain of the PMOS transistor and the drain of the NMOS transistor is configured to output an output voltage.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: April 17, 2018
    Assignees: NORTHWESTERN UNIVERSITY, REGENTS OF THE UNIVERSITY OF MINNESOTA
    Inventors: Mark C. Hersam, Michael L. Geier, Pradyumna L. Prabhumirashi, Weichao Xu, Hyungil Kim
  • Patent number: 9941263
    Abstract: Disclosed herein is a semiconductor integrated circuit device which includes a standard cell with a plurality of fins extending in a first direction and arranged in a second direction that is perpendicular to the first direction. An active fin of the fins forms part of an active transistor. A dummy fin of the fins is disposed between the active fin and an end of the standard cell.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: April 10, 2018
    Assignee: SOCIONEXT INC.
    Inventor: Hiroyuki Shimbo
  • Patent number: 9940993
    Abstract: A storage bitcell comprising a first inverter cross-coupled with a second inverter, both the first and second inverter being in a path between a first potential and a second potential; wherein a first isolator is connected in the path between the first inverter and the first potential. The storage bitcell has particular application as Static Random-Access Memory (SRAM) circuitry.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: April 10, 2018
    Assignee: ARM Limited
    Inventors: Parameshwarappa Anand Kumar Savanth, James Edward Myers, Pranay Prabhat, David Walter Flynn, Shidhartha Das, David Michael Bull
  • Patent number: 9941887
    Abstract: An integrated circuit includes a field programmable gate array including: (i) a plurality of memory cells (e.g., static memory cells) to store data, wherein each memory cell includes a first output, (ii) a multiplexer including inputs, an output and input selects, (iii) a plurality of poly-silicon conductors, each poly-silicon conductor is disposed in the substrate and connected to the first output of an associated memory cell, (iv) poly-silicon extensions, each poly-silicon extension is (a) connected to an associated poly-silicon conductor and (b) coupled to an associated input select of the multiplexer, wherein the poly-silicon extensions are disposed in the substrate and at least partially under a metal conductor, disposed above the substrate, in the field programmable gate array.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: April 10, 2018
    Assignee: Flex Logix Technologies, Inc.
    Inventor: Cheng C. Wang
  • Patent number: 9929140
    Abstract: An ESD cell includes an n+ buried layer (NBL) within a p-epi layer on a substrate. An outer deep trench isolation ring (outer DT ring) includes dielectric sidewalls having a deep n-type diffusion (DEEPN diffusion) ring (DEEPN ring) contacting the dielectric sidewall extending downward to the NBL. The DEEPN ring defines an enclosed p-epi region. A plurality of inner DT structures are within the enclosed p-epi region having dielectric sidewalls and DEEPN diffusions contacting the dielectric sidewalls extending downward from the topside surface to the NBL. The inner DT structures have a sufficiently small spacing with one another so that adjacent DEEPN diffusion regions overlap to form continuous wall of n-type material extending from a first side to a second side of the outer DT ring dividing the enclosed p-epi region into a first and second p-epi region. The first and second p-epi region are connected by the NBL.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: March 27, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Henry Litzmann Edwards, Akram A. Salman, Binghua Hu
  • Patent number: 9919518
    Abstract: A printing element substrate includes a plurality of printing elements, a first transistor forming an electrical pathway common to the plurality of printing elements, and a plurality of second transistors for driving the plurality of printing elements independently of each other. An electrical pathway is formed between a first power node and a second power node in the order of the first transistor, one of the plurality of printing elements, and one of the plurality of second transistors. The electrical pathway connecting each of the plurality of printing elements and the first transistor includes a plurality of electrical paths.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: March 20, 2018
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takaaki Yamaguchi, Yosuke Miura, Chiaki Muraoka, Yasushi Nakano
  • Patent number: 9917056
    Abstract: A layer of a mask material is deposited on a substrate. A beam of energy is scanned across the mask material in a rasterized linear pattern and in accordance with a scan pitch that is based on a pitch of conductive structure segments to be formed on the substrate. The beam of energy is defined to transform the mask material upon which the beam of energy is incident into a removable state. During scanning the beam of energy across the mask material, the beam of energy is turned on at locations where a conductive structure is to be formed on the substrate, and the beam of energy is turned off at locations where a conductive structure is not to be formed on the substrate.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: March 13, 2018
    Assignee: Tela Innovations, Inc.
    Inventors: Michael C. Smayling, Scott T. Becker
  • Patent number: 9899365
    Abstract: A layout of a semiconductor device includes a first active area, a second active area, plural gates, a first conductive layout and plural plugs. The first and the second active areas are disposed on a substrate and surrounded by a shallow trench isolation (STI). The plural gates are parallel with one another and cross the first and the second active areas. The first conductive layer covers the plural gates, and the plural gates are electrically connected to each other through the first conductive layer. The plural plugs are disposed on the first conductive layer to electrically connect the plural gates.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: February 20, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhibiao Zhou, Ding-Lung Chen
  • Patent number: 9899384
    Abstract: A semiconductor device and a method for fabricating the device. The method includes: forming a STI in a substrate having a nFET and a pFET region; depositing a high-k layer and a TiN layer; depositing a polycrystalline silicon layer; forming a block level litho layer; removing a portion of the polycrystalline silicon layer; removing the block level litho layer; forming a first protective layer; depositing a fill layer above the pFET region; removing the first protective layer; cutting the TiN layer and the high-k layer to expose a portion of the STI; depositing a second protective layer on the STI; removing the fill layer; removing the TiN layer above the pFET region; treating the high-k layer with a work function tuning process; removing the polycrystalline silicon layer and TiN layer; and depositing a metal layer on the high-k layer and the second protective layer.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: February 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 9859188
    Abstract: A die interconnect system having a plurality of connection pads, a heat generating element thermally isolated from the die, one or more leads extending from the die to the heat generating element, each lead having a metal core with a core diameter, a dielectric layer surrounding the metal core with a dielectric thickness, and an outer metal layer attached to ground, wherein one or more leads are exposed to ambient conditions and/or are convectively or contact cooled for at least a portion of their length to minimize heat transfer from the heat generating element to the die.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: January 2, 2018
    Assignee: Rosenberger Hochfrequenztechnik GmbH & Co. KG
    Inventors: Sean S. Cahill, Eric A. Sanjuan