With Bipolar Transistors Or With Fets Of Only One Channel Conductivity Type (e.g., Enhancement-depletion Fets) Patents (Class 257/205)
  • Patent number: 10535599
    Abstract: An integrated circuit (IC) device includes: a channel region that extends on the substrate to penetrate a plurality of word lines; a bit line contact pad that contacts an upper surface of the channel region; a bit line that contacts the bit line contact pad and extends on the bit line contact pad in a direction parallel to the main surface of the substrate; a common source line that partially fills a word line cut region and has a height lower than that of the channel region; and a common source via contact that contacts an upper surface of the common source line in the word line cut region.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: January 14, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Kwang-Soo Kim
  • Patent number: 10522556
    Abstract: An antifuse structure includes an active area and a gate electrode over the active area. The active area includes a first body portion and a first extending portion extending in a first direction. The gate electrode includes a second body portion and a second extending portion extending in a second direction perpendicular to the first direction. The first body portion includes a first surface facing a portion of the second body portion, and the second body portion includes a second surface facing a portion of the first extending portion. The first extending portion and the second extending portion are partially overlapped in a third direction perpendicular to both the first direction and the second direction, with a dielectric layer sandwiched between the first and second extending portions, forming an intersection area.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: December 31, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chin-Ling Huang, Chiang-Lin Shih, Zi-Yin Chen
  • Patent number: 10504899
    Abstract: A semiconductor device includes a first circuit and a second circuit. The first circuit includes a first gate, a first drain, and a first source. The second circuit includes a second gate, a second drain, and a second source. The first drain and the first source of the first circuit include a first doping material with a first concentration. A gate pitch and a gate critical dimension of the first gate of the first circuit are the same as a gate pitch and a gate critical dimension of the second gate of the second circuit. The second drain and the second source of the second circuit include a second doping material with a second concentration, wherein the first concentration is different from the second concentration.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: December 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 10163979
    Abstract: Memory devices and manufacturing methods thereof are presented. A memory device a substrate and a memory cell having at least one selector and a storage element. The selector includes a well of a first polarity type disposed in the substrate, a region of a second polarity type disposed over the well and in the substrate, and first and second regions of the first polarity type disposed adjacent to the region of the second polarity type. The storage element includes a programmable resistive layer disposed on the region of the second polarity type and an electrode disposed over the programmable resistive layer.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: December 25, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Xuan Anh Tran, Eng Huat Toh, Shyue Seng Tan, Yuan Sun, Elgin Kiok Boone Quek
  • Patent number: 9972649
    Abstract: A sensor comprises a substrate; an array of nanowire field effect transistors (NWFETs) formed in said substrate, each of the NWFETs having source, drain and gate terminals; a nanowire coupled between the source terminal and the drain terminal of each NWFET; and a layer of radiation sensitive material disposed over said NWFETs and said nanowires with each of the source, drain and gate terminals configured to be coupled to respective ones of first, second or third reference potentials, wherein each NWFET is configured such that the conductivity between the source and drain changes in response to radiation absorbed in the layer of radiation sensitive material such that the sensor generates an output signal in response to radiation absorbed by the radiation sensitive material.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: May 15, 2018
    Inventors: Virginia Spanoudaki, Daniel G. Anderson, Robert S. Langer
  • Patent number: 9712183
    Abstract: A current source device having a current source array includes a plurality of current source units, a plurality of least significant bits, and a plurality of most significant bits. The current source units are arranged along a plurality rows and columns of a current source array. Each of the least significant bits includes a first amount of current source units is placed at the geometric center of the current source array. Each of the most significant bits includes a second amount of current source units. The second amount is the first amount multiplied by a positive integer. The two adjacent bits in the most significant bits are centrally symmetrical to the geometric center.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: July 18, 2017
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: Jade Deng, Keith Ma
  • Patent number: 9646855
    Abstract: Semiconductor device including a metal carrier substrate. Above the carrier substrate a first semiconductor layer of Alx1Gay1Inz1N (x1+y1+z1=1, x1?0, y1?0, z1?0) is formed. A second semiconductor layer of Alx2Gay2Inz2N (x2+y2+z2=1, x2>x1, y2?0, z2?0) is arranged on the first semiconductor layer and a gate region is arranged on the second semiconductor layer. The semiconductor device furthermore includes a source region and a drain region, wherein one of these regions is electrically coupled to the metal carrier substrate and includes a conductive region extending through the first semiconductor layer.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: May 9, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Oliver Haeberlen, Walter Rieger, Christoph Kadow, Markus Zundel
  • Patent number: 9542999
    Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: January 10, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Shinji Tanaka, Makoto Yabuuchi, Yuta Yoshida
  • Patent number: 9478552
    Abstract: A static random access memory and the manufacturing method thereof are provided. By forming the specific gate structure(s) to be concave gate structure(s) and by adjusting the ratio of the effective channel width for these gate structures, the performance of the static random access memory is enhanced.
    Type: Grant
    Filed: January 19, 2015
    Date of Patent: October 25, 2016
    Assignee: Powerchip Technology Corporation
    Inventors: Yi-Chung Liang, Chen-Hao Huang, Li-Wei Liu, Hann-Ping Hwang
  • Patent number: 9356015
    Abstract: In a composite semiconductor device which is provided with a normally-on-type first transistor and a normally-off-type second transistor which are serially connected, the second transistor is selected so as to satisfy Formula (1): C oss > C ds ? V ds V br - C ds - C gs ( 1 ) In this regard: Coss: output capacitance of second transistor Cds: drain to source capacitance of first transistor Cgs: gate to source capacitance of first transistor Vds: power supply voltage Vbr: breakdown voltage of second transistor.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: May 31, 2016
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Yoshifumi Ohshima
  • Patent number: 9012270
    Abstract: Methods for forming a DSA pre-patterned semiconductor transistor layout and the resulting devices are disclosed. Embodiments may include forming a pre-patterned transistor layout by directed self-assembly (DSA), forming a metal layer over the DSA pre-patterned transistor layout, including: forming a plurality of horizontal metal lines; and forming a plurality of vertical metal segments discontinuous from and between adjacent horizontal metal lines; and forming one or more bridging dots each connecting one of the plurality of horizontal metal lines to one of the plurality of vertical metal segments, wherein locations of the bridging dots determine logic functions of resulting transistor cells.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 21, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ji Xu, Vito Dai
  • Patent number: 9000489
    Abstract: A multi-field effect transistor (FET) device includes a first FET device arranged on a substrate, the first FET device including a first active region and a second active region, a second FET device arranged on the substrate, the second FET device including a first active region and a second active region, and a first conductive interconnect electrically connecting the first active region of the first FET device to the first active region of the second FET device, the first conductive interconnect having a first cross sectional area proximate to the first active region of the first FET device that is greater than a second cross sectional area proximate to the first active region of the second FET device.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventor: Ning Lu
  • Patent number: 8946018
    Abstract: Some embodiments include methods of forming semiconductor constructions. A heavily-doped region is formed within a first semiconductor material, and a second semiconductor material is epitaxially grown over the first semiconductor material. The second semiconductor material is patterned to form circuit components, and the heavily-doped region is patterned to form spaced-apart buried lines electrically coupling pluralities of the circuit components to one another. At least some of the patterning of the heavily-doped region occurs simultaneously with at least some of the patterning of the second semiconductor material.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: February 3, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Jaydip Guha, Shyam Surthi
  • Patent number: 8937358
    Abstract: An integrated circuit includes a first and a second standard cell. The first standard cell includes a first gate electrode, and a first channel region underlying the first gate electrode. The first channel region has a first channel doping concentration. The second standard cell includes a second gate electrode, and a second channel region underlying the second gate electrode. The second channel region has a second channel doping concentration. A dummy gate includes a first half and a second half in the first and the second standard cells, respectively. The first half and the second half are at the edges of the first and the second standard cells, respectively, and are abutted to each other. A dummy channel is overlapped by the dummy gate. The dummy channel has a third channel doping concentration substantially equal to a sum of the first channel doping concentration and the second channel doping concentration.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: January 20, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Nan Yang, Chou-Kun Lin, Jerry Chang-Jui Kao, Yi-Chuin Tsai, Chien-Ju Chao, Chung-Hsing Wang
  • Patent number: 8912576
    Abstract: A bipolar junction transistor built with a mesh structure of cells provided on a semiconductor body is disclosed. The mesh structure has at least one emitter cell with a first type of implant. At least one emitter cell has at least one side coupled to at least one cell with a first type of implant to serve as collector of the bipolar. The spaces between the emitter and collector cells are the intrinsic base of a bipolar device. At least one emitter cell has at least one vortex coupled to at least one cell with a second type of implant to serve as the extrinsic base of the bipolar. The emitter, collector, or base cells can be arbitrary polygons as long as the overall geometry construction can be very compact and expandable. The implant regions between cells can be separated with a space. A silicide block layer can cover the space and overlap into at least a portion of both implant regions.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 16, 2014
    Inventor: Shine C. Chung
  • Patent number: 8901669
    Abstract: A method of manufacturing an integrated circuit comprising bipolar transistors including first and second type bipolar transistors, the method comprising providing a substrate comprising first isolation regions each separated from a second isolation region by an active region comprising a collector impurity of one of the bipolar transistors; forming a base layer stack over the substrate; forming a first emitter cap layer of a first effective thickness over the base layer stack in the areas of the first type bipolar transistor; forming a second emitter cap layer of a second effective thickness different from the first effective thickness over the base layer stack in the areas of the second type bipolar transistor; and forming an emitter over the emitter cap layer of each of the bipolar transistors. An IC in accordance with this method.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: December 2, 2014
    Assignee: NXP, B.V.
    Inventors: Hans Mertens, Johannes Theodorus Marinus Donkers, Evelyne Gridelet, Tony Vanhoucke, Petrus Hubertus Cornelis Magnee
  • Patent number: 8895980
    Abstract: The present invention discloses a tunneling current amplification transistor, which relates to an area of field effect transistor logic devices in CMOS ultra large scale semiconductor integrated circuits (ULSI). The tunneling current amplification transistor includes a semiconductor substrate, a gate dielectric layer, an emitter, a drain, a floating tunneling base and a control gate, wherein the drain, the floating tunneling base and the control gate forms a conventional TFET structure, and a doping type of the emitter is opposite to that of the floating tunneling base. A position of the emitter is at the other side of the floating tunneling base with respect to the drain. A type of the semiconductor between the emitter and the floating tunneling base is the same as that of the floating tunneling base.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: November 25, 2014
    Assignee: Peking University
    Inventors: Ru Huang, Zhan Zhan, Qianqian Huang, Yangyuan Wang
  • Patent number: 8896122
    Abstract: Schottky barrier semiconductor devices are provided including a wide bandgap semiconductor layer and a gate on the wide bandgap semiconductor layer. The gate includes a metal layer on the wide bandgap semiconductor layer including a nickel oxide (NiO) layer. Related methods of fabricating devices are also provided herein.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: November 25, 2014
    Assignee: Cree, Inc.
    Inventors: Van Mieczkowski, Helmut Hagleitner, Kevin Haberern
  • Patent number: 8872222
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a first doped region, a second doped region, a doped strip and a top doped region. The first doped region has a first type conductivity. The second doped region is formed in the first doped region and has a second type conductivity opposite to the first type conductivity. The doped strip is formed in the first doped region and has the second type conductivity. The top doped region is formed in the doped strip and has the first type conductivity. The top doped region has a first sidewall and a second sidewall opposite to the first sidewall. The doped strip is extended beyond the first sidewall or the second sidewall.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: October 28, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Ching-Lin Chan, Chen-Yuan Lin, Cheng-Chi Lin, Shih-Chin Lien
  • Patent number: 8872236
    Abstract: Bipolar transistor structures, methods of designing and fabricating bipolar transistors, methods of designing circuits having bipolar transistors. The method of designing the bipolar transistor includes: selecting an initial design of a bipolar transistor; scaling the initial design of the bipolar transistor to generate a scaled design of the bipolar transistor; determining if stress compensation of the scaled design of the bipolar transistor is required based on dimensions of an emitter of the bipolar transistor after the scaling; and if stress compensation of the scaled design of the bipolar transistor is required then adjusting a layout of a trench isolation layout level of the scaled design relative to a layout of an emitter layout level of the scaled design to generate a stress compensated scaled design of the bipolar transistor.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Alvin Jose Joseph, Ramana Murty Malladi, James Albert Slinkman
  • Patent number: 8866194
    Abstract: A semiconductor device (npn bipolar transistor) includes an n-type collector layer, a base layer constituted by a p+ diffusion layer, a SiGe layer and a p-type silicon film, an n-type emitter layer and a charge transport prevention film formed between the n-type collector layer and the n-type emitter layer and having an effect as a potential barrier with respect to either electrons or holes.
    Type: Grant
    Filed: September 24, 2007
    Date of Patent: October 21, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Shinya Naito, Hideaki Fujiwara, Toru Dan
  • Patent number: 8860037
    Abstract: A thin-film transistor device includes a gate electrode formed above a substrate, a gate insulating film formed on the gate electrode, a crystalline silicon thin film that is formed above the gate insulating film and has a channel region, an amorphous silicon thin film formed on the crystalline silicon thin film, and a source electrode and a drain electrode that are formed above the channel region, and the crystalline silicon thin film has a half-width of a Raman band corresponding to a phonon mode specific to the crystalline silicon thin film of 5.0 or more and less than 6.0 cm?1, and an average crystal grain size of about 50 nm or more and 300 nm or less.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: October 14, 2014
    Assignee: Panasonic Corporation
    Inventors: Takahiro Kawashima, Tomohiko Oda, Hikaru Nishitani
  • Patent number: 8853043
    Abstract: A heterojunction bipolar transistor (HBT), an integrated circuit (IC) chip including at least one HBT and a method of forming the IC. The HBT includes an extrinsic base with one or more buried interstitial barrier layer. The extrinsic base may be heavily doped with boron and each buried interstitial barrier layer is doped with a dopant containing carbon, e.g., carbon or SiGe:C. The surface of the extrinsic base may be silicided.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Wade J. Hodge, Alvin J. Joseph, Rajendran Krishnasamy, Qizhi Liu, Bradley A. Orner
  • Patent number: 8809911
    Abstract: Plural gate trenches are formed in the surface of an n-type drift region. A gate electrode is formed across a gate oxide film on the inner walls of the gate trenches. P-type base regions are selectively formed so as to neighbor each other in the gate trench longitudinal direction between neighboring gate trenches. An n-type emitter region is formed in contact with the gate trench in a surface layer of the p-type base regions. Also, a p-type contact region with a concentration higher than that of the p-type base region is formed in the surface layer of the p-type base region so as to be in contact with the gate trench side of the n-type emitter region. An edge portion on the gate trench side of the n-type emitter region terminates inside the p-type contact region.
    Type: Grant
    Filed: October 19, 2011
    Date of Patent: August 19, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Koh Yoshikawa
  • Patent number: 8791507
    Abstract: A layout of a semiconductor device is capable of reliably reducing a variation in gate length due to the optical proximity effect, and enables flexible layout design to be implemented. Gate patterns (G1, G2, G3) of a cell (C1) are arranged at the same pitch, and terminal ends (e1, e2, e3) of the gate patterns are located at the same position in the Y direction, and have the same width in the X direction. A gate pattern (G4) of a cell (C2) has protruding portions (4b) protruding toward the cell (C1) in the Y direction, and the protruding portions (4b) form opposing terminal ends (eo1, eo2, eo3). The opposing terminal ends (eo1, eo2, eo3) are arranged at the same pitch as the gate patterns (G1, G2, G3), are located at the same position in the Y direction, and have the same width in the X direction.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: July 29, 2014
    Assignee: Panasonic Corporation
    Inventors: Kazuyuki Nakanishi, Masaki Tamaru
  • Patent number: 8788984
    Abstract: An integrated circuit includes a gate array layer having a two-dimensional array of logic gates, each logic gate including multiple transistors. At least one upper template-based metal layer is coupled to the gate array layer and is configured to define at least one of a power distribution network, a clock network and a global signal network. A configuration of traces of the upper template-based metal layer is at least mainly predetermined prior to design of the integrated circuit.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: July 22, 2014
    Assignee: Baysand Inc.
    Inventors: Jonathan C Park, Salah M Werfelli, WeiZhi Kang, Wan Tat Hooi, Kok Siong Tee, Jeremy Jia Jian Lee
  • Patent number: 8685799
    Abstract: An RRAM at an STI region is disclosed with a vertical BJT selector. Embodiments include defining an STI region in a substrate, implanting dopants in the substrate to form a well of a first polarity around and below an STI region bottom portion, a band of a second polarity over the well on opposite sides of the STI region, and an active area of the first polarity over each band of second polarity at the surface of the substrate, forming a hardmask on the active areas, removing an STI region top portion to form a cavity, forming an RRAM liner on cavity side and bottom surfaces, forming a top electrode in the cavity, removing a portion of the hardmask to form spacers on opposite sides of the cavity, and implanting a dopant of the second polarity in a portion of each active area remote from the cavity.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: April 1, 2014
    Assignee: GlobalFoundries Singapore Pte. Ltd.
    Inventors: Shyue Seng Tan, Eng Huat Toh, Elgin Quek
  • Patent number: 8653565
    Abstract: Various aspects of the technology includes a quad semiconductor power and/or switching FET comprising a pair of control/sync FET devices. Current may be distributed in parallel along source and drain fingers. Gate fingers and pads may be arranged in a serpentine configuration for applying gate signals to both ends of gate fingers. A single continuous ohmic metal finger includes both source and drain regions and functions as a source-drain node. A set of electrodes for distributing the current may be arrayed along the width of the source and/or drain fingers and oriented to cross the fingers along the length of the source and drain fingers. Current may be conducted from the electrodes to the source and drain fingers through vias disposed along the surface of the fingers. Heat developed in the source, drain, and gate fingers may be conducted through the vias to the electrodes and out of the device.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: February 18, 2014
    Assignee: Sarda Technologies, Inc.
    Inventor: James L. Vorhaus
  • Publication number: 20130215683
    Abstract: A three-dimensional NAND-based NOR nonvolatile memory cell has two three-dimensional SONOS-type charge-retaining transistors arranged in a series string such that one of the charge-retaining transistors functions as a select gate transistor to prevent leakage current through the charge-retaining transistors when the charge-retaining transistors is not selected for determining a data state of the three-dimensional NAND-based NOR nonvolatile memory cell. The first charge retaining transistor's drain is connected to a bit line parallel to the charge retaining transistors and the second charge retaining transistor's source is connected to a source line and is parallel to the bit line.
    Type: Application
    Filed: August 15, 2012
    Publication date: August 22, 2013
    Applicant: APLUS FLASH TECHNOLOGY, INC.
    Inventors: Peter Wung Lee, Hsing-Ya Tsao
  • Patent number: 8487375
    Abstract: A semiconductor device includes a compound semiconductor layer provided over a substrate, a plurality of source electrodes and a plurality of drain electrodes provided over the compound semiconductor layer, a plurality of first vias each of which is configured to pass through the compound semiconductor layer and be coupled to a corresponding one of the plurality of source electrodes, a plurality of second vias each of which is configured to pass through the compound semiconductor layer and be coupled to a corresponding one of the plurality of drain electrodes, a common source wiring line configured to be coupled to the plurality of first vias and be buried in the substrate, and a common drain wiring line configured to be coupled to the plurality of second vias and be buried in the substrate.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: July 16, 2013
    Assignee: Fujitsu Limited
    Inventor: Naoya Okamoto
  • Patent number: 8471295
    Abstract: A flash memory cell string and a method of fabricating the same are provided. The flash memory cell string includes a plurality of cell devices and switching devices connected to ends of the cell devices. Each of the cell devices includes a semiconductor substrate, a tunneling insulating layer, a charge storage node, a control insulating layer, and a control electrode which are sequentially laminated on the semiconductor substrate. In each cell device, a source/drain region is not formed. The switching device does not include a source or drain region in a side connected to the cell devices. The switching device includes a source or drain region in the other side that is not connected to the cell devices. The source or drain region does or does not overlap the control electrode. Accordingly, it is possible to improve a miniaturization property and performance of NAND flash memory cell devices.
    Type: Grant
    Filed: December 4, 2007
    Date of Patent: June 25, 2013
    Assignee: SNU R&DB Foundation
    Inventor: Jong-Ho Lee
  • Patent number: 8390032
    Abstract: A field effect transistor is provided having a reduced drain capacitance per unit gate width. A gate electrode 21 (G) having a plurality of sides is formed in first-conductivity first semiconductor region 14. Drain region 18D (D) is formed inside the gate electrode, and source regions 18S (S) are formed in respective regions outside the plurality of sides in widths that do not reduce the corresponding channel widths of the drain region. The gate electrode is formed along all the plurality of sides of the drain region in order to form a transistor.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: March 5, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Yohichi Okumura, Josef Muenz
  • Patent number: 8304814
    Abstract: A bipolar power semiconductor device is provided with an emitter electrode on an emitter side and a collector electrode on a collector side. The device has a trench gate electrode and a structure with a plurality of layers of different conductivity types in the following order: at least one n doped source region, a p doped base layer, which surrounds the at least one source region, an n doped enhancement layer, a p doped additional well layer, an additional n doped enhancement layer, an additional p doped well layer, an n doped drift layer and a p doped collector layer. The trench gate electrode has a gate bottom, which is located closer to the collector side than the additional enhancement layer bottom.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: November 6, 2012
    Assignee: ABB Research Ltd
    Inventor: Friedhelm Bauer
  • Patent number: 8305109
    Abstract: An object is to obtain a desired threshold voltage of a thin film transistor using an oxide semiconductor. Another object is to suppress a change of the threshold voltage over time. Specifically, an object is to apply the thin film transistor to a logic circuit formed using a transistor having a desired threshold voltage. In order to achieve the above object, thin film transistors including oxide semiconductor layers with different thicknesses may be formed over the same substrate, and the thin film transistors whose threshold voltages are controlled by the thicknesses of the oxide semiconductor layers may be used to form a logic circuit. In addition, by using an oxide semiconductor film in contact with an oxide insulating film formed after dehydration or dehydrogenation treatment, a change in threshold voltage over time is suppressed and the reliability of a logic circuit can be improved.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: November 6, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kenichi Okazaki, Yoshiaki Oikawa, Hotaka Maruyama, Hiromichi Godo, Shunpei Yamazaki
  • Patent number: 8283730
    Abstract: A negative differential resistance (NDR) device is designed and a possible compact device implementation is presented. The NDR device includes a voltage blocker and a current blocker and exhibits high peak-to-valley current ratio (PVCR) as well as high switching speed. The corresponding process and design are completely compatible with contemporary Si CMOS technology and area efficient. A single-NDR element SRAM cell prototype with a compact size and high speed is also proposed as its application suitable for embedded memory.
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: October 9, 2012
    Inventor: Shu-Lu Chen
  • Patent number: 8274095
    Abstract: A semiconductor device having the present high withstand voltage power device IGBT has at a back surface a p collector layer with boron injected in an amount of approximately 3×1013/cm2 with an energy of approximately 50 KeV to a depth of approximately 0.5 ?m, and an n+ buffer layer with phosphorus injected in an amount of approximately 3×1012/cm2 with an energy of 120 KeV to a depth of approximately 20 ?m. To control lifetime, a semiconductor substrate is exposed to protons at the back surface. Optimally, it is exposed to protons at a dose of approximately 1×1011/cm2 to a depth of approximately 32 ?m as measured from the back surface. Thus snapback phenomenon can be eliminated and an improved low saturation voltage (Vce (sat))-offset voltage (Eoff) tradeoff can be achieved.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: September 25, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yoshiaki Hisamoto
  • Patent number: 8242541
    Abstract: A technique which reduces the influence of external noise such as crosstalk noise in a semiconductor device to prevent a circuit from malfunctioning. A true signal wire and a bar signal wire which are susceptible to noise and part of an input signal line to a level shifter circuit, and shield wires for shielding these signal wires are laid on an I/O cell. Such I/O cells are placed side by side to complete a true signal wire connection and a bar signal wire connection. These wires are arranged in a way to pass over a plurality of I/O cells and are parallel to each other or multilayered.
    Type: Grant
    Filed: January 9, 2007
    Date of Patent: August 14, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Takayuki Sasaki, Yasuto Igarashi, Naozumi Morino
  • Patent number: 8227836
    Abstract: A technology which allows a reduction in the thermal resistance of a semiconductor device and the miniaturization thereof is provided. The semiconductor device has a plurality of unit transistors Q, transistor formation regions 3a, 3b, and 3e each having a first number (e.g., seven) of the unit transistors Q, and transistor formation regions 3c and 3d each having a second number (e.g., four) of the unit transistors Q. The transistor formation regions 3c and 3d are located between the transistor formation regions 3a, 3b, 3e, and 3f, and the first number is larger than the second number.
    Type: Grant
    Filed: October 15, 2009
    Date of Patent: July 24, 2012
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Satoshi Sasaki, Yasunari Umemoto, Yasuo Osone, Tsutomu Kobori, Chushiro Kusano, Isao Ohbu, Kenji Sasaki
  • Patent number: 8217425
    Abstract: The cell size is reduced and device reliability is improved for a semiconductor device including plural transistors making up a multi-channel output circuit. In a multi-channel circuit configuration, a group of transistors having a common function of plural channels are surrounded by a common trench for insulated isolation from another group of transistors having another function. The collectors of mutually adjacent transistors on the high side are commonly connected to a VH power supply, whereas the emitters of mutually adjacent transistors on the low side are commonly connected to a GND power supply.
    Type: Grant
    Filed: July 20, 2009
    Date of Patent: July 10, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Tomoyuki Miyoshi, Shinichiro Wada, Yohei Yanagida
  • Patent number: 8193563
    Abstract: A structure and method of fabricating the structure. The structure including: a dielectric isolation in a semiconductor substrate, the dielectric isolation extending in a direction perpendicular to a top surface of the substrate into the substrate a first distance, the dielectric isolation surrounding a first region and a second region of the substrate, a top surface of the dielectric isolation coplanar with the top surface of the substrate; a dielectric region in the second region of the substrate; the dielectric region extending in the perpendicular direction into the substrate a second distance, the first distance greater than the second distance; and a first device in the first region and a second device in the second region, the first device different from the second device, the dielectric region isolating a first element of the second device from a second element of the second device.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: June 5, 2012
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey Peter Gambino, Steven Howard Voldman, Michael Joseph Zierak
  • Patent number: 8169039
    Abstract: A disclosed semiconductor device includes an MOS transistor having an N-type low-concentration drain region, a source region, an ohmic drain region, a P-type channel region, an ohmic channel region, a gate isolation film, and a gate electrode. The N-type low-concentration drain region includes two low-concentration drain layers in which the N-type impurity concentration of the upper layer is higher than that of the lower layer; the P-type channel region includes two channel layers in which the P-type impurity concentration of the upper layer is lower than that of the lower layer; and the gate electrode is formed on the P-type channel region and the N-type low-concentration drain region and disposed to be separated from the ohmic drain region when viewed from the top.
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: May 1, 2012
    Assignee: Ricoh Company, Ltd.
    Inventor: Takaaki Negoro
  • Patent number: 8093131
    Abstract: In a semiconductor device of the present invention, a first base region 16 is extended to a part under a gate electrode 7 while having a vertical concentration profile of an impurity that increases from the surface of a semiconductor layer 3 and becomes maximum under an emitter region 5, and the length in the lateral direction from a point where the impurity concentration becomes maximum located under an end of the gate electrode 7 to the boundary with a second base region 15 is not smaller than the length in the vertical direction from the point where the impurity concentration becomes maximum to the boundary with the second base region 15.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: January 10, 2012
    Assignee: Panasonic Corporation
    Inventors: Teruhisa Ikuta, Yoshinobu Sato
  • Patent number: 8053346
    Abstract: A gate in a semiconductor device is formed to have a dummy gate pattern that protects a gate. Metal lines are formed to supply power for a semiconductor device and transfer a signal. A semiconductor device includes a quad coupled receiver type input/output buffer. The semiconductor device is formed with a gate line that extends over an active region, and a gate pad located outside of the active region. The gate line and the gate pad are adjoined such that the gate line and a side of the gate pad form a line. Dummy gates may also be applied. The semiconductor device includes a first metal line patterns supplying power to a block having a plurality of cells, a second metal line pattern transferring a signal to the cells, and dummy metal line patterns divided into in a longitudinal direction.
    Type: Grant
    Filed: April 25, 2008
    Date of Patent: November 8, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Nam Gyu Ryu, Ho Ryong Kim, Won John Choi, Jae Hwan Kim, Seoung Hyun Kang, Young Hee Yoon
  • Patent number: 8035149
    Abstract: A nonvolatile memory device includes an active region defined by a device isolation layer in a semiconductor substrate, a word line passing over the active region and a charge storage region defined by a crossing of the active region and the word line and disposed between the active region and the word line. The charge storage region is disposed at an oblique angle with respect to the word line.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: October 11, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Woon-Kyung Lee
  • Patent number: 8026572
    Abstract: A semiconductor device having plural active and passive elements on one semiconductor substrate is manufactured in the following cost effective manner even when the active and passive elements include double sided electrode elements. When the semiconductor substrate is divided into plural field areas, an insulation separation trench that penetrates the semiconductor substrate surrounds each of the field areas, and each of the either of the plural active elements or the plural passive elements. Further, each of the plural elements has a pair of power electrodes for power supply respectively disposed on each of both sides of the semiconductor substrate to serve as the double sided electrode elements.
    Type: Grant
    Filed: December 4, 2007
    Date of Patent: September 27, 2011
    Assignee: DENSO CORPORATION
    Inventors: Yoshihiko Ozeki, Kenji Kouno, Tetsuo Fujii
  • Patent number: 8017974
    Abstract: A semiconductor device having the present high withstand voltage power device IGBT has at a back surface a p collector layer with boron injected in an amount of approximately 3×1013/cm2 with an energy of approximately 50 KeV to a depth of approximately 0.5 ?m, and an n+ buffer layer with phosphorus injected in an amount of approximately 3×1012/cm2 with an energy of 120 KeV to a depth of approximately 20 ?m. To control lifetime, a semiconductor substrate is exposed to protons at the back surface. Optimally, it is exposed to protons at a dose of approximately 1×1011/cm2 to a depth of approximately 32 ?m as measured from the back surface. Thus snapback phenomenon can be eliminated and an improved low saturation voltage (Vce (sat))-offset voltage (Eoff) tradeoff can be achieved.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: September 13, 2011
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yoshiaki Hisamoto
  • Patent number: 7998807
    Abstract: A method for increasing the speed of a bipolar transistor, includes the following steps: providing a bipolar transistor having emitter, base, and collector regions; providing electrodes for coupling electrical signals with the emitter, base, and collector regions; and adapting the base region to enhance stimulated emission to the detriment of spontaneous emission, so as to reduce carrier recombination lifetime in the base region.
    Type: Grant
    Filed: June 4, 2004
    Date of Patent: August 16, 2011
    Assignee: The Board of Trustees of The University of Illinois
    Inventors: Milton Feng, Nick Holonyak, Jr.
  • Patent number: 7985987
    Abstract: A HEMT-type field-effect semiconductor device has a main semiconductor region comprising two layers of dissimilar materials such that a two-dimensional electron gas layer is generated along the heterojunction between the two layers. A source and a drain electrode are placed in spaced positions on a major surface of the main semiconductor region. Between these electrodes, a gate electrode is received in a recess in the major surface of the main semiconductor region via a p-type metal oxide semiconductor film whereby a depletion zone is normally created in the electron gas layer, with a minimum of turn-on resistance and gate leak current.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: July 26, 2011
    Assignee: Sanken Electric Co., Ltd.
    Inventor: Nobuo Kaneko
  • Patent number: 7956384
    Abstract: A semiconductor power device supported on a semiconductor substrate that includes a plurality of transistor cells, each cell has a source and a drain region disposed on opposite sides of a gate region in the semiconductor substrate. A gate electrode is formed as an electrode layer on top of the gate region for controlling an electric current transmitted between the source and the drain regions. The gate electrode layer disposed on top of the semiconductor substrate is patterned into a wave-like shaped stripes for substantially increasing an electric current conduction area between the source and drain regions across the gate.
    Type: Grant
    Filed: June 23, 2006
    Date of Patent: June 7, 2011
    Assignee: Alpha & Omega Semiconductor Ltd.
    Inventor: Shekar Mallikararjunaswamy
  • Patent number: RE43945
    Abstract: A semiconductor device is the semiconductor device which includes more than one field effect transistor having a gate electrode to which an electrical interconnect wire is connected and a gate insulation film with a thickness of 6.0 nm or less and which comprises a first transistor group made up of a plurality of field effect transistors that are the same in thickness of gate insulation film, a second transistor group made up of a plurality of field effect transistors that are the same in thickness of gate insulation film with the thickness of gate insulation film being less than the thickness of the gate insulation film of the first transistor group, and a semiconductor substrate on which the first and second transistor groups are mounted together in a mixed manner, wherein an antenna ratio which is a ratio of the area of a wire to the gate area of a gate electrode is such that the maximum value of the second transistor group is greater than the maximum value of the first transistor group.
    Type: Grant
    Filed: July 25, 2008
    Date of Patent: January 29, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Noriaki Matsunaga, Hitomi Yamaguchi