Particular Layout Of Complementary Fets With Regard To Each Other Patents (Class 257/206)
  • Patent number: 10700063
    Abstract: Devices and methods for layout-dependent voltage handling improvement in switch stacks. In some embodiments, a switching device can include a first terminal and a second terminal, a radio-frequency signal path implemented between the first terminal and the second terminal, and a plurality of switching elements connected in series to form a stack between the second terminal and ground. The stack can have an orientation relative to the radio-frequency signal path, and the switching elements can have a non-uniform distribution of a first parameter based in part on the orientation of the stack.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: June 30, 2020
    Assignee: Skyworks Solutions, Inc.
    Inventors: Guillaume Alexandre Blin, Ambarish Roy, Seungwoo Jung
  • Patent number: 10651175
    Abstract: Disclosed herein is a semiconductor device including two standard cells which are arranged adjacent to each other in an X direction. One of the two standard cells includes a plurality of first fins which extend in the X direction, and which are arranged along a boundary between the two standard cells in a Y direction. The other standard cell includes a plurality of second fins which extend in the X direction, and which are arranged along the boundary between the two standard cells in the Y direction. The plurality of second fins includes a dummy fin.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: May 12, 2020
    Assignee: SOCIONEXT INC.
    Inventor: Hiroyuki Shimbo
  • Patent number: 10575382
    Abstract: The present disclosure generally relates to optical modules, and in particular, to an optical module comprising a printed circuit board for reducing crosstalk between differential signal lines. In one implementation, the printed circuit board comprises a top layer, a first intermediate signal transmission layer, a second intermediate signal transmission layer, a bottom layer and multiple ground layers between signal transmission layers. Each signal transmission layer comprises one or more differential signal line pairs. The top layer and the bottom layer each comprises an edge connector, and the top layer further comprises a laser driver chip. The signal transmission layers are connected to the edge connectors and laser driver chips via a combination of blind and through connection holes such that the interference between the differential signal line pairs of various signal transmission layers are reduced.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: February 25, 2020
    Assignees: Hisense Broadband Multimedia Technologies Co., Ltd., Hisense Broadband Multimedia Technologies, Ltd.
    Inventor: Long Zheng
  • Patent number: 10528696
    Abstract: A customizable routing system allows designers to create custom connection layouts that can be stored, turned into templates, reused, and further customized. The system describes designer-input custom connection layouts in terms of “structural directives” that specify its patterns and properties instead of using precise dimensions. Structural directives may describe particular connection patterns between structural components (e.g., backbone or fishbone), the placement, width, direction or layer of specific structural components, and properties of structural components relative to other components. These structural directives are implemented generally during routing, such as through design constraints, which allows the router to locally optimize the design (e.g., for cost or wire length) while considering the structural intentions of the designer.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: January 7, 2020
    Assignee: Synopsys, Inc.
    Inventors: Hsiang-Wen Jimmy Lin, Friedrich Gunter Kurt Sendig, Mathieu Eric Drut, Philippe Aubert McComber
  • Patent number: 10497692
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a SRAM structure with alternate gate pitches and methods of manufacture. The structure includes an array of memory cells having a plurality of gate structures with varying gate pitches, the varying gate pitches comprising a first dimension sized for placement of a bitline contact and a second dimension sized for placement of source/drain contacts, the first dimension being larger than the second dimension.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: December 3, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Randy W. Mann
  • Patent number: 10490543
    Abstract: In certain aspects, a semiconductor die includes a first cell and a second cell. The first cell includes first transistors, and a first interconnect structure interconnecting the first transistors to form a first circuit. The second cell includes second transistors, and a second interconnect structure interconnecting the second transistors to form a second circuit. The first circuit and the second circuit are configured to perform a same function, and a length of the first cell in a first lateral direction is greater than a length of the second cell in the first lateral direction.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: November 26, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Xiangdong Chen, Sorin Adrian Dobre, Hyeokjin Lim, Venugopal Boynapalli
  • Patent number: 10380308
    Abstract: Power distribution networks (PDNs) using hybrid grid and pillar arrangements are disclosed. In particular, a process for designing an integrated circuit (IC) considers various design criteria when placing and routing the PDN for the IC. Exemplary design criteria include switching frequencies, current densities, and decoupling capacitance and their impact on temperature. In areas of high localized temperature, a power grid structure is used. In other areas, shared metal track pillars may be used. By mixing power grids with pillars, the IC may reduce local hotspots by allowing the grid to help dissipate heat and assist with decoupling capacitance while at the same time providing pillars in areas of high current density to reduce resistive losses.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: August 13, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Anthony Correale, Jr., Philip Michael Iles
  • Patent number: 10366196
    Abstract: Disclosed systems and methods pertain to finfet based integrated circuits designed with logic cell architectures which support multiple diffusion regions for n-type and p-type diffusions. Different diffusion regions of each logic cell can have different widths or fin counts. Abutting two logic cells is enabled based on like fin counts for corresponding p-diffusion regions and n-diffusion regions of the two logic cells. Diffusion fills are used at common edges between the two logic cells for extending lengths of diffusion, based on the like fin counts. The logic cell architectures support via redundancy and the ability to selectively control threshold voltages of different logic cells with implant tailoring. Half-row height cells can be interleaved with standard full-row height cells.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: July 30, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Anthony Correale, Jr., Benjamin Bowers, Tracey Della Rova, William Goodall, III
  • Patent number: 10325775
    Abstract: A semiconductor memory device includes a semiconductor layer including a memory cell region; a memory cell array including a plurality of first gate electrode layers stacked over the semiconductor layer, and disposed in the memory cell region; and a capacitor circuit disposed over the semiconductor layer outside the memory cell region. The capacitor circuit includes a plurality of gate structural bodies each including second gate electrode layers stacked over the semiconductor layer, and arranged along a first direction; a plurality of electrodes disposed between the gate structural bodies; and dielectric layers interposed between the gate structural bodies and the electrodes.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: June 18, 2019
    Assignee: SK hynix Inc.
    Inventors: Sang-Hyun Sung, Jeong-Hwan Kim, Jin-Ho Kim
  • Patent number: 10257910
    Abstract: The present disclosure generally relates to optical modules, and in particular, to an optical module comprising a printed circuit board for reducing crosstalk between differential signal lines. In one implementation, the printed circuit board comprises a top layer, a first intermediate signal transmission layer, a second intermediate signal transmission layer, a bottom layer and multiple ground layers between signal transmission layers. Each signal transmission layer comprises one or more differential signal line pairs. The top layer and the bottom layer each comprises an edge connector, and the top layer further comprises a laser driver chip. The signal transmission layers are connected to the edge connectors and laser driver chips via a combination of blind and through connection holes such that the interference between the differential signal line pairs of various signal transmission layers are reduced.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: April 9, 2019
    Assignees: Hisense Broadband Multimedia Technologies Co., Ltd., Hisense Broadband Multimedia Technologies, Ltd.
    Inventor: Long Zheng
  • Patent number: 10163787
    Abstract: The semiconductor structure includes a first conductive path including first and second segments. The first segment is in a first conductive layer. The second segment is in a second conductive layer. The first and second segments are electrically connected. The semiconductor structure includes a second conductive path including third and fourth segments. The third segment is in the first conductive layer. The fourth segment is in the second conductive layer. The third and fourth segments are electrically connected. The semiconductor structure includes a third conductive path between the first conductive path and the second conductive path, the third conductive path includes fifth and sixth segments. The fifth segment is in the second conductive layer. The sixth segment is in the first conductive layer. The fifth and sixth segments are electrically connected. An area of the first conductive layer between the first and third segments is free of the sixth segment.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hui Yu Lee, Feng Wei Kuo, Jui-Feng Kuan, Yi-Kan Cheng
  • Patent number: 10148517
    Abstract: An information handling system is provided. The information handling system includes a network orchestration service running on a computer processor. The network orchestration service provides a Border Gateway Protocol (BGP) listener module and a topology builder module. The BGP listener module is configured to receive information from a plurality of spine devices configured as an autonomous system and the topology builder module is configured to use the information received by the BGP listener module to create a topology of a data center that includes the plurality of spine devices. Additionally, the network orchestration service is in communication with a memory that is used to store information received by the BGP listener module and the topology of the data center. Applications of the information handling system for better operating the data center are also provided.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: December 4, 2018
    Assignee: Dell Products L.P.
    Inventors: Balaji Venkat Venkataswami, Bhargav Bhikkaji, Narayana Swamy Perumal
  • Patent number: 10134951
    Abstract: A method of manufacturing a light emitting device includes preparing a wafer having a sapphire substrate with semiconductor structures, forming a plurality of straight-line cleavage starting portions within the substrate by scanning a laser beam, and cleaving the wafer along the cleavage starting portions to obtain a plurality of light emitting devices each having a hexagonal shape. The forming step includes forming first cleavage starting portions with each first cleavage starting portion separated by a first interval from a common vertex point of three adjacent light emitting devices, forming second cleavage starting portions with each first cleavage starting portion separated by a second interval, which is shorter than the first interval, away from the common vertex point, and forming third cleavage starting portions with each first cleavage starting portion separated by a third interval, which is shorter than the first interval, away from the common vertex point.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: November 20, 2018
    Assignee: NICHIA CORPORATION
    Inventor: Kazuto Okamoto
  • Patent number: 10114919
    Abstract: The present disclosure provides a placing and routing method for implementing back bias in fully depleted silicon-on-insulator. In accordance with some illustrative embodiments herein, the placing and routing method comprises placing a first plurality of a standard tap well cell along a first direction, the standard tap well cell being formed by: routing a p-BIAS wire VPW and an n-BIAS wire VNW in a first a first metallization layer, and routing a power rail and a ground rail in a second metallization layer, the VPW and the VNW extending across each of the power and ground rail, wherein the VPWs of the first plurality of standard tap well cells are continuously connected and the VNWs of the first plurality of standard tap well cells are continuously connected.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: October 30, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Herbert Johannes Preuthen, Stefan Block, Ulrich Hensel, Christian Haufe, Fulvio Pugliese
  • Patent number: 10096520
    Abstract: A method of fabricating a semiconductor device having a first region, a second region, and a third region between the first and second regions includes forming first and second preliminary active patterns protruding from a substrate in the first and second regions, respectively, forming mask patterns exposing the third region on the substrate, performing a first etching process using the mask patterns an etch mask to form first and second active patterns, respectively, and forming gate structures on the substrate.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: October 9, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sanghoon Baek, Jae-Ho Park, Seolun Yang, Taejoong Song, Sang-Kyu Oh
  • Patent number: 10090316
    Abstract: In 3D stacked multilayer semiconductor memories including NAND and NOR flash memories, a lightly boron-doped layer is formed on top of a heavily boron-doped layer to form a select transistor, wherein the former serves as a channel of the select transistor and the latter serves as an isolation region which isolates the select transistor from a memory transistor.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: October 2, 2018
    Assignee: ASM IP Holding B.V.
    Inventor: Fumio Ootsuka
  • Patent number: 9985014
    Abstract: Minimum track standard cell circuits for reduced area are provided. In one aspect, a minimum track standard cell circuit employs a first high aspect ratio voltage rail disposed over a first one-half track and configured to provide a first voltage (e.g., VDD) to the minimum track standard cell circuit. A second high aspect ratio voltage rail is disposed over a second one-half track substantially parallel to the first high aspect ratio voltage rail. The second high aspect ratio voltage rail is configured to provide a second voltage less than the first voltage (e.g., VSS) to the minimum track standard cell circuit. The minimum track standard cell circuit employs multiple tracks disposed between the first and second one-half tracks. The number of tracks can be limited based on particular factors. Minimizing tracks reduces area compared to conventional standard cell circuits.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: May 29, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Jeffrey Junhao Xu, Mustafa Badaroglu, Da Yang
  • Patent number: 9964987
    Abstract: A current mirror circuit includes a first current mirror leg and a second current mirror leg. The first current mirror leg is configured with N stages of first transistors coupled in series and with their respective gates tied together. The second current mirror leg is configured with N stages of second transistors coupled in series and with their respective gates tied together. The first transistors and the second transistors are implemented within a transistor array, the first transistors and the second transistors are coupled between a first reference terminal and a second reference terminal, the first transistors and the second transistors at 1st to Kth stages adjacent to the first reference terminal are implemented at corner regions of the transistor array, N and K are positive integers and K<N. The first transistors have the same channel length, and the second transistors have the same channel length.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: May 8, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Ho Chang, Jaw-Juinn Horng, Yung-Chow Peng
  • Patent number: 9865603
    Abstract: A semiconductor structure includes a semiconductor substrate, at least one first elongated region of n-type or p-type, and at least one other second elongated region of the other of n-type or p-type, the first and second elongated regions crossing such that the first elongated region and the second elongated region intersect at a common area, and a shared gate structure over each common area.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: January 9, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Min-hwa Chi
  • Patent number: 9847260
    Abstract: A method for co-integrating finFETs of two semiconductor material types, e.g., Si and SiGe, on a bulk substrate is described. Fins for finFETs may be formed in an epitaxial layer of a first semiconductor type, and covered with an insulator. A portion of the fins may be removed to form voids in the insulator, and the voids may be filled by epitaxially growing a semiconductor material of a second type in the voids. The co-integrated finFETs may be formed at a same device level.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: December 19, 2017
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Nicolas Loubet, Prasanna Khare, Qing Liu
  • Patent number: 9837398
    Abstract: Integrated circuit layouts are disclosed that include metal layers with metal tracks having separate metal sections along the metal tracks. The separate metal sections along a single track may be electrically isolated from each other. The separate metal sections may then be electrically connected to different voltage tracks in metal layers above and/or below the metal layer with the separate metal sections. One or more of the metal layers in the integrated circuit layouts may also include metal tracks at different voltages (e.g., power and ground) that are adjacent to each other within a power grid layout. The metal tracks may be separated by electrically insulating material. The metal tracks and the electrically insulating material between the tracks may create capacitance in the power grid layout.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: December 5, 2017
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Omid Rowhani, Jason P. Cain, Ioan Cordos, Michael Davinson Sherriff, Hoang Q. Dao
  • Patent number: 9831236
    Abstract: An electro-static discharge (ESD) protection transistor device includes a plurality of transistor gates that extend parallel to one another in a first direction and a plurality of source/drain diffusion areas that extend parallel to one another in a second direction perpendicular to the first direction. Each source/drain diffusion area comprises a plurality of source/drain areas disposed between respective ones of the plurality of transistor gates. The ESD protection transistor device further includes a source contact positioned over each source area of the plurality of source areas and a drain contact positioned over each drain area of the plurality of drain areas. With respect to each source/drain diffusion area of the plurality of source/drain diffusion areas, the source contacts are offset from the drain contacts with respect to the first direction.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: November 28, 2017
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Chien-Hsin Lee, Xiangxiang Lu, Mahadeva Iyer Natarajan
  • Patent number: 9831230
    Abstract: A layout of a standard cell is stored on a non-transitory computer-readable medium and includes a first conductive pattern, a second conductive pattern, a plurality of active area patterns and a first central conductive pattern. The plurality of active area patterns is isolated from each other and arranged in a first row and a second row between the first and second conductive patterns. The first row is adjacent the first conductive pattern and includes a first active area pattern and a second active area pattern among the plurality of active area patterns. The second row is adjacent the second conductive pattern and includes a third active area pattern and a fourth active area pattern among the plurality of active area patterns. The first central conductive pattern is arranged between the first and second active area patterns. The first central conductive pattern overlaps the first conductive pattern.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: November 28, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Li-Chun Tien, Ya-Chi Chou, Hui-Zhong Zhuang, Chun-Fu Chen, Ting-Wei Chiang, Hsiang Jen Tseng
  • Patent number: 9831272
    Abstract: A standard cell IC includes pMOS transistors in a pMOS region of a MOS device. The pMOS region extends between a first cell edge and a second cell edge opposite the first cell edge. The standard cell IC further includes nMOS transistors in an nMOS region of the MOS device. The nMOS region extends between the first cell edge and the second cell edge. The standard cell IC further includes at least one single diffusion break located in an interior region between the first cell edge and the second cell edge that extends across the pMOS region and the nMOS region to separate the pMOS region into pMOS subregions and the nMOS region into nMOS subregions. The standard cell IC includes a first double diffusion break portion at the first cell edge. The standard cell IC further includes a second double diffusion break portion at the second cell edge.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: November 28, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Xiangdong Chen, Venugopal Boynapalli, Satyanarayana Sahu, Hyeokjin Lim, Mukul Gupta
  • Patent number: 9799774
    Abstract: A switch circuit that can control an electrical connection state without additionally providing a control circuit is provided. The switch circuit includes a transistor, a first switch which control an electrical connection state between a gate of the transistor and a wiring, a second switch, a first diode including an anode and a cathode, a third switch, and a second diode including an anode and a cathode. An electrical connection state between the anode of the first diode and the gate of the transistor is controlled by the second switch, and the cathode of the first diode is electrically connected to a source of the transistor. An electrical connection state between the anode of the second diode and the gate of the transistor is controlled by the third switch, and the cathode of the second diode is electrically connected to a drain of the transistor.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: October 24, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Patent number: 9780045
    Abstract: An integrated circuit includes a substrate with several functional blocks formed thereon. At least two identical functional blocks are respectively disposed at two or more different locations on the integrated circuit. Electrically inactive dummy modules in the neighborhoods and/or inside of the functional blocks are provided, wherein at least two different electrically inactive dummy modules are includes in the respective neighborhoods and/or inside of the at least two identical functional blocks.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: October 3, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero, Guilhem Bouton
  • Patent number: 9748247
    Abstract: A semiconductor device aims to prevent a leak current from flowing between a well and a corner of an active region formed on an upper surface of another well in an SRAM. In a memory cell of the SRAM, a load MOSFET is formed. An end of an active region extending in y-direction is arranged to gradually go away from a p-well as it goes from a gate electrode G2 side to a gate electrode G4 side in such a manner that a distance in x-direction between the end of the active region and the p-well is larger than a shortest distance in the x-direction between the p-well and the active region.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: August 29, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Tohru Kawai, Masahiro Shimizu
  • Patent number: 9741725
    Abstract: A semiconductor device can be reduced in size. The semiconductor device has a first conductivity type p type well layer extending in the X direction of the main surface of a semiconductor substrate; a reference potential wire coupled with the p type well layer, and extending in the X direction; first and second active regions arranged on the opposite sides of the reference potential wire in the Y direction; and a gate electrode layer extending in the Y direction in such a manner as to cross with the first and second active regions. Then, the gate electrode layer has a first gate electrode of a second conductivity type at the crossing part with the first active region, a second gate electrode of the second conductivity type at the crossing part with the second active region, and a non-doped electrode between the first gate electrode and the second gate electrode.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: August 22, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Nobuo Tsuboi
  • Patent number: 9728549
    Abstract: A semiconductor device may include a cell gate conductive pattern in a cell array area that extends to a step area, a cell vertical structure in the cell array area that extends through the cell gate conductive pattern, a cell gate contact structure on the cell gate conductive pattern in the step area, a cell gate contact region in the cell gate conductive pattern and aligned with the cell gate contact structure, a first peripheral contact structure spaced apart from the cell gate conductive pattern, a second peripheral contact structure spaced apart from the first peripheral contact structure, a first peripheral contact region under the first peripheral contact structure, and a second peripheral contact region under the second peripheral contact structure. The cell gate contact region may include a first element and a remainder of the cell gate conductive pattern may not substantially include the first element.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: August 8, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jang-Gn Yun, Sunghoi Hur, Jaesun Yun, Joon-Sung Lim
  • Patent number: 9716106
    Abstract: An integrated circuit (IC) may include at least one cell including a plurality of conductive lines that extend in a first direction and are in parallel to each other in a second direction that is perpendicular to the first direction, first contacts respectively disposed at two sides of at least one conductive line from among the plurality of conductive lines, and a second contact disposed on the at least one conductive line and the first contacts and forming a single node by being electrically connected to the at least one conductive line and the first contacts.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: July 25, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-hoon Baek, Sang-kyu Oh, Jung-Ho Do, Sun-young Park, Seung-young Lee, Hyo-sig Won
  • Patent number: 9704845
    Abstract: A linear-shaped core structure of a first material is formed on an underlying material. A layer of a second material is conformally deposited over the linear-shaped core structure and exposed portions of the underlying material. The layer of the second material is etched so as to leave a filament of the second material on each sidewall of the linear-shaped core structure, and so as to remove the second material from the underlying material. The linear-shaped core structure of the first material is removed so as to leave each filament of the second material on the underlying material. Each filament of the second material provides a mask for etching the underlying material. Each filament of the second material can be selectively etched further to adjust its size, and to correspondingly adjust a size of a feature to be formed in the underlying material.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: July 11, 2017
    Assignee: Tela Innovations, Inc.
    Inventors: Michael C. Smayling, Scott T. Becker
  • Patent number: 9690896
    Abstract: A method for manufacturing a semiconductor device is provided. The method includes disposing pre-conductive lines and post-conductive lines for forming first and second cells. The first and second cells are adjacent to each other in a first direction. A first conductive line of the first cell extends in a second direction perpendicular to the first direction and is adjacent to a boundary between the first and second cells. A second conductive line and a third conductive line of the second cell extend in the first direction and are adjacent to the boundary. The second and third conductive lines are respectively disposed on two non-adjacent tracks, among a plurality of tracks that extend in the first direction. The first conductive line intersects one of the two non-adjacent tracks and one track disposed between the two non-adjacent tracks.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: June 27, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Woo Seo, Jaeha Lee
  • Patent number: 9659919
    Abstract: In some embodiments, an integrated circuit includes a central array region having a first layout feature density. A background region surrounds the central array region and has a second layout feature density, which is different from the first density. A peripheral array region surrounds the central array region and separates the central array region from the background region. The peripheral array region has a third layout feature density between the first and second layout feature densities.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: May 23, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yung-Chow Peng, Jaw-Juinn Horng, Szu-Lin Liu, Po-Zeng Kang
  • Patent number: 9601600
    Abstract: A process for fabricating a fin-type field effect transistor (FinFET) structure is described. A semiconductor substrate is patterned to form a fin. A spacer is formed on the sidewall of the fin. A portion of the fin is removed, such that the spacer and the surface of the remaining fin together define a cavity. A piece of a semiconductor compound is formed from the cavity, wherein the upper portion of the piece of the semiconductor compound laterally extends over the spacer.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: March 21, 2017
    Assignee: United Microelectronics Corp.
    Inventors: Yu-Hsiang Hung, Ssu-I Fu, Chung-Fu Chang, Yen-Liang Wu, Cho-Han Fan, Chien-Ting Lin
  • Patent number: 9583493
    Abstract: An embodiment includes an integrated circuit comprising a standard cell, the standard cell comprising: first and second active regions having different conductivity types and extending in a first direction; first, second, and third conductive lines extending over the first and second active regions in a second direction substantially perpendicular to the first direction, and disposed parallel to each other; and a cutting layer extending in the first direction between the first and second active regions and separating the first conductive line into a first upper conductive line and a first lower conductive line, the second conductive line into a second upper conductive line and a second lower conductive line, and the third conductive line into a third upper conductive line and a third lower conductive line; wherein: the first upper conductive line and the third lower conductive line are electrically connected together; and the second upper conductive line and the second lower conductive line are electrically c
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: February 28, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ha-young Kim, Sung-we Cho, Tae-joong Song, Sang-hoon Baek
  • Patent number: 9570591
    Abstract: A method for fabricating a semiconductor device comprises forming active regions on a semiconductor substrate, forming a gate stack over the active regions and regions adjacent to the active regions, depositing a layer of conductive material over the active regions and the substrate, patterning a first mask over the conductive material, etching to remove exposed portions of the conductive material and form conductive contacts, patterning a second mask over portions of the gate stacks and conductive contacts, and etching to remove exposed portions of the gate stack.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: February 14, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus Standaert, Junli Wang
  • Patent number: 9570432
    Abstract: A semiconductor device has a first and second transistors formed on an active region defined by an insulating region. The active region is divided into a first and second portions arranged in a first direction, and into a third and fourth portions interposed between the first portion and the second portion, and provided adjacent to each other in a second direction orthogonal to the first direction. The first transistor is provided in the first and third portions, and the second transistor is provided in the second and fourth portions.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: February 14, 2017
    Assignee: Longitude Semiconductor S.a.r.l.
    Inventor: Mamoru Nishizaki
  • Patent number: 9478259
    Abstract: The area consumed by switching transistors for a 3D NAND memory array can be reduced with 3D voltage switching transistors with reduced aggregate area in comparison with 2D voltage switching transistors such as transistors in the substrate. The integrated circuit comprises a 3D NAND array of memory transistors; a plurality of bit lines, with different ones of the plurality of bit lines electrically coupled to different parts of the 3D NAND array; and a plurality of transistor pairs with a stack of semiconductor layers. Different layers in the stack of semiconductor layers include different transistor pairs of the plurality of transistor pairs. Each of the plurality of transistor pairs includes first and second transistors with first, second, and third source/drain terminals. The first transistor includes the first and the third source/drain terminals, and the second transistor includes the second and the third source/drain terminals.
    Type: Grant
    Filed: May 5, 2015
    Date of Patent: October 25, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Teng-Hao Yeh, Chih-Wei Hu, Lee-Yin Lin
  • Patent number: 9478550
    Abstract: An array includes vertically-oriented transistors. The array includes rows of access lines and columns of data/sense lines. Individual of the rows include an access line interconnecting transistors in that row. Individual of the columns include a data/sense line interconnecting transistors in that column. The array includes a plurality of conductive lines which individually extend longitudinally parallel and laterally between immediately adjacent of the data/sense lines. Additional embodiments are disclosed.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: October 25, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Shyam Surthi, Wolfgang Mueller, Sanh D. Tang
  • Patent number: 9471376
    Abstract: Techniques are generally described relating to methods, apparatuses and articles of manufactures for scheduling and/or organizing execution of tasks on a computing platform. In various embodiments, the method may include identifying successively one or more critical time intervals, and scheduling and/or organizing task execution for each of the one or more identified critical time intervals. In various embodiments, one or more tasks to be executed may be scheduled to execute based in part on their execution completion deadlines. In various embodiments, organizing one or more tasks to execute may include selecting a virtual operating mode of the platform using multiple operating speeds lying on a convexity energy-speed envelope of the platform. Intra-task delay caused by switching operating mode may be considered. Other embodiments may also be described and/or claimed.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: October 18, 2016
    Assignee: Empire Technology Development LLC
    Inventor: Miodrag Potkonjak
  • Patent number: 9460259
    Abstract: Methods of generating an integrated circuit layout include forming a standard cell by providing a first active area adjacent to a first cell boundary line. The first active area is spaced apart from the first cell boundary line by a first distance. A second active area is provided adjacent to a second cell boundary line. The second cell boundary line opposes the first cell boundary line. The second active area is spaced apart from the second cell boundary line by a second distance. Fins are formed on the first and second active areas. The fins extend in a first direction and parallel to one another in a second direction substantially perpendicular to the first direction. The first cell boundary line is parallel to the fins. The first distance and the second distance remain constant when a number of the fins on the first and second active areas is changed.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: October 4, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-hoon Baek, Jae-woo Seo, Gi-young Yang, Dal-hee Lee, Sung-wee Cho
  • Patent number: 9449970
    Abstract: A semiconductor device includes first and second gate structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, a third gate structure extending in the first direction and provided between the first and second gate structures, a first contact connected to the first gate structure and having a first width in the second direction, a second contact connected to the second gate structure and having a second width in the second direction, and a third contact connected to the third gate structure and having a third width in the second direction. The first, second, and third contacts may be aligned with each other in the second direction to constitute one row. The first and second widths may be greater than the third width.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: September 20, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Ho Do, Sanghoon Baek, Sunyoung Park, Moo-Gyu Bae, Taejoong Song
  • Patent number: 9425159
    Abstract: A wiring board includes a first insulation layer, first conductive patterns formed on the first insulation layer and including first mounting pads positioned to mount a semiconductor element, a wiring structure positioned in the first insulation layer and including a second insulation layer, second conductive patterns formed on the second insulation layer, and second mounting pads connected to the second conductive patterns, and third mounting pads formed on the first insulation layer above the second mounting pads and connected to the second mounting pads such that the third mounting pads are positioned to mount the semiconductor element and are set off from the second mounting pads toward the semiconductor element.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: August 23, 2016
    Assignee: IBIDEN CO., LTD.
    Inventors: Makoto Terui, Masatoshi Kunieda, Yoshinori Shizuno, Asuka Il
  • Patent number: 9419014
    Abstract: An integrated circuit includes a plurality of N wells disposed on a P substrate. A plurality of tap columns is located across the plurality of N wells and a plurality of standard cells is located between the tap columns. A plurality of tap cells is disposed consecutively in the plurality of tap columns. Each tap cell further includes a first tap active and a second tap active. The first tap active of a first tap cell extends to the first tap active of a second tap cell which further extends to a well boundary of either the first tap cell or the second tap cell. The first tap active of the first tap cell and the first tap active of the second tap cell are adjacent to each other in the tap column.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: August 16, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Girishankar Gurumurthy
  • Patent number: 9412742
    Abstract: A layout design usable for manufacturing a memory cell includes a first and second active area layout pattern associated with forming a first and second active area, an isolation region outside the first and second active area, a first polysilicon layout pattern associated with forming a first polysilicon structure, a second polysilicon layout pattern associated with forming a second polysilicon structure, a first interconnection layout pattern associated with forming a first interconnection structure, and a second interconnection layout pattern associated with forming a second interconnection structure. The first active area does not overlap the second active area. The first polysilicon layout pattern overlaps the first active area layout pattern. The second polysilicon layout pattern overlaps the first active area layout pattern and the second active area layout pattern. The first interconnection layout pattern overlaps the second active area layout pattern.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: August 9, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hidehiro Fujiwara, Kao-Cheng Lin, Ming-Yi Lee, Yen-Huei Chen, Hung-Jen Liao
  • Patent number: 9405873
    Abstract: By considering a Deep Nwell diffusing into a Pwell region, accuracy of a substrate parasitic-resistance extraction is improved. A well region of a semiconductor integrated circuit where a Pwell and a Deep Nwell are formed in a substrate is divided into two or more meshes each including two or more resistor segments and a substrate noise is analyzed based thereon. In this regard, parallel components of resistors coupling the Pwell with the substrate are deleted in accordance with a state of the Deep Nwell diffusing into the Pwell region, so that an arithmetic processing unit executes a process for expressing a rise in the resistance value. By deleting the parallel components of the resistors coupling the Pwell with the substrate, the rise in the resistance value caused by the Deep Nwell can be reflected in the substrate parasitic-resistance extraction. Therefore, the accuracy of the substrate parasitic-resistance extraction can be improved.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: August 2, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiki Kanamoto, Hisato Inaba
  • Patent number: 9406356
    Abstract: A latch circuit may include first to fourth storage nodes; first to fourth transistor pairs, each including a PMOS transistor and an NMOS transistor connected in series through a corresponding one of the first to fourth storage nodes, wherein each of the first to fourth storage nodes is connected to a gate of an NMOS transistor of a transistor pair in a previous stage and a gate of a PMOS transistor of a transistor pair in a next stage; a first connection unit suitable for connecting a data bus with a Kth storage node of the first to fourth storage nodes when read and write operations are performed, wherein K is an integer from 1 to 4; and second connection units suitable for connecting the data bus with one or more of the first to fourth storage nodes, except for the Kth storage node, when the write operation is performed.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: August 2, 2016
    Assignee: SK Hynix Inc.
    Inventors: Chang-Hyun Kim, Hyun-Gyu Lee
  • Patent number: 9397083
    Abstract: There is provided a technique capable of reducing a layout area of a standard cell configuring a digital circuit even under a circumstance that a new layout rule introduced in accordance with microfabrication of a MISFET is provided. For example, a protruding wiring PL1A protrudes from a power supply wiring L1A at each corner of both ends of a standard cell CL toward an inside of the standard cell CL (in a Y direction), and a bent portion BD1A which is bent from the protruding wiring PL1A in an X direction is formed. And, this bent portion BD1A and a p-type semiconductor region PDR are connected to each other via a plug PLG.
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: July 19, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hiroharu Shimizu
  • Patent number: 9391157
    Abstract: A semiconductor device including an oxide semiconductor that is miniaturized and has favorable electrical characteristics is provided. The semiconductor device includes an oxide semiconductor film and a blocking film; a source electrode and a drain electrode electrically connected to the oxide semiconductor film; a gate insulating film in contact with the oxide semiconductor film, the source electrode, and the drain electrode; and a gate electrode in contact with the gate insulating film. The blocking film contains the same material as the oxide semiconductor film, is on the same surface as the oxide semiconductor film, and has a higher conductivity than the oxide semiconductor film.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: July 12, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasutaka Suzuki, Yuki Hata, Yoshinori Ieda
  • Patent number: 9373621
    Abstract: An analog circuit cell array includes a plurality of transistor cell arranged in an array. Each of the transistor cells includes a first source region, a first channel region, a common drain region, a second channel region, and a second source region arranged in sequence one adjacent to another; and a first gate electrode and a second gate electrode formed on the first channel region and the second channel region, respectively, and wherein the first gate electrode and the second gate electrode are connected together for use, and the first source region and the second source region are connected together for use.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: June 21, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Kenta Aruga, Suguru Tachibana, Koji Okada