With Wiring Channel Area Patents (Class 257/210)
  • Patent number: 10714391
    Abstract: A method of manufacturing a semiconductor device includes: providing a substrate including a first stacked fin structure for forming a channel of a first gate-all-around (GAA) transistor, the first stacked fin structure including an initial volume of first channel material, and a second stacked fin structure for forming a channel of a second GAA transistor, the second stacked fin structure including an initial volume of second channel material; reducing said initial volume of the second channel material relative to the initial volume of first channel material by a predetermined amount corresponding to a delay of the first GAA transistor; and forming first and second GAA gate structures around said first channel material and said second channel material respectively.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: July 14, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Jeffrey Smith, Subhadeep Kal, Anton Devilliers
  • Patent number: 10665515
    Abstract: Embodiments herein describe binning and placement techniques for assembling a multi-die device to improve yield when a customer requests a high performance feature from the device. For example, the multi-die device may include multiple dies that are interconnected to form a single device or package. In one embodiment, the multiple dies are the same semiconductor die (e.g., have the same circuit layout) which are disposed on a common interposer or stacked on each other. The multi-die device can then be attached to a printed circuit board (PCB). Although the dies in the multi-die device may each include the same feature (e.g., a PCIe interface, SerDes interface, transmitter, memory interface, etc.), the multi-die device is assembled so that not all of the dies have a feature that satisfies the high performance requested by the customer. That is, at least one of the die includes a lower performance feature.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: May 26, 2020
    Assignee: XILINX, INC.
    Inventors: Matthew H. Klein, Gregory Meredith, Joshua Tan
  • Patent number: 10571427
    Abstract: A molecular detection apparatus according to an embodiment includes: a collection unit collecting detection target gas containing molecules to be detected; a detector including a plurality of detection cells each having an organic probe disposed at a sensor unit, the organic probe capturing the molecules collected in the collection unit; and a discriminator discriminating the molecules by a signal pattern based on an intensity difference of detection signals generated by the molecules being captured by the organic probes in a plurality of the detection cells. In the molecular detection apparatus according to the embodiment, at least one of the detection cells has a plurality of different types of the organic probes disposed at the sensor unit.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: February 25, 2020
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hirohisa Miyamoto, Ko Yamada, Reiko Yoshimura
  • Patent number: 10553679
    Abstract: A semiconductor structure containing a gate-all-around nanosheet field effect transistor having a self-limited inner spacer composed of a rare earth doped germanium dioxide that provides source/drain isolation between rare earth metal silicide ohmic contacts is provided.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: February 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Jingyun Zhang, Takashi Ando, Choonghyun Lee, Alexander Reznicek, Pouya Hashemi
  • Patent number: 10453937
    Abstract: Methods of forming a semiconductor device include forming a layer of activating material on sidewalls of a stack of alternating layers of channel material and sacrificial material. The layer of activating material is annealed to cause the activating material to react with the sacrificial material and to form insulating spacers at ends of the layers of sacrificial material. The layer of activating material is etched away to expose ends of the layers of channel material. Source/drain regions are formed on the ends of the layers of channel material.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: October 22, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robinhsinku Chao, ChoongHyun Lee, Heng Wu, Chun W. Yeung, Jingyun Zhang
  • Patent number: 10418325
    Abstract: A metal wiring layer includes a plurality of hierarchical blocks each divided by a side that serves as a boundary. One of the hierarchical blocks is placed to extend along the outer periphery of the self hierarchical block, and includes: a shield ring wire formed by a single metal wire or by a plurality of metal wires; and a plurality of metal wires that are placed inside the shield ring wire and extend in a preferential direction determined in advance. The shield ring wire has a first section extending in the preferential direction and a second section extending in a non-preferential direction perpendicular to the preferential direction.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: September 17, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroki Nishida, Naozumi Morino, Toshimi Mizutani
  • Patent number: 10411021
    Abstract: A static random access memory (SRAM) device includes an inverter including a ninth first-conductivity-type semiconductor layer formed on a semiconductor substrate; a first pillar-shaped semiconductor layer which is formed on the semiconductor substrate and in which a first first-conductivity-type semiconductor layer, a first body region, a second first-conductivity-type semiconductor layer, a first second-conductivity-type semiconductor layer, a second body region, and a second second-conductivity-type semiconductor layer are formed from the substrate side in that order; a first gate insulating film formed around the first body region; a first gate formed around the first gate insulating film; a second gate insulating film formed around the second body region; a second gate formed around the second gate insulating film; and a first output terminal connected to the second first-conductivity-type semiconductor layer and the first second-conductivity-type semiconductor layer.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: September 10, 2019
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 10204985
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a first semiconductor layer and a second semiconductor layer vertically stacked over a semiconductor substrate. The first semiconductor layer and the second semiconductor layer include different materials. The semiconductor device structure also includes a gate stack covering a first portion of the first semiconductor layer. The semiconductor device structure further includes a spacer element over a sidewall of the gate stack. The spacer element covers the second semiconductor layer and a second portion of the first semiconductor layer. The thickness of the second semiconductor layer is different from the thickness of the second portion.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: February 12, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tung-Ying Lee, Chih-Chieh Yeh, Chen-Feng Hsu
  • Patent number: 10147804
    Abstract: An alternating stack of layers of a first epitaxial semiconductor material and a second epitaxial semiconductor material is formed on a substrate. A fin stack is formed by patterning the alternating stack into a shape of a fin having a parallel pair of vertical sidewalls. After formation of a disposable gate structure and an optional gate spacer, raised active regions can be formed on end portions of the fin stack. A planarization dielectric layer is formed, and the disposable gate structure is subsequently removed to form a gate cavity. A crystallographic etch is performed on the first epitaxial semiconductor material to form vertically separated pairs of an upright triangular semiconductor nanowire and an inverted triangular semiconductor nanowire. Portions of the epitaxial disposable material are subsequently removed. After an optional anneal, the gate cavity is filled with a gate dielectric and a gate electrode to form a field effect transistor.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: December 4, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ali Khakifirooz, Juntao Li
  • Patent number: 10140415
    Abstract: A method and system for verifying a layout of an integrated circuit (IC) is disclosed. The IC may include a plurality of strings each including a plurality of memory cells which are vertically stacked on a substrate. The method may include receiving schematic data of the IC including instances of a string symbol and layout data, preparing a layout versus schematic (LVS) rule file in which a string device is defined, and performing LVS verification.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: November 27, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-eun Lee, Sung-hoon Kim, Jae-ick Son, Hyang-ja Yang
  • Patent number: 10115644
    Abstract: A plurality of interposers are made from a material substrate. The material substrate includes a glass substrate partitioned by a plurality of crossing division lines to define a plurality of separate regions. A multilayer member is provided on a first surface or a second surface opposite to the first surface of the glass substrate and has an insulating layer and a wiring layer. An exposed surface of the multilayer member is cut along each division line by using a first cutting blade to form a cut groove on the exposed surface of the multilayer member, the cut groove having a depth not reaching the glass substrate. The glass substrate is cut along each cut groove by using a second cutting blade having a thickness smaller than the width of each cut groove to thereby divide the glass substrate and manufacture the plural interposers.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: October 30, 2018
    Assignee: Disco Corporation
    Inventor: Katsuhiko Suzuki
  • Patent number: 10090244
    Abstract: Standard cell circuits employing high aspect ratio voltage rails for reduced resistance are disclosed. In one aspect, a standard cell circuit is provided that employs a first high aspect ratio voltage rail configured to receive a first supply voltage. A second high aspect ratio voltage rail is employed that is disposed substantially parallel to the first high aspect ratio voltage rail. A voltage differential between the first and second high aspect ratio voltage rails is used to power a circuit device in the standard cell circuit. The first and second high aspect ratio voltage rails each have a height-to-width ratio greater than 1.0. The height of each respective first and second high aspect ratio voltage rail is greater than each respective width. Employing the first and second high aspect ratio voltage rails allows each to have a cross-sectional area that limits the resistance and corresponding IR drop.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: October 2, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Jeffrey Junhao Xu, Mustafa Badaroglu, Da Yang, Periannan Chidambaram
  • Patent number: 10026681
    Abstract: A fan-out semiconductor package includes a first connection member having a through-hole, a semiconductor chip disposed in the through-hole, a first encapsulant encapsulating at least portions of the first connection member and the semiconductor chip, a second connection member disposed on the first connection member and the semiconductor chip. The first connection member and the second connection member respectively include redistribution layers electrically connected to the connection pads of the semiconductor chip. The fan-out semiconductor package may have excellent rigidity, may be thinned, and may be manufactured in a simplified process.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: July 17, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Tae Ho Ko, Dae Hee Lee, Bong Soo Kim, Myeong Ho Hong, Do Young Jeong, Joon Seok Oh
  • Patent number: 9947767
    Abstract: A semiconductor devices and methods of forming the same include forming a layer of activating material on sidewalls of a stack of alternating layers of channel material and sacrificial material. The layer of activating material is annealed to cause the activating material to react with the sacrificial material and to form insulating spacers at ends of the layers of sacrificial material. The layer of activating material is etched away to expose ends of the layers of channel material. Source/drain regions are formed on the ends of the layers of channel material.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: April 17, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robinhsinku Chao, ChoongHyun Lee, Heng Wu, Chun W. Yeung, Jingyun Zhang
  • Patent number: 9947670
    Abstract: A static random access memory (SRAM) device includes an inverter including a ninth first-conductivity-type semiconductor layer formed on a semiconductor substrate; a first pillar-shaped semiconductor layer which is formed on the semiconductor substrate and in which a first first-conductivity-type semiconductor layer, a first body region, a second first-conductivity-type semiconductor layer, a first second-conductivity-type semiconductor layer, a second body region, and a second second-conductivity-type semiconductor layer are formed from the substrate side in that order; a first gate insulating film formed around the first body region; a first gate formed around the first gate insulating film; a second gate insulating film formed around the second body region; a second gate formed around the second gate insulating film; and a first output terminal connected to the second first-conductivity-type semiconductor layer and the first second-conductivity-type semiconductor layer.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: April 17, 2018
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 9837517
    Abstract: The present invention provides a field effect transistor and the method for preparing such a filed effect transistor. The filed effect transistor comprises a semiconductor, germanium nanowires, a first III-V compound layer surrounding the germanium nanowires, a semiconductor barrier layer, a gate dielectric layer and a gate electrode sequentially formed surrounding the first III-V compound layer, and source/drain electrodes are respectively located at each side of the gate electrode and on the first III-V compound layer. According to the present invention, the band width of the barrier layer is greater than that of the first III-V compound layer, and the band curvatures of the barrier layer and the first III-V compound layer are different, therefore, a two-dimensional electron gas (2DEG) is formed in the first III-V compound layer near the barrier layer boundary. Since the 2DEG has higher mobility, the performance of the filed effect transistor improved.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: December 5, 2017
    Assignee: ZING SEMICONDUCTOR CORPORATION
    Inventors: Deyuan Xiao, Richard R. Chang
  • Patent number: 9837472
    Abstract: A method for fabricating 3-D cross-point memory arrays, and more particularly to fabricating phase change memory (PCM) and resistive RAM (ReRAM or RRAM) 3-D memory arrays having a cell size footprint of 4F2. The method for forming a plurality of layers of memory cells using a limited number of photolithographic patterning steps is applicable to memory devices having single or multiple storage bits per cell, such as cells having anywhere from one to eight bits per cell or more. These bits are stacked three dimensionally and include memory cells based on phase change material, on resistive change material, on magnetic field alignment, on mechanical switching, and on other memory cells based on other information storage technologies.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: December 5, 2017
    Assignee: HGST, Inc.
    Inventor: Daniel Robert Shepard
  • Patent number: 9729587
    Abstract: There is proposed a method and corresponding apparatuses allowing a change from a packet switched communication domain to a circuit switched communication domain. When a user equipment as a connection terminating point receives a connection initialization message with a media flow, such as audio, which cannot be delivered by the packet switched access, it sends a specific response rejecting the connection via the packet switched access to an application server for service centralization and continuity. In the application server, it is checked whether several conditions are met in order to determine whether the communication connection comprising the media flow is allowed to be changed to the circuit switched domain. If yes, the communication connection is changed from the packet switched communication domain to the circuit switched communication domain.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: August 8, 2017
    Assignee: Nokia Technology Oy
    Inventors: Georg Mayer, Jari Mutikainen, Peter Leis
  • Patent number: 9715987
    Abstract: A semiconductor device may include the following elements: a semiconductor substrate, an insulator positioned on the substrate, a source electrode positioned on the insulator, a drain electrode positioned on the insulator, a gate electrode positioned between the source electrode and the drain electrode, a hollow channel surrounded by the gate electrode and positioned between the source electrode and the drain electrode, a dielectric member positioned between the hollow channel and the gate electrode, a first insulating member positioned between the gate electrode and the source electrode, and a second insulating member positioned between the gate electrode and the drain electrode.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: July 25, 2017
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Deyuan Xiao
  • Patent number: 9614038
    Abstract: A method of manufacturing a nanowire device is disclosed. The method includes providing a substrate, wherein the substrate comprises a pair of support pads, a recess disposed between the support pads, a second insulating layer disposed on the support pads, a third insulating layer disposed on a bottom of the recess, and at least one nanowire suspended between the support pads at a top portion of the recess; forming a first insulating layer on the nanowire; depositing a dummy gate material over the substrate on the first insulating layer, and patterning the dummy gate material to form a dummy gate structure surrounding a channel region; forming a first oxide layer on laterally opposite sidewalls of the dummy gate; and extending the nanowire on laterally opposite ends of the channel region to the respective support pads, so as to form a source region and a drain region.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: April 4, 2017
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Zhongshan Hong
  • Patent number: 9597893
    Abstract: If the shape of an element substrate is a parallelogram, a trapezoid, an uneven shape, or the like, there is no region where a driver transistor corresponding to a heater in the vicinity of an end portion of the element substrate is arranged, and thus the heater cannot be arranged near the end portion. The layout arrangement of driving circuits suitable for the substrate shape is required while suppressing an increase in the area of the element substrate. In an embodiment of this invention, the diffusion layer of the drain electrode of a driver transistor for driving a heater is divided in a direction perpendicular to that in which heaters are arranged, and the divided portions are connected to form one driver transistor. The divided portions are arranged stepwise.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: March 21, 2017
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tomoko Kudo, Ryo Kasai
  • Patent number: 9543440
    Abstract: An alternating stack of layers of a first epitaxial semiconductor material and a second epitaxial semiconductor material is formed on a substrate. A fin stack is formed by patterning the alternating stack into a shape of a fin having a parallel pair of vertical sidewalls. After formation of a disposable gate structure and an optional gate spacer, raised active regions can be formed on end portions of the fin stack. A planarization dielectric layer is formed, and the disposable gate structure is subsequently removed to form a gate cavity. A crystallographic etch is performed on the first epitaxial semiconductor material to form vertically separated pairs of an upright triangular semiconductor nanowire and an inverted triangular semiconductor nanowire. Portions of the epitaxial disposable material are subsequently removed. After an optional anneal, the gate cavity is filled with a gate dielectric and a gate electrode to form a field effect transistor.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: January 10, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ali Khakifirooz, Juntao Li
  • Patent number: 9472574
    Abstract: For fabrication of a semiconductor structure, there is set forth herein a method of fabricating a semiconductor structure, the method including forming a multilayer structure, the multilayer structure having a bulk substrate, a first layer defining an ultrathin body spaced apart from the bulk substrate, and a second layer above the first layer having material for defining a fin, and patterning the second layer to define a fin above the ultrathin body.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: October 18, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Hui Zang
  • Patent number: 9431350
    Abstract: A crack-stopping structure includes a semiconductor wafer comprising a plurality of dies defined by a plurality of scribe line regions, a plurality of metal patterns formed in the scribe line regions, and a plurality of groups of through silicon holes (TSHs) formed in the scribe line regions. The wafer further includes a front side and a back side, and the TSHs respectively include at least a bottom opening formed in the bottom side of the wafer. The groups of TSHs are formed between the metal patterns and the dies.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: August 30, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Kuang-Hui Tang
  • Patent number: 9401324
    Abstract: According to one embodiment, a semiconductor device includes a transistor formed on a semiconductor chip, a lower-layer wiring connected to a diffusion layer of the transistor, and drawn outside the diffusion layer, and an upper-layer wiring drawn out from a pad electrode formed on the semiconductor chip, connected to the lower-layer wiring, and having resistivity lower than that of the lower-layer wiring.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: July 26, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaru Koyanagi, Yasuhiro Suematsu
  • Patent number: 9390991
    Abstract: A semiconductor die has active circuits formed on its active surface. Contact pads are formed on the active surface of the semiconductor die and coupled to the active circuits. A die extension region is formed around a periphery of the semiconductor die. Conductive THVs are formed in the die extension region. A wafer level conductive plane or ring is formed on a center area of the active surface. The conductive plane or ring is connected to a first contact pad to provide a first power supply potential to the active circuits, and is electrically connected to a first conductive THV. A conductive ring is formed partially around a perimeter of the conductive plane or ring and connected to a second contact pad for providing a second power supply potential to the active circuits. The conductive ring is electrically connected to a second THV.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: July 12, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Guruprasad G. Badakere, Zigmund R. Camacho, Lionel Chien Hui Tay
  • Patent number: 9324750
    Abstract: Disclosed herein is an imaging device including at least one special pixel with a configuration having a layout made different from the layout of the configuration of each pixel other than the special pixel. The special pixel is a pixel having an imaging characteristic steadily different from that of the other pixels. A difference in layout between the configuration of the special pixel and the configuration of the other pixels is used to suppress a non-uniformity of the imaging characteristic exhibited by the special pixel.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: April 26, 2016
    Assignee: SONY CORPORATION
    Inventor: Shunsuke Ishii
  • Patent number: 9269702
    Abstract: A semiconductor device is disclosed to include a plurality of cells. Each of the cells has a respective outer cell boundary defined to circumscribe the cell in an orthogonal manner. Also, each of the cells includes circuitry for performing one or more logic functions. This circuitry includes a plurality of conductive features defined in one or more levels of the cell. One or more of the conductive features in at least one level of a given cell is an encroaching feature positioned to encroach by an encroachment distance into an exclusion zone. The exclusion zone occupies an area within the cell defined by an exclusion distance extending perpendicularly inward into the given cell from a first segment of the outer cell boundary. The exclusion distance is based on a design rule distance representing a minimum separation distance required between conductive features in adjacently placed cells on the semiconductor device.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: February 23, 2016
    Assignee: Tela Innovations, Inc.
    Inventors: Jonathan R. Quandt, Scott T. Becker, Dhrumil Gandhi
  • Patent number: 9059036
    Abstract: A semiconductor integrated circuit includes a plurality of memory cells arranged in a cell-placement row extending in a first direction, a first N well and a first P well arranged in a second direction perpendicular to the first direction in each area of the memory cells, and a second N well and a second P well each having the same length as a width of the cell-placement row and situated between at least two adjacent memory cells of the plurality of memory cells, wherein the first N well and the second N well are integrated, and the first P well and the second P well are integrated.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: June 16, 2015
    Assignee: FUJITSU LIMITED
    Inventor: Kazuhiro Abe
  • Patent number: 9059142
    Abstract: A method for forming a semiconductor device with a vertical gate is disclosed, including providing a substrate, forming a recess in the substrate, forming a gate dielectric layer on a sidewall and a bottom of the recess, forming an adhesion layer in the recess and on the gate dielectric layer, wherein the adhesion layer is a metal silicide nitride layer, and forming a gate layer in the recess and on the adhesion layer.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: June 16, 2015
    Assignee: Nanya Technology Corporation
    Inventors: Wen-Ping Liang, Chiang-Hung Lin, Kuo-Hui Su
  • Patent number: 9029859
    Abstract: An object is to provide a display device with a high aperture ratio or a semiconductor device in which the area of an element is large. A channel formation region of a TFT with a multi-gate structure is provided under a wiring that is provided between adjacent pixel electrodes (or electrodes of an element). In addition, a channel width direction of each of a plurality of channel formation regions is parallel to a longitudinal direction of the pixel electrode. In addition, when a channel width is longer than a channel length, the area of the channel formation region can be increased.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: May 12, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Mizuki Sato
  • Patent number: 9000489
    Abstract: A multi-field effect transistor (FET) device includes a first FET device arranged on a substrate, the first FET device including a first active region and a second active region, a second FET device arranged on the substrate, the second FET device including a first active region and a second active region, and a first conductive interconnect electrically connecting the first active region of the first FET device to the first active region of the second FET device, the first conductive interconnect having a first cross sectional area proximate to the first active region of the first FET device that is greater than a second cross sectional area proximate to the first active region of the second FET device.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventor: Ning Lu
  • Patent number: 8987787
    Abstract: A semiconductor structure includes first and second chips assembled to each other. The first chip includes N of first conductive lines, M of second conductive lines disposed on the first conductive lines, N of third conductive lines perpendicularly on the second conductive lines and parallel to the first conductive lines, N of first vias connected to the first conductive lines, M sets of second vias connected to the second conductive lines, and N sets of third vias connected to the third conductive lines. The second and first conductive lines form an overlapping area. The third conductive lines and N sets of the third vias include at least two groups respectively disposed in a first and a third regions of the overlapping area. M sets of second vias include at least two groups respectively disposed in a second region and a fourth region of the overlapping area.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: March 24, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Shih-Hung Chen, Kuang-Yeu Hsieh, Cheng-Yuan Wang
  • Patent number: 8981422
    Abstract: To prevent contact plugs formed to sandwich an abutting portion between gate electrodes, from being short-circuited via a void formed inside an insulating film of the abutting portion. Over sidewalls SW facing each other in the abutting portion between gate electrodes G2 and G5, a liner insulating film 6 and an interlayer insulating film 7 are formed. Between the sidewalls SW, the liner insulating film 6 formed on each of the side walls of the sidewalls SW are brought in contact with each other to close a space between the sidewalls SW to prevent a void from being generated inside the interlayer insulating film 7 and the liner insulating film 6.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: March 17, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Masahiko Takeuchi
  • Patent number: 8969190
    Abstract: Disclosed herein are various methods of forming a layer of silicon on a layer of silicon/germanium. In one example, a method disclosed herein includes forming a silicon/germanium material on a semiconducting substrate, after forming the silicon/germanium material, performing a heating process to raise a temperature of the substrate to a desired silicon formation temperature while flowing a silicon-containing precursor and a chlorine-containing precursor into the deposition chamber during the heating process, and, after the temperature of the substrate reaches the desired silicon formation temperature, forming a layer of silicon on the silicon/germanium material.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: March 3, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Joachim Patzer
  • Patent number: 8941521
    Abstract: To decrease the burden of digital processing, provided is an AD conversion apparatus comprising a pattern generating section that, for each target bit specified one bit at a time moving downward in the output data, generates a pattern signal having a pulse width or number of pulses corresponding to a weighting of the target bit; an integrating section that integrates the pattern signals according to a judgment value for judging a value of the target bit each time a pattern signal is generated, and outputs a reference signal obtained by accumulating the integrated value of each pattern signal; a comparing section that, each time generation of a pattern signal is finished, compares the input signal to the reference signal; and an output section that outputs the output data to have values corresponding to the comparison results obtained after each generation of a pattern signal corresponding to a bit is finished.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: January 27, 2015
    Assignee: Advantest Corporation
    Inventor: Yasuhide Kuramochi
  • Patent number: 8921898
    Abstract: A device includes an array of a plurality of memory cells, at least one N-well contact area and at least one P-well contact area. The memory cells are arranged in a plurality of rows and a plurality of columns. Each column includes an N-well region and at least one P-well region. The N-well and P-well regions extend between a first end of the column and a second end of the column. Each N-well contact area electrically contacts at least one of the N-well regions, wherein the N-well region of at least one of the columns is electrically contacted at only one of the first and second ends of the column. Each P-well contact area electrically contacts at least one of the P-well regions, wherein the P-well region of at least one of the columns is electrically contacted at only one of the first and second ends of the column.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: December 30, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Nigel Chan, Michael Otto
  • Patent number: 8923057
    Abstract: A three-dimensional semiconductor device comprises active patterns arranged two-dimensionally on a substrate, electrodes arranged three-dimensionally between the active patterns, and memory regions arranged three-dimensionally at intersecting points defined by the active patterns and the electrodes. Each of the active patterns is used as a common current path for an electrical connection to two different memory regions that are formed at the same height from the substrate.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: December 30, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Hoon Son, Myoung Bum Lee, Ki Hyun Hwang, Seung Jae Baik
  • Patent number: 8901614
    Abstract: Described is a method for adjusting an operating temperature of MOS power components composed of a plurality of identical individual cells and a component for carrying out the method. As a characteristic feature, the gate electrode network (4) of the active chip region is subdivided into several gate electrode network sectors (B1, B2, B3) which are electrically isolated from one another by means of isolating points and to each of which a different gate voltage is fed via corresponding contacts.
    Type: Grant
    Filed: May 19, 2009
    Date of Patent: December 2, 2014
    Assignee: X-Fab Semiconductor Foundries AG
    Inventors: Michael Stoisiek, Michael Gross
  • Patent number: 8884396
    Abstract: According to one embodiment, a first back surface of a first substrate and a second front surface of a second substrate are jointed together so as to connect a first conductor with a second conductor. The first conductor includes a portion having a diameter equal to that of a first gap formed above a first metal layer in a range between the first metal layer and a first front surface, and a portion having a diameter greater than that of the first gap and smaller than an outer diameter of the first metal layer in a range between the first metal layer and the first back surface. A first insulating layer has a gap formed above the first metal layer, the gap being greater than the first gap and smaller than the outer diameter of the first metal layer.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: November 11, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Mitsuyoshi Endo
  • Patent number: 8816403
    Abstract: Provided are semiconductor device cells, methods for forming the semiconductor device cells and a layout style for the semiconductor device cells. The device cells may be repetitive cells used throughout an integrated circuit. The layout style utilizes an area at the polysilicon level that is void of polysilicon and which can accommodate conductive leads therein or thereover. The conductive leads are formed of material typically used for contacts or vias and are disposed beneath the first metal interconnect level which couples device cells to one another. The subjacent local conductive leads may form subjacent signal lines allowing for additional power mesh lines to be included within the limited number of metal tracks that can be accommodated within a device cell and in accordance with metal track design spacing rules.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: August 26, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jung-Hsuan Chen, May Chang, Chiting Cheng, Li-Chun Tien
  • Patent number: 8796740
    Abstract: Techniques and design methodologies for using a single mask set to create devices of different sizes are disclosed. A mask with a plurality of tiles is disclosed. Each of the tiles has a number of fixed resource blocks, multiple logic blocks and is surrounded by a scribe region. The tiles may be connected to one or more adjacent tiles through interconnect lines that enable the fixed resource blocks and logic blocks in one tile to communicate with the fixed resource and logic blocks in an adjacent tile. The mask set may be used to produce devices of different sizes. Using a mask set that can handle a variety of design sizes with varying resources may in turn reduce mask cost.
    Type: Grant
    Filed: January 13, 2009
    Date of Patent: August 5, 2014
    Assignee: Altera Corporation
    Inventors: Lawrence David Landis, Richard Price
  • Patent number: 8791507
    Abstract: A layout of a semiconductor device is capable of reliably reducing a variation in gate length due to the optical proximity effect, and enables flexible layout design to be implemented. Gate patterns (G1, G2, G3) of a cell (C1) are arranged at the same pitch, and terminal ends (e1, e2, e3) of the gate patterns are located at the same position in the Y direction, and have the same width in the X direction. A gate pattern (G4) of a cell (C2) has protruding portions (4b) protruding toward the cell (C1) in the Y direction, and the protruding portions (4b) form opposing terminal ends (eo1, eo2, eo3). The opposing terminal ends (eo1, eo2, eo3) are arranged at the same pitch as the gate patterns (G1, G2, G3), are located at the same position in the Y direction, and have the same width in the X direction.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: July 29, 2014
    Assignee: Panasonic Corporation
    Inventors: Kazuyuki Nakanishi, Masaki Tamaru
  • Patent number: 8710553
    Abstract: An integrated circuit includes a substrate. The substrate includes diffusion lines. The diffusion lines include impurities diffused into the substrate. A signal line layer includes first signal lines. A first metal layer includes second signal lines. The second signal lines include a first metallic material. A second metal layer includes third signal lines. The third signal lines include a second metallic material. First contacts connect the diffusion lines to (i) a first set of the second signal lines, or (ii) a first set of the third signal lines. Second contacts connect a first set of the first signal lines to a second set of the third signal lines. Each signal line in a first set of the second signal lines includes first portions and second portions. The first portions extend towards and are not connected to the second contacts. The first portions are not parallel to the second portions.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: April 29, 2014
    Assignee: Marvell International Ltd.
    Inventors: Qiang Tang, Min She, Ken Liao
  • Patent number: 8673216
    Abstract: The invention provides devices, systems, and methods for detecting an analyte vapor. Particularly, electronegative analyte vapors, such as those vapors evolving from explosive compounds, are typical analytes detected the devices. The devices operate using a resistivity change mechanism wherein a nanostructured chemiresistive material undergoes a resistivity change in the presence of an analyte vapor. A resistivity change indicates the presence of an analyte.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: March 18, 2014
    Assignee: The University of Washington
    Inventors: Antao Chen, Danling Wang, Qifeng Zhang, Guozhong Cao
  • Patent number: 8653565
    Abstract: Various aspects of the technology includes a quad semiconductor power and/or switching FET comprising a pair of control/sync FET devices. Current may be distributed in parallel along source and drain fingers. Gate fingers and pads may be arranged in a serpentine configuration for applying gate signals to both ends of gate fingers. A single continuous ohmic metal finger includes both source and drain regions and functions as a source-drain node. A set of electrodes for distributing the current may be arrayed along the width of the source and/or drain fingers and oriented to cross the fingers along the length of the source and drain fingers. Current may be conducted from the electrodes to the source and drain fingers through vias disposed along the surface of the fingers. Heat developed in the source, drain, and gate fingers may be conducted through the vias to the electrodes and out of the device.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: February 18, 2014
    Assignee: Sarda Technologies, Inc.
    Inventor: James L. Vorhaus
  • Patent number: 8633547
    Abstract: Structures for spanning gap in body-bias voltage routing structure. In an embodiment, a structure is comprised of at least one metal wire.
    Type: Grant
    Filed: June 16, 2008
    Date of Patent: January 21, 2014
    Inventors: Robert Masleid, James B. Burr, Michael Pelham
  • Patent number: 8614462
    Abstract: A method of fabricating an array substrate for an organic electroluminescent device includes forming a semiconductor layer of polysilicon in an element region, and a semiconductor pattern of polysilicon in a storage region on a substrate; forming a multiple-layered gate electrode corresponding to a center portion of the semiconductor layer and a first storage electrode corresponding to the semiconductor pattern; performing an impurity-doping to make a portion of the semiconductor layer not covered by the gate electrode into an ohmic contact layer and make the semiconductor pattern into a second storage electrode; forming source and drain electrodes and a third storage electrode corresponding to the first storage electrode; forming a first electrode contacting the drain electrode and a fourth storage electrode corresponding to the third storage electrode.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: December 24, 2013
    Assignee: LG Display Co., Ltd.
    Inventors: Hee-Dong Choi, Ki-Sul Cho, Seong-Moh Seo
  • Patent number: 8569168
    Abstract: Method of forming a semiconductor structure which includes forming first conductive spacers on a semiconductor substrate; forming second conductive spacers with respect to the first conductive spacers, at least one of the second conductive spacers adjacent to and in contact with each of the first conductive spacers to form combined conductive spacers; recessing the second conductive spacers with respect to the first conductive spacers so that the first conductive spacers extend beyond the second conductive spacers; depositing an ILD to cover the first and second spacers except for an exposed edge of the first conductive spacers; patterning the exposed edges of the first conductive spacers to recess the edges of the first conductive spacers in predetermined locations to form recesses with respect to the ILD; and filling the recesses with an insulating material to leave unrecessed edges of the first conductive spacers as vias to subsequent wiring features.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: October 29, 2013
    Assignee: International Business Machines Corporation
    Inventors: Steven J. Holmes, David V. Horak, Charles W. Koburger, III, Shom Ponoth, Chih-Chao Yang
  • Patent number: 8558283
    Abstract: A semiconductor device or a memory which includes the same have a line pattern, and a contact plug, the line pattern including a first linear feature to which the contact plug is connected by design, and a second linear feature having a connecting portion and a dummy portion adjacent the location at which the contact plug is electrically connected to the first linear feature. A second contact plug is electrically connected to the connecting portion of the second linear feature of the line pattern. In the case of a misalignment error or the like, the first contact plug may also be electrically connected to the second linear feature of the line pattern but at the dummy portion thereof so as to not create a short circuit in that case. The dummy portion thus allows a sufficiently large process margin to be secured for the contact plug.
    Type: Grant
    Filed: June 7, 2010
    Date of Patent: October 15, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-sun Sel, Nam-su Lim, In-wook Oh