Abstract: Resistance measuring structures for a stacked integrated circuit device are provided. The resistance measuring structures may include a first Complementary Field Effect Transistor (CFET) stack, a second CFET stack, and a conductive connection. The first CFET may include a first upper transistor that includes a first upper drain region and a first lower transistor that is between the substrate and the first upper transistor and includes a first lower drain region. The second CFET may include a second upper transistor that includes a second upper drain region and a second lower transistor that is between the substrate and the second upper transistor and includes a second lower drain region. The conductive connection may electrically connect the first upper drain region and the second upper drain region.

Abstract: Provided is a static random-access memory (SRAM) device.

Abstract: Various implementations described herein are related to a device having multiple transistors that are arranged as a bitcell. The multiple transistors may include multiple P-type transistors that are arranged in a P-over-P stack configuration, and the multiple transistors may include multiple N-type transistors that are arranged in an N-over-N stack configuration.

Abstract: The present disclosure provides a standard cell template and a semiconductor structure. The standard cell template includes a first well region and a second well region, arranged along a first direction; a first gate pattern, located in the first well region and extending along the first direction, for defining a first gate; a second gate pattern, located in the second well region and extending along the first direction, for defining a second gate; and a gate electrical connection pattern, located between the first gate pattern and the second gate pattern, for defining a gate electrical connection structure; where the gate electrical connection structure is arranged on the same layer as the first gate and the second gate to electrically connect the first gate and/or the second gate.

Abstract: A manufacturing method of an input circuit of a flip-flop including: depositing a first gate strip, a second gate strip, a third gate strip, and a fourth gate strip, wherein a distance between the first and second gate strips, a distance between the second and third gate strips, and a distance between the third and fourth gate strips equal; executing a cut-off operation upon the first gate strip to generate a first first gate strip and a second first gate strip; executing a cut-off operation upon the third gate strip to generate a first third gate strip and a second third gate strip; and directing a first signal to the first first gate strip and the second third gate strip, and a second signal to the second first gate strip and the first third gate strip.

Abstract: A probe position monitoring structure includes a first common line and a contact portion configured for being directly contacted with a probe. The contact portion includes a first zigzag structure, and a first end of the first zigzag structure is directly connected with the first common line. A method of monitoring a position of a probe includes the following steps. The probe position monitoring structure is provided. The first zigzag structure is directly contacted with a first probe. A resistance measurement is performed to measure a resistance of a portion of the first zigzag structure located between the first probe and the first end for monitoring a position of the first probe.

Abstract: An integrated circuit is disclosure. The integrated circuit includes a first pair of power rails, a set of conductive lines arranged in the first layer parallel to the first pair of power rails, a first set of active areas. The integrated circuit further includes a first gate arranged along the second direction, between the first pair of power rails, and crossing the first set of active areas in a layout view, wherein the first gate is configured to be shared by a first transistor of a first type and a second transistor of a second type; and a second gate and a third gate, in which the second gate is configured to be a control terminal of a third transistor, and the third gate is configured to be a control terminal of a fourth transistor which is coupled to the control terminal of the third transistor.

Abstract: Embodiments herein may present an integrated circuit or a computing system having an integrated circuit, where the integrated circuit includes a physical network layer, a physical computing layer, and a physical memory layer, each having a set of dies, and a die including multiple tiles. The physical network layer further includes one or more signal pathways dynamically configurable between multiple pre-defined interconnect topologies for the multiple tiles, where each topology of the multiple pre-defined interconnect topologies corresponds to a communication pattern related to a workload. At least a tile in the physical computing layer is further arranged to move data to another tile in the physical computing layer or a storage cell of the physical memory layer through the one or more signal pathways in the physical network layer. Other embodiments may be described and/or claimed.

Abstract: Semiconductor memory devices may include first and second stacks on a substrate and first and second interconnection lines on the first and second stacks. Each of the first and second stacks may include semiconductor patterns vertically stacked on the substrate, conductive lines connected to the semiconductor patterns, respectively, and a gate electrode that is adjacent to the semiconductor patterns and extends in a vertical direction. The first stack may include a first conductive line and a first gate electrode, and the second stack may include a second conductive line and a second gate electrode. Lower surfaces of the first and second conductive lines may be coplanar. The first interconnection line may be electrically connected to at least one of the first and second conductive lines. The second interconnection line may be electrically connected to at least one of the first and second gate electrodes.

Abstract: The task of the present invention is to realize chips of different sizes, in particular FPGAs, without the need for ever new production mask sets. In the conventional way, a single die can be used or almost any number of dies from one wafer. According to the invention, only one lithography mask set is used for chip production and multi-die chips of different sizes with 1 . . . n single dies are separated from a wafer. The single dies are connected by the scribeline between the dies. According to the patent claims, various precautions must be taken to ensure that the dies are reliably connected and that no problems occur when separating the multi-die chips.

Abstract: An interposer includes a stacked body including insulating base material layers that are stacked on one another, first and second electrodes, a conductor pattern, and an interlayer connection conductor. The stacked body includes a first mounting surface including a first electrode, and a second mounting surface facing the first mounting surface and including a second electrode. The first electrode is electrically connected to the second electrode through the conductor pattern and the interlayer connection conductor. A length of an electrical path including conductor patterns connecting the first electrode and the second electrode is larger than a total length of the interlayer connection conductor in a stacking direction.

Abstract: Provided is a semiconductor device including a substrate, a gate structure, a first metal layer, and a gate via. The substrate has at least three semiconductor fins to define an active region. The gate structure is across the at least three semiconductor fins and extends along a first direction. The first metal layer extends along a second direction and is disposed over the gate structure. The gate via is disposed between the gate structure and the first metal layer. The gate via has a longitudinal axis extending along the first direction and across the first metal layer. A length of the longitudinal axis of the gate via is greater than a width of the first metal layer.

Abstract: An integrated circuit (IC) device includes: a fin-type active area protruding from a substrate and extending in a first horizontal direction; a first nanosheet disposed above an upper surface of the fin-type active area with a first separation space therebetween; a second nanosheet disposed above the first nanosheet with a second separation space therebetween; a gate line extending on the substrate in a second horizontal direction intersecting the first horizontal direction, at least a portion of the gate line being disposed in the second separation space; and a bottom insulation structure disposed in the first separation space.

Abstract: An interposer includes a stacked body including first and second mounting surfaces that face each other, a first electrode on the first mounting surface, and a second electrode on the second mounting surface. The stacked body includes flexible insulating layers stacked on each other, and a folded portion. The first and second electrodes are electrically connected to each other. The stacked body includes an upright portion between the first and second mounting surfaces and in which a stacking direction in which the insulating layers are stacked is parallel to the first and second mounting surfaces, and a bent portion bent in a plan view of the first and second mounting surfaces.

Abstract: A wiring structure includes a conductive structure, a surface structure and at least one through via. The conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The surface structure is disposed adjacent to a top surface of the conductive structure. The through via extends through the surface structure and extending into at least a portion of the conductive structure.

Abstract: An apparatus comprises a base structure, a memory structure, and interconnect structures. The base structure comprises odd sense amplifiers and even sense amplifiers. The memory structure comprises 3D memory arrays having decks each comprising digit lines, additional digit lines, memory cells, and word lines. The digit lines comprise odd digit lines and even digit lines, and the additional digit lines comprise additional odd digit lines and additional even digit lines. The memory cells are connected to the digit lines and the additional digit lines, and each comprise two transistors and one capacitor. The word lines are connected to the memory cells, and comprise odd word lines and even word lines. The interconnect structures comprise odd interconnect structures connecting the odd sense amplifiers to the odd digit lines and the additional odd digit lines, and even interconnect structures connecting the even sense amplifiers to the even digit lines and the additional even digit lines.

Abstract: An integrated circuit structure includes a set of gate structures, a first conductive structure, a first and second set of vias, and a first set of conductive structures. The set of gate structures is located at a first level. The first conductive structure extends in a first direction, overlaps the set of gate structures and is located at a second level. The first set of vias is between the set of gate structures and the first conductive structure. The first set of vias couple the set of gate structures to the first conductive structure. The first set of conductive structures extend in a second direction, overlap the first conductive structure, and is located at a third level. The second set of vias couple the first set of conductive structures to the first conductive structure, and is between the first set of conductive structures and the first conductive structure.

Abstract: A method of manufacturing a semiconductor device includes: providing a substrate including a first stacked fin structure for forming a channel of a first gate-all-around (GAA) transistor, the first stacked fin structure including an initial volume of first channel material, and a second stacked fin structure for forming a channel of a second GAA transistor, the second stacked fin structure including an initial volume of second channel material; reducing said initial volume of the second channel material relative to the initial volume of first channel material by a predetermined amount corresponding to a delay of the first GAA transistor; and forming first and second GAA gate structures around said first channel material and said second channel material respectively.

Abstract: Embodiments herein describe binning and placement techniques for assembling a multi-die device to improve yield when a customer requests a high performance feature from the device. For example, the multi-die device may include multiple dies that are interconnected to form a single device or package. In one embodiment, the multiple dies are the same semiconductor die (e.g., have the same circuit layout) which are disposed on a common interposer or stacked on each other. The multi-die device can then be attached to a printed circuit board (PCB). Although the dies in the multi-die device may each include the same feature (e.g., a PCIe interface, SerDes interface, transmitter, memory interface, etc.), the multi-die device is assembled so that not all of the dies have a feature that satisfies the high performance requested by the customer. That is, at least one of the die includes a lower performance feature.

Abstract: A molecular detection apparatus according to an embodiment includes: a collection unit collecting detection target gas containing molecules to be detected; a detector including a plurality of detection cells each having an organic probe disposed at a sensor unit, the organic probe capturing the molecules collected in the collection unit; and a discriminator discriminating the molecules by a signal pattern based on an intensity difference of detection signals generated by the molecules being captured by the organic probes in a plurality of the detection cells. In the molecular detection apparatus according to the embodiment, at least one of the detection cells has a plurality of different types of the organic probes disposed at the sensor unit.

Abstract: A semiconductor structure containing a gate-all-around nanosheet field effect transistor having a self-limited inner spacer composed of a rare earth doped germanium dioxide that provides source/drain isolation between rare earth metal silicide ohmic contacts is provided.

Abstract: Methods of forming a semiconductor device include forming a layer of activating material on sidewalls of a stack of alternating layers of channel material and sacrificial material. The layer of activating material is annealed to cause the activating material to react with the sacrificial material and to form insulating spacers at ends of the layers of sacrificial material. The layer of activating material is etched away to expose ends of the layers of channel material. Source/drain regions are formed on the ends of the layers of channel material.

Abstract: A metal wiring layer includes a plurality of hierarchical blocks each divided by a side that serves as a boundary. One of the hierarchical blocks is placed to extend along the outer periphery of the self hierarchical block, and includes: a shield ring wire formed by a single metal wire or by a plurality of metal wires; and a plurality of metal wires that are placed inside the shield ring wire and extend in a preferential direction determined in advance. The shield ring wire has a first section extending in the preferential direction and a second section extending in a non-preferential direction perpendicular to the preferential direction.

Abstract: A static random access memory (SRAM) device includes an inverter including a ninth first-conductivity-type semiconductor layer formed on a semiconductor substrate; a first pillar-shaped semiconductor layer which is formed on the semiconductor substrate and in which a first first-conductivity-type semiconductor layer, a first body region, a second first-conductivity-type semiconductor layer, a first second-conductivity-type semiconductor layer, a second body region, and a second second-conductivity-type semiconductor layer are formed from the substrate side in that order; a first gate insulating film formed around the first body region; a first gate formed around the first gate insulating film; a second gate insulating film formed around the second body region; a second gate formed around the second gate insulating film; and a first output terminal connected to the second first-conductivity-type semiconductor layer and the first second-conductivity-type semiconductor layer.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a first semiconductor layer and a second semiconductor layer vertically stacked over a semiconductor substrate. The first semiconductor layer and the second semiconductor layer include different materials. The semiconductor device structure also includes a gate stack covering a first portion of the first semiconductor layer. The semiconductor device structure further includes a spacer element over a sidewall of the gate stack. The spacer element covers the second semiconductor layer and a second portion of the first semiconductor layer. The thickness of the second semiconductor layer is different from the thickness of the second portion.

Abstract: An alternating stack of layers of a first epitaxial semiconductor material and a second epitaxial semiconductor material is formed on a substrate. A fin stack is formed by patterning the alternating stack into a shape of a fin having a parallel pair of vertical sidewalls. After formation of a disposable gate structure and an optional gate spacer, raised active regions can be formed on end portions of the fin stack. A planarization dielectric layer is formed, and the disposable gate structure is subsequently removed to form a gate cavity. A crystallographic etch is performed on the first epitaxial semiconductor material to form vertically separated pairs of an upright triangular semiconductor nanowire and an inverted triangular semiconductor nanowire. Portions of the epitaxial disposable material are subsequently removed. After an optional anneal, the gate cavity is filled with a gate dielectric and a gate electrode to form a field effect transistor.

Abstract: A method and system for verifying a layout of an integrated circuit (IC) is disclosed. The IC may include a plurality of strings each including a plurality of memory cells which are vertically stacked on a substrate. The method may include receiving schematic data of the IC including instances of a string symbol and layout data, preparing a layout versus schematic (LVS) rule file in which a string device is defined, and performing LVS verification.

Abstract: A plurality of interposers are made from a material substrate. The material substrate includes a glass substrate partitioned by a plurality of crossing division lines to define a plurality of separate regions. A multilayer member is provided on a first surface or a second surface opposite to the first surface of the glass substrate and has an insulating layer and a wiring layer. An exposed surface of the multilayer member is cut along each division line by using a first cutting blade to form a cut groove on the exposed surface of the multilayer member, the cut groove having a depth not reaching the glass substrate. The glass substrate is cut along each cut groove by using a second cutting blade having a thickness smaller than the width of each cut groove to thereby divide the glass substrate and manufacture the plural interposers.

Abstract: Standard cell circuits employing high aspect ratio voltage rails for reduced resistance are disclosed. In one aspect, a standard cell circuit is provided that employs a first high aspect ratio voltage rail configured to receive a first supply voltage. A second high aspect ratio voltage rail is employed that is disposed substantially parallel to the first high aspect ratio voltage rail. A voltage differential between the first and second high aspect ratio voltage rails is used to power a circuit device in the standard cell circuit. The first and second high aspect ratio voltage rails each have a height-to-width ratio greater than 1.0. The height of each respective first and second high aspect ratio voltage rail is greater than each respective width. Employing the first and second high aspect ratio voltage rails allows each to have a cross-sectional area that limits the resistance and corresponding IR drop.

Abstract: A fan-out semiconductor package includes a first connection member having a through-hole, a semiconductor chip disposed in the through-hole, a first encapsulant encapsulating at least portions of the first connection member and the semiconductor chip, a second connection member disposed on the first connection member and the semiconductor chip. The first connection member and the second connection member respectively include redistribution layers electrically connected to the connection pads of the semiconductor chip. The fan-out semiconductor package may have excellent rigidity, may be thinned, and may be manufactured in a simplified process.

Abstract: A static random access memory (SRAM) device includes an inverter including a ninth first-conductivity-type semiconductor layer formed on a semiconductor substrate; a first pillar-shaped semiconductor layer which is formed on the semiconductor substrate and in which a first first-conductivity-type semiconductor layer, a first body region, a second first-conductivity-type semiconductor layer, a first second-conductivity-type semiconductor layer, a second body region, and a second second-conductivity-type semiconductor layer are formed from the substrate side in that order; a first gate insulating film formed around the first body region; a first gate formed around the first gate insulating film; a second gate insulating film formed around the second body region; a second gate formed around the second gate insulating film; and a first output terminal connected to the second first-conductivity-type semiconductor layer and the first second-conductivity-type semiconductor layer.

Abstract: A semiconductor devices and methods of forming the same include forming a layer of activating material on sidewalls of a stack of alternating layers of channel material and sacrificial material. The layer of activating material is annealed to cause the activating material to react with the sacrificial material and to form insulating spacers at ends of the layers of sacrificial material. The layer of activating material is etched away to expose ends of the layers of channel material. Source/drain regions are formed on the ends of the layers of channel material.

Abstract: A method for fabricating 3-D cross-point memory arrays, and more particularly to fabricating phase change memory (PCM) and resistive RAM (ReRAM or RRAM) 3-D memory arrays having a cell size footprint of 4F2. The method for forming a plurality of layers of memory cells using a limited number of photolithographic patterning steps is applicable to memory devices having single or multiple storage bits per cell, such as cells having anywhere from one to eight bits per cell or more. These bits are stacked three dimensionally and include memory cells based on phase change material, on resistive change material, on magnetic field alignment, on mechanical switching, and on other memory cells based on other information storage technologies.

Abstract: The present invention provides a field effect transistor and the method for preparing such a filed effect transistor. The filed effect transistor comprises a semiconductor, germanium nanowires, a first III-V compound layer surrounding the germanium nanowires, a semiconductor barrier layer, a gate dielectric layer and a gate electrode sequentially formed surrounding the first III-V compound layer, and source/drain electrodes are respectively located at each side of the gate electrode and on the first III-V compound layer. According to the present invention, the band width of the barrier layer is greater than that of the first III-V compound layer, and the band curvatures of the barrier layer and the first III-V compound layer are different, therefore, a two-dimensional electron gas (2DEG) is formed in the first III-V compound layer near the barrier layer boundary. Since the 2DEG has higher mobility, the performance of the filed effect transistor improved.

Abstract: There is proposed a method and corresponding apparatuses allowing a change from a packet switched communication domain to a circuit switched communication domain. When a user equipment as a connection terminating point receives a connection initialization message with a media flow, such as audio, which cannot be delivered by the packet switched access, it sends a specific response rejecting the connection via the packet switched access to an application server for service centralization and continuity. In the application server, it is checked whether several conditions are met in order to determine whether the communication connection comprising the media flow is allowed to be changed to the circuit switched domain. If yes, the communication connection is changed from the packet switched communication domain to the circuit switched communication domain.

Abstract: A semiconductor device may include the following elements: a semiconductor substrate, an insulator positioned on the substrate, a source electrode positioned on the insulator, a drain electrode positioned on the insulator, a gate electrode positioned between the source electrode and the drain electrode, a hollow channel surrounded by the gate electrode and positioned between the source electrode and the drain electrode, a dielectric member positioned between the hollow channel and the gate electrode, a first insulating member positioned between the gate electrode and the source electrode, and a second insulating member positioned between the gate electrode and the drain electrode.

Abstract: A method of manufacturing a nanowire device is disclosed. The method includes providing a substrate, wherein the substrate comprises a pair of support pads, a recess disposed between the support pads, a second insulating layer disposed on the support pads, a third insulating layer disposed on a bottom of the recess, and at least one nanowire suspended between the support pads at a top portion of the recess; forming a first insulating layer on the nanowire; depositing a dummy gate material over the substrate on the first insulating layer, and patterning the dummy gate material to form a dummy gate structure surrounding a channel region; forming a first oxide layer on laterally opposite sidewalls of the dummy gate; and extending the nanowire on laterally opposite ends of the channel region to the respective support pads, so as to form a source region and a drain region.

Abstract: If the shape of an element substrate is a parallelogram, a trapezoid, an uneven shape, or the like, there is no region where a driver transistor corresponding to a heater in the vicinity of an end portion of the element substrate is arranged, and thus the heater cannot be arranged near the end portion. The layout arrangement of driving circuits suitable for the substrate shape is required while suppressing an increase in the area of the element substrate. In an embodiment of this invention, the diffusion layer of the drain electrode of a driver transistor for driving a heater is divided in a direction perpendicular to that in which heaters are arranged, and the divided portions are connected to form one driver transistor. The divided portions are arranged stepwise.

Abstract: An alternating stack of layers of a first epitaxial semiconductor material and a second epitaxial semiconductor material is formed on a substrate. A fin stack is formed by patterning the alternating stack into a shape of a fin having a parallel pair of vertical sidewalls. After formation of a disposable gate structure and an optional gate spacer, raised active regions can be formed on end portions of the fin stack. A planarization dielectric layer is formed, and the disposable gate structure is subsequently removed to form a gate cavity. A crystallographic etch is performed on the first epitaxial semiconductor material to form vertically separated pairs of an upright triangular semiconductor nanowire and an inverted triangular semiconductor nanowire. Portions of the epitaxial disposable material are subsequently removed. After an optional anneal, the gate cavity is filled with a gate dielectric and a gate electrode to form a field effect transistor.

Abstract: For fabrication of a semiconductor structure, there is set forth herein a method of fabricating a semiconductor structure, the method including forming a multilayer structure, the multilayer structure having a bulk substrate, a first layer defining an ultrathin body spaced apart from the bulk substrate, and a second layer above the first layer having material for defining a fin, and patterning the second layer to define a fin above the ultrathin body.

Abstract: A crack-stopping structure includes a semiconductor wafer comprising a plurality of dies defined by a plurality of scribe line regions, a plurality of metal patterns formed in the scribe line regions, and a plurality of groups of through silicon holes (TSHs) formed in the scribe line regions. The wafer further includes a front side and a back side, and the TSHs respectively include at least a bottom opening formed in the bottom side of the wafer. The groups of TSHs are formed between the metal patterns and the dies.

Abstract: According to one embodiment, a semiconductor device includes a transistor formed on a semiconductor chip, a lower-layer wiring connected to a diffusion layer of the transistor, and drawn outside the diffusion layer, and an upper-layer wiring drawn out from a pad electrode formed on the semiconductor chip, connected to the lower-layer wiring, and having resistivity lower than that of the lower-layer wiring.

Abstract: A semiconductor die has active circuits formed on its active surface. Contact pads are formed on the active surface of the semiconductor die and coupled to the active circuits. A die extension region is formed around a periphery of the semiconductor die. Conductive THVs are formed in the die extension region. A wafer level conductive plane or ring is formed on a center area of the active surface. The conductive plane or ring is connected to a first contact pad to provide a first power supply potential to the active circuits, and is electrically connected to a first conductive THV. A conductive ring is formed partially around a perimeter of the conductive plane or ring and connected to a second contact pad for providing a second power supply potential to the active circuits. The conductive ring is electrically connected to a second THV.

Abstract: Disclosed herein is an imaging device including at least one special pixel with a configuration having a layout made different from the layout of the configuration of each pixel other than the special pixel. The special pixel is a pixel having an imaging characteristic steadily different from that of the other pixels. A difference in layout between the configuration of the special pixel and the configuration of the other pixels is used to suppress a non-uniformity of the imaging characteristic exhibited by the special pixel.

Abstract: A semiconductor device is disclosed to include a plurality of cells. Each of the cells has a respective outer cell boundary defined to circumscribe the cell in an orthogonal manner. Also, each of the cells includes circuitry for performing one or more logic functions. This circuitry includes a plurality of conductive features defined in one or more levels of the cell. One or more of the conductive features in at least one level of a given cell is an encroaching feature positioned to encroach by an encroachment distance into an exclusion zone. The exclusion zone occupies an area within the cell defined by an exclusion distance extending perpendicularly inward into the given cell from a first segment of the outer cell boundary. The exclusion distance is based on a design rule distance representing a minimum separation distance required between conductive features in adjacently placed cells on the semiconductor device.

Abstract: A semiconductor integrated circuit includes a plurality of memory cells arranged in a cell-placement row extending in a first direction, a first N well and a first P well arranged in a second direction perpendicular to the first direction in each area of the memory cells, and a second N well and a second P well each having the same length as a width of the cell-placement row and situated between at least two adjacent memory cells of the plurality of memory cells, wherein the first N well and the second N well are integrated, and the first P well and the second P well are integrated.

Abstract: A method for forming a semiconductor device with a vertical gate is disclosed, including providing a substrate, forming a recess in the substrate, forming a gate dielectric layer on a sidewall and a bottom of the recess, forming an adhesion layer in the recess and on the gate dielectric layer, wherein the adhesion layer is a metal silicide nitride layer, and forming a gate layer in the recess and on the adhesion layer.

Abstract: An object is to provide a display device with a high aperture ratio or a semiconductor device in which the area of an element is large. A channel formation region of a TFT with a multi-gate structure is provided under a wiring that is provided between adjacent pixel electrodes (or electrodes of an element). In addition, a channel width direction of each of a plurality of channel formation regions is parallel to a longitudinal direction of the pixel electrode. In addition, when a channel width is longer than a channel length, the area of the channel formation region can be increased.

Abstract: A multi-field effect transistor (FET) device includes a first FET device arranged on a substrate, the first FET device including a first active region and a second active region, a second FET device arranged on the substrate, the second FET device including a first active region and a second active region, and a first conductive interconnect electrically connecting the first active region of the first FET device to the first active region of the second FET device, the first conductive interconnect having a first cross sectional area proximate to the first active region of the first FET device that is greater than a second cross sectional area proximate to the first active region of the second FET device.

Abstract: A semiconductor structure includes first and second chips assembled to each other. The first chip includes N of first conductive lines, M of second conductive lines disposed on the first conductive lines, N of third conductive lines perpendicularly on the second conductive lines and parallel to the first conductive lines, N of first vias connected to the first conductive lines, M sets of second vias connected to the second conductive lines, and N sets of third vias connected to the third conductive lines. The second and first conductive lines form an overlapping area. The third conductive lines and N sets of the third vias include at least two groups respectively disposed in a first and a third regions of the overlapping area. M sets of second vias include at least two groups respectively disposed in a second region and a fourth region of the overlapping area.