Abstract: The present invention provides a fundamental cell, semiconductor integrated circuit device, wiring method and wiring apparatus for designing a layout of a functional circuit block or a semiconductor integrated circuit device using the fundamental cells, with a higher degree of freedom of wirings. The connection terminals 2 and 3 of the fundamental cell 1 are terminals for supplying the power source voltage VDD and ground potential VSS to the N and P type wells. The terminals may be defined as a contact structure between a metal layer and N and P type well areas, and alternatively defined as stacked VIA structure for multilayered metal wiring layers and N and P type well areas if desired in correspondence with the manufacturing process used for manufacturing the semiconductor integrated circuit device implementing the fundamental cell 1. The fundamental cell 1 has neither the connection terminals 2 and 3, nor the power source voltage VDD and ground potential VSS to those two PMOS and NMOS transistors.

Abstract: A plurality of gate lines formed on an insulating substrate, each gate line including a pad for connection to an external device; a plurality of data lines intersecting the gate lines and insulated from the gate lines, each data line including a pad for connection to an external device; and a conductor overlapping at least one of the gate lines and the data lines are included. An overlapping distance of the gate lines or the data lines and a width of the conductor decreases as the length of the gate lines or the data lines increases. Accordingly, the difference in the RC delays due to the difference of the length of the signal lines is compensated to be reduced.

Abstract: A semiconductor test chip including a plurality of test functions. The test functions of the semiconductor test chip include bond pad pitch and size effects on chip design, wire bond placement accuracy regarding placement of the wire bond on the bond pad, evaluation of bond pad damage (cratering) effect on the area of the chip below the bond pad during bonding of the wire on the bond pad, street width effects regarding the use of thinner saw cuts in cutting the individual chips from the wafer, thermal impedance effects for thermal testing capabilities, ion mobility evaluation capabilities and chip on board in flip chip application test capabilities.

Abstract: A very efficient gate array core cell in which the base core cell consists of a group of 6 PMOS transistors and a group of 6 NMOS transistors. It also includes pre-wiring of 2 of the 6 PMOS transistors, with 2 of the 6 NMOS transistors at polysilicon level or at local interconnect level while leaving the remaining PMOS and NMOS transistors as individual transistors to be interconnected during the functional ASIC metallization process. The core cell also has 2 polysilicon or local interconnect wires embedded in it, which can be used to interconnect transistors for logic function implementation. The core cell defined in this invention is highly flexible and has been analyzed to interconnect all types of logic and memory functions needed for ASIC designs. The layout of the transistors, pre-wiring of the strategic transistors at polysilicon level or at local interconnect level, and embedded polysilicon or local interconnect wires reduce the core cell size significantly.

Abstract: An integrated circuit interconnect is provided having a dielectric layer disposed between a wide top metal line and a wide bottom metal line. A via-sea in the dielectric layer connects the wide top and wide bottom metal lines by means of a first via having a width, a second via having a width and spaced more than two widths away and less than four widths away from the first via.

Abstract: A semiconductor integrated circuit device has: a semiconductor substrate defining a plurality of rows, each row including areas for a sequence of cells; a plurality of active regions disposed in each of the rows constituting semiconductor elements of associated cells; and a wiring region of stripe shape elongated along a direction of row, defined on the semiconductor substrate outside of the active regions in each row, and including wirings belonging to the associated cells, each wiring region having height in a direction crossing the row direction, the wiring region having locally different height.

Abstract: Bit lines are arranged with minimum width and minimum space in a chip, and each bit line is given a maximum of first potential difference. The minimum space is the value which will not make a line short-circuit in a line due to dielectric strength, when the first potential difference is applied across the bit lines. This value may be the design rule or the minimum dimensions capable of being processed by lithography. A second potential difference lager than the first potential difference is applied across a shielded power line and the bit lines. The shielded power line is not adjacent to the bit lines in the wiring width direction in the area where the bit lines are arranged with the minimum space.

Abstract: There is provided a semiconductor integrated circuit device which has realized high speed operation, high integration density and highly efficient layout of the RAM macro, in which a memory array which is divided into four sections in the X and Y coordinates directions is disposed, a first input circuit for receiving a signal which requires optimization for a signal delay is disposed to the center of such four memory arrays, a second input circuit for receiving a data input and control signals thereof is disposed to the center of Y coordinate corresponding to the extending direction of the word line and a signal line for transferring an input signal from the external circuit of the RAM macro to the first and second input circuits is formed using an upper layer wiring for the wiring to form the memory array.

Abstract: A semiconductor device includes an SRAM section and a logic circuit section formed on a single semiconductor substrate. First and second gate electrode layers located in a first conductive layer, first and second drain-drain contact layers located in a second conductive layer, first and second drain-gate contact layers located in a third conductive layer become conductive layers for forming a flip-flop of the SRAM section. The logic circuit section has no wiring layer at the same level as the first and second drain-drain contact layers.

Abstract: In a method of manufacturing a semiconductor device comprising: having a first wiring extending in a first direction; and a second wiring connected to the first wiring through a connection and extending in a second direction orthogonal to the first direction, the second wiring having a surplus portion projecting from the connection in a direction opposite to the second direction, the first and second wirings are arranged such that a center of the connection is offset in the second direction from a center of the first wiring, and a projecting portion of the first wiring is disposed under the connection.

Abstract: An interconnect bus for a microelectromechanical system is disclosed. Various attributes for an electrical trace bus that facilitate the routing of signals throughout at least a portion of the system and/or the layout of the microelectromechanical system on a wafer are disclosed.

Abstract: The present invention discloses a semiconductor memory device having a bit line and a metal contact stud, wherein the metal contact stud is formed on a different layer from a layer on which the bit lines are formed.

Abstract: A novel bi-level DRAM architecture is described which achieves significant reductions in die size while maintaining the noise performance of traditional folded architectures. Die size reduction results primarily by building the memory arrays with 6F2 or smaller memory cells in a type of cross-point memory cell layout. The memory arrays utilize stacked digitlines and vertical digitline twisting to achieve folded architecture operation and noise performance.

Abstract: Disclosed herewith is a semiconductor device improved to prevent withstand voltage defects that might occur in each MOSFET used therein and a system to be designed easily and prevented from withstand voltage defects that might occur in each semiconductor used therein. The system includes the first and second input circuits, each being constituted by MOSFETs manufactured in the same process. The first input circuit receives a voltage of a first signal inputted from a first external terminal and divided by first and second resistor means while the AC component of the input signal is transmitted to the input circuit through a capacitor disposed in parallel to the first resistor means. The second input circuit receives a second input signal inputted from a second external terminal and reduced in signal amplitude so as to become smaller than that of the first input signal.

Abstract: A semiconductor device having at least two layers formed on a semiconductor substrate includes a first dielectric layer formed on the semiconductor substrate; a first interconnection layer which is formed on the first dielectric layer and has a first interconnection pattern and a dummy pattern formed around the first interconnection pattern; a second dielectric layer formed on the first interconnection layer; and a second interconnection layer which is formed on the second dielectric layer and has a second interconnection pattern. The dummy pattern is placed in the vicinity of only an area where the first and second interconnection patterns are superposed on each other.

Abstract: In a semiconductor integrated circuit having a functional macro, plural first and second power lines extending over the functional macro and supplying first-level and second-level voltages respectively to the functional macro are electrically connected through plural first and second power terminal patterns to plural third and fourth power lines extending over the semiconductor integrated circuit in the second direction and supplying the first-level and second-level voltages respectively to the semiconductor integrated circuit.

Abstract: Bit lines are arranged with minimum width and minimum space in a chip, and each bit line is given a maximum of first potential difference. The minimum space is the value which will not make a line short-circuit in a line due to dielectric strength, when the first potential difference is applied across the bit lines. This value may be the design rule or the minimum dimensions capable of being processed by lithography. A second potential difference lager than the first potential difference is applied across a shielded power line and the bit lines. The shielded power line is not adjacent to the bit lines in the wiring width direction in the area where the bit lines are arranged with the minimum space.

Abstract: A new method is provided that allows placing or stacking staggered bond I/O buffers into linear bond I/O buffers. The bond pads are linearly arranged, the interface between the staggered bond pad I/O buffers and the linearly arranged bond pads is achieved by a frame design that sequentially connects the staggered bond pad I/O buffers to the linearly arranged bond pads.

Abstract: A semiconductor switching device of mirror logic includes two FETs having a gate width of 600 &mgr;m, a common input terminal, two control terminal and two output terminals. The resistors connecting the control terminals and the gate electrodes of FETs are placed underneath a pad metal layer extending from the common input terminal. Both FETs extend into the space between the control terminals and the output terminals. The device can be housed in the same package as the device of non-mirror logic.

Abstract: A unit cell is disclosed that facilitates the creation of a layout of at least a portion of a microelectromechanical system. The unit cell includes a plurality of electrical traces. Some of these electrical traces pass through the unit cell. Other electrical traces extend only part way through the unit cell. At least certain boundary conditions exist for the unit cell that allow the same to be tiled in a row and in a manner that results in adjacently disposed unit cells in the row being electrically interconnected in the desired manner.

Abstract: A semiconductor chip has standard cells which are disposed in a plurality of mutually adjacent rows, wiring channels are disposed between the rows and at at least one location along at least one wiring channel, the width of the wiring channel determined by a prescribed unambiguous and variable assignment specification. The width of the wiring channels can thus be varied in a flexible manner, so that a circuit can be fabricated in a space-saving manner.

Abstract: A semiconductor memory device assembled in a flip chip package includes a memory cell array divided into subarrays arranged in matrix form, and a peripheral circuit area and a pad area formed in middle sections of the subarray matrix. The pad area includes pads arranged at the same pitches as those of the subarrays, and a signal connecting the peripheral circuit area and each of the subarrays is linearly formed so as to pass between the pads. The variations of delay time of signals supplied to the subarrays are avoided and the transmission time of signals is kept constant, thereby achieving a high-speed operation.

Abstract: In a bit line contact section, a contact hole is formed through a silicon oxide film, and a contact plug made of a polysilicon film doped with impurities is buried in the contact hole. The silicon oxide film is formed with a wiring groove overlapping the contact hole. A bit line made of a metal film is buried in the wiring groove. The contact plug extends through the bit line, and has its upper surface substantially coplanar with an upper surface of the bit line. The contact plug is in contact with the bit line only on its side surfaces.

Abstract: A base cell is configured such that P-type regions 11 to 13 are arrayed in a column direction in an N-type well 10, N-type regions 21 to 23 are arrayed in a column direction in a P-type well 20 next to the N-type well, gate lines 34A and 35B passing above a channel between the P-type regions and further between the N-type regions are formed in a row direction, and well contact regions 16C and 26C are formed in the wells 10 and 20 at outer ends thereof, respectively, while no gate contacts are formed at the outer ends. Power supply lines VDD and VSS connected to the well contact regions are formed in the column direction in a second wiring layer above a first wiring layer.

Abstract: The invention provides a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each having a first, second, third, fourth, fifth, and sixth transistors. While each of channels of the first, second, third, and fourth transistors are formed vertical against a substrate of the semiconductor memory device. Each of semiconductor regions forming a source or a drain of the fifth and sixth transistors forms a PN junction against the substrate. According to another aspect of the invention, the SRAM device of the invention has a plurality of SRAM cells, at least one of which is a vertical SRAM cell comprising at least four vertical transistors onto a substrate, and each vertical transistor includes a source, a drain, and a channel therebetween aligning in one aligning line which penetrates into the substrate surface at an angle greater than zero degree.

Abstract: An array of memory cells includes a plurality of memory cells interconnected via a grid of M wordlines and M bitlines, wherein M=2, 3, 4, 5, . . . wherein each of the M bitlines is buried. The array further includes a plurality of contacts, wherein each of the plurality of contacts is formed every N wordlines, N=1, 2, 3, . . . , wherein each of the plurality of contacts overlies a gate of a different one of the plurality of memory cells. A strap connects one of the buried bitlines to a gate that underlies one of the plurality of contacts, and wherein contacts overlying a first bit line are staggered with respect to contacts overlying a second bit line that is adjacent to the first bit line.

Abstract: A novel bi-level DRAM architecture is described which achieves significant reductions in die size while maintaining the noise performance of traditional folded architectures. Die size reduction results primarily by building the memory arrays with 6F2 or smaller memory cells in a type of cross point memory cell layout. The memory arrays utilize stacked digitlines and vertical digitline twisting to achieve folded architecture operation and noise performance.

Abstract: A layout structure of a semiconductor memory device having a memory cell array region, a word line drive region proximate the memory cell array, a bit line equalization region spaced apart from the memory cell array region, an impurity region formed between the memory cell array region and the bit line equalization region electrically coupled to the bit line equalization region, and a metal line supplying a bit line equalization voltage to the impurity region, wherein a contact connecting the metal line and the impurity region is formed lateral to the word line drive region rather than between the memory cell array region and the bit line equalization region, so that no contacts are formed directly between the memory cell array region and the bit line equalization region.

Abstract: A memory array including a bit cell row, a strap cell row, a first power supply line, and a first offset supply line is provided. The bit cell row may include a bit cell that includes a first transistor disposed in a first bit cell body region. The first transistor may include a first active region. The strap cell row may include a strap cell that includes a first strap cell body region. The first strap cell body region may be conductively coupled to the first bit cell body region. The first power supply line may be electrically coupled to the first active region and may provide a first supply voltage potential to the first active region. The first offset supply line may be electrically coupled to the first strap cell body region and may provide a first offset voltage potential to the first bit cell body region via the first strap cell body region. The first supply voltage potential is operable to be different from the first offset voltage potential.

Abstract: A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has a plurality of contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.

Abstract: A semiconductor switching device includes two FETs with different device characteristics, a common input terminal, and two output terminals. A signal transmitting FET has a gate width of 500 &mgr;m and a signal receiving FET has a gate width of 400 &mgr;m. A resistor connecting a gate electrode and a control terminal of the signal transmitting FET is tightly configured to provide expanding space for the FET. Despite the reduced size, the switching device can allow a maximum power of 22.5 dBm to pass through because of the asymmetrical device design. The switching device operates at frequencies of 2.4 GHz or higher without use of shunt FET.

Abstract: Concave portions and convex portions are formed on an insulating layer. First bit lines are arranged on the convex portions. A width of the first bit lines is set to L, and a space between the first bit lines is set to L+2S. Each of the first bit lines is electrically connected to a drain diffusion layer by a contact plug. Second bit lines are arranged in a trench between the first bit lines. A width of the second bit lines is set to L, and a space between the first and second bit lines is equal to a width S of a side wall. Each of the second bit lines is electrically connected to a drain diffusion layer by a contact plug.

Abstract: A transistor 28a including a first gate electrode 26 is formed on a substrate 10 through a gate insulation film 24. An insulation film 30 is formed on the transistor 28a and the substrate 10. A plurality of first wirings 40a, 40b are formed on the insulation film 30, spaced from each other by a first gap d1. A second wiring 42 is formed, spaced from either of the first wiring 40a, 40b by a second gap d2 which is substantially equal to the first gap d1. Either of the first wirings 40a, 40b is electrically connected to the first gate electrode 26, and the second wiring 42 is electrically connected to the substrate 10.

Abstract: A method for measuring bridge induced by mask layout amendment. Provide a mask with a layout that comprises a conductor line pattern, numerous gate patterns which are connected with conductor line pattern, and numerous contact pattern groups, each contact pattern group has numerous contact patterns and at least surrounds one terminal, which does not contact with conductor line, of one corresponding gate pattern. Then, amend this layout and transfer amended layout into a substrate to form a conductor line, numerous gates and numerous contact groups in and on this substrate. Finally, electrically couple these contact groups with a terminal, then, apply an electrical signal into this conductor line and measure whether the electrical signal appears at this terminal.

Abstract: A semiconductor test chip including a plurality of test functions. The test functions of the semiconductor test chip include bond pad pitch and size effects on chip design, wire bond placement accuracy regarding placement of the wire bond on the bond pad, evaluation of bond pad damage (cratering) effect on the area of the chip below the bond pad during bonding of the wire on the bond pad, street width effects regarding the use of thinner saw cuts in cutting the individual chips from the wafer, thermal impedance effects for thermal testing capabilities, ion mobility evaluation capabilities and chip on board in flip chip application test capabilities.

Abstract: A semiconductor integrated circuit device comprises vertical power supply wiring 12 divided into first and second narrow-width vertical power supply wirings 12a and 12b, vertical ground wiring 14 disposed in parallel with vertical power supply wiring 12 and divided into first and second narrow-width vertical ground wirings 14a and 14b, auxiliary vertical power supply wiring 22 connecting first narrow-width vertical power supply wiring 12a and second narrow-width vertical power supply wiring 12b, and auxiliary vertical ground wiring 24 connecting first narrow-width vertical ground wiring 14a and second narrow-width vertical ground wiring 14b.

Abstract: A basic cell is disclosed, which is small in area and has sufficient connection flexibility. for achieving a semiconductor integrated circuit with a higher density and a reduced manufacturing cost. In a basic cell, a terminal wire, which is connected to a transistor terminal with a contact, is placed in a first metal wiring layer, and a plurality of terminal wire connection points, which can be connected to a second metal wire through a first via, are provided on the terminal wire. Further, in a semiconductor integrated circuit, a circuit wire in a second metal wiring layer is placed along grid points with a fixed pitch, and is connected to a terminal connection point of a transistor terminal, which is displaced from the grid points, through a terminal wire provided in the first metal wiring layer.

Abstract: In a semiconductor storage device, a line of lower-side backing wiring is provided on a line of gate wiring via an insulation layer, and a line of upper-side backing wiring is provided further on the top layer thereof via another insulation layer. Contacts between the gate wiring and upper-side backing wiring are distributed and arranged on two or more different lines extending in a vertical direction with respect to a direction to which the gate wiring extends, and any contacts adjacent to each other of the contacts are arranged on different lines. The lower-side backing wiring passes through between the adjacent contacts.

Abstract: There is provided a semiconductor integrated circuit device which has realized high speed operation, high integration density and highly efficient layout of the RAM macro, in which a memory array which is divided into four sections in the X and Y coordinates directions is disposed, a first input circuit for receiving a signal which requires optimization for a signal delay is disposed to the center of such four memory arrays, a second input circuit for receiving a data input and control signals thereof is disposed to the center of Y coordinate corresponding to the extending direction of the word line and a signal line for transferring an input signal from the external circuit of the RAM macro to the first and second input circuits is formed using an upper layer wiring for the wiring to form the memory array.

Abstract: A shield portion 5 has such a multi-layer wiring construction comprised of three wiring layers as to correspond to a macro cell and also via contacts formed with a predetermined spacing therebetween and is supplied with a predetermined potential (for example, a ground potential) but not connected to a power wiring or a ground wiring in the macro cell. This configuration makes it possible to hold the wiring layers of the shield portion at roughly the same potential. Accordingly, noise originated from the wiring layer as a signal line is blocked in propagation by the shield portion and so does not affect a signal flowing through a wiring layer.

Abstract: The present invention relates to an improved memory circuit with a divided bit-line, shared sense amplifier architecture. In a conventional divided bit-line, shared sense amplifier configuration, two adjacent memory sub-arrays are generally located between two banks of sense amplifiers and selected bit lines of the two adjacent memory sub-arrays are generally connected to metal lines with metal contacts to reduce capacitive loading. Under the present invention, some sense amplifiers from either banks of sense amplifiers are repositioned to the area between the two adjacent memory sub-arrays thereby permitting the repositioned sense amplifiers to be shared. As a result, any two adjacent memory sub-arrays share a bank of sense amplifiers. Furthermore, selected bit lines from the two adjacent memory sub-arrays are coupled to metal lines within the repositioned sense amplifiers.

Abstract: A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has a plurality of contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.

Abstract: A novel bi-level DRAM architecture is described which achieves significant reductions in die size while maintaining the noise performance of traditional folded architectures. Die size reduction results primarily by building the memory arrays with 6F2 or smaller memory cells in a type of cross point memory cell layout. The memory arrays utilize stacked digitlines and vertical digitline twisting to achieve folded architecture operation and noise performance.

Abstract: A fuse array having a plurality of fusible links that can be addressed by two electrodes is disclosed. The fuse array includes two conductive strips having the plurality of fusible links located therebetween and electrically coupled to the conductive strips. The fusible links have different electrical resistance and each fusible link includes a fuse portion. A voltage potential applied across the conductive strips induces current flow through the fusible links in accordance with Ohm's law and ohmic heating occurs at the fuse portion in proportion to the square of the current. The voltage is increased to cause sufficient ohmic heating to occur in the most conductive fusible link (the fusible link having the lowest electrical resistance) so that the fuse portion in that fusible link fuses.

Abstract: A semiconductor element wherein only one of two mutually adjacent electrodes has a split pattern that is formed on the same layer as the other electrode. The split electrode is connected to a wiring layer provided on a separate layer. When the semiconductor element is a MOSFET, the mutually adjacent electrodes are provided on a source diffusion layer and a drain diffusion layer. Specifically, they serve as a source electrode and a drain electrode, respectively. The split electrode is connected to the source diffusion layer or drain diffusion layer through a single contact hole. This allows the parasitic capacitance in the semiconductor element region to be easily reduced even when the semiconductor element, such as a MOSFET, which comprises the semiconductor integrated circuit is miniaturized.

Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

Abstract: An object of the present invention is to provide a semiconductor device and a method of manufacturing the semiconductor device which can improve the flatness after the chemical mechanical polishing by inserting necessary and minimum dummy patterns and has high throughput.

Abstract: A method of routing power supply voltage electrodes and reference voltage electrodes which makes efficient use of chip area, maximizes decoupling capacitance, and reduces voltage drops due to electrode resistance is described. The two top wiring layers of an integrated circuit chip are used as power distribution layers to distribute the power supply voltage and reference voltage so that the power supply voltage bus electrode and reference voltage bus electrode are in separate wiring layers. The chip is partitioned into a number of sub-blocks with spaces between the sub-blocks. In a first wiring layer the power supply voltage bus electrode is routed so as to surround each of the sub-blocks. In a second wiring layer the reference voltage bus electrode is routed so as to surround each of the sub-blocks.

Abstract: A semiconductor device comprises a substrate having at least first, second and third metal layers formed over it. The metal layers comprise parallel strips. The strips of a given metal layer may be arranged such that they extend in a direction perpendicular to that of the direction in which the strips of a metal layer immediately above or below the given metal layer extend. The strips may further be arranged in parallel bands. The metal layers may comprise repeating patterns of strips. They may further provide customization. Vias may be formed to provide connections between metal layers. Such vias and/or one or more of the metal layers themselves may be used to provide customization.

Abstract: The memory cells are arranged to all intersections of the first word line and one line of the bit-line pair and all intersections of the second word line and the other line of the bit-line pair by arranging in parallel the first word line and the second word line consisting of different layers in the row direction with the identical pitch and also alternately arranging the first word line and the second word line at an interval equal to a half of the pitch in the horizontal direction. Moreover, the selection MISFET of the memory cell is formed in the vertical construction and the bit line located at the upper side of the substrate where a channel region is formed is shielded with a conductive film, a part of which forms the gate electrode.