With Particular Signal Path Connections Patents (Class 257/208)
  • Patent number: 10740530
    Abstract: Aspects of the present disclosure address systems and methods for shortening clock tree wirelength based on target offsets in connected routes. A method may include accessing a clock tree comprising routes that interconnect a plurality of pins. Each pin corresponds to a terminal of a clock tree instance. The method further includes identifying a first and second terminal of a clock tree instance in the clock tree. The method further includes determining a first offset based on a distance between the first terminal and a branch in a first route connected to the first terminal and determining a second offset based on a distance between the second terminal and a branch in a second route connected to the second terminal. The method further includes moving the clock tree instance from a first location to a second location based on a target offset determined by comparing the first and second offsets.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: August 11, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Andrew Mark Chapman, Zhuo Li
  • Patent number: 10707218
    Abstract: One illustrative device disclosed herein includes a first pull-up transistor positioned in a first P-type nano-sheet and a first pull-down transistor and a first pass gate transistor positioned in a first N-type nano-sheet. The device further includes a second pull-up transistor positioned in a second P-type nano-sheet and a second pull-down transistor and a second pass gate transistor positioned in a second N-type nano-sheet. The device further includes a read pull-down transistor and a read pass gate transistor positioned in a third N-type nano-sheet. The device also includes a first shared gate structure positioned adjacent the first pull-up transistor and the first pull-down transistor and a second shared gate structure positioned adjacent the second pull-up transistor, the second pull-down transistor and the read pull-down transistor.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: July 7, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Bipul C. Paul, Ruilong Xie
  • Patent number: 10672657
    Abstract: A method of forming a semiconductor device assembly comprises forming tiers comprising conductive structures and insulating structures in a stacked arrangement over a substrate. Portions of the tiers are selectively removed to form a stair step structure comprising a selected number of steps exhibiting different widths corresponding to variances in projected error associated with forming the steps. Contact structures are formed on the steps of the stair step structure. Semiconductor device structures and semiconductor devices are also described.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: June 2, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Matthew Park, Adam L. Olson, Jixin Yu
  • Patent number: 10672706
    Abstract: A semiconductor device includes a multilayer wiring structure on a substrate. The multilayer wiring structure includes: a top wiring; a fuse element, which is located on a lower layer-side of the top wiring, and is made of metal having a melting point that is higher than that of the top wiring; and a lower-layer wiring, which is connected to each of ends of the fuse element. Provided is a semiconductor device in which fuse elements made of the high-melting point metal are arranged at high density.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: June 2, 2020
    Assignee: ABLIC INC.
    Inventor: Yoshitaka Kimura
  • Patent number: 10541240
    Abstract: The semiconductor device includes a first inserter and a second inverter which is connected thereto in series. Each of the first and the second inserters includes a p-channel transistor and an n-channel transistor, respectively. The number of projection semiconductor layers each as the active region of the p-channel and the n-channel transistors of the second inverter is smaller than the number of the projection semiconductor layers each as the active region of the p-channel and the n-channel transistors of the first inverter.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: January 21, 2020
    Assignee: Renesas Electronics Corporation
    Inventor: Takeshi Okagaki
  • Patent number: 10535710
    Abstract: Some embodiments include a method of forming integrated circuitry. A structure has first conductive lines over a dielectric bonding region, has semiconductor material pillars extending upwardly from the first conductive lines, and has second conductive lines over the first conductive lines and extending along sidewalls of the semiconductor material pillars. The first conductive lines extend along a first direction, and the second conductive lines extend along a second direction which intersects the first direction. The structure includes semiconductor material under the dielectric bonding region. Memory structures are formed over the semiconductor material pillars. The memory structures are within a memory array. Third conductive lines are formed over the memory structures. The third conductive lines extend along the first direction. Individual memory structures of the memory array are uniquely addressed through combinations of the first, second and third conductive lines.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: January 14, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Mitsunari Sukekawa
  • Patent number: 10522469
    Abstract: A first metal layer of a semiconductor device includes a plurality of first metal lines that each extend along a first axis, and a first rail structure that extends along the first axis. The first rail structure is physically separated from the first metal lines. A second metal layer is located over the first metal layer. The second metal layer includes a plurality of second metal lines that each extend along a second axis orthogonal to the first axis, and a second rail structure that extends along the first axis. The second rail structure is physically separated from the second metal lines. The second rail structure is located directly over the first rail structure. A plurality of vias is located between the first metal layer and the second metal layer. A subset of the vias electrically interconnects the first rail structure to the second rail structure.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Tien Wu, Hsiang-Wei Liu, Wei-Chen Chu
  • Patent number: 10497633
    Abstract: The present invention provides electronic systems, including device arrays, comprising functional device(s) and/or device component(s) at least partially enclosed via one or more fluid containment chambers, such that the device(s) and/or device component(s) are at least partially, and optionally entirely, immersed in a containment fluid. Useful containment fluids for use in fluid containment chambers of electronic devices of the invention include lubricants, electrolytes and/or electronically resistive fluids. In some embodiments, for example, electronic systems of the invention comprise one or more electronic devices and/or device components provided in free-standing and/or tethered configurations that decouple forces originating upon deformation, stretching or compression of a supporting substrate from the free standing or tethered device or device component.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 3, 2019
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: John A. Rogers, Sheng Xu, Jonathan A. Fan, Lin Jia
  • Patent number: 10483125
    Abstract: A semiconductor device includes a first interlayer film formed on an upper surface of a substrate, a first metal wiring line, a second interlayer film, a second metal wiring line, a first via electrically connecting the first metal wiring line and the second metal wiring line, a landing pad embedded in an upper portion of the first interlayer film and penetrating the second interlayer film, and a second via penetrating the substrate and the first interlayer film from a back side of the substrate and connected to the landing pad. The lower surface position of the landing pad is different from that of the first metal wiring line.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: November 19, 2019
    Assignee: TOWERJAZZ PANASONIC SEMICONDUCTOR CO., LTD.
    Inventors: Yuka Inoue, Mitsunori Fukura, Nobuyoshi Takahashi, Masahiro Oda, Hisashi Yano, Yutaka Ito, Yasunori Morinaga
  • Patent number: 10481203
    Abstract: In one embodiment, a system comprises: a global clock input for receiving a global clock, a plurality of partitions; and a skew tolerant interface configured to compensate for clock skew differences between a global clock from outside at least one of the partitions and a balanced local clock within at least one of the partitions. The partitions can be test partitions. The skew tolerant interface can cross a mesochronous boundary. In one exemplary implementation, the skew tolerant interface includes a deskew ring buffer on communication path of the at least one partition. pointers associated with the ring buffer can be free-running and depend only on clocks being pulsed when out of reset. The scheme can be fully synchronous and deterministic. The scheme can be modeled for the ATPG tools using simple pipeline flops. The depth of the pipeline can be dependent on the pointer difference for the read/write interface. The global clock input can be part of a scan link.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: November 19, 2019
    Assignee: Nvidia Corporation
    Inventors: Shantanu Sarangi, Milind Sonawane, Adarsh Kalliat Balagopala, Amit Sanghani
  • Patent number: 10446536
    Abstract: A cell circuit and corresponding layout is disclosed to include linear-shaped diffusion fins defined to extend over a substrate in a first direction so as to extend parallel to each other. Each of the linear-shaped diffusion fins is defined to project upward from the substrate along their extent in the first direction. A number of gate level structures are defined to extend in a conformal manner over some of the number of linear-shaped diffusion fins. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins extend in a second direction that is substantially perpendicular to the first direction. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins form gate electrodes of a corresponding transistor. The diffusion fins and gate level structures can be placed in accordance with a diffusion fin virtual grate and a gate level virtual grate, respectively.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: October 15, 2019
    Assignee: Tela Innovations, Inc.
    Inventor: Scott T. Becker
  • Patent number: 10423026
    Abstract: An array substrate, a display panel and a display device. The array substrate includes a base substrate including a plurality of pixel areas and a first data line on the base substrate and between adjacent pixel areas; a side slope angle of the first data line is not greater than about 60°.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: September 24, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Yujie Gao
  • Patent number: 10403442
    Abstract: The present invention generally relates to a MEMS DVC having a shielding electrode structure between the RF electrode and one or more other electrodes that cause a plate to move. The shielding electrode structure may be grounded and, in essence, block or shield the RF electrode from the one or more electrodes that cause the plate to move. By shielding the RF electrode, coupling of the RF electrode to the one or more electrodes that cause the plate to move is reduced and capacitance modulation is reduced or even eliminated.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: September 3, 2019
    Assignee: CAVENDISH KINETICS, INC.
    Inventors: Robertus Petrus Van Kampen, Ramadan A. Alhalabi
  • Patent number: 10388606
    Abstract: Some embodiments include a method of forming an integrated assembly. Conductive lines are formed to extend along a first direction, and are spaced from one another by a first pitch. Protective knobs are formed over the conductive lines and are arranged in rows. The protective knobs within each row are spaced along a second pitch which is greater than the first pitch. The protective knobs protect regions of the conductive lines while leaving other regions of the conductive lines unprotected. The unprotected regions are recessed so that the protected regions become tall regions and the unprotected regions become short regions. The protective knobs are removed. Conductive structures are formed over the conductive lines. The conductive structures are spaced along the second pitch. Each of the conductive lines is uniquely coupled to only one of the conductive structures. Some embodiments include integrated assemblies.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: August 20, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 10366913
    Abstract: A method for manufacturing a semiconductor element includes forming a first region in a semiconductor region by ion-implanting impurities using a first mask; forming an interconnect including a gate portion extending in a first direction over the first region; and forming a source/drain region by ion-implanting impurities into a second region. A gate threshold voltage of the semiconductor element has first to third correlations dependent respectively on distances between an inner wall of the first mask and an outer edge of the second region, between the gate portion and the outer edge of the second region and between the outer edge of the second portion and a portion of the interconnect other than the gate portion. At least one of the distances is determined based on the first to third correlations to obtain a prescribed gate threshold voltage of the semiconductor element.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: July 30, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masafumi Hamaguchi
  • Patent number: 10340348
    Abstract: A semiconductor device includes a fin structure, first and second gate structures, a source/drain region, a source/drain contact layer and a separation layer. The fin structure protrudes from an isolation insulating layer disposed over a substrate and extends in a first direction. The first and second gate structures are formed over the fin structure and extend in a second direction crossing the first direction. The source/drain region is disposed between the first and second gate structures. The interlayer insulating layer is disposed over the fin structure, the first and second gate structures and the source/drain region. The first source/drain contact layer is disposed on the first source/drain region. The separation layer is disposed adjacent to the first source/drain contact layer. Ends of the first and second gate structures and an end of the source drain contact layer are in contact with a same face of the separation layer.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: July 2, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Jyun Huang, Tung-Heng Hsieh, Bao-Ru Young
  • Patent number: 10297587
    Abstract: An integrated circuit is provided. In one implementation, the integrated circuit includes a first standard cell, comprising at least one first PMOS transistor disposed in a first row in a semiconductor substrate and at least one first NMOS transistor disposed in a first area of a second row in the semiconductor substrate, and a second standard cell, comprising a plurality of second PMOS transistors disposed in the first row and a third row in the semiconductor substrate and a plurality of second NMOS transistors disposed in a second area of the second row in the semiconductor substrate, wherein the second row is adjacent to the first and third rows and arranged between the first and third rows.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: May 21, 2019
    Assignee: MEDIATEK INC.
    Inventor: Jen-Hang Yang
  • Patent number: 10290626
    Abstract: Methods of integrating a HV ESD PNP bipolar transistor in a VFET process and the resulting devices are provided. Embodiments include forming a DNW region in a portion of a p-sub; forming a HVPDDD region in a portion of the DNW region; forming a first and a second NW in a portion of the DNW region, the second NW between the first NW and the HVPDDD region and laterally separated from the HVPDDD region; forming a PW in a portion of the HVPDDD region; forming an N+ implant in a portion of the first NW and a P+ implant in a portion of the PW; forming a first, a second and a third fin structures over the first and the second NW and the PW, respectively; and forming a N+ S/D, a P+ S/D and a P+ S/D over the first, the second and the third fin structures, respectively.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: May 14, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: You Li, Alain Loiseau, Tsung-Che Tsai, Mickey Yu, Souvick Mitra, Robert Gauthier, Jr.
  • Patent number: 10276581
    Abstract: An integrated circuit chip includes a substrate, a first type memory cell, and a second type memory cell. The first type memory cell is disposed over the substrate and includes an N-type transistor. The N-type transistor of the first type memory cell includes a gate electrode including a first work function layer having a first thickness. The second type memory cell is disposed over the substrate and includes an N-type transistor. The N-type transistor of the second type memory cell includes a gate electrode including a second work function layer having a second thickness different from the first thickness. The first type memory cell and the second type memory cell substantially have the same cell size.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 10248017
    Abstract: A method for structure design including a processor performing error processing of an initial design file layout. The processor detects a structure design violation at a design cell boundary for a metal layer above (Ma) a via (Vx) at a tip of the Ma for the initial design file layout for a semiconductor structure based on a library of pattern rules. Upon detection of the structure design violation, the processor retargets the Vx for generating a resulting design file layout of the semiconductor structure. A physical semiconductor structure is generated based on the resulting design file layout of the semiconductor structure.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Geng Han, Dongbing Shao
  • Patent number: 10229914
    Abstract: A three-dimensional (3D) semiconductor memory device may include a substrate including a cell array region and a connection region, an electrode structure including pluralities of first and second electrodes that are vertically and alternately stacked on a surface of the substrate, extending in a first direction that is parallel to the surface of the substrate, and may include a stair step structure on the connection region, first and second string selection electrodes that extend in the first direction on the electrode structure and spaced apart from each other in a second direction that is parallel to the surface of the substrate and perpendicular to the first direction. The first and second string selection electrodes may each include an electrode portion on the cell array region and a pad portion that extends from the electrode portion in the first direction and on the connection region.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: March 12, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung-Hoon Kim, Sangyoun Jo
  • Patent number: 10204179
    Abstract: A method for defining a structure of a photovoltaic system on a system surface with a local topology is provided, including: first placement of a block at a location on the system surface with the local topology; placing additional blocks at additional locations on the system surface without overlapping previously placed blocks, wherein prior to each placement, row spacing of the solar panels of each additional block is adapted to the topology at the location at which the respective additional block was placed, resulting in a change in the extension of the additional block in the direction of the column of solar panels of the additional block, and ending the placement of additional blocks if, by the placement of an additional block, the nominal capacity of a photovoltaic system corresponding to the structure were to be exceeded, or if no additional block can be placed without overlapping previously placed blocks.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: February 12, 2019
    Assignee: SIEMENS AKTIENGSELLSCHAFT
    Inventors: Martin Bischoff, Frederik Brandes, Oliver Hennig, Karl-Heinz Kufer, Kai Plociennik, Ingmar Schule
  • Patent number: 10192882
    Abstract: According to one embodiment, a semiconductor device includes a stacked body, a columnar portion, and a first air gap. The stacked body includes a plurality of conductive layers stacked with an insulator interposed. The columnar portion extends through the stacked body in a stacking direction of the stacked body. The first air gap extends through the stacked body in the stacking direction. The insulator includes an insulating layer provided at a periphery of a side surface of the columnar portion, and a second air gap communicating with the first air gap and being provided between the insulating layer and the first air gap. The insulating layer has a protrusion at an end adjacent to the second air gap.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: January 29, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Yasuhito Yoshimizu
  • Patent number: 10181450
    Abstract: A pad formed in a semiconductor chip is formed such that a thickness of an aluminum film in a wire bonding portion is smaller than that of an aluminum film in a peripheral portion covered with a protective film. On the other hand, a thickness of a wiring formed in the same step as the pad is larger than that of the pad in the wire bonding portion. The main conductive film of the pad in the wire bonding portion is comprised of only one layer of a first aluminum film, while the main conductive film of the wiring is comprised of at least two layers of aluminum films (the first aluminum film and a second aluminum film) in any region of the wiring.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: January 15, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Seiya Isozaki, Takashi Moriyama, Takehiko Maeda
  • Patent number: 10163782
    Abstract: A fuse structure includes a fusing line including a first portion, a second portion, and a central portion between the first portion and the second portion; and a dummy fuse neighboring the fusing line, the dummy fuse may include: a first air dummy fuse including a plurality of first air gaps extending in a first direction parallel to the fusing line; and a second air dummy fuse including a second air gap extending in a second direction crossing the fusing line.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: December 25, 2018
    Assignee: SK Hynix Inc.
    Inventors: Jae-Hong Kim, Seo-Woo Nam
  • Patent number: 10153287
    Abstract: A layout pattern of a static random access memory (SRAM) includes a substrate, a first pull-up transistor (PL1), a first pull-down transistor (PD1), a second (PL2), and a second pull-down transistor (PD2) on the substrate, and a first pass gate transistor (PG1A), a second pass gate transistor (PG1B), a third pass gate transistor (PG2A) and a fourth pass gate transistor (PG2B), wherein the PG1A and the PG1B comprise an identical first fin structure, the PG2A and the PG2B comprise an identical second fin structure, a first local interconnection layer disposed between the PG1A and the PG1B and disposed on the fin structures of the PL1 and the PD1, a second local interconnection layer disposed between the PG2A and the PG2B and disposed between the fin structures of the PL2 and the PD2.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: December 11, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shu-Ru Wang, Ching-Cheng Lung, Yu-Tse Kuo, Chien-Hung Chen, Chun-Hsien Huang, Li-Ping Huang, Chun-Yen Tseng, Meng-Ping Chuang
  • Patent number: 10147730
    Abstract: Provided is a memory device including a substrate, a source region, a drain region, a source contact, a drain contact, at least two stack gates, and at least two selection gates. The source region and the drain region are both located in the substrate. The source contact is located on the source region and the drain contact is located on the drain region. A bottom area of the drain contact is greater than a bottom area of the source contact. The stack gates are located on the substrate at two sides of the source region respectively. The selection gates are located on the substrate at two sides of the drain region respectively. A distance between the selection gates located at two sides of the drain region is greater than a distance between the stack gates located at two sides of the source region.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: December 4, 2018
    Assignee: Winbond Electronics Corp.
    Inventors: Che-Fu Chuang, Hsiu-Han Liao, Yao-Ting Tsai
  • Patent number: 10141239
    Abstract: A package includes a die, which includes a semiconductor substrate, a plurality of through-vias penetrating through the semiconductor substrate, a seal ring overlapping and connected to the plurality of through-vias, and a plurality of electrical connectors underlying the semiconductor substrate and connected to the seal ring. An interposer is underlying and bonded to the die. The interposer includes a substrate, and a plurality of metal lines over the substrate. The plurality of metal lines is electrically coupled to the plurality of electrical connectors. Each of the plurality metal lines has a first portion overlapped by the first die, and a second portion misaligned with the die. A thermal conductive block encircles the die, and is mounted on the plurality of metal lines of the interposer.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: November 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jing-Cheng Lin
  • Patent number: 10127855
    Abstract: The array substrate according to the present disclosure may include within its fanout region a plurality of signal transmission lines for transmitting signals between a driver chip and a display region of the array substrate, and each signal transmission line may correspond to one data transmission channel. The array substrate may further include at least one impedance balancing line arranged corresponding to a signal transmission line in the plurality of signal transmission lines, wherein the impedance balancing line is electrically connected to the signal transmission line, so that a difference between impedances of different data transmission channels within the fanout region meets a first predetermined condition.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: November 13, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Ming Zhang, Huaxing Zu, Yinzhong Zhang, Zhaohui Hao, Xiongxuan Yin
  • Patent number: 10043817
    Abstract: A highly integrated semiconductor memory device includes a substrate, a plurality of vertical pillars above the substrate, a plurality of connection lines extending over the vertical pillars, a plurality of lower via plugs provided above the vertical pillars and connecting the vertical pillars to the connection lines, a dummy connection line provided at a same level as the connection lines with respect to a main surface of the substrate, and a dummy via plug connected to a lower surface of the dummy connection line and having a different height than each of the lower via plugs. The vertical pillars, the connection lines, the lower via plugs are provided in a cell region, and the dummy connection line and the dummy via plug are provided in a dummy region.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: August 7, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Hee Lee, Hong-Soo Kim, Kyoung-Hoon Kim, Young-Suk Lee
  • Patent number: 10038008
    Abstract: Some embodiments include an integrated structure having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include primary regions of a first vertical thickness, and terminal projections of a second vertical thickness which is greater than the first vertical thickness. Charge-blocking material is adjacent the terminal projections. Charge-storage material is adjacent the charge-blocking material. Gate-dielectric material is adjacent the charge-storage material. Channel material is adjacent the gate-dielectric material. Some embodiments include NAND memory arrays. Some embodiments include methods of forming integrated structures.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: July 31, 2018
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, David Daycock
  • Patent number: 10026748
    Abstract: According to the embodiment, the semiconductor device includes: a stacked body; first interconnect and a second interconnect; a first columnar portion, a second columnar portion, a third columnar portion, and a fourth columnar portion; a first intermediate interconnect; a first connection portion; a second connection portion; and a second intermediate interconnect. The stacked body includes a plurality of electrode layers. The first interconnect and the second interconnect are provided on the stacked body, and extend in a first direction crossing a stacking direction of the stacked body. The first intermediate interconnect is electrically connected to the first interconnect, the first columnar portion, and the second columnar portion. The second intermediate interconnect is provided at a height different from a height of the first intermediate interconnect, and is electrically connected to the second interconnect, the third columnar portion, and the fourth columnar portion.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: July 17, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hiroshi Nakaki
  • Patent number: 10020261
    Abstract: A first metal layer of a semiconductor device includes a plurality of first metal lines that each extend along a first axis, and a first rail structure that extends along the first axis. The first rail structure is physically separated from the first metal lines. A second metal layer is located over the first metal layer. The second metal layer includes a plurality of second metal lines that each extend along a second axis orthogonal to the first axis, and a second rail structure that extends along the first axis. The second rail structure is physically separated from the second metal lines. The second rail structure is located directly over the first rail structure. A plurality of vias is located between the first metal layer and the second metal layer. A subset of the vias electrically interconnects the first rail structure to the second rail structure.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: July 10, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Tien Wu, Hsiang-Wei Liu, Wei-Chen Chu
  • Patent number: 10007422
    Abstract: A steering wheel for a vehicle, including front and back semi-toroidal surfaces joined at their outer circumferences by a light guide in the shape of a circular rim, and enclosing a toroidal volume having a cavity therein, a PCB mounted in the cavity, an alternating array of invisible-light emitters and receivers mounted on the PCB, such that the light guide projects invisible-light beams emitted by the emitters radially outward of the steering wheel, and directs reflections of the projected light beams off of a driver's hands radially inward to the steering wheel toward the receivers, and a processor connected to equipment mounted away from the steering wheel, the processor synchronously activating each emitter with a respective neighboring receiver, identifying a driver's hand gestures along an arc of the light guide based on reflected light detected by the receivers, and controlling the equipment in response to the thus-identified hand gestures.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: June 26, 2018
    Assignee: Neonode Inc.
    Inventors: Gunnar Martin Fröjdh, Simon Fellin, Thomas Eriksson, John Karlsson, Maria Hedin, Richard Berglind
  • Patent number: 9997423
    Abstract: A semiconductor wafer has an array of integrated circuit dies formed on it. Each die is enclosed by a respective seal ring. Each die has a group of bond pads and test pads coupled to the bond pads. A test pad region is formed on the wafer. The test pad region has probe pads and common electrical interconnects that selectively electrically couple each of the probe pads to a bond pad on each of the dies. The common electrical interconnects in the test pad region reduce the possibility of probe damage to the integrated circuits and allow the dies to be tested concurrently before being cut from the wafer.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: June 12, 2018
    Assignee: NXP USA, INC.
    Inventor: Dewey Killingsworth
  • Patent number: 9972638
    Abstract: Three dimensional semiconductor memory devices and methods of fabricating the same are provided. According to the method, sacrificial layers and insulating layers are alternately and repeatedly stacked on a substrate, and a cutting region penetrating an uppermost sacrificial layer of the sacrificial layers is formed. The cutting region is filled with a non sacrificial layer. The insulating layers and the sacrificial layers are patterned to form a mold pattern. The mold pattern includes insulating patterns, sacrificial patterns, and the non sacrificial layer in the cutting region. The sacrificial patterns may be replaced with electrodes. The related semiconductor memory device is also provided.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: May 15, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sunghae Lee, Daehong Eom, JinGyun Kim, Daehyun Jang, Kihyun Hwang, Seongsoo Lee, Kyunghyun Kim, Chadong Yeo, Jun-Youl Yang, Se-Ho Cha
  • Patent number: 9972548
    Abstract: A method of proving inline characterization of electrical properties of a fin-shaped field effect transistor (finFET) is provided. Embodiments include applying an electrical current along a length of at least one fin of a finFET disposed over a wafer surface; generating a magnetic field across a width of the at least one fin, wherein the magnetic field is perpendicular in direction to the electrical current; and detecting electron flow concentrated at an upper portion of the at least one fin.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: May 15, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Carlos Strocchia-Rivera
  • Patent number: 9947752
    Abstract: A semiconductor device may include a semiconductor substrate, a first metal film covering a surface of the semiconductor substrate; a protection film covering a peripheral portion of a surface of the first metal film; and a second metal film covering a range extending across a center portion of the surface of the first metal film and a surface of the protection film, wherein a recess may be provided in the surface of the protection film, and a part of the second metal film may be in contact with an inner surface of the recess.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: April 17, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Akitaka Soeno
  • Patent number: 9940422
    Abstract: A method for reducing congestion regions of an integrated circuit is provided. A placement of the IC is obtained, wherein the placement includes a signal path between a first macro module and a second macro module. The signal path passes through a routing area of the placement for transmitting a specific signal. A congestion region of the routing area is identified. The signal path includes at least one cell or routing path in the congestion region. A cost evaluation is obtained for each candidate position of the routing area by moving the cell or the routing path out of the congestion region. The cell is moved to the candidate position having a minimum cost evaluation among the cost evaluations. The placement and the routing paths are simultaneously updated according to the cell moved to the candidate position having the minimum cost evaluation.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: April 10, 2018
    Assignee: MEDIATEK INC.
    Inventors: Chin-Hsiung Hsu, Chun-Chih Yang
  • Patent number: 9917253
    Abstract: Some embodiments include a memory array having a first series of access/sense lines which extend along a first direction, a second series of access/sense lines over the first series of access/sense lines and which extend along a second direction substantially orthogonal to the first direction, and memory cells vertically between the first and second series of access/sense lines. Each memory cell is uniquely addressed by a combination of an access/sense line from the first series and an access/sense line from the second series. The memory cells have programmable material. At least some of the programmable material within each memory cell is a polygonal structure having a sidewall that extends along a third direction which is different from the first and second directions. Some embodiments include methods of forming memory arrays.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: March 13, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Fabio Pellizzer
  • Patent number: 9893206
    Abstract: The present disclosure provides a TFT, an array substrate, their manufacturing methods, and a display device. A source electrode and a drain electrode of the TFT are each of a multi-layered structure including a metal layer and a metal barrier layer. An a-Si active layer of the TFT is covered with an etch stop layer, via-holes penetrating through the etch stop layer are provided at positions corresponding to the source electrode and the drain, and the source electrode and the drain electrode are connected to the a-Si active layer through the via-holes.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: February 13, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Yuliang Wang, Daeyoung Choi, Zengli Liu, Daojie Li, Fei Al, Jun Zhou
  • Patent number: 9870990
    Abstract: Methods for forming semiconductor structures are disclosed, including a method that involves forming sets of conductive material and insulating material, forming a first mask over the sets, forming a first number of contact regions, forming a second mask over a first region of the sets, and removing material from of the sets in a second, exposed region laterally adjacent the first region to form a second number of contact regions. Another method includes forming first and second contact regions on portions of sets of conductive materials and insulating materials, each of the second contact regions more proximal to an underlying substrate than each of the first contact regions. Apparatuses such as memory devices including laterally adjacent first and second regions each of which including contact regions of a different portion of a plurality of conductive materials and related methods of forming such devices are also disclosed.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: January 16, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Eric H. Freeman, Michael A. Smith
  • Patent number: 9865325
    Abstract: Provided is a memory device with a reduced layout area. The memory device includes a sense amplifier electrically connected to first and second wirings and positioned in a first layer, and first and second circuits positioned in a second layer over the first layer. The first circuit includes a first switch being turned on and off in accordance with a potential of a third wiring, and a first capacitor electrically connected to the first wiring via the first switch. The second circuit includes a second switch being turned on and off in accordance with a potential of a fourth wiring, and a second capacitor electrically connected to the second wiring via the second switch. The first wiring intersects the third wiring and does not intersect the fourth wiring in the second layer. The second wiring intersects the fourth wiring and does not intersect the third wiring in the second layer.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: January 9, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tatsuya Onuki
  • Patent number: 9853041
    Abstract: A semiconductor device includes a memory cell array including a vertical channel layer, two or more selection transistors, and a plurality of memory cells formed along the vertical channel; a peripheral circuit suitable for programming the two or more selection transistors and the memory cells; and a control circuit suitable for controlling the peripheral circuit to decrease a pass voltage applied to one word line adjacent to two or more selection lines coupled to the respective selection transistors, during a program operation in which the peripheral circuit applies a program voltage to the two or more selection lines and applies the pass voltage to a plurality of word lines connected to the memory cells.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: December 26, 2017
    Assignee: SK Hynix Inc.
    Inventor: Keon Soo Shim
  • Patent number: 9853040
    Abstract: A semiconductor memory device according to an embodiment includes: a semiconductor substrate; a plurality of first insulating layers and first conductive layers stacked alternately in a first direction above the semiconductor substrate; a first semiconductor layer extending in the first direction; and a memory layer disposed between one of the first insulating layers and the first semiconductor layer and between one of the first conductive layers and the first semiconductor layer, the memory layer including a charge accumulation layer, the first semiconductor layer and the memory layer having a gap, between one of the first insulating layers and the first semiconductor layer, and the first semiconductor layer and the memory layer being contacted each other, between one of the first conductive layers and the first semiconductor layer.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: December 26, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tomoya Kawai, Tsutomu Tezuka
  • Patent number: 9824174
    Abstract: Techniques for power-density-based clock cell spacing and resulting integrated circuits (ICs) are disclosed herein. In one example, the techniques determine power-usage density for different types of clock cells, as power-usage density relates to heat and IR droop. With the power-usage density for each type of clock cell determined, the techniques assign a keep-out region for each type of clock cell that is not fixed for all types of clock cells. These regions are instead based on the heat and IR droop corresponding to estimated power-usage density for each type of clock cell. Clock cells are then placed in a layout of an IC. The resulting IC has clock cells spaced sufficiently to reduce heat and IR droop while concurrently having excellent timing closure and performance.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: November 21, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Ankita Nayak, David Anthony Kidd, Paul Ivan Penzes
  • Patent number: 9818701
    Abstract: A semiconductor device includes wiring layers formed over a semiconductor wafer, a via-layer between the wiring layers, conductive films in the wiring layers, and a via-plug in the via-layer connecting the conductive films of the wiring layers above and below, a scribe region at an outer periphery of a chip region along an edge of the semiconductor substrate and including a pad region in the vicinity of the edge, the pad region overlapping the conductive films of the plurality of wiring layers in the plan view, the plurality of wiring layers including first second wiring layers, the conductive film of the first wiring layer includes a first conductive pattern formed over an entire surface of said pad region in a plan view, and the conductive film of the second wiring layer includes a second conductive pattern formed in a part of the pad region in a plan view.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: November 14, 2017
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Kazutaka Yoshizawa, Taiji Ema, Takuya Moriki
  • Patent number: RE46782
    Abstract: Controlling a power supply which supplies a voltage to target circuit of an integrated circuit. An adjustable delay line powered by the supply voltage is co-located on the IC with the target circuit. The adjustable delay line is subjected to substantially the same operating conditions as the target circuit. A control unit measures a delay time of the adjustable delay line. Based on the measured delay time, the control unit outputs a control signal by which the power supply adjusts the supply voltage. The adjustable delay line comprises multiple distinct delay elements, each with delay properties and responsivity to changes in operating conditions. Each delay element emulates delay properties of physical elements (e.g., gates and wires) in the target circuit. In this manner, power consumption may be reduced, while still maintaining proper operation of the target circuit.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: April 10, 2018
    Assignee: Marvell International Ltd.
    Inventors: Nir Paz, Mark N. Fullerton
  • Patent number: RE47251
    Abstract: A semiconductor memory having a memory cell structure capable of reducing soft error without complicating a circuit configuration. Specifically, an inverter (I1) consists of a NMOS transistor (N1) and a PMOS transistor (P1), and an inverter (I2) consists of a NMOS transistor (N2) and a PMOS transistor (P2). The inverters (I1, I2) are subjected to cross section. The NMOS transistor (N1) is formed within a P well region (PW0), and the NMOS transistor (N2) is formed within a P well region (PW1). The P well regions (PW0, PW1) are oppositely disposed with an N well region (NW) interposed therebetween.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: February 19, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Koji Nii
  • Patent number: RE47679
    Abstract: A semiconductor memory having a memory cell structure capable of reducing soft error without complicating a circuit configuration. Specifically, an inverter (I1) consists of a NMOS transistor (N1) and a PMOS transistor (P1), and an inverter (I2) consists of a NMOS transistor (N2) and a PMOS transistor (P2). The inverters (I1, I2) are subjected to cross section. The NMOS transistor (N1) is formed within a P well region (PW0), and the NMOS transistor (N2) is formed within a P well region (PW1). The P well regions (PW0, PW1) are oppositely disposed with an N well region (NW) interposed therebetween.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: October 29, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Koji Nii