With Particular Signal Path Connections Patents (Class 257/208)
  • Patent number: 11145666
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: October 12, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhenyu Lu, Jun Chen, Xiaowang Dai, Jifeng Zhu, Qian Tao, Yu Ru Huang, Si Ping Hu, Lan Yao, Li Hong Xiao, A Man Zheng, Kun Bao, Haohao Yang
  • Patent number: 11099814
    Abstract: A semiconductor device capable of performing product-sum operation is provided. The semiconductor device includes a first memory cell, a second memory cell, and an offset circuit. The semiconductor device retains first analog data and reference analog data in the first memory cell and the second memory cell, respectively. A potential corresponding to second analog data is applied to each of them as a selection signal, whereby current depending on the sum of products of the first analog data and the second analog data is obtained. The offset circuit includes a constant current circuit comprising a transistor and a capacitor. A first terminal of the transistor is electrically connected to a first gate of the transistor and a first terminal of the capacitor. A second gate of the transistor is electrically connected to a second terminal of the capacitor.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: August 24, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shintaro Harada, Yoshiyuki Kurokawa, Takeshi Aoki
  • Patent number: 11094627
    Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. First dummy pillars in the memory blocks extend through at least a majority of the insulative tiers and the conductive tiers through which the channel-material strings extend. Second dummy pillars are laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks. The second dummy pillars extend through at least a majority of the insulative tiers and the conductive tiers through which the operative channel-material strings extend laterally-between the immediately-laterally-adjacent memory blocks. Other embodiments, including method, are disclosed.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: August 17, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Vladimir Machkaoutsan, Pieter Blomme, Emilio Camerlenghi, Justin B. Dorhout, Jian Li, Ryan L. Meyer, Paolo Tessariol
  • Patent number: 11080431
    Abstract: Method and apparatus for authenticating analog mixed-signal integrated circuits using process-specific functions (PSF) comprising: presenting wafer having plurality of dies, each die having circuit with identical design but having inherent physical differences due to process variation in their manufacture, each circuit designed to enhance the effects of the inherent differences; defining selected number of inputs/stimuli for authenticating and identifying each integrated circuit; defining expected response for each circuit, wherein the expected response for each circuit is the same due to the identical design; defining statistical window for analog response by the circuit to the inputs/stimuli; applying the inputs/stimuli to each circuit; receiving analog response corresponding to the applied inputs/stimuli, wherein the analog response falls outside statistical window when there are functional or physical changes to the circuit; separating from plurality of dies each die providing a response outside the stati
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: August 3, 2021
    Assignee: United States of America as represented by the Secretary of the Air Force
    Inventors: Matthew J Casto, Waleed Khalil, Brian Dupaix
  • Patent number: 11075219
    Abstract: In some embodiments, a memory array comprising strings of memory cells comprise laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Insulative pillars are laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The pillars comprise vertically-spaced and radially-projecting insulative rings in the conductive tiers as compared to the insulative tiers. Other embodiments, including methods, are disclosed.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: July 27, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Xiaosong Zhang, Yi Hu, Tom J. John, Wei Yeeng Ng, Chandra Tiwari
  • Patent number: 11056431
    Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and first fuse branches and second fuse branches are formed in the substrate, in which the first fuse branches and the second fuse branches are separated by a shallow trench isolation (STI) and the second fuse branches include different sizes. Next, fuse elements are formed to connect the first fuse branches and the second fuse branches.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: July 6, 2021
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventor: Yukihiro Nagai
  • Patent number: 11041211
    Abstract: Active-on-active microelectronic devices are described. For example, a first die is on a second die with a bottom surface of a first substrate facing a top surface of a second substrate, respectively, to provide a die stack. The first and second dies each have metal layers in ILD layers to provide a first stack structure and a second stack structure, respectively. The first stack structure is interconnected to an upper end of a TSV of the first die. A metal layer of the second stack structure near a bottom surface of the first substrate is interconnected to a lower end of the TSV. A power distribution network layer of the second stack structure is located between lower and upper layers of the metal layers thereof. A transistor located at least in part in the second substrate is interconnected to the power distribution network layer to receive supply voltage or ground.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: June 22, 2021
    Assignee: XILINX, INC.
    Inventor: Praful Jain
  • Patent number: 11043986
    Abstract: A mesh interconnect interface includes a dielectric slice; first micro-bumps aligned along a longitudinal axis and positioned closest to a driver bank, which is to be coupled to a first mesh stop of a first chiplet; second micro-bumps similarly aligned and positioned farthest from the first driver bank; third micro-bumps similarly aligned and positioned closest to a second driver bank, which is to be coupled to a second mesh stop of a second chiplet; fourth micro-bumps similarly aligned and positioned farthest from the second driver bank, wherein the longitudinal axis is orthogonal to a gap between the chiplets. The groups of micro-bumps are disposed on the slice. A first group of wires are embedded in the slice to couple the first and second micro-bumps. A second group of wires are interleaved with the first group of wires and embedded in the slice to couple the second and third micro-bumps.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: June 22, 2021
    Assignee: Intel Corporation
    Inventor: Edward Burton
  • Patent number: 11004969
    Abstract: A trench MOSFET layout with multiple trenched floating gates and at least one trenched channel stop gate in termination area shorted with drain region is disclosed to make it feasibly achieved after die sawing. The layout consisted of multiple trench MOSFETs connected together with multiple sawing trenched gates across a space between two trench MOSFETs having a width same as scribe line. Dummy cells formed between an edge trench and active area act as buffer cells to absorb avalanche energy when gate bias is increasing for turning on channel, therefore, the UIS failure issue is avoided and the avalanche capability of the trench MOSFET is enhanced.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: May 11, 2021
    Assignee: NAMI MOS CO., LTD.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 10985104
    Abstract: A semiconductor device according to an embodiment includes a first electrode pad containing copper as a main component and having a thickness equal to or more than 5 ?m and less than 50 ?m; an electrode layer containing copper as a main component and having a thickness equal to or more than 5 ?m and less than 50 ?m; and a semiconductor layer provided between the first electrode pad and the electrode layer.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: April 20, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Seiji Inumiya, Kyoichi Suguro
  • Patent number: 10950278
    Abstract: According to one embodiment, a nonvolatile memory device includes first and second word lines, first and second bit lines, memory cells each including a resistance change memory element, a global word line including a first global word line portion including a first end portion, a global bit line including a first global bit line portion including a second end portion. The first and second word lines and the first global bit line portion have a first line width and a first line thickness, the first and second bit lines and the first global word line portion have a second line width and a second line thickness.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: March 16, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takahiko Iizuka, Daisaburo Takashima, Ryu Ogiwara
  • Patent number: 10892748
    Abstract: A power module includes a power circuit which includes one or more power semiconductors; and a control circuit which supplies a gate signal to each of the one or more power semiconductors. The control circuit includes one or more gate drivers which generate the gate signal in accordance with a control signal and in which a side to which the control signal is input and a side on which the gate signal is generated are insulated, a control input circuit to which the control signal is input and which supplies the control signal to the one or more gate drivers, and a control output circuit which supplies the gate signal to each of the power semiconductors.
    Type: Grant
    Filed: July 4, 2020
    Date of Patent: January 12, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hiroki Kanai, Tomotoshi Satoh, Koichiro Fujita, Kenichi Tanaka, Hiroyuki Komeda, Naomichi Fujii
  • Patent number: 10891986
    Abstract: The subject in the past is that there are a large number of data wirings in a semiconductor device including multiple memory cell arrays and that the area occupied by the data wirings is large. In a selected memory cell array among multiple memory cell arrays, a data wiring functions as a local wiring that transmits the data of the selected memory cell. In a memory cell array that is not selected among the memory cell arrays and is located between a data circuit and the selected memory cell array, the data wiring functions as a global wiring that transmits the data of a memory cell of the selected memory cell array.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: January 12, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tetsuo Fukushi, Hiroyuki Takahashi
  • Patent number: 10886354
    Abstract: A display device includes a substrate having a pixel area and a peripheral area, a plurality of pixels disposed on the substrate in the pixel area, a plurality of data lines that supply a plurality of data signals to the pixels, a plurality of scan lines that supply a plurality of scan signals to the pixels, a plurality of power supply lines that supply a first voltage to the pixels, and first through third insulating layers. The first insulating layer is disposed on the substrate, the second insulating layer is disposed on the first insulating layer, and the third insulating layer is disposed on the second insulating layer. The scan lines are disposed below the third insulating layer on the substrate in the pixel area, and are disposed on the third insulating layer in the peripheral area.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: January 5, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Byung Sun Kim, Sun Ja Kwon, Yang Wan Kim, Hyun Ae Park, Su Jin Lee, Jae Yong Lee
  • Patent number: 10825816
    Abstract: A recessed access device comprises a conductive gate in a trench in semiconductor material. A gate insulator is along sidewalls and a base of the trench between the conductive gate and the semiconductor material. A pair of source/drain regions is in upper portions of the semiconductor material on opposing sides of the trench. A channel region is in the semiconductor material below the pair of source/drain regions along the trench sidewalls and around the trench base. At least some of the channel region comprises GaP.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: November 3, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Yunfei Gao, Richard J. Hill, Gurtej S. Sandhu, Haitao Liu, Deepak Chandra Pandey, Srinivas Pulugurtha, Kamal M. Karda
  • Patent number: 10784264
    Abstract: Some embodiments include an integrated assembly having a semiconductor-containing structure with a body region vertically between an upper region and a lower region. The upper region includes a first source/drain region. The lower region is split into two legs which are both joined to the body region. One of the legs includes a second source/drain region and the other of the legs includes a body contact region. The first and second source/drain regions are of a first conductivity type, and the body contact region is of a second conductivity type which is opposite to the first conductivity type. An insulative material is adjacent to the body region. A conductive gate is adjacent to the insulative material. A transistor includes the semiconductor-containing structure, the conductive gate and the insulative material. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: September 22, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 10776362
    Abstract: Memory devices for facilitating pattern matching and having an array of memory cells, a plurality of key registers to store a representation of a key word, and a plurality of multiplexers, each multiplexer of the plurality of multiplexers to select a representation of a bit from a key register of the plurality of key registers to compare to data stored in the array of memory cells.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: September 15, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Luca De Santis, Giulio G. Marotta, Marco-Domenico Tiburzi, Tommaso Vali, Frankie F. Roohparvar, Agostino Macerola
  • Patent number: 10740530
    Abstract: Aspects of the present disclosure address systems and methods for shortening clock tree wirelength based on target offsets in connected routes. A method may include accessing a clock tree comprising routes that interconnect a plurality of pins. Each pin corresponds to a terminal of a clock tree instance. The method further includes identifying a first and second terminal of a clock tree instance in the clock tree. The method further includes determining a first offset based on a distance between the first terminal and a branch in a first route connected to the first terminal and determining a second offset based on a distance between the second terminal and a branch in a second route connected to the second terminal. The method further includes moving the clock tree instance from a first location to a second location based on a target offset determined by comparing the first and second offsets.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: August 11, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Andrew Mark Chapman, Zhuo Li
  • Patent number: 10707218
    Abstract: One illustrative device disclosed herein includes a first pull-up transistor positioned in a first P-type nano-sheet and a first pull-down transistor and a first pass gate transistor positioned in a first N-type nano-sheet. The device further includes a second pull-up transistor positioned in a second P-type nano-sheet and a second pull-down transistor and a second pass gate transistor positioned in a second N-type nano-sheet. The device further includes a read pull-down transistor and a read pass gate transistor positioned in a third N-type nano-sheet. The device also includes a first shared gate structure positioned adjacent the first pull-up transistor and the first pull-down transistor and a second shared gate structure positioned adjacent the second pull-up transistor, the second pull-down transistor and the read pull-down transistor.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: July 7, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Bipul C. Paul, Ruilong Xie
  • Patent number: 10672706
    Abstract: A semiconductor device includes a multilayer wiring structure on a substrate. The multilayer wiring structure includes: a top wiring; a fuse element, which is located on a lower layer-side of the top wiring, and is made of metal having a melting point that is higher than that of the top wiring; and a lower-layer wiring, which is connected to each of ends of the fuse element. Provided is a semiconductor device in which fuse elements made of the high-melting point metal are arranged at high density.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: June 2, 2020
    Assignee: ABLIC INC.
    Inventor: Yoshitaka Kimura
  • Patent number: 10672657
    Abstract: A method of forming a semiconductor device assembly comprises forming tiers comprising conductive structures and insulating structures in a stacked arrangement over a substrate. Portions of the tiers are selectively removed to form a stair step structure comprising a selected number of steps exhibiting different widths corresponding to variances in projected error associated with forming the steps. Contact structures are formed on the steps of the stair step structure. Semiconductor device structures and semiconductor devices are also described.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: June 2, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Matthew Park, Adam L. Olson, Jixin Yu
  • Patent number: 10541240
    Abstract: The semiconductor device includes a first inserter and a second inverter which is connected thereto in series. Each of the first and the second inserters includes a p-channel transistor and an n-channel transistor, respectively. The number of projection semiconductor layers each as the active region of the p-channel and the n-channel transistors of the second inverter is smaller than the number of the projection semiconductor layers each as the active region of the p-channel and the n-channel transistors of the first inverter.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: January 21, 2020
    Assignee: Renesas Electronics Corporation
    Inventor: Takeshi Okagaki
  • Patent number: 10535710
    Abstract: Some embodiments include a method of forming integrated circuitry. A structure has first conductive lines over a dielectric bonding region, has semiconductor material pillars extending upwardly from the first conductive lines, and has second conductive lines over the first conductive lines and extending along sidewalls of the semiconductor material pillars. The first conductive lines extend along a first direction, and the second conductive lines extend along a second direction which intersects the first direction. The structure includes semiconductor material under the dielectric bonding region. Memory structures are formed over the semiconductor material pillars. The memory structures are within a memory array. Third conductive lines are formed over the memory structures. The third conductive lines extend along the first direction. Individual memory structures of the memory array are uniquely addressed through combinations of the first, second and third conductive lines.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: January 14, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Mitsunari Sukekawa
  • Patent number: 10522469
    Abstract: A first metal layer of a semiconductor device includes a plurality of first metal lines that each extend along a first axis, and a first rail structure that extends along the first axis. The first rail structure is physically separated from the first metal lines. A second metal layer is located over the first metal layer. The second metal layer includes a plurality of second metal lines that each extend along a second axis orthogonal to the first axis, and a second rail structure that extends along the first axis. The second rail structure is physically separated from the second metal lines. The second rail structure is located directly over the first rail structure. A plurality of vias is located between the first metal layer and the second metal layer. A subset of the vias electrically interconnects the first rail structure to the second rail structure.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Tien Wu, Hsiang-Wei Liu, Wei-Chen Chu
  • Patent number: 10497633
    Abstract: The present invention provides electronic systems, including device arrays, comprising functional device(s) and/or device component(s) at least partially enclosed via one or more fluid containment chambers, such that the device(s) and/or device component(s) are at least partially, and optionally entirely, immersed in a containment fluid. Useful containment fluids for use in fluid containment chambers of electronic devices of the invention include lubricants, electrolytes and/or electronically resistive fluids. In some embodiments, for example, electronic systems of the invention comprise one or more electronic devices and/or device components provided in free-standing and/or tethered configurations that decouple forces originating upon deformation, stretching or compression of a supporting substrate from the free standing or tethered device or device component.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 3, 2019
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: John A. Rogers, Sheng Xu, Jonathan A. Fan, Lin Jia
  • Patent number: 10483125
    Abstract: A semiconductor device includes a first interlayer film formed on an upper surface of a substrate, a first metal wiring line, a second interlayer film, a second metal wiring line, a first via electrically connecting the first metal wiring line and the second metal wiring line, a landing pad embedded in an upper portion of the first interlayer film and penetrating the second interlayer film, and a second via penetrating the substrate and the first interlayer film from a back side of the substrate and connected to the landing pad. The lower surface position of the landing pad is different from that of the first metal wiring line.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: November 19, 2019
    Assignee: TOWERJAZZ PANASONIC SEMICONDUCTOR CO., LTD.
    Inventors: Yuka Inoue, Mitsunori Fukura, Nobuyoshi Takahashi, Masahiro Oda, Hisashi Yano, Yutaka Ito, Yasunori Morinaga
  • Patent number: 10481203
    Abstract: In one embodiment, a system comprises: a global clock input for receiving a global clock, a plurality of partitions; and a skew tolerant interface configured to compensate for clock skew differences between a global clock from outside at least one of the partitions and a balanced local clock within at least one of the partitions. The partitions can be test partitions. The skew tolerant interface can cross a mesochronous boundary. In one exemplary implementation, the skew tolerant interface includes a deskew ring buffer on communication path of the at least one partition. pointers associated with the ring buffer can be free-running and depend only on clocks being pulsed when out of reset. The scheme can be fully synchronous and deterministic. The scheme can be modeled for the ATPG tools using simple pipeline flops. The depth of the pipeline can be dependent on the pointer difference for the read/write interface. The global clock input can be part of a scan link.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: November 19, 2019
    Assignee: Nvidia Corporation
    Inventors: Shantanu Sarangi, Milind Sonawane, Adarsh Kalliat Balagopala, Amit Sanghani
  • Patent number: 10446536
    Abstract: A cell circuit and corresponding layout is disclosed to include linear-shaped diffusion fins defined to extend over a substrate in a first direction so as to extend parallel to each other. Each of the linear-shaped diffusion fins is defined to project upward from the substrate along their extent in the first direction. A number of gate level structures are defined to extend in a conformal manner over some of the number of linear-shaped diffusion fins. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins extend in a second direction that is substantially perpendicular to the first direction. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins form gate electrodes of a corresponding transistor. The diffusion fins and gate level structures can be placed in accordance with a diffusion fin virtual grate and a gate level virtual grate, respectively.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: October 15, 2019
    Assignee: Tela Innovations, Inc.
    Inventor: Scott T. Becker
  • Patent number: 10423026
    Abstract: An array substrate, a display panel and a display device. The array substrate includes a base substrate including a plurality of pixel areas and a first data line on the base substrate and between adjacent pixel areas; a side slope angle of the first data line is not greater than about 60°.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: September 24, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Yujie Gao
  • Patent number: 10403442
    Abstract: The present invention generally relates to a MEMS DVC having a shielding electrode structure between the RF electrode and one or more other electrodes that cause a plate to move. The shielding electrode structure may be grounded and, in essence, block or shield the RF electrode from the one or more electrodes that cause the plate to move. By shielding the RF electrode, coupling of the RF electrode to the one or more electrodes that cause the plate to move is reduced and capacitance modulation is reduced or even eliminated.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: September 3, 2019
    Assignee: CAVENDISH KINETICS, INC.
    Inventors: Robertus Petrus Van Kampen, Ramadan A. Alhalabi
  • Patent number: 10388606
    Abstract: Some embodiments include a method of forming an integrated assembly. Conductive lines are formed to extend along a first direction, and are spaced from one another by a first pitch. Protective knobs are formed over the conductive lines and are arranged in rows. The protective knobs within each row are spaced along a second pitch which is greater than the first pitch. The protective knobs protect regions of the conductive lines while leaving other regions of the conductive lines unprotected. The unprotected regions are recessed so that the protected regions become tall regions and the unprotected regions become short regions. The protective knobs are removed. Conductive structures are formed over the conductive lines. The conductive structures are spaced along the second pitch. Each of the conductive lines is uniquely coupled to only one of the conductive structures. Some embodiments include integrated assemblies.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: August 20, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 10366913
    Abstract: A method for manufacturing a semiconductor element includes forming a first region in a semiconductor region by ion-implanting impurities using a first mask; forming an interconnect including a gate portion extending in a first direction over the first region; and forming a source/drain region by ion-implanting impurities into a second region. A gate threshold voltage of the semiconductor element has first to third correlations dependent respectively on distances between an inner wall of the first mask and an outer edge of the second region, between the gate portion and the outer edge of the second region and between the outer edge of the second portion and a portion of the interconnect other than the gate portion. At least one of the distances is determined based on the first to third correlations to obtain a prescribed gate threshold voltage of the semiconductor element.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: July 30, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masafumi Hamaguchi
  • Patent number: 10340348
    Abstract: A semiconductor device includes a fin structure, first and second gate structures, a source/drain region, a source/drain contact layer and a separation layer. The fin structure protrudes from an isolation insulating layer disposed over a substrate and extends in a first direction. The first and second gate structures are formed over the fin structure and extend in a second direction crossing the first direction. The source/drain region is disposed between the first and second gate structures. The interlayer insulating layer is disposed over the fin structure, the first and second gate structures and the source/drain region. The first source/drain contact layer is disposed on the first source/drain region. The separation layer is disposed adjacent to the first source/drain contact layer. Ends of the first and second gate structures and an end of the source drain contact layer are in contact with a same face of the separation layer.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: July 2, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Jyun Huang, Tung-Heng Hsieh, Bao-Ru Young
  • Patent number: 10297587
    Abstract: An integrated circuit is provided. In one implementation, the integrated circuit includes a first standard cell, comprising at least one first PMOS transistor disposed in a first row in a semiconductor substrate and at least one first NMOS transistor disposed in a first area of a second row in the semiconductor substrate, and a second standard cell, comprising a plurality of second PMOS transistors disposed in the first row and a third row in the semiconductor substrate and a plurality of second NMOS transistors disposed in a second area of the second row in the semiconductor substrate, wherein the second row is adjacent to the first and third rows and arranged between the first and third rows.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: May 21, 2019
    Assignee: MEDIATEK INC.
    Inventor: Jen-Hang Yang
  • Patent number: 10290626
    Abstract: Methods of integrating a HV ESD PNP bipolar transistor in a VFET process and the resulting devices are provided. Embodiments include forming a DNW region in a portion of a p-sub; forming a HVPDDD region in a portion of the DNW region; forming a first and a second NW in a portion of the DNW region, the second NW between the first NW and the HVPDDD region and laterally separated from the HVPDDD region; forming a PW in a portion of the HVPDDD region; forming an N+ implant in a portion of the first NW and a P+ implant in a portion of the PW; forming a first, a second and a third fin structures over the first and the second NW and the PW, respectively; and forming a N+ S/D, a P+ S/D and a P+ S/D over the first, the second and the third fin structures, respectively.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: May 14, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: You Li, Alain Loiseau, Tsung-Che Tsai, Mickey Yu, Souvick Mitra, Robert Gauthier, Jr.
  • Patent number: 10276581
    Abstract: An integrated circuit chip includes a substrate, a first type memory cell, and a second type memory cell. The first type memory cell is disposed over the substrate and includes an N-type transistor. The N-type transistor of the first type memory cell includes a gate electrode including a first work function layer having a first thickness. The second type memory cell is disposed over the substrate and includes an N-type transistor. The N-type transistor of the second type memory cell includes a gate electrode including a second work function layer having a second thickness different from the first thickness. The first type memory cell and the second type memory cell substantially have the same cell size.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 10248017
    Abstract: A method for structure design including a processor performing error processing of an initial design file layout. The processor detects a structure design violation at a design cell boundary for a metal layer above (Ma) a via (Vx) at a tip of the Ma for the initial design file layout for a semiconductor structure based on a library of pattern rules. Upon detection of the structure design violation, the processor retargets the Vx for generating a resulting design file layout of the semiconductor structure. A physical semiconductor structure is generated based on the resulting design file layout of the semiconductor structure.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Geng Han, Dongbing Shao
  • Patent number: 10229914
    Abstract: A three-dimensional (3D) semiconductor memory device may include a substrate including a cell array region and a connection region, an electrode structure including pluralities of first and second electrodes that are vertically and alternately stacked on a surface of the substrate, extending in a first direction that is parallel to the surface of the substrate, and may include a stair step structure on the connection region, first and second string selection electrodes that extend in the first direction on the electrode structure and spaced apart from each other in a second direction that is parallel to the surface of the substrate and perpendicular to the first direction. The first and second string selection electrodes may each include an electrode portion on the cell array region and a pad portion that extends from the electrode portion in the first direction and on the connection region.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: March 12, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung-Hoon Kim, Sangyoun Jo
  • Patent number: 10204179
    Abstract: A method for defining a structure of a photovoltaic system on a system surface with a local topology is provided, including: first placement of a block at a location on the system surface with the local topology; placing additional blocks at additional locations on the system surface without overlapping previously placed blocks, wherein prior to each placement, row spacing of the solar panels of each additional block is adapted to the topology at the location at which the respective additional block was placed, resulting in a change in the extension of the additional block in the direction of the column of solar panels of the additional block, and ending the placement of additional blocks if, by the placement of an additional block, the nominal capacity of a photovoltaic system corresponding to the structure were to be exceeded, or if no additional block can be placed without overlapping previously placed blocks.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: February 12, 2019
    Assignee: SIEMENS AKTIENGSELLSCHAFT
    Inventors: Martin Bischoff, Frederik Brandes, Oliver Hennig, Karl-Heinz Kufer, Kai Plociennik, Ingmar Schule
  • Patent number: 10192882
    Abstract: According to one embodiment, a semiconductor device includes a stacked body, a columnar portion, and a first air gap. The stacked body includes a plurality of conductive layers stacked with an insulator interposed. The columnar portion extends through the stacked body in a stacking direction of the stacked body. The first air gap extends through the stacked body in the stacking direction. The insulator includes an insulating layer provided at a periphery of a side surface of the columnar portion, and a second air gap communicating with the first air gap and being provided between the insulating layer and the first air gap. The insulating layer has a protrusion at an end adjacent to the second air gap.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: January 29, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Yasuhito Yoshimizu
  • Patent number: 10181450
    Abstract: A pad formed in a semiconductor chip is formed such that a thickness of an aluminum film in a wire bonding portion is smaller than that of an aluminum film in a peripheral portion covered with a protective film. On the other hand, a thickness of a wiring formed in the same step as the pad is larger than that of the pad in the wire bonding portion. The main conductive film of the pad in the wire bonding portion is comprised of only one layer of a first aluminum film, while the main conductive film of the wiring is comprised of at least two layers of aluminum films (the first aluminum film and a second aluminum film) in any region of the wiring.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: January 15, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Seiya Isozaki, Takashi Moriyama, Takehiko Maeda
  • Patent number: 10163782
    Abstract: A fuse structure includes a fusing line including a first portion, a second portion, and a central portion between the first portion and the second portion; and a dummy fuse neighboring the fusing line, the dummy fuse may include: a first air dummy fuse including a plurality of first air gaps extending in a first direction parallel to the fusing line; and a second air dummy fuse including a second air gap extending in a second direction crossing the fusing line.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: December 25, 2018
    Assignee: SK Hynix Inc.
    Inventors: Jae-Hong Kim, Seo-Woo Nam
  • Patent number: 10153287
    Abstract: A layout pattern of a static random access memory (SRAM) includes a substrate, a first pull-up transistor (PL1), a first pull-down transistor (PD1), a second (PL2), and a second pull-down transistor (PD2) on the substrate, and a first pass gate transistor (PG1A), a second pass gate transistor (PG1B), a third pass gate transistor (PG2A) and a fourth pass gate transistor (PG2B), wherein the PG1A and the PG1B comprise an identical first fin structure, the PG2A and the PG2B comprise an identical second fin structure, a first local interconnection layer disposed between the PG1A and the PG1B and disposed on the fin structures of the PL1 and the PD1, a second local interconnection layer disposed between the PG2A and the PG2B and disposed between the fin structures of the PL2 and the PD2.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: December 11, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shu-Ru Wang, Ching-Cheng Lung, Yu-Tse Kuo, Chien-Hung Chen, Chun-Hsien Huang, Li-Ping Huang, Chun-Yen Tseng, Meng-Ping Chuang
  • Patent number: 10147730
    Abstract: Provided is a memory device including a substrate, a source region, a drain region, a source contact, a drain contact, at least two stack gates, and at least two selection gates. The source region and the drain region are both located in the substrate. The source contact is located on the source region and the drain contact is located on the drain region. A bottom area of the drain contact is greater than a bottom area of the source contact. The stack gates are located on the substrate at two sides of the source region respectively. The selection gates are located on the substrate at two sides of the drain region respectively. A distance between the selection gates located at two sides of the drain region is greater than a distance between the stack gates located at two sides of the source region.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: December 4, 2018
    Assignee: Winbond Electronics Corp.
    Inventors: Che-Fu Chuang, Hsiu-Han Liao, Yao-Ting Tsai
  • Patent number: 10141239
    Abstract: A package includes a die, which includes a semiconductor substrate, a plurality of through-vias penetrating through the semiconductor substrate, a seal ring overlapping and connected to the plurality of through-vias, and a plurality of electrical connectors underlying the semiconductor substrate and connected to the seal ring. An interposer is underlying and bonded to the die. The interposer includes a substrate, and a plurality of metal lines over the substrate. The plurality of metal lines is electrically coupled to the plurality of electrical connectors. Each of the plurality metal lines has a first portion overlapped by the first die, and a second portion misaligned with the die. A thermal conductive block encircles the die, and is mounted on the plurality of metal lines of the interposer.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: November 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jing-Cheng Lin
  • Patent number: 10127855
    Abstract: The array substrate according to the present disclosure may include within its fanout region a plurality of signal transmission lines for transmitting signals between a driver chip and a display region of the array substrate, and each signal transmission line may correspond to one data transmission channel. The array substrate may further include at least one impedance balancing line arranged corresponding to a signal transmission line in the plurality of signal transmission lines, wherein the impedance balancing line is electrically connected to the signal transmission line, so that a difference between impedances of different data transmission channels within the fanout region meets a first predetermined condition.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: November 13, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Ming Zhang, Huaxing Zu, Yinzhong Zhang, Zhaohui Hao, Xiongxuan Yin
  • Patent number: 10043817
    Abstract: A highly integrated semiconductor memory device includes a substrate, a plurality of vertical pillars above the substrate, a plurality of connection lines extending over the vertical pillars, a plurality of lower via plugs provided above the vertical pillars and connecting the vertical pillars to the connection lines, a dummy connection line provided at a same level as the connection lines with respect to a main surface of the substrate, and a dummy via plug connected to a lower surface of the dummy connection line and having a different height than each of the lower via plugs. The vertical pillars, the connection lines, the lower via plugs are provided in a cell region, and the dummy connection line and the dummy via plug are provided in a dummy region.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: August 7, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Hee Lee, Hong-Soo Kim, Kyoung-Hoon Kim, Young-Suk Lee
  • Patent number: 10038008
    Abstract: Some embodiments include an integrated structure having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include primary regions of a first vertical thickness, and terminal projections of a second vertical thickness which is greater than the first vertical thickness. Charge-blocking material is adjacent the terminal projections. Charge-storage material is adjacent the charge-blocking material. Gate-dielectric material is adjacent the charge-storage material. Channel material is adjacent the gate-dielectric material. Some embodiments include NAND memory arrays. Some embodiments include methods of forming integrated structures.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: July 31, 2018
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, David Daycock
  • Patent number: RE47251
    Abstract: A semiconductor memory having a memory cell structure capable of reducing soft error without complicating a circuit configuration. Specifically, an inverter (I1) consists of a NMOS transistor (N1) and a PMOS transistor (P1), and an inverter (I2) consists of a NMOS transistor (N2) and a PMOS transistor (P2). The inverters (I1, I2) are subjected to cross section. The NMOS transistor (N1) is formed within a P well region (PW0), and the NMOS transistor (N2) is formed within a P well region (PW1). The P well regions (PW0, PW1) are oppositely disposed with an N well region (NW) interposed therebetween.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: February 19, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Koji Nii
  • Patent number: RE47679
    Abstract: A semiconductor memory having a memory cell structure capable of reducing soft error without complicating a circuit configuration. Specifically, an inverter (I1) consists of a NMOS transistor (N1) and a PMOS transistor (P1), and an inverter (I2) consists of a NMOS transistor (N2) and a PMOS transistor (P2). The inverters (I1, I2) are subjected to cross section. The NMOS transistor (N1) is formed within a P well region (PW0), and the NMOS transistor (N2) is formed within a P well region (PW1). The P well regions (PW0, PW1) are oppositely disposed with an N well region (NW) interposed therebetween.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: October 29, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Koji Nii