With Particular Signal Path Connections Patents (Class 257/208)
  • Patent number: 10340348
    Abstract: A semiconductor device includes a fin structure, first and second gate structures, a source/drain region, a source/drain contact layer and a separation layer. The fin structure protrudes from an isolation insulating layer disposed over a substrate and extends in a first direction. The first and second gate structures are formed over the fin structure and extend in a second direction crossing the first direction. The source/drain region is disposed between the first and second gate structures. The interlayer insulating layer is disposed over the fin structure, the first and second gate structures and the source/drain region. The first source/drain contact layer is disposed on the first source/drain region. The separation layer is disposed adjacent to the first source/drain contact layer. Ends of the first and second gate structures and an end of the source drain contact layer are in contact with a same face of the separation layer.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: July 2, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Jyun Huang, Tung-Heng Hsieh, Bao-Ru Young
  • Patent number: 10297587
    Abstract: An integrated circuit is provided. In one implementation, the integrated circuit includes a first standard cell, comprising at least one first PMOS transistor disposed in a first row in a semiconductor substrate and at least one first NMOS transistor disposed in a first area of a second row in the semiconductor substrate, and a second standard cell, comprising a plurality of second PMOS transistors disposed in the first row and a third row in the semiconductor substrate and a plurality of second NMOS transistors disposed in a second area of the second row in the semiconductor substrate, wherein the second row is adjacent to the first and third rows and arranged between the first and third rows.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: May 21, 2019
    Assignee: MEDIATEK INC.
    Inventor: Jen-Hang Yang
  • Patent number: 10290626
    Abstract: Methods of integrating a HV ESD PNP bipolar transistor in a VFET process and the resulting devices are provided. Embodiments include forming a DNW region in a portion of a p-sub; forming a HVPDDD region in a portion of the DNW region; forming a first and a second NW in a portion of the DNW region, the second NW between the first NW and the HVPDDD region and laterally separated from the HVPDDD region; forming a PW in a portion of the HVPDDD region; forming an N+ implant in a portion of the first NW and a P+ implant in a portion of the PW; forming a first, a second and a third fin structures over the first and the second NW and the PW, respectively; and forming a N+ S/D, a P+ S/D and a P+ S/D over the first, the second and the third fin structures, respectively.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: May 14, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: You Li, Alain Loiseau, Tsung-Che Tsai, Mickey Yu, Souvick Mitra, Robert Gauthier, Jr.
  • Patent number: 10276581
    Abstract: An integrated circuit chip includes a substrate, a first type memory cell, and a second type memory cell. The first type memory cell is disposed over the substrate and includes an N-type transistor. The N-type transistor of the first type memory cell includes a gate electrode including a first work function layer having a first thickness. The second type memory cell is disposed over the substrate and includes an N-type transistor. The N-type transistor of the second type memory cell includes a gate electrode including a second work function layer having a second thickness different from the first thickness. The first type memory cell and the second type memory cell substantially have the same cell size.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 10248017
    Abstract: A method for structure design including a processor performing error processing of an initial design file layout. The processor detects a structure design violation at a design cell boundary for a metal layer above (Ma) a via (Vx) at a tip of the Ma for the initial design file layout for a semiconductor structure based on a library of pattern rules. Upon detection of the structure design violation, the processor retargets the Vx for generating a resulting design file layout of the semiconductor structure. A physical semiconductor structure is generated based on the resulting design file layout of the semiconductor structure.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Geng Han, Dongbing Shao
  • Patent number: 10229914
    Abstract: A three-dimensional (3D) semiconductor memory device may include a substrate including a cell array region and a connection region, an electrode structure including pluralities of first and second electrodes that are vertically and alternately stacked on a surface of the substrate, extending in a first direction that is parallel to the surface of the substrate, and may include a stair step structure on the connection region, first and second string selection electrodes that extend in the first direction on the electrode structure and spaced apart from each other in a second direction that is parallel to the surface of the substrate and perpendicular to the first direction. The first and second string selection electrodes may each include an electrode portion on the cell array region and a pad portion that extends from the electrode portion in the first direction and on the connection region.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: March 12, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung-Hoon Kim, Sangyoun Jo
  • Patent number: 10204179
    Abstract: A method for defining a structure of a photovoltaic system on a system surface with a local topology is provided, including: first placement of a block at a location on the system surface with the local topology; placing additional blocks at additional locations on the system surface without overlapping previously placed blocks, wherein prior to each placement, row spacing of the solar panels of each additional block is adapted to the topology at the location at which the respective additional block was placed, resulting in a change in the extension of the additional block in the direction of the column of solar panels of the additional block, and ending the placement of additional blocks if, by the placement of an additional block, the nominal capacity of a photovoltaic system corresponding to the structure were to be exceeded, or if no additional block can be placed without overlapping previously placed blocks.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: February 12, 2019
    Assignee: SIEMENS AKTIENGSELLSCHAFT
    Inventors: Martin Bischoff, Frederik Brandes, Oliver Hennig, Karl-Heinz Kufer, Kai Plociennik, Ingmar Schule
  • Patent number: 10192882
    Abstract: According to one embodiment, a semiconductor device includes a stacked body, a columnar portion, and a first air gap. The stacked body includes a plurality of conductive layers stacked with an insulator interposed. The columnar portion extends through the stacked body in a stacking direction of the stacked body. The first air gap extends through the stacked body in the stacking direction. The insulator includes an insulating layer provided at a periphery of a side surface of the columnar portion, and a second air gap communicating with the first air gap and being provided between the insulating layer and the first air gap. The insulating layer has a protrusion at an end adjacent to the second air gap.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: January 29, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Yasuhito Yoshimizu
  • Patent number: 10181450
    Abstract: A pad formed in a semiconductor chip is formed such that a thickness of an aluminum film in a wire bonding portion is smaller than that of an aluminum film in a peripheral portion covered with a protective film. On the other hand, a thickness of a wiring formed in the same step as the pad is larger than that of the pad in the wire bonding portion. The main conductive film of the pad in the wire bonding portion is comprised of only one layer of a first aluminum film, while the main conductive film of the wiring is comprised of at least two layers of aluminum films (the first aluminum film and a second aluminum film) in any region of the wiring.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: January 15, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Seiya Isozaki, Takashi Moriyama, Takehiko Maeda
  • Patent number: 10163782
    Abstract: A fuse structure includes a fusing line including a first portion, a second portion, and a central portion between the first portion and the second portion; and a dummy fuse neighboring the fusing line, the dummy fuse may include: a first air dummy fuse including a plurality of first air gaps extending in a first direction parallel to the fusing line; and a second air dummy fuse including a second air gap extending in a second direction crossing the fusing line.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: December 25, 2018
    Assignee: SK Hynix Inc.
    Inventors: Jae-Hong Kim, Seo-Woo Nam
  • Patent number: 10153287
    Abstract: A layout pattern of a static random access memory (SRAM) includes a substrate, a first pull-up transistor (PL1), a first pull-down transistor (PD1), a second (PL2), and a second pull-down transistor (PD2) on the substrate, and a first pass gate transistor (PG1A), a second pass gate transistor (PG1B), a third pass gate transistor (PG2A) and a fourth pass gate transistor (PG2B), wherein the PG1A and the PG1B comprise an identical first fin structure, the PG2A and the PG2B comprise an identical second fin structure, a first local interconnection layer disposed between the PG1A and the PG1B and disposed on the fin structures of the PL1 and the PD1, a second local interconnection layer disposed between the PG2A and the PG2B and disposed between the fin structures of the PL2 and the PD2.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: December 11, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shu-Ru Wang, Ching-Cheng Lung, Yu-Tse Kuo, Chien-Hung Chen, Chun-Hsien Huang, Li-Ping Huang, Chun-Yen Tseng, Meng-Ping Chuang
  • Patent number: 10147730
    Abstract: Provided is a memory device including a substrate, a source region, a drain region, a source contact, a drain contact, at least two stack gates, and at least two selection gates. The source region and the drain region are both located in the substrate. The source contact is located on the source region and the drain contact is located on the drain region. A bottom area of the drain contact is greater than a bottom area of the source contact. The stack gates are located on the substrate at two sides of the source region respectively. The selection gates are located on the substrate at two sides of the drain region respectively. A distance between the selection gates located at two sides of the drain region is greater than a distance between the stack gates located at two sides of the source region.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: December 4, 2018
    Assignee: Winbond Electronics Corp.
    Inventors: Che-Fu Chuang, Hsiu-Han Liao, Yao-Ting Tsai
  • Patent number: 10141239
    Abstract: A package includes a die, which includes a semiconductor substrate, a plurality of through-vias penetrating through the semiconductor substrate, a seal ring overlapping and connected to the plurality of through-vias, and a plurality of electrical connectors underlying the semiconductor substrate and connected to the seal ring. An interposer is underlying and bonded to the die. The interposer includes a substrate, and a plurality of metal lines over the substrate. The plurality of metal lines is electrically coupled to the plurality of electrical connectors. Each of the plurality metal lines has a first portion overlapped by the first die, and a second portion misaligned with the die. A thermal conductive block encircles the die, and is mounted on the plurality of metal lines of the interposer.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: November 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jing-Cheng Lin
  • Patent number: 10127855
    Abstract: The array substrate according to the present disclosure may include within its fanout region a plurality of signal transmission lines for transmitting signals between a driver chip and a display region of the array substrate, and each signal transmission line may correspond to one data transmission channel. The array substrate may further include at least one impedance balancing line arranged corresponding to a signal transmission line in the plurality of signal transmission lines, wherein the impedance balancing line is electrically connected to the signal transmission line, so that a difference between impedances of different data transmission channels within the fanout region meets a first predetermined condition.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: November 13, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Ming Zhang, Huaxing Zu, Yinzhong Zhang, Zhaohui Hao, Xiongxuan Yin
  • Patent number: 10043817
    Abstract: A highly integrated semiconductor memory device includes a substrate, a plurality of vertical pillars above the substrate, a plurality of connection lines extending over the vertical pillars, a plurality of lower via plugs provided above the vertical pillars and connecting the vertical pillars to the connection lines, a dummy connection line provided at a same level as the connection lines with respect to a main surface of the substrate, and a dummy via plug connected to a lower surface of the dummy connection line and having a different height than each of the lower via plugs. The vertical pillars, the connection lines, the lower via plugs are provided in a cell region, and the dummy connection line and the dummy via plug are provided in a dummy region.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: August 7, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Hee Lee, Hong-Soo Kim, Kyoung-Hoon Kim, Young-Suk Lee
  • Patent number: 10038008
    Abstract: Some embodiments include an integrated structure having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include primary regions of a first vertical thickness, and terminal projections of a second vertical thickness which is greater than the first vertical thickness. Charge-blocking material is adjacent the terminal projections. Charge-storage material is adjacent the charge-blocking material. Gate-dielectric material is adjacent the charge-storage material. Channel material is adjacent the gate-dielectric material. Some embodiments include NAND memory arrays. Some embodiments include methods of forming integrated structures.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: July 31, 2018
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, David Daycock
  • Patent number: 10026748
    Abstract: According to the embodiment, the semiconductor device includes: a stacked body; first interconnect and a second interconnect; a first columnar portion, a second columnar portion, a third columnar portion, and a fourth columnar portion; a first intermediate interconnect; a first connection portion; a second connection portion; and a second intermediate interconnect. The stacked body includes a plurality of electrode layers. The first interconnect and the second interconnect are provided on the stacked body, and extend in a first direction crossing a stacking direction of the stacked body. The first intermediate interconnect is electrically connected to the first interconnect, the first columnar portion, and the second columnar portion. The second intermediate interconnect is provided at a height different from a height of the first intermediate interconnect, and is electrically connected to the second interconnect, the third columnar portion, and the fourth columnar portion.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: July 17, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hiroshi Nakaki
  • Patent number: 10020261
    Abstract: A first metal layer of a semiconductor device includes a plurality of first metal lines that each extend along a first axis, and a first rail structure that extends along the first axis. The first rail structure is physically separated from the first metal lines. A second metal layer is located over the first metal layer. The second metal layer includes a plurality of second metal lines that each extend along a second axis orthogonal to the first axis, and a second rail structure that extends along the first axis. The second rail structure is physically separated from the second metal lines. The second rail structure is located directly over the first rail structure. A plurality of vias is located between the first metal layer and the second metal layer. A subset of the vias electrically interconnects the first rail structure to the second rail structure.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: July 10, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Tien Wu, Hsiang-Wei Liu, Wei-Chen Chu
  • Patent number: 10007422
    Abstract: A steering wheel for a vehicle, including front and back semi-toroidal surfaces joined at their outer circumferences by a light guide in the shape of a circular rim, and enclosing a toroidal volume having a cavity therein, a PCB mounted in the cavity, an alternating array of invisible-light emitters and receivers mounted on the PCB, such that the light guide projects invisible-light beams emitted by the emitters radially outward of the steering wheel, and directs reflections of the projected light beams off of a driver's hands radially inward to the steering wheel toward the receivers, and a processor connected to equipment mounted away from the steering wheel, the processor synchronously activating each emitter with a respective neighboring receiver, identifying a driver's hand gestures along an arc of the light guide based on reflected light detected by the receivers, and controlling the equipment in response to the thus-identified hand gestures.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: June 26, 2018
    Assignee: Neonode Inc.
    Inventors: Gunnar Martin Fröjdh, Simon Fellin, Thomas Eriksson, John Karlsson, Maria Hedin, Richard Berglind
  • Patent number: 9997423
    Abstract: A semiconductor wafer has an array of integrated circuit dies formed on it. Each die is enclosed by a respective seal ring. Each die has a group of bond pads and test pads coupled to the bond pads. A test pad region is formed on the wafer. The test pad region has probe pads and common electrical interconnects that selectively electrically couple each of the probe pads to a bond pad on each of the dies. The common electrical interconnects in the test pad region reduce the possibility of probe damage to the integrated circuits and allow the dies to be tested concurrently before being cut from the wafer.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: June 12, 2018
    Assignee: NXP USA, INC.
    Inventor: Dewey Killingsworth
  • Patent number: 9972638
    Abstract: Three dimensional semiconductor memory devices and methods of fabricating the same are provided. According to the method, sacrificial layers and insulating layers are alternately and repeatedly stacked on a substrate, and a cutting region penetrating an uppermost sacrificial layer of the sacrificial layers is formed. The cutting region is filled with a non sacrificial layer. The insulating layers and the sacrificial layers are patterned to form a mold pattern. The mold pattern includes insulating patterns, sacrificial patterns, and the non sacrificial layer in the cutting region. The sacrificial patterns may be replaced with electrodes. The related semiconductor memory device is also provided.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: May 15, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sunghae Lee, Daehong Eom, JinGyun Kim, Daehyun Jang, Kihyun Hwang, Seongsoo Lee, Kyunghyun Kim, Chadong Yeo, Jun-Youl Yang, Se-Ho Cha
  • Patent number: 9972548
    Abstract: A method of proving inline characterization of electrical properties of a fin-shaped field effect transistor (finFET) is provided. Embodiments include applying an electrical current along a length of at least one fin of a finFET disposed over a wafer surface; generating a magnetic field across a width of the at least one fin, wherein the magnetic field is perpendicular in direction to the electrical current; and detecting electron flow concentrated at an upper portion of the at least one fin.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: May 15, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Carlos Strocchia-Rivera
  • Patent number: 9947752
    Abstract: A semiconductor device may include a semiconductor substrate, a first metal film covering a surface of the semiconductor substrate; a protection film covering a peripheral portion of a surface of the first metal film; and a second metal film covering a range extending across a center portion of the surface of the first metal film and a surface of the protection film, wherein a recess may be provided in the surface of the protection film, and a part of the second metal film may be in contact with an inner surface of the recess.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: April 17, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Akitaka Soeno
  • Patent number: 9940422
    Abstract: A method for reducing congestion regions of an integrated circuit is provided. A placement of the IC is obtained, wherein the placement includes a signal path between a first macro module and a second macro module. The signal path passes through a routing area of the placement for transmitting a specific signal. A congestion region of the routing area is identified. The signal path includes at least one cell or routing path in the congestion region. A cost evaluation is obtained for each candidate position of the routing area by moving the cell or the routing path out of the congestion region. The cell is moved to the candidate position having a minimum cost evaluation among the cost evaluations. The placement and the routing paths are simultaneously updated according to the cell moved to the candidate position having the minimum cost evaluation.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: April 10, 2018
    Assignee: MEDIATEK INC.
    Inventors: Chin-Hsiung Hsu, Chun-Chih Yang
  • Patent number: 9917253
    Abstract: Some embodiments include a memory array having a first series of access/sense lines which extend along a first direction, a second series of access/sense lines over the first series of access/sense lines and which extend along a second direction substantially orthogonal to the first direction, and memory cells vertically between the first and second series of access/sense lines. Each memory cell is uniquely addressed by a combination of an access/sense line from the first series and an access/sense line from the second series. The memory cells have programmable material. At least some of the programmable material within each memory cell is a polygonal structure having a sidewall that extends along a third direction which is different from the first and second directions. Some embodiments include methods of forming memory arrays.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: March 13, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Fabio Pellizzer
  • Patent number: 9893206
    Abstract: The present disclosure provides a TFT, an array substrate, their manufacturing methods, and a display device. A source electrode and a drain electrode of the TFT are each of a multi-layered structure including a metal layer and a metal barrier layer. An a-Si active layer of the TFT is covered with an etch stop layer, via-holes penetrating through the etch stop layer are provided at positions corresponding to the source electrode and the drain, and the source electrode and the drain electrode are connected to the a-Si active layer through the via-holes.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: February 13, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Yuliang Wang, Daeyoung Choi, Zengli Liu, Daojie Li, Fei Al, Jun Zhou
  • Patent number: 9870990
    Abstract: Methods for forming semiconductor structures are disclosed, including a method that involves forming sets of conductive material and insulating material, forming a first mask over the sets, forming a first number of contact regions, forming a second mask over a first region of the sets, and removing material from of the sets in a second, exposed region laterally adjacent the first region to form a second number of contact regions. Another method includes forming first and second contact regions on portions of sets of conductive materials and insulating materials, each of the second contact regions more proximal to an underlying substrate than each of the first contact regions. Apparatuses such as memory devices including laterally adjacent first and second regions each of which including contact regions of a different portion of a plurality of conductive materials and related methods of forming such devices are also disclosed.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: January 16, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Eric H. Freeman, Michael A. Smith
  • Patent number: 9865325
    Abstract: Provided is a memory device with a reduced layout area. The memory device includes a sense amplifier electrically connected to first and second wirings and positioned in a first layer, and first and second circuits positioned in a second layer over the first layer. The first circuit includes a first switch being turned on and off in accordance with a potential of a third wiring, and a first capacitor electrically connected to the first wiring via the first switch. The second circuit includes a second switch being turned on and off in accordance with a potential of a fourth wiring, and a second capacitor electrically connected to the second wiring via the second switch. The first wiring intersects the third wiring and does not intersect the fourth wiring in the second layer. The second wiring intersects the fourth wiring and does not intersect the third wiring in the second layer.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: January 9, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tatsuya Onuki
  • Patent number: 9853040
    Abstract: A semiconductor memory device according to an embodiment includes: a semiconductor substrate; a plurality of first insulating layers and first conductive layers stacked alternately in a first direction above the semiconductor substrate; a first semiconductor layer extending in the first direction; and a memory layer disposed between one of the first insulating layers and the first semiconductor layer and between one of the first conductive layers and the first semiconductor layer, the memory layer including a charge accumulation layer, the first semiconductor layer and the memory layer having a gap, between one of the first insulating layers and the first semiconductor layer, and the first semiconductor layer and the memory layer being contacted each other, between one of the first conductive layers and the first semiconductor layer.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: December 26, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tomoya Kawai, Tsutomu Tezuka
  • Patent number: 9853041
    Abstract: A semiconductor device includes a memory cell array including a vertical channel layer, two or more selection transistors, and a plurality of memory cells formed along the vertical channel; a peripheral circuit suitable for programming the two or more selection transistors and the memory cells; and a control circuit suitable for controlling the peripheral circuit to decrease a pass voltage applied to one word line adjacent to two or more selection lines coupled to the respective selection transistors, during a program operation in which the peripheral circuit applies a program voltage to the two or more selection lines and applies the pass voltage to a plurality of word lines connected to the memory cells.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: December 26, 2017
    Assignee: SK Hynix Inc.
    Inventor: Keon Soo Shim
  • Patent number: 9824174
    Abstract: Techniques for power-density-based clock cell spacing and resulting integrated circuits (ICs) are disclosed herein. In one example, the techniques determine power-usage density for different types of clock cells, as power-usage density relates to heat and IR droop. With the power-usage density for each type of clock cell determined, the techniques assign a keep-out region for each type of clock cell that is not fixed for all types of clock cells. These regions are instead based on the heat and IR droop corresponding to estimated power-usage density for each type of clock cell. Clock cells are then placed in a layout of an IC. The resulting IC has clock cells spaced sufficiently to reduce heat and IR droop while concurrently having excellent timing closure and performance.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: November 21, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Ankita Nayak, David Anthony Kidd, Paul Ivan Penzes
  • Patent number: 9818701
    Abstract: A semiconductor device includes wiring layers formed over a semiconductor wafer, a via-layer between the wiring layers, conductive films in the wiring layers, and a via-plug in the via-layer connecting the conductive films of the wiring layers above and below, a scribe region at an outer periphery of a chip region along an edge of the semiconductor substrate and including a pad region in the vicinity of the edge, the pad region overlapping the conductive films of the plurality of wiring layers in the plan view, the plurality of wiring layers including first second wiring layers, the conductive film of the first wiring layer includes a first conductive pattern formed over an entire surface of said pad region in a plan view, and the conductive film of the second wiring layer includes a second conductive pattern formed in a part of the pad region in a plan view.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: November 14, 2017
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Kazutaka Yoshizawa, Taiji Ema, Takuya Moriki
  • Patent number: 9793284
    Abstract: A method of controlling the thickness of gate oxides in an integrated CMOS process which includes performing a two-step gate oxidation process to concurrently oxidize and therefore consume at least a first portion of the cap layer of the NV gate stack to form a blocking oxide and form a gate oxide of at least one metal-oxide-semiconductor (MOS) transistor in the second region, wherein the gate oxide of the at least one MOS transistor is formed during both a first oxidation step and a second oxidation step of the gate oxidation process.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: October 17, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventor: Krishnaswamy Ramkumar
  • Patent number: 9748269
    Abstract: Transistor pillars have multiple transistor stacks of drain, source and gate rings. Layer fuses connect the rings to conductive layers surrounding the transistor pillars. In between individual transistor stacks are core fuses positioned along the transistor core columns. In one embodiment, layer fuses are fused prior to the core fuses. In a second embodiment, the core fuses may be fuse programmable separated by fusing currents applied preferably via top and bottom stripe layers immediately above and below the core fuses. A core fuse set current applied to predetermined core fuses via individual stripes above and below thermally disintegrates the core fuses. By selectively disintegrating core fuses independently from disintegrating layer fuses, a three dimensional logic circuitry architecture may be fuse programmed into a homogeneous original manufactured transistor pillar structure.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: August 29, 2017
    Inventor: Janusz Liberkowsky
  • Patent number: 9741731
    Abstract: A 3D stacked semiconductor structure is provided, comprising a plurality of stacks vertically formed on a substrate and disposed parallel to each other, a dielectric layer formed on the stacks, a plurality of conductive plugs independently formed in the dielectric layer; and a metal-oxide-semiconductor (MOS) layer formed on the dielectric layer. One of the stacks at least comprises a plurality of multi-layered pillars, and each of the multi-layered pillars comprises a plurality of insulating layers and a plurality of semiconductor layers arranged alternately. The MOS layer comprises a plurality of MOS structures connected to the conductive plugs respectively, and function as layer-selectors for selecting and decoding the to-be-operated layer.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: August 22, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Erh-Kun Lai, Yen-Hao Shih
  • Patent number: 9735104
    Abstract: A fuse structure includes a fusing line including a first portion, a second portion, and a central portion between the first portion and the second portion; and a dummy fuse neighboring the fusing line, the dummy fuse may include: a first air dummy fuse including a plurality of first air gaps extending in a first direction parallel to the fusing line; and a second air dummy fuse including a second air gap extending in a second direction crossing the fusing line.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: August 15, 2017
    Assignee: SK Hynix Inc.
    Inventors: Jae-Hong Kim, Seo-Woo Nam
  • Patent number: 9691884
    Abstract: Methods of making a monolithic three dimensional NAND string that include forming a stack of alternating first material layers and second material layers over a substrate, where each of the second material layers includes a layer of a first silicon oxide material between two layers of a second silicon oxide material different from the first silicon oxide material, etching the stack to form a front side opening in the stack, forming a memory film over a sidewall of the front side opening, and forming a semiconductor channel in the front side opening such that at least a portion of the memory film is located between the semiconductor channel and the sidewall of the front side opening, where at least one of an air gap or a material which has a dielectric constant below 3.9 is formed between the respective two layers of second silicon oxide material.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: June 27, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Raghuveer S. Makala, Yanli Zhang, Rahul Sharangpani, Yao-Sheng Lee, Senaka Krishna Kanakamedala, George Matamis, Johann Alsmeier
  • Patent number: 9673393
    Abstract: Some embodiments include a memory array having a first series of access/sense lines which extend along a first direction, a second series of access/sense lines over the first series of access/sense lines and which extend along a second direction substantially orthogonal to the first direction, and memory cells vertically between the first and second series of access/sense lines. Each memory cell is uniquely addressed by a combination of an access/sense line from the first series and an access/sense line from the second series. The memory cells have programmable material. At least some of the programmable material within each memory cell is a polygonal structure having a sidewall that extends along a third direction which is different from the first and second directions. Some embodiments include methods of forming memory arrays.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: June 6, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Fabio Pellizzer
  • Patent number: 9647449
    Abstract: An integrated circuit arrangement (100, 200, 600) has a first circuit part (102, 202, 602) which can be supplied with a first supply voltage (106, 206, 606), and a second circuit part (104, 204, 604) which can be supplied with a second supply voltage (108, 208, 608). The first circuit part and the second circuit part are arranged in a manner spatially separate from one another. The first circuit part has a first conduction element (110, 210, 310, 410, 610), and the second circuit part has a second conduction element (112, 212, 312, 412, 612). The integrated circuit arrangement also has a third conduction element (114, 214, 314, 414, 614), the third conduction element being arranged between the first conduction element and the second conduction element in such a manner that the third conduction element is arranged adjacent to the first conduction element and the third conduction element is also arranged adjacent to the second conduction element.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: May 9, 2017
    Assignee: Infineon Technologies AG
    Inventor: Markus Zannoth
  • Patent number: 9640357
    Abstract: There is provided an electronic device including a first member formed to include at least a part of a substrate material, a second member formed to include at least a part of the substrate material and configured to be relatively movable with respect to the first member, and a fuse configured to include at least a part of the substrate material and configured to electrically connect the first member to the second member via the substrate material.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: May 2, 2017
    Assignee: Sony Corporation
    Inventors: Mitsuo Hashimoto, Akira Akiba, Hideo Niikura, Satoshi Mitani, Shinya Morita, Kunihiko Saruta
  • Patent number: 9640229
    Abstract: A memory circuit includes a transistor, a signal line and a plurality of information lines. The transistor includes a first electrode, a second electrode and a control electrode. The transistor is included in a memory cell. The signal line is connected to the first electrode of the transistor. The voltage on the signal line is programmable. At most one of the information lines is connected to the second electrode of the transistor via a contact. Information stored in the memory cell is coded according to the voltage programmed on the signal line and an option of which information line the contact should connect to the second electrode of the transistor.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: May 2, 2017
    Assignee: MEDIATEK INC.
    Inventors: Dao-Ping Wang, Chia-Wei Wang
  • Patent number: 9620229
    Abstract: An integrated circuit includes a memory array, a wordline circuit, divided into at least two subcircuits, to control the memory array, and a bitline circuit, divided into at least two subcircuits, to control the memory array. The wordline subcircuits and the bitline subcircuits at least partially overlap separate respective regions of the memory array.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: April 11, 2017
    Assignee: Intel Corporation
    Inventors: Mark Helm, Jung Sheng Hoei, Aaron Yip, Dzung Nguyen
  • Patent number: 9620217
    Abstract: A method is provided for operating a NAND array that includes a plurality of blocks of memory cells. A block of memory cells in the plurality of blocks includes a plurality of NAND strings having channel lines between first string select switches and second string select switches. The plurality of NAND strings shares a set of word lines between the first and second string select switches. A channel-side erase voltage is applied to the channel lines through the first string select switches in a selected block. Word line-side erase voltages are applied to a selected subset including more than one member of the set of word lines shared by NAND strings in the selected block to induce tunneling in memory cells coupled to the selected subset, while tunneling is inhibited in memory cells coupled to an unselected subset including more than one member of the set of word lines.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: April 11, 2017
    Assignee: Macronix International Co., Ltd.
    Inventors: Hang-Ting Lue, Kuo-Pin Chang
  • Patent number: 9607893
    Abstract: Disclosed are embodiments of a method, wherein metal lines and vias of an integrated circuit IC) metal level of are formed without requiring separate cut masks to pattern the trenches for the metal lines and the via holes for the vias. Trenches are formed in an upper portion of a dielectric layer. Each trench is filled with a sacrificial material. A mask is formed above the dielectric layer and patterned with one or more openings, each opening exposing one or more segments of the sacrificial material in one or more of the trenches, respectively. A sidewall spacer is formed in each opening and a selective etch process is performed to form one or more via holes that extend through the sacrificial material and through the lower portion of the dielectric layer below. Subsequently, all the sacrificial material is removed and metal is deposited, thereby forming self-aligned metal lines and via(s).
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: March 28, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John H. Zhang, Carl J. Radens, Lawrence A. Clevenger
  • Patent number: 9589955
    Abstract: Systems on chips are provided. A system on chip (SoC) includes a first gate line, a second gate line and a third gate line extending in a first direction, a gate isolation region cutting the first gate line, the second gate line and the third gate line and extending in a second direction across the first direction, a first gate contact formed on the second gate line arranged between the first gate line and the third gate line, and electrically connecting the cut second gate line, a second gate contact formed on the first gate line, a third gate contact formed on the third gate line, a first metal line electrically connecting the second gate contact and the third gate contact, and a second metal line electrically connected to the first gate contact.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: March 7, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Hoon Baek, Sun-Young Park, Sang-Kyu Oh, Ha-Young Kim, Jung-Ho Do, Moo-Gyu Bae, Seung-Young Lee
  • Patent number: 9568960
    Abstract: A semiconductor structure includes a substrate with cooling layers, cooling channels, coolant inlets and outlets in fluid communication with the cooling channels, and a device layer on the cooling layers with one or more connection points and a device layer area. The device layer thermal coefficient of expansion is substantially equal to that of the cooling layers. A plurality of laminate substrates are disposed on, and electrically attached to, the device layer. The laminate substrate thermal coefficient of expansion differs from that of the device layer, each laminate substrate is smaller than the device layer portion to which it is attached, and each laminate substrate includes gaps between sides of adjacent laminate substrates. The laminate substrates are not electrically or mechanically connected to each other across the gaps therebetween and the laminate substrates are small enough to prevent warping of the device, interconnection and cooling layers due to thermal expansion.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: February 14, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Evan G. Colgan, Monty M. Denneau, John Knickerbocker
  • Patent number: 9564471
    Abstract: A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion and an end portion. At least some of the features extend farther in the horizontal direction in the end portion moving deeper into the stack in the end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Horizontally elongated openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend from the primary portion into the end portion, and individually laterally about sides of vertically extending portions of both the operative structures and the dummy structures.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: February 7, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Roger W. Lindsay, Krishna K. Parat
  • Patent number: 9559055
    Abstract: A semiconductor device includes a fuse element that can be cut and removed by laser irradiation. The fuse element has a large width portion having a large sectional area to be irradiated with a laser spot, and two small width portions having a small sectional area connected to opposite sides of the large width portion. Penetration of moisture is suppressed even after cutting of the fuse element since the large width portion is removed by the laser irradiation and only the small width portions having the small sectional area remain as exposed cut surfaces.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: January 31, 2017
    Assignee: SII Semiconductor Corporation
    Inventor: Yuichiro Kitajima
  • Patent number: RE46782
    Abstract: Controlling a power supply which supplies a voltage to target circuit of an integrated circuit. An adjustable delay line powered by the supply voltage is co-located on the IC with the target circuit. The adjustable delay line is subjected to substantially the same operating conditions as the target circuit. A control unit measures a delay time of the adjustable delay line. Based on the measured delay time, the control unit outputs a control signal by which the power supply adjusts the supply voltage. The adjustable delay line comprises multiple distinct delay elements, each with delay properties and responsivity to changes in operating conditions. Each delay element emulates delay properties of physical elements (e.g., gates and wires) in the target circuit. In this manner, power consumption may be reduced, while still maintaining proper operation of the target circuit.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: April 10, 2018
    Assignee: Marvell International Ltd.
    Inventors: Nir Paz, Mark N. Fullerton
  • Patent number: RE47251
    Abstract: A semiconductor memory having a memory cell structure capable of reducing soft error without complicating a circuit configuration. Specifically, an inverter (I1) consists of a NMOS transistor (N1) and a PMOS transistor (P1), and an inverter (I2) consists of a NMOS transistor (N2) and a PMOS transistor (P2). The inverters (I1, I2) are subjected to cross section. The NMOS transistor (N1) is formed within a P well region (PW0), and the NMOS transistor (N2) is formed within a P well region (PW1). The P well regions (PW0, PW1) are oppositely disposed with an N well region (NW) interposed therebetween.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: February 19, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Koji Nii