Abstract: A nonvolatile semiconductor memory device comprises a semiconductor substrate; a cell array block formed on the semiconductor substrate and including plural stacked cell array layers each with a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of via-holes extending in the stacked direction of the cell array layers to individually connect the first or second line in the each cell array layer to the semiconductor substrate. The via-holes are formed continuously through the plural cell array layers, and multiple via-holes having equal lower end positions and upper end positions are connected to the first or second lines in different cell array layers.

Abstract: A method of manufacturing a semiconductor memory device according to the embodiment includes: forming a first stacked-structure; forming a first stripe part and a first hook part at the first stacked-structure; forming a second stacked-structure on the first stacked-structure; forming a second stripe part and a second hook part at the second stacked-structure; repeating the above-described four steps for a certain number of times; and forming a contact plug contacting the first or second hook parts. The etching is conducted to remove the first stacked-structure in a region at which the second hook part is to be formed in the second stacked-structure higher than the first stacked-structure by one layer. The etching is conducted to remove the second stacked-structure in a region at which the first hook part is to be formed in the first stacked-structure higher than the second stacked-structure by one layer.

Abstract: A semiconductor device is provided. The semiconductor device includes: a substrate; device isolation regions formed in the substrate; an impurity region formed in a region of the substrate between every two adjacent ones of the device isolation regions; a gate electrode formed on the substrate; first and second interlayer insulating films sequentially formed on the substrate; a metal interlayer insulating film formed on the second interlayer insulating film and comprising metal wiring layers; a first contact plug electrically connecting each of the metal wiring layers and the impurity region; and a second contact plug electrically connecting each of the metal wiring layers and the gate electrode, wherein the first contact plug is formed in the first and second interlayer insulating films, and the second contact plug is formed in the second interlayer insulating film.

Abstract: Briefly, in accordance with one or more embodiments, multilayer memory device, comprising a lower deck and an upper deck disposed on the lower deck, the decks comprising one or more memory cells coupled via one or more contacts. An isolation layer is disposed between the upper deck, and one or more contacts are formed between the upper deck and the lower deck to couple one or more of the contact lines of the upper deck with one or more contact lines of the lower deck.

Abstract: A flat panel display includes a gate line, a data line, and a power supply line and a plurality of pixels connected to the lines, wherein each of the pixels includes a first thin film transistor that includes an active layer having a channel region, a source region, and a drain region and a bias supply layer in contact with the channel region so as to apply a voltage to the channel region of the first thin film transistor, wherein the bias supply layer of the first thin film transistor is connected to the power supply line.

Abstract: An integrated circuit chip includes a semiconductor substrate, a first circuit in or coupled to the semiconductor substrate, a second circuit device in or coupled the semiconductor substrate, a dielectric structure coupled the semiconductor substrate, a first interconnecting structure in the dielectric structure, a first pad connected to the first node of the voltage regulator through the first interconnecting structure, a second interconnecting structure in the dielectric structure, a second pad connected to the first node of the analog circuit through the second interconnecting structure, a passivation layer coupled the dielectric structure, wherein multiple openings in the passivation layer exposes the first and second pads, and a third interconnecting structure coupled the passivation layer and coupled the first and second pads.

Abstract: The present invention relates to a method of manufacturing a semiconductor device by which the length of nanowires perpendicularly formed can be fabricated with high reproducibility. The method of manufacturing a semiconductor device includes the steps of forming a first layer; forming a stop layer on the first layer, the stop layer having a higher Young's modulus than the first layer; forming a recess by partially removing the first layer and the stop layer; growing nanowires in the recess; forming a planarizing layer; removing the planarizing layer to the level of the stop layer to expose the nanowires from the surface of the planarizing layer; and forming an electrode so as to be in contact with the upper ends of the nanowires.

Abstract: A semiconductor device includes a semiconductor substrate having a diffusion region. A transistor is formed within the diffusion region. A power rail is disposed outside the diffusion region. A contact layer is disposed above the substrate and below the power rail. A via is disposed between the contact layer and the power rail to electrically connect the contact layer to the power rail. The contact layer includes a first length disposed outside the diffusion region and a second length extending from the first length into the diffusion region and electrically connected to the transistor.

Abstract: A semiconductor device includes conductive features within a gate electrode level region that are each fabricated from respective originating rectangular-shaped layout features having its centerline aligned parallel to a first direction. The conductive features form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and first NMOS transistor devices extend along a first gate electrode track. The gate electrodes of the second PMOS and second NMOS transistor devices extend along second and third gate electrode tracks, respectively. A first set of interconnected conductors electrically connect the gate electrodes of the first PMOS and second NMOS transistor devices. A second set of interconnected conductors electrically connect the gate electrodes of the second PMOS and first NMOS transistor devices.

Abstract: A semiconductor device includes conductive features within a gate electrode level region that are each fabricated from respective originating rectangular-shaped layout features having its centerline aligned parallel to a first direction. The conductive features form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS, second PMOS, first NMOS, and second NMOS transistor devices respectively extend along different gate electrode tracks. A first set of interconnected conductors electrically connect the gate electrodes of the first PMOS and second NMOS transistor devices. A second set of interconnected conductors electrically connect the gate electrodes of the second PMOS and first NMOS transistor devices. The first and second sets of interconnected conductors traverse across each other within different levels of the semiconductor device.

Abstract: According to one embodiment, an information recording/reproducing device including a semiconductor substrate, a first interconnect layer on the semiconductor substrate, a first memory cell array layer on the first interconnect layer, and a second interconnect layer on the first memory cell array layer. The first memory cell array layer comprises an insulating layer having an alignment mark, and a stacked layer structure on the insulating layer and including a storage layer and an electrode layer. All of the layers in the stacked layer structure comprises a material with a permeability of visible light of 1% or more.

Abstract: A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. Each of a number of conductive features within a gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature having a centerline aligned parallel to a first direction. The conductive features respectively form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and second NMOS transistor devices are electrically connected. The gate electrodes of the second PMOS and first NMOS transistor devices are electrically connected. The electrical connection between the gate electrodes of the first PMOS and second NMOS transistor devices is formed in part by one or more electrical conductors present within at least one interconnect level above the gate electrode level region.

Abstract: A memory cell 6 includes a M3 metal layer which incorporate continuous word lines 12 and power conductors formed of a plurality of separate power line sections 14 running parallel to the word lines. Interstitial gaps between the separate power line sections are larger in size than the power line sections themselves. The power line sections are disposed in a staggered arrangement either side of the word lines.

Abstract: Method of forming a semiconductor structure which includes forming first conductive spacers on a semiconductor substrate; forming second conductive spacers with respect to the first conductive spacers, at least one of the second conductive spacers adjacent to and in contact with each of the first conductive spacers to form combined conductive spacers; recessing the second conductive spacers with respect to the first conductive spacers so that the first conductive spacers extend beyond the second conductive spacers; depositing an ILD to cover the first and second spacers except for an exposed edge of the first conductive spacers; patterning the exposed edges of the first conductive spacers to recess the edges of the first conductive spacers in predetermined locations to form recesses with respect to the ILD; and filling the recesses with an insulating material to leave unrecessed edges of the first conductive spacers as vias to subsequent wiring features.

Abstract: An integrated circuit comprising an electromigration barrier includes a line, the line comprising a first conductive material, the line further comprising a plurality of line segments separated by one or more electromigration barriers, wherein the one or more electromigration barriers comprise a second conductive material that isolates electromigration effects within individual segments of the line.

Abstract: A method of forming a memory device includes forming a first interlayer insulating layer on a semiconductor substrate, forming a first electrode in the first interlayer insulating layer, the first electrode having a top surface of a rectangular shape extending in a first direction, and forming a variable resistance pattern on the first electrode, the variable resistance pattern having a bottom surface of a rectangular shape extending in a second direction crossing the first direction, the bottom surface of the variable resistance pattern contacting the first electrode, wherein the area of contact between the lower electrode and the variable resistance pattern is substantially equal to a multiplication of a minor axis length of a top surface of the first electrode and a minor axis length of a bottom surface of the variable resistance pattern.

Abstract: A semiconductor device or a memory which includes the same have a line pattern, and a contact plug, the line pattern including a first linear feature to which the contact plug is connected by design, and a second linear feature having a connecting portion and a dummy portion adjacent the location at which the contact plug is electrically connected to the first linear feature. A second contact plug is electrically connected to the connecting portion of the second linear feature of the line pattern. In the case of a misalignment error or the like, the first contact plug may also be electrically connected to the second linear feature of the line pattern but at the dummy portion thereof so as to not create a short circuit in that case. The dummy portion thus allows a sufficiently large process margin to be secured for the contact plug.

Abstract: Disclosed is a semiconductor device having a multilayer wiring structure, in which a dummy pattern is formed in a wiring void with favorable manufacturing efficiency. In a semiconductor device having a multilayer wiring structure, dummy pattern (21) is formed in relatively narrow wiring void (Area_S1) so as to extend in a direction different from that of dummy patterns (22, 23) formed in relatively wide wiring void (Area_S2).

Abstract: A signal routing grid. A first metal layer has wires running in a first direction. A second metal layer, spaced from and substantially parallel to the first metal layer, has wires running in a second direction different to the first direction, such that the wires of the first and second metal layers appear from above or below to form virtual intersections. Vias or contacts are coupled between the first and second metal layers and configured to route signals between the first and second metal layers. Pins are coupled to the first metal layer and configured to provide input signals or receive output signals from a standard cell, the pins being positioned along the wires in the first metal layer so as to be spaced from the virtual intersections.

Abstract: A semiconductor device including: a first mono-crystal layer and a second mono-crystal layer and at least one conductive layer in-between; where the at least one conductive layer includes a first conductive layer overlaying a second conductive layer overlying a third conductive layer, and where the second conductive layer having a predetermined second layer current carrying capacity greater than the current carrying capacity of the first conductive layer, and the second conductive layer current carrying capacity being greater than the current carrying capacity of the third conductive layer.

Abstract: A method of manufacturing an organic light-emitting display device includes forming a silicon layer and a gate insulating film over a substrate having a transistor region and a capacitor region; forming a halftone photoresist over the substrate; patterning the silicon layer and the gate insulating film; forming a residual photoresist by subjecting the halftone photoresist to an ashing process to leave part of the halftone photoresist over the transistor region; and doping at least a portion of the silicon layer with impurities by applying the impurities over an entire region of the substrate.

Abstract: A standard cell semiconductor integrated circuit device design provides a standard cell semiconductor device that includes first standard cells and user-defined target standard cells which consume more power or include other operational characteristics that differ from the operational characteristics of the first standard cells. The standard cells are routed to ground and power wires using one power rail and the target cells are routed to the ground and power lines using the first power rail and a second power rail to alleviate electromigration in either of the power rails. The two power rails include an upper power rail and a lower power rail. An intermediate conductive layer may be disposed between the upper and lower power rails to provide for signal routing by lateral interconnection between cells.

Abstract: Some embodiments include cross-point memory structures. The structures may include a line of first electrode material extending along a first horizontal direction, a multi-sided container of access device materials over the first electrode material, a memory element material within the multi-sided container, and a line of second electrode material over the memory element material and extending along a second horizontal direction that is orthogonal to the first horizontal direction. Some embodiments include methods of forming memory arrays. The methods may include forming a memory cell stack over a first electrode material, and then patterning the first electrode material and the memory cell stack into a first set of spaced lines extending along a first horizontal direction. Spaced lines of second electrode material may be formed over the first set of spaced lines, and may extend along a second horizontal direction that is orthogonal to the first horizontal direction.

Abstract: A display device according to an exemplary embodiment includes: gate wires, at least one of the gate wires having a first multi-layered structure including a first transparent conductive layer formed on the substrate and a first metal layer formed on the first transparent conductive layer and at least another one of the gate wires having a first single-layered structure formed with the first transparent conductive layer; a semiconductor layer formed on a part of the gate wires; and data wires with at least one of the data wires having a second multi-layered structure including a second transparent conductive layer formed on the semiconductor layer and a second metal layer formed on the second transparent conductive layer and at least another one of the data wires having a second single-layered structure formed with the second transparent conductive layer.

Abstract: A semiconductor device comprising a first semiconductor section including a first wiring layer at one side thereof, a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together with the respective first and second wiring layer sides of the first and second semiconductor sections facing each other, a conductive material extending through the first semiconductor section to the second wiring layer of the second semiconductor section and by means of which the first and second wiring layers are in electrical communication.

Abstract: Disclosed is a semiconductor device that is capable of preventing impurities such as moisture from being introduced into an active region at the time of dicing and at the time of bonding and that is capable of being easily miniaturized. The semiconductor device includes a cylindrical dummy wire having an opening for allowing a wire interconnecting a semiconductor element and an external connection terminal to pass therethrough, extending in an insulation film provided on a semiconductor layer having the semiconductor element to surround the semiconductor element, and disposed inside the external connection terminal.

Abstract: An integrated circuit includes four parallel positioned linear-shaped structures each including a gate electrode portion and an extension portion. Gate electrode portions of two of the four linear-shaped structures respectively form gate electrodes of first and second transistors of a first transistor type. Gate electrode portions of two of the four linear-shaped structures respectively form a gate electrodes of first and second transistors of a second transistor type. Four contacting structures are respectively connected to the extension portions of the four linear-shaped structures such that each extension portion has a respective contact-to-end distance. At least two of the contact-to-end distances are different. A fifth linear-shaped structure forms gate electrodes of transistors respectively positioned next to the first transistors of the first and second transistor types.

Abstract: A high voltage (HV) device includes a gate dielectric structure over a substrate. The gate dielectric structure has a first portion and a second portion. The first portion has a first thickness and is over a first well region of a first dopant type in the substrate. The second portion has a second thickness and is over a second well region of a second dopant type. The first thickness is larger than the second thickness. A gate electrode is disposed over the gate dielectric structure. A metallic layer is over and coupled with the gate electrode. The metallic layer extends along a direction of a channel under the gate dielectric structure. At least one source/drain (S/D) region is disposed within the first well region of the first dopant type.

Abstract: Embodiments of the invention describe compact memory arrays. In one embodiment, the memory cell array includes first, second, and third gate lines disposed over a substrate, the second gate lines are disposed between the first and the third gate lines. The first, the second, and the third gate lines form adjacent gate lines of the memory cell array. The memory cell array further includes first metal lines disposed over the first gate lines, the first metal lines coupled to the first gate lines; second metal lines disposed over the second gate lines, the second metal lines coupled to the second gate lines; and third metal lines disposed over the third gate lines, the third metal lines coupled to the third gate lines. The first metal lines, the second metal lines and the third metal lines are disposed in different metallization levels.

Abstract: An integrated circuit includes active circuitry disposed at a surface of a semiconductor body and an interconnect region disposed above the semiconductor body. A thermoelectric material is disposed in an upper portion of the interconnect region away from the semiconductor body. The thermoelectric material is configured to deliver electrical energy when exposed to a temperature gradient. This material can be used, for example, in a method for detecting the repackaging of the integrated circuit after it has been originally packaged.

Abstract: An image display panel includes a gate electrode; a gate insulating film over the gate electrode; a source electrode, a drain electrode, and a first adhesive on the gate insulating film; an organic semiconductor layer on the source and drain electrodes including a space; an interlayer insulating film covering the gate insulating film, source electrode, organic semiconductor layer, and part of the drain electrode; a conductive layer on the interlayer insulating film; a second adhesive formed over the interlayer insulating film and conductive layer; an image display medium on the second adhesive; an inorganic film on the image display medium and first adhesive; and a second substrate on the inorganic film, where the first adhesive is arranged outside the second adhesive between the display medium and the conductive layer, and forms bonding between the inorganic film and the gate insulating film having a hydrophilic treatment formed on the first substrate.

Abstract: A memory unit including a first transistor spanning a first transistor region in a first layer of the memory unit; a second transistor spanning a second transistor region in a second layer of the memory unit; a first resistive sense memory (RSM) cell spanning a first memory region in a third layer of the memory unit; and a second RSM cell spanning a second memory region in the third layer of the memory unit, wherein the first transistor is electrically coupled to the first RSM cell, and the second transistor is electrically coupled to the second RSM cell, wherein the second layer is between the first and third layers, wherein the first and second transistor have an transistor overlap region, and wherein the first memory region and the second memory region do not extend beyond the first transistor region and the second transistor region.

Abstract: A memory array includes a first layer, a second layer, a third layer and a contact. The first layer is disposed on a substrate. The second layer includes a first conductive line. The first conductive line includes first line segments and second line segments. Each of the second line segments are connected to a respective one of the first line segments. The first line segments extend in a first direction on the first layer. The second line segments extend in a second direction on the first layer. The first direction is different than the second direction. The third layer is disposed on the second layer. The contact is disposed through the second layer and connects the third layer to the first conductive line. One of the first line segments extends towards the contact. Each of the first and second line segments are at least a predetermined distance from the contact.

Abstract: In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-through layers 3 (4), to which a first layer wirings 11a, 11d (M1) are connected and, further, backing second layer wirings 12a to 12d are connected on the conductor plugs 13 (P1) to the first layer wirings 11s, 11d (M1).

Abstract: A semiconductor device that prevents the leaning of storage node when forming a capacitor having high capacitance includes a plurality of cylinder-shaped storage nodes formed over a semiconductor substrate; and support patterns formed to fix the storage nodes in the form of an ‘L’ or a ‘+’ when viewed from the top. This semiconductor device having support patterns in the form of an ‘L’ or a ‘+’ reduces stress on the storage nodes when subsequently forming a dielectric layer and plate nodes that prevents the capacitors from leaking.

Abstract: Electrical devices comprised of nanoscopic wires are described, along with methods of their manufacture and use. The nanoscopic wires can be nanotubes, preferably single-walled carbon nanotubes. They can be arranged in crossbar arrays using chemically patterned surfaces for direction, via chemical vapor deposition. Chemical vapor deposition also can be used to form nanotubes in arrays in the presence of directing electric fields, optionally in combination with self-assembled monolayer patterns. Bistable devices are described.

Abstract: A semiconductor memory device according to an embodiment includes a cell array block having a plurality of cell arrays stacked therein, each of the cell arrays including a plurality of memory cells and a plurality of selective wirings selecting the plurality of memory cells are stacked, a pillar-shaped first via extending in a stack direction from a first height to a second height and having side surfaces connected to a first wiring, and a pillar-shaped second via extending in the stack direction from the first height to the second height and having side surfaces connected to a second wiring upper than the first wiring, the second wiring being thicker in the stack direction than the first wiring and having a higher resistivity than the first wiring.

Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Abstract: Multilevel metallization layouts for an integrated circuit chip including transistors having first, second and third elements to which metallization layouts connect. The layouts minimize current limiting mechanism including electromigration by positioning the connection for the second contact vertically from the chip, overlapping the planes and fingers of the metallization layouts to the first and second elements and forming a pyramid or staircase of multilevel metallization layers to smooth diagonal current flow.

Abstract: To provide a structure of a semiconductor device that realizes an increase in a capacitor capacitance of a memory circuit to the maximum while inhibiting an increase in a contact resistance of a logic circuit, and a manufacture method thereof. When designating the number of layers of the local interconnect layers having wiring that makes up a logic circuit area as M and designating the number of layers of the local interconnect layers having wiring that makes up the memory circuit as N (M and N are natural numbers and satisfy M>N), capacitance elements are provided over the interconnect layers comprised of (M?N) layers or (M?N+1) layers.

Abstract: A three-dimensional (3D) integrated circuit (IC) structure includes a first layer of graphene formed over a substrate; a first level of one or more active devices formed using the first layer of graphene; an insulating layer formed over the first level of one or more active devices; a second layer of graphene formed over the insulating layer; and a second level of one or more active devices formed using the second layer of graphene, the second level of one or more active devices electrically interconnected with the first level of one or more active devices.

Abstract: A device includes a package component, and a metal trace on a surface of the package component. A first and a second dielectric mask cover a top surface and sidewalls of the metal trace, wherein a landing portion of the metal trace is located between the first and the second dielectric masks. The landing portion includes a first portion having a first width, and a second portion connected to an end of the first portion. The second portion has a second width greater than the first width, wherein the first and the second widths are measured in a direction perpendicular to a lengthwise direction of the metal trace.

Abstract: An integrated circuit memory device, in one embodiment, includes a substrate and first and second inter-level dielectric layers successively disposed on the substrate. One or more contacts in the peripheral extend through the first inter-level dielectric layer to respective components. One or more vias and a plurality of dummy vias extend through the second inter-level dielectric layer in the peripheral area. Each of the one or more peripheral vias extend to a respective peripheral contact. The peripheral dummy vias are located proximate the peripheral vias.

Abstract: A three-dimensional semiconductor device includes stacked structures arranged two-dimensionally on a substrate, a first interconnection layer including first interconnections and disposed on the stacked structures, and a second interconnection layer including second interconnections and disposed on the first interconnection layer. Each of the stacked structures has a lower region including a plurality of stacked lower word lines, and an upper region including a plurality of stacked upper word lines disposed on the stack of lower word lines. Each of the first interconnections is connected to one of the lower word lines and each of the second interconnections is connected to one of the upper word lines.

Abstract: Embodiments disclosed herein may relate to electrically conductive vias in cross-point memory array devices. In an embodiment, the vias may be formed using a lithographic operation also utilized to form electrically conductive lines in a first electrode layer of the cross-point memory array device.

Abstract: A standard cell semiconductor integrated circuit device design provides a standard cell semiconductor device that includes first standard cells and user-defined target standard cells which consume more power or include other operational characteristics that differ from the operational characteristics of the first standard cells. The standard cells are routed to ground and power wires using one power rail and the target cells are routed to the ground and power lines using the first power rail and a second power rail to alleviate electromigration in either of the power rails. The two power rails include an upper power rail and a lower power rail. An intermediate conductive layer may be disposed between the upper and lower power rails to provide for signal routing by lateral interconnection between cells.

Abstract: Embodiments of the invention describe compact memory arrays. In one embodiment, the memory cell array includes first, second, and third gate lines disposed over a substrate, the second gate lines are disposed between the first and the third gate lines. The first, the second, and the third gate lines form adjacent gate lines of the memory cell array. The memory cell array further includes first metal lines disposed over the first gate lines, the first metal lines coupled to the first gate lines; second metal lines disposed over the second gate lines, the second metal lines coupled to the second gate lines; and third metal lines disposed over the third gate lines, the third metal lines coupled to the third gate lines. The first metal lines, the second metal lines and the third metal lines are disposed in different metallization levels.

Abstract: A first wiring (1) has a bending portion (2), a first wiring region (1a) extending from the bending portion (2) in the X direction, and a second wiring region (1b) extending from the bending portion (2) in the Y direction. A via (3) is formed under the wiring (1). The via (3) is formed so as not to overlap with a region of the bending portion (2) in the first wiring region (1a). The length of the via (3) in the X direction (x) is longer than the length thereof in the Y direction (y) and both ends of the via (3) in the Y direction overlap with both ends of the first wiring region (1a) in the Y direction.

Abstract: An object is to provide a display device with a high aperture ratio or a semiconductor device in which the area of an element is large. A channel formation region of a TFT with a multi-gate structure is provided under a wiring that is provided between adjacent pixel electrodes (or electrodes of an element). In addition, a channel width direction of each of a plurality of channel formation regions is parallel to a longitudinal direction of the pixel electrode. In addition, when a channel width is longer than a channel length, the area of the channel formation region can be increased.

Abstract: A semiconductor device includes a conductive pattern formed on a substrate, a conductive land formed to come into contact with at least part of the top surface of the conductive pattern, and a conductive section formed on the conductive land. The conductive section is electrically connected through the conductive land to the conductive pattern.