Multi-level Metallization Patents (Class 257/211)
  • Patent number: 7372714
    Abstract: A memory structure includes a memory storage element electrically coupled to a control element. The control element comprises a tunnel-junction device. The memory storage element may also comprise a tunnel-junction device. Methods for fusing a tunnel-junction device of a memory storage element without fusing a tunnel-junction device of an associated control element are disclosed. The memory storage element may have an effective cross-sectional area that is greater than an effective cross-sectional area of the control element. A reference element comprising a tunnel-junction device may be used with a current source to fuse a memory storage element without fusing a tunnel-junction device of an associated control element. Methods of making the memory structure and using it in electronic devices are disclosed.
    Type: Grant
    Filed: July 26, 2006
    Date of Patent: May 13, 2008
    Inventors: Peter Fricke, Andrew L. Van Brocklin, James E. Ellenson
  • Patent number: 7372085
    Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
    Type: Grant
    Filed: September 19, 2005
    Date of Patent: May 13, 2008
    Inventor: Mou-Shiung Lin
  • Patent number: 7372155
    Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length-by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
    Type: Grant
    Filed: May 18, 2005
    Date of Patent: May 13, 2008
    Inventor: Mou-Shiung Lin
  • Patent number: 7372164
    Abstract: A semiconductor forming transistors on a semiconductor substrate includes a low concentration source/drain region formed in the semiconductor substrate, a high concentration source/drain region formed in the source/drain region, a gate electrode formed on the substrate through gate oxide film, a P type body region formed under the gate electrode and placed between the source/drain regions and, plug contact portions contacting the source/drain region and arranged in plural, and a source/drain electrode connecting to the source/drain region with contact through the contact portions.
    Type: Grant
    Filed: February 2, 2005
    Date of Patent: May 13, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yoshinori Hino, Naoei Takeishi, Toshimitsu Taniguchi
  • Publication number: 20080099790
    Abstract: A layout structure is provided with a conducting line extending in a conducting line direction, the conducting line being arranged within a substrate area, a fill element being arranged within the substrate area at a predetermined distance from the conducting line, the fill element having a fill element axis extending perpendicularly to a side of the fill element in a fill element direction, an angle between the conducting line direction and the fill element direction being greater than 0° and smaller than 90°.
    Type: Application
    Filed: October 27, 2006
    Publication date: May 1, 2008
    Inventors: Alexander Nielsen, Bernhard Dobler, Georg Georgakos
  • Patent number: 7365376
    Abstract: A semiconductor integrated circuit effectively makes use of wiring channels of wiring formed by a damascene method. When first cells are used, since the M1 power source lines are laid out at positions spaced away from a boundary between the cells, the power source lines are not combined in laying out a semiconductor integrated circuit. As a result, the width of the power source lines is not changed. Accordingly, an interval between the line and a line which is arranged close to the line, determined in response to a line width of the lines, can satisfy a design rule; and, hence, the reduction of the wiring channels can be obviated, whereby the supply rate of the wiring channels can be enhanced, and, further, the integrity of a semiconductor chip can be enhanced.
    Type: Grant
    Filed: September 14, 2006
    Date of Patent: April 29, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Masayuki Ohayashi, Takashi Yokoi
  • Patent number: 7358549
    Abstract: In accordance with the objectives of the invention a new method and structure is provided for the creation of multiple overlying layers of interconnect metal. A channel is reserved for the creation of via interconnects, no vias are placed on metal lines. The metal lines are stacked and parallel, whereby a space is provided between lines that is reserved for the creation of vias for layer interconnection. This structure can be repeated, the vias are placed on the therefore reserved channel, interconnections are provided to the interconnect traces.
    Type: Grant
    Filed: January 24, 2006
    Date of Patent: April 15, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Tzong-Shi Jan
  • Patent number: 7358610
    Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
    Type: Grant
    Filed: July 27, 2007
    Date of Patent: April 15, 2008
    Inventor: Mou-Shiung Lin
  • Publication number: 20080083937
    Abstract: Wiring of a PDP address driver IC is disclosed which affords an adequate permitted current capacity. In the PDP address driver IC that drives the PDP, a layer, in which a planar high voltage ground wiring layer and a planar high voltage power wiring layer are formed, is provided atop a layer in which planar high voltage ground wiring layers that supply a ground potential to the active element that is formed within the PDP address driver IC and in which planar high voltage power wiring layers that supply a source potential to the active element are formed. Accordingly, the PDP address driver IC can comprise an adequate permitted current capacity while maintaining a compact size and comprising a multiplicity of output bit portions.
    Type: Application
    Filed: September 25, 2007
    Publication date: April 10, 2008
    Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
    Inventors: Takahiro NOMIYAMA, Gen TADA, Yoshihiro SHIGETA
  • Patent number: 7355217
    Abstract: A transistor device structured such that the bulk, gate, drain, and source are all accessible from all four edges of the device is provided. The transistor is created with a four-metal CMOS process. A bulk connection can be made with Metal 1, which is all around the device. A gate connection can be made with Metal 2, which is all around the device. Additionally, a drain/source connection can be made with Metal 3, which is all around the device. A source/drain connection can be made with Metal 4, which is all around the device. The transistor structure may be used to create an array of transistors for a high power output stage, with the transistors arranged in a checkerboard pattern. The connections of each transistor are automatic by abutting edges of the transistors.
    Type: Grant
    Filed: November 22, 2005
    Date of Patent: April 8, 2008
    Assignee: National Semiconductor Corporation
    Inventor: Joerg Brand
  • Publication number: 20080079028
    Abstract: A semiconductor device is formed by providing a semiconductor substrate comprising a cell region, a peripheral circuit region, and a resistor region, forming a device isolation layer on the semiconductor substrate so as to define an active region, forming a first insulating layer and a polysilicon pattern on the active region of the peripheral circuit region, forming a second insulating layer, a charge storage layer, and a third insulating layer on the active region of the cell region, forming a conductive layer on the semiconductor substrate, and patterning the conductive layer to form conductive patterns on the third insulating layer of the cell region, the polysilicon pattern of the active region of peripheral circuit region, and the semiconductor substrate of the resistor region, respectively.
    Type: Application
    Filed: January 3, 2007
    Publication date: April 3, 2008
    Inventors: Jong-Sun Sel, Jung-Dal Choi
  • Patent number: 7352059
    Abstract: A low loss on-die interconnect structure includes first and second differential signal lines on one of the metal layers of a microelectronic die. One or more traces may also be provided on another metal layer of the die that are non-parallel (e.g., orthogonal) to the differential signal lines. Because the traces are non-parallel, they provide a relatively high impedance return path for signals on the differential signal lines. Thus, a signal return path through the opposite differential line predominates for the signals on the differential lines. In one application, the low loss interconnect structure is used within an on-die salphasic clock distribution network.
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: April 1, 2008
    Assignee: Intel Corporation
    Inventors: Frank O'Mahony, Mark A. Anders, Krishnamurthy Soumyanath
  • Patent number: 7352048
    Abstract: The present invention generally relates to filling of a feature by depositing a barrier layer, depositing a seed layer over the barrier layer, and depositing a conductive layer over the seed layer. In one embodiment, the seed layer comprises a copper alloy seed layer deposited over the barrier layer. For example, the copper alloy seed layer may comprise copper and a metal, such as aluminum, magnesium, titanium, zirconium, tin, and combinations thereof. In another embodiment, the seed layer comprises a copper alloy seed layer deposited over the barrier layer and a second seed layer deposited over the copper alloy seed layer. The copper alloy seed layer may comprise copper and a metal, such as aluminum, magnesium, titanium, zirconium, tin, and combinations thereof. The second seed layer may comprise a metal, such as undoped copper. In still another embodiment, the seed layer comprises a first seed layer and a second seed layer.
    Type: Grant
    Filed: February 22, 2005
    Date of Patent: April 1, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Hua Chung, Ling Chen, Jick Yu, Mei Chang
  • Publication number: 20080073673
    Abstract: The height H of several kinds of basic cell are made the same and several kinds of macro cell which have a length which is an integral multiplication of the height H of this basic cell, are prepared, the basic cell and macro cell are mixed and the circuit of a peripheral circuit is designed. A M0 wire of a first wiring layer which is formed on a semiconductor substrate is used as a wire used within a macro cell. The basic cell and the macro cell are connected by a M1 wire of a second wiring layer which is formed on the first wiring layer and a M2 wire M2 of a third wiring layer. The transistor layout of basic cells and macro cells is designed and verified in advance and stored in a cell library, and auto routing by a standard method may be carried out.
    Type: Application
    Filed: September 20, 2007
    Publication date: March 27, 2008
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Hitoshi SHIGA
  • Patent number: 7348640
    Abstract: A memory capable of reducing the memory cell size is provided. In this memory, a first gate electrode of a first selection transistor and a second gate electrode of a second selection transistor are provided integrally with a word line, and arranged to obliquely extend with respect to the longitudinal direction of a first impurity region on a region formed with memory cells and to intersect with the first impurity region on regions formed with the first selection transistor and the second selection transistor in plan view.
    Type: Grant
    Filed: August 16, 2005
    Date of Patent: March 25, 2008
    Assignee: Sanyo Electric Company, Ltd.
    Inventor: Kouichi Yamada
  • Publication number: 20080067554
    Abstract: A NAND flash memory device includes a plurality of stacked semiconductor layers, device isolation layer patterns disposed in predetermined regions of each of the plurality of semiconductor layers, the device isolation layers defining active regions, source and drain impurity regions in the active regions, a source line plug structure electrically connecting the source impurity regions, and a bit-line plug structure electrically connecting the drain impurity regions, wherein the source impurity regions are electrically connected to the semiconductor layers.
    Type: Application
    Filed: February 12, 2007
    Publication date: March 20, 2008
    Inventors: Jae-Hun Jeong, Ki-Nam Kim, Soon-Moon Jung, Jae-Hoon Jang
  • Publication number: 20080070401
    Abstract: A memory device and a method for fabricating the same provide a device capable of increasing or maximizing the performance of a microstructure device. The device includes: a plurality of word lines formed with a gap therebetween and extending in parallel with each other in a first direction of extension; and a bit line insulated from the plurality of word lines, intersecting the plurality of word lines and extending in a second direction of extension, a transition electrode portion of the bit line positioned in the gap and spaced apart from the plurality of word lines by a predetermined distance, the transition electrode portion of the bit line configured and arranged to be bent toward any one of the plurality of word lines in response to an electrical signal applied to at least one of the plurality of word lines.
    Type: Application
    Filed: March 23, 2007
    Publication date: March 20, 2008
    Applicant: Samsung Electronics Co., Ltd.
    Inventor: Jin-Jun Park
  • Patent number: 7345352
    Abstract: An insulating tube includes a underlying insulating film, a first sidewall insulating film disposed on the underlying insulating film, a second sidewall insulating film disposed on the underlying insulating film, opposite to the first sidewall insulating film so as to provide a cavity between the first and second sidewall insulating films having the same height as the first sidewall insulating film, and an upper insulating film provided over the first and second sidewall insulating films.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: March 18, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuyoshi Matsumura, Takahito Nakajima, Hiroshi Kawamoto, Mikie Miyasato, Yoshihiro Uozumi
  • Patent number: 7341891
    Abstract: A method for making a memory cell for reducing the cost and complexity of modifying a revision identifier (ID) or default register values associated with an integrated circuit (IC) chip, and a method for manufacturing the same. The cell, which may be termed a “Meta-Memory Cell” (MMCEL), is implemented on metal layers only and utilizes a dual parallel metal ladder structure which traverses and covers each metal and via layer from the bottom to the top of the metal layer structure of the chip. One of the metal ladders is connected to a power supply at the bottom metal layer, corresponding to a logic 1, and another metal ladder is connected to ground at the bottom metal layer, corresponding to a logic 0. The output of the MMCEL can thus be inverted at any metal or via layer and can be inverted as often as required. Significant cost savings are achieved because a revision ID or default register bits may be modified by altering only those metal layers where design changes are necessary.
    Type: Grant
    Filed: October 31, 2003
    Date of Patent: March 11, 2008
    Assignee: Broadcom Corporation
    Inventors: Manolito M Catalasan, Vafa J Rakshani, Edmund H Spittles, Tim Sippel, Richard Unda
  • Patent number: 7342314
    Abstract: The present invention provides a device having a useful structure which is arranged on a substrate and has a useful structure side edge. In addition, an auxiliary structure is arranged on the substrate adjacent to the useful structure, the auxiliary structure having an auxiliary structure side edge, wherein the useful structure side edge is opposite to the auxiliary structure side edge separated by a distance, and wherein the auxiliary structure useful structure distance is dimensioned such that a form of the useful structure side edge or a form of the substrate next to the useful structure side edge differs from a form in a device where there is no auxiliary structure.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: March 11, 2008
    Assignee: Infineon Technologies AG
    Inventors: Jens Bachmann, Klaus Goller, Dirk Grueneberg, Reiner Schwab
  • Patent number: 7332753
    Abstract: A process margin of an interconnect is to be expanded, to minimize the impact of vibration generated during a scanning motion of a scanning type exposure equipment. In a semiconductor device, the interconnect handling a greater amount of data (frequently used interconnect) is disposed in a same orientation such that the longitudinal direction of the interconnects is aligned with a scanning direction of a scanning type exposure equipment, in an interconnect layer that includes a narrowest interconnect or a narrowest spacing between the interconnects. Aligning thus the direction of the vibration with the longitudinal direction of the pattern can minimize the positional deviation due to the vibration.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: February 19, 2008
    Assignee: NEC Electronics Corporation
    Inventors: Yoshihisa Matsubara, Hiromasa Kobayashi
  • Patent number: 7332817
    Abstract: A die metallization and bump design/arrangement, and a die-package interface metallization and bump design/arrangement are described herein.
    Type: Grant
    Filed: July 20, 2004
    Date of Patent: February 19, 2008
    Assignee: Intel Corporation
    Inventor: Edward A. Burton
  • Patent number: 7330369
    Abstract: Systems and methods are disclosed to process a semiconductor substrate by fabricating a first layer on the substrate using semiconductor fabrication techniques; fabricating a second layer above the first layer having one or more NANO-bonding areas; self-assemblying one or more NANO-elements; and bonding the NANO-elements to the NANO-bonding areas.
    Type: Grant
    Filed: February 23, 2005
    Date of Patent: February 12, 2008
    Inventor: Bao Tran
  • Patent number: 7326973
    Abstract: A method is disclosed to make a hard-coded bit in an integrated circuit on a semiconductor chip changeable in any one and only one metal layer of the semiconductor chip. In one embodiment, the method further comprising fabricating a cell on each metal layer of the semiconductor chip and a logic circuitry on the semiconductor chip. The cells are coupled to the inputs of the logic circuitry. The output of the logic circuitry changes in response to a change in any single cell to cause the hard-coded bit to change.
    Type: Grant
    Filed: February 1, 2005
    Date of Patent: February 5, 2008
    Assignee: Intel Corporation
    Inventor: Maurice Velandia
  • Patent number: 7323727
    Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.
    Type: Grant
    Filed: March 8, 2007
    Date of Patent: January 29, 2008
    Assignees: Hitachi, Ltd., Texas Instruments Incorporated
    Inventors: Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William R. McKee, Jeffrey E. Koelling, Troy H. Herndon
  • Publication number: 20080017889
    Abstract: A wiring structure of a semiconductor device may include an insulation interlayer on a substrate, the insulation interlayer having a linear first trench having a first width and a linear second trench having a second width, the linear second trench being in communication with a lower portion of the linear first trench, the first width being wider than the second width, and a conductive layer pattern in the linear first and second trenches.
    Type: Application
    Filed: May 16, 2007
    Publication date: January 24, 2008
    Inventors: Young-Ho Koh, Byung-Hong Chung, Won-Jin Kim, Hyun Park, Ji-Young Min
  • Patent number: 7321139
    Abstract: A layout for a transistor in a standard cell is disclosed. The layout for a transistor includes an active region with at least one portion having a first edge and at least one portion having a second edge all perpendicular to a channel of the transistor; and a gate placed on top of the active region with a distance from an edge of the gate to the first edge being shorter than a distance from the edge of the gate to the second edge of the active region, wherein the active region is of a non-rectangular shape.
    Type: Grant
    Filed: May 26, 2006
    Date of Patent: January 22, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mi-Chang Chang, Liang-Kai Han, Huan-Tsung Huang, Wen-Jya Liang, Li-Chun Tien
  • Patent number: 7319270
    Abstract: An interconnect includes an opening formed in a dielectric layer. A conductive barrier is deposited in the opening, over which a first conductive layer is deposited. A conductive oxide is deposited over the first conductive layer, and a second conductive layer, formed from the same material as the first conductive layer, is deposited over the conductive liner.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: January 15, 2008
    Assignee: Infineon Technologies AG
    Inventors: Jingyu Lian, Chenting Lin, Nicolas Nagel, Michael Wise
  • Publication number: 20080001176
    Abstract: A structure, memory devices using the structure, and methods of fabricating the structure. The structure includes: an array of nano-fins, each nano-fin comprising an elongated block of semiconductor material extending axially along a first direction, the nano-fins arranged in groups of at least two nano-fins each, wherein ends of nano-fins of each adjacent group of nano-fins are staggered with respect to each other on both a first and a second side of the array; wherein nano-fins of each group of nano-fins are electrically connected to a common contact that is specific to each group of nano-fins such that the common contacts comprise a first common contact on the first side of the array and a second common contact on the second side of the array; and wherein each group of nano-fins has at least two gates that electrically control the conductance of nano-fins of the each group of nano-fins.
    Type: Application
    Filed: June 29, 2006
    Publication date: January 3, 2008
    Inventors: Kailash Gopalakrishnan, Rohit Sudhir Shenpy
  • Publication number: 20070296000
    Abstract: A method for manufacturing a semiconductor device, includes: partially forming an epitaxial growth stopper film on a single crystal semiconductor substrate; sequentially depositing a first semiconductor layer and a second semiconductor layer on the semiconductor substrate by an epitaxial growth process; forming a first groove penetrating through the second semiconductor layer and the first semiconductor layer on the semiconductor substrate, at a region inside from an outer peripheral portion of the epitaxial growth stopper film, by partially etching the second semiconductor layer and the first semiconductor layer; forming a support body film on an entire surface of the semiconductor substrate, so as to fill the first groove and cover the second semiconductor layer; forming a support body in a shape covering the second semiconductor layer from the first groove to an element region extending over the outer peripheral portion of the epitaxial growth stopper film, by partially etching the support body film; formi
    Type: Application
    Filed: June 15, 2007
    Publication date: December 27, 2007
    Applicant: Seiko Epson Corporation
    Inventor: Toshiki Hara
  • Patent number: 7309885
    Abstract: There are provided PRAMS having a plurality of active regions located vertically in sequence and methods of forming the same. The PRAM and the method provide an approach to rapidly changing phase in a phase change layer pattern with a given design rule. A semiconductor substrate defining at least one reference active region is prepared in a cell array region and a peripheral circuit region. Other semiconductor substrates on a vertical line passing a main surface of the reference active region are located in sequence. The other semiconductor substrates define other active regions, respectively. A lower cell gate pattern is formed on the semiconductor substrate of the reference active region, and upper cell gate patterns are disposed on the other semiconductor substrates of the other active regions, respectively.
    Type: Grant
    Filed: October 7, 2005
    Date of Patent: December 18, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hyun Park, Hyeong-Geun An, Su-Jin Ahn, Yoon-Jong Song, Hyung-Joo Youn, Kyu-Chul Kim
  • Patent number: 7307345
    Abstract: Various embodiments of the present invention are directed to crossbar array designs that interfaces wires to address wires, despite misalignments between electrical components and wires. In one embodiment, a nanoscale device may be composed of a first layer of two or more wires and a second layer of two or more address wires that overlays the first layer. The nanoscale device may also include an intermediate layer positioned between the first layer and the second layer. Two or more redundant electrical component patterns may be fabricated within the intermediate layer so that one or more of the electrical component patterns is aligned with the first and second layers.
    Type: Grant
    Filed: November 1, 2005
    Date of Patent: December 11, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Wei Wu, Philip J. Kuekes, R. Stanley Williams
  • Patent number: 7307293
    Abstract: A direct-connect signaling system including a printed circuit board and first and second integrated circuit packages disposed on the printed circuit board. A plurality of electric signal conductors extend between the first and second integrated circuit packages suspended above the printed circuit board.
    Type: Grant
    Filed: April 29, 2003
    Date of Patent: December 11, 2007
    Assignee: Silicon Pipe, Inc.
    Inventors: Joseph C. Fjelstad, Para K. Segaram, Belgacem Haba
  • Publication number: 20070267659
    Abstract: A chip-type electronic component includes a substrate, a common potential layer formed on an upper side of the substrate, an insulating film formed on the common potential layer, and provided to expose at least part of the common potential layer. At least one common potential electrode is provided on the exposed part of the common potential layer, and a plurality of conductors provided on the insulating film, each of the conductors forming a part of a thin-film circuit element. At least one columnar electrode is electrically connected to at least one of the conductors, and a sealing film is formed around the columnar electrode.
    Type: Application
    Filed: May 17, 2007
    Publication date: November 22, 2007
    Applicant: Casio Computer Co., Ltd.
    Inventor: Yutaka Aoki
  • Publication number: 20070267658
    Abstract: An image sensor and methods of fabricating the same are provided. An example method may include forming at least one gate on a substrate, forming first, second and third layers on the at least one gate, first etching the third layer with a first etching process, the second layer configured to be resistant to the first etching process, the first etching process reducing at least a portion of the third layer and exposing at least a portion of the second layer and second etching at least the exposed portion of the second layer with a second etching process other than the first etching process, the first layer configured to be resistant to the second etching process.
    Type: Application
    Filed: May 14, 2007
    Publication date: November 22, 2007
    Inventors: Jae-Ho Song, Jong-Chae Kim, Jong-Wook Hong, Keo-Sung Park
  • Patent number: 7294870
    Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
    Type: Grant
    Filed: May 4, 2005
    Date of Patent: November 13, 2007
    Inventor: Mou-Shiung Lin
  • Patent number: 7294871
    Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
    Type: Grant
    Filed: September 19, 2005
    Date of Patent: November 13, 2007
    Inventor: Mou-Shiung Lin
  • Patent number: 7291875
    Abstract: A semiconductor device comprising a first insulation layer, a second insulation layer, a first barrier film, a second barrier film, a diffusion layer. The device further comprises an upper contact hole, a lower contact hole, and a contact plug. The upper contact hole penetrates the second insulation layer and has a bottom in the second barrier film. The bottom has a width greater than a trench made in the first insulation layer, as measured in a direction crossing the widthwise direction of the trench. The lower contact hole penetrates the first insulation layer and first barrier film, communicates with the first contact hole via the trench and is provided on the diffusion layer. The upper portion of the lower contact hole has the same width as the trench. The contact plug is provided in the upper contact hole and lower contact hole.
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: November 6, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Sakuma, Yasuhiko Matsunaga, Fumitaka Arai, Kikuko Sugimae
  • Patent number: 7288786
    Abstract: During the creation of wiring plans for logic modules, the regions which are left free of interconnects by synthesis methods in upper metal planes are filled to a maximum degree with further interconnects. These interconnects serve to protect the integrated circuit. These further interconnects, depending on the availability of components for driving or evaluation, are embodied as sensor interconnects or else as connectionless interconnects only to confuse potential hackers.
    Type: Grant
    Filed: May 23, 2003
    Date of Patent: October 30, 2007
    Assignee: Infineon Technologies A.G.
    Inventor: Marcus Janke
  • Publication number: 20070246744
    Abstract: A method of manufacturing a coreless package substrate together with a conductive structure of the substrate is disclosed. The method can produce a coreless package substrate which comprises: at least a built-up structure having a first solder mask and a second solder mask, wherein a plurality of openings are formed in the first and second solder mask to expose the conductive pads of the built-up structure; and a plurality of solder bumps as well as solder layers formed on the conductive pads. Therefore, the invention can produce the coreless package substrate with high density of circuit layout, less manufacturing steps, and small size.
    Type: Application
    Filed: October 19, 2006
    Publication date: October 25, 2007
    Applicant: Phoenix Precision Technology Corporation
    Inventors: Bo-Wei Chen, Hsien-Shou Wang, Shih-Ping Hsu
  • Patent number: 7285862
    Abstract: The present invention includes the steps of forming a first resin film uncured on a wiring substrate including a wiring pattern, burying an electronic parts having a connection terminal on an element formation surface in the first resin film uncured in a state where the connection terminal is directed upward, forming a second resin film for covering the electronic parts, obtaining an insulation film by curing the first and second resin films by heat treatment, forming a via hole in a predetermined portion of the insulation film on the wiring pattern and the connection terminal, and forming an upper wiring pattern connected to the wiring pattern and the connection terminal through the via hole, on the insulation film.
    Type: Grant
    Filed: January 14, 2004
    Date of Patent: October 23, 2007
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Masahiro Sunohara, Kei Murayama, Mitsutoshi Higashi, Toshinori Koyama
  • Publication number: 20070235767
    Abstract: This document discloses an organic light emitting device comprising a first electrode and a wire comprising a contact part formed on a substrate, an insulating layer formed on the first electrode and a portion of the wire, the insulating layer comprising an opening which exposes a portion of the first electrode and a contact hole which exposes an entire upper surface of the contact part, an emission layer formed in the opening, a second electrode formed on the emission layer and the upper surface of the contact part though the contact hole.
    Type: Application
    Filed: December 27, 2006
    Publication date: October 11, 2007
    Inventor: Chun Tak Lee
  • Publication number: 20070235768
    Abstract: A semiconductor device includes: a semiconductor layer made of a group-III nitride semiconductor and having a first surface and a second surface opposed to the first surface; a Schottky electrode formed on the first surface of the semiconductor layer; and an ohmic electrode electrically connected to the second surface of the semiconductor layer. The semiconductor layer has, in at least the upper portion thereof, highly-resistive regions selectively formed to have a high resistance.
    Type: Application
    Filed: April 2, 2007
    Publication date: October 11, 2007
    Inventors: Kazushi Nakazawa, Hiroaki Ueno, Manabu Yanagihara, Yasuhiro Uemoto, Tsuyoshi Tanaka
  • Patent number: 7279787
    Abstract: A microelectronic complex including a body of semi-conductor material containing an integrated circuit, and a plurality of contact pads on the body for receiving signal conducting members for connection to an external substrate. The contact pads allow signals to be exchanged between the integrated circuit and the external substrate via the signal conducting members. A majority of the contact pads are disposed on the body of the microelectronic complex according to a configuration whereby the stress effects on the signal conducting members caused by thermal expansion mismatch between the microelectronic complex and the external substrate are minimized. In a specific configuration, a majority of the contact pads form a cluster circumscribing a predetermined area of the microelectronic complex body, whereby the cluster is characterized by a minimum inter-pad distance among the majority of contact pads on the body of the microelectronic complex.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: October 9, 2007
    Inventors: Richard S. Norman, David Chamberlain
  • Publication number: 20070228420
    Abstract: A nonvolatile semiconductor memory device is provided in such a manner that a semiconductor layer is formed over a substrate, a charge accumulating layer is formed over the semiconductor layer with a first insulating layer interposed therebetween, and a gate electrode is provided over the charge accumulating layer with a second insulating layer interposed therebetween. The semiconductor layer includes a channel formation region provided in a region overlapping with the gate electrode, a first impurity region for forming a source region or drain region, which is provided to be adjacent to the channel formation region, and a second impurity region provided to be adjacent to the channel formation region and the first impurity region. A conductivity type of the first impurity region is different from that of the second impurity region.
    Type: Application
    Filed: March 23, 2007
    Publication date: October 4, 2007
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tamae Takano, Shunpei Yamazaki
  • Publication number: 20070221958
    Abstract: A circuit board includes: a substrate; source and drain electrodes formed on the substrate; an organic semiconductor layer formed on the source and drain electrodes; a gate insulating layer formed on the organic semiconductor layer; and a gate electrode formed on the gate insulating layer, wherein: the substrate includes a first part, a second part, and a third part interposed between the first and second parts and a thickness of the first part or a thickness of the second part is greater than that of the third part; the source electrode is formed on the first part; the drain electrode is formed on the second part; a part of the organic semiconductor layer is formed on the third part; and a thickness of the gate insulating layer disposed on the first and second parts is smaller than that of the gate insulating layer disposed on the third part.
    Type: Application
    Filed: March 19, 2007
    Publication date: September 27, 2007
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Takashi AOKI
  • Patent number: 7271492
    Abstract: A photo mask set for forming multi-layered interconnection lines and a semiconductor device fabricated using the same includes a first photo mask for forming lower interconnection lines and a second photo mask for forming upper interconnection lines. The first and second photo masks have lower opaque patterns parallel with each other and upper opaque patterns that overlap the lower opaque patterns. In this case, ends of the lower opaque patterns are located on a straight line that crosses the lower opaque patterns. As a result, when upper interconnection lines are formed using the second photo mask, poor photo resist patterns can be prevented from being formed despite the focusing of reflected light.
    Type: Grant
    Filed: October 14, 2003
    Date of Patent: September 18, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Jin Kim, Seung-Hyun Chang, Ki-Heum Nam
  • Patent number: 7271017
    Abstract: An electroluminescent display device includes first and second substrates facing each other, data and gate lines crossing each other on the first substrate to define a plurality of pixel regions, a switching transistor connected to the gate and data lines, a driving transistor connected to the switching transistor, a dummy pattern on the first substrate, a connection electrode on the dummy pattern and connected to the driving transistor, a power line connected to the driving transistor, and an emitting diode on the second substrate and connected to the connection electrode.
    Type: Grant
    Filed: December 23, 2004
    Date of Patent: September 18, 2007
    Assignee: LG.Philips LCD Co., Ltd.
    Inventor: Jae-Yong Park
  • Patent number: 7268432
    Abstract: A method for forming an interconnect structure with nanocolumnar intermetal dielectric is described involving the construction of an interconnect structure using a solid dielectric, and introducing a regular array of vertically aligned nanoscale pores through stencil formation and etching to form a hole array and subsequently pinching off the tops of the hole array with a cap dielectric. Variations of the method and means to construct a multilevel nanocolumnar interconnect structure are also described.
    Type: Grant
    Filed: October 10, 2003
    Date of Patent: September 11, 2007
    Assignee: International Business Machines Corporation
    Inventors: Matthew E. Colburn, Satya V. Nitta, Sampath Purushothaman, Charles Black, Kathryn Guarini
  • Patent number: 7265396
    Abstract: A basic cell placed in a semiconductor device comprises a via contact placed on a wiring grid having a pitch narrower than a pitch between a contact placed in a source region and a contact placed in a drain region of a transistor in a basic cell, and a wiring layer connected to the via contact, being used as a source terminal, a drain terminal, and a gate terminal of the transistor.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: September 4, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Muneaki Maeno, Toshiki Morimoto, Hiroaki Suzuki