Abstract: This disclosure describes system(s) and/or method(s) enabling contacts for individual nanometer-scale-thickness layers of a multilayer film.

Abstract: In one aspect of the present invention, a semiconductor device may include an inter-wiring dielectric film in which a wiring trench is formed, a metal wiring layer formed in the wiring trench in the inter-wiring dielectric film, a first barrier layer formed on a side surface of the wiring trench, the first barrier layer being an oxide film made from a metal different from a main constituent metal element in the wiring layer, a second barrier layer formed on a side surface of the wiring layer, the second barrier layer having a Si atom of the metal used in the wiring layer, and a gap formed between the first barrier layer and the second barrier layer.

Abstract: A semiconductor device includes a plurality of signal lines which are arranged at a predetermined pitch; first and second MOS transistors which are connected to the signal lines, and also serially connected to each other; and a connection device which functions as a connection node between the serially-connected first and second MOS transistors, and connects a source area of one of the first and second MOS transistors to a drain area of the other of the first and second MOS transistors via contact holes, which are formed through an insulating layer, and a conduction layer connected to the contact holes.

Abstract: An SiC semiconductor device is provided, which comprises: a substrate made of silicon carbide and having a principal surface; a drift layer made of silicon carbide and disposed on the principal surface; an insulating layer disposed on the drift layer and including an opening; a Schottky electrode contacting with the drift layer through the opening; a termination structure disposed around an outer periphery of the opening; and second conductivity type layers disposed in a surface part of the drift layer, contacting the Schottky electrode, surrounded by the termination structure, and separated from one another. The second conductivity type layers include a center member and ring members. Each ring member surrounds the center member and is arranged substantially in a point symmetric manner with respect to the center member.

Abstract: A semiconductor memory includes a memory cell array area having a memory cell, a word line contact area adjacent to the memory cell array area, a word line arranged straddling the memory cell array area and the word line contact area, a contact hole provided on the word line in the word line contact area, and a word line driver connected to the word line via the contact hole. A size of the contact hole is larger than a width of the word line, and the lowest parts of the contact hole exist on a position lower than a top surface of the word line and higher than a bottom surface of the word line.

Abstract: N-ary three-dimensional mask-programmable read-only memory (N-3DMPROM) stores multi-bit-per-cell. Its memory cells can have N states (N>2) and data are stored as N-ary codes. N-3DMPROM has a larger storage density than the prior-art binary 3D-MPROM. One advantage of N-3DROM over other N-ary memory (e.g. multi-level-cell flash) is that its array efficiency can be kept high. N-3DMPROM could be geometry-defined, junction-defined, or a combination thereof.

Abstract: A semiconductor device is formed by providing a semiconductor substrate comprising a cell region, a peripheral circuit region, and a resistor region, forming a device isolation layer on the semiconductor substrate so as to define an active region, forming a first insulating layer and a polysilicon pattern on the active region of the peripheral circuit region, forming a second insulating layer, a charge storage layer, and a third insulating layer on the active region of the cell region, forming a conductive layer on the semiconductor substrate, and patterning the conductive layer to form conductive patterns on the third insulating layer of the cell region, the polysilicon pattern of the active region of peripheral circuit region, and the semiconductor substrate of the resistor region, respectively.

Abstract: A semiconductor memory device includes a first substrate having at least one string including a first select transistor, a second select transistor, and first memory cells connected in series between the first and second select transistors of the first substrate. The semiconductor memory device further includes a second substrate having at least one string including a first select transistor, a second select transistor, and second memory cells connected in series between the first and second select transistors of the second substrate. The number of the first memory cells of the at least one string of the first substrate is different from a number of the second memory cells of the at least one string of the second substrate. For example, the number of second memory cells may be less than the number of first memory cells.

Abstract: A semiconductor device includes a first interlayer insulating film formed above a semiconductor substrate, a first source line formed on the first interlayer insulating film, a second interlayer insulating film formed on the first source line, a plurality of bit lines formed on the second interlayer insulating film so as to extend in a direction, the bit lines being arranged at same width and same width, a third interlayer insulating film formed above the bit lines, a second source line formed on the third interlayer insulating film, and a source shunt line formed between the second and third interlayer insulating films, the source shunt line electrically connecting the first and second source lines to each other, the source shunt line being located between the bit lines so as to extend in the same direction as the bit lines, the source shunt line including a width same as the bit lines.

Abstract: In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another. The second bus has a size larger than a size of the first bus.

Abstract: A semiconductor device capable of improving the efficiency of dispersing heat via a dummy pad. The semiconductor device may be included in a semiconductor package, stack module, card, or system. Also disclosed is a method of manufacturing the semiconductor device. In the semiconductor device, a semiconductor substrate has a first surface and a second surface opposite to the first surface, and at least one conductive pad is arranged on a predetermined region of the first surface. At least one dummy pad is arranged on the first or second surface, and is not electrically coupled to the at least one conductive pad. The dummy pad or pads may be used to disperse heat. Accordingly, it is possible to increase the efficiency of dispersing heat of a semiconductor device, thereby improving the yield of semiconductor devices.

Abstract: The height H of several kinds of basic cell are made the same and several kinds of macro cell which have a length which is an integral multiplication of the height H of this basic cell, are prepared, the basic cell and macro cell are mixed and the circuit of a peripheral circuit is designed. A M0 wire of a first wiring layer which is formed on a semiconductor substrate is used as a wire used within a macro cell. The basic cell and the macro cell are connected by a M1 wire of a second wiring layer which is formed on the first wiring layer and a M2 wire M2 of a third wiring layer. The transistor layout of basic cells and macro cells is designed and verified in advance and stored in a cell library, and auto routing by a standard method may be carried out.

Abstract: It is an object of the present invention to provide a semiconductor integrated circuit having a chip layout that reduces line length to achieve faster processing. A cache comprises a TAG memory module and a cache data memory module. The cache data memory module is divided into first and second cache data memory modules which are disposed on both sides of the TAG memory module, and input/output circuits of a data TLB are opposed to the input/output circuit of the TAG memory module and the input/output circuits of the first and second cache data memory modules across a bus area to reduce the line length to achieve faster processing.

Abstract: A semiconductor device includes a first metal region, a plurality of vias, a plurality of second metal regions, a plurality of openings and a third metal region. The first metal region conducts source/drain current. The second metal regions are electrically connected to the first metal region through the vias for conducting the source/drain current, in which each of the second metal regions is disposed in a distance from the adjacent second metal regions. The third metal region is electrically connected to the second metal regions through the openings, in which the resistance of the third metal region is smaller than the resistances of the first metal region and the second metal regions.

Abstract: A non-volatile memory array includes a multiplicity of memory cells, each of whose area is less than 4 F2 per cell (where F is a minimum feature size), and periphery elements to control the memory cells. The present invention also includes a non-volatile memory array which includes word lines and bit lines generally perpendicular to the word lines, with a word line pitch of less than 2 F. In one embodiment, the word lines are made of polysilicon spacers.

Abstract: A semiconductor device is provided that includes a substrate, a static random access memory (SRAM) unit cell formed in the substrate, a first metal layer formed over the substrate, the first metal layer providing local interconnection to the SRAM unit cell, a second metal layer formed over the first metal layer, the second metal layer including: a bit line and a complementary bit line each having a first thickness and a Vcc line disposed between the bit line and the complementary bit line, and a third metal layer formed over the second metal layer, the third metal layer including a word line having a second thickness greater than the first thickness.

Abstract: Programmable metallization memory cells having a planarized silver electrode and methods of forming the same are disclosed. The programmable metallization memory cells include a first metal contact and a second metal contact, an ion conductor solid electrolyte material is between the first metal contact and the second metal contact, and either a silver alloy doping electrode separates the ion conductor solid electrolyte material from the first metal contact or the second metal contact, or a silver doping electrode separates the ion conductor solid electrolyte material from the first metal contact. The silver electrode includes a silver layer and a metal seed layer separating the silver layer from the first metal contact.

Abstract: Disclosed herein is an ASIC having a base array of function blocks. Each function block includes a plurality of primitive cells. Each primitive cell is defined by a component from a standard cell library. The base array is prefabricated for use later with a custom circuit design.

Abstract: A memory cell for reducing the cost and complexity of modifying a revision identifier (ID) or default register values associated with an integrated circuit (IC) chip, and a method for manufacturing the same. The cell, which may be termed a “Meta-Memory Cell” (MMCEL), is implemented on metal layers only and utilizes a dual parallel metal ladder structure that traverses and covers each metal and via layer from the bottom to the top of the metal layer structure of the chip. One of the metal ladders is connected to a power supply at the bottom metal layer, corresponding to a logic 1, and another metal ladder is connected to ground at the bottom metal layer, corresponding to a logic 0. The output of the MMCEL can thus be inverted at any metal or via layer and can be inverted as often as required. Significant cost savings are achieved because a revision ID or default register bits may be modified by altering only those metal layers where design changes are necessary.

Abstract: A method to form a vertical interconnect advantageous for high-density semiconductor devices. A conductive etch stop layer, preferably of cobalt silicide, is formed. The etch stop layer may be in the form of patterned lines or wires. A layer of contact material is formed on and in contact with the etch stop layer. The layer of contact material is patterned to form posts. Dielectric is deposited over and between the posts, then the dielectric planarized to expose the tops of the posts. The posts can serve as vertical interconnects which electrically connect a next conductive layer formed on and in contact with the vertical interconnects with the underlying etch stop layer. The patterned dimension of vertical interconnects formed according to the present disclosure can be substantially the same as the minimum feature size, even at very small minimum feature size.

Abstract: A memory cell for reducing the cost and complexity of modifying a revision identifier (ID) or default register values associated with an integrated circuit (IC) chip, and a method for manufacturing the same. The cell, which may be termed a “Meta-Memory Cell” (MMCEL), is implemented on metal layers only and utilizes a dual parallel metal ladder structure that traverses and covers each metal and via layer from the bottom to the top of the metal layer structure of the chip. One of the metal ladders is connected to a power supply at the bottom metal layer, corresponding to a logic 1, and another metal ladder is connected to ground at the bottom metal layer, corresponding to a logic 0. The output of the MMCEL can thus be inverted at any metal or via layer and can be inverted as often as required. Significant cost savings are achieved because a revision ID or default register bits may be modified by altering only those metal layers where design changes are necessary.

Abstract: The present invention discloses several preferred mask-programmable 3-D memory (3D-MPROM) structures, including pillar-shaped 3D-MPROM, natural-junction 3D-MPROM, interleaved 3D-MPROM, and separate 3D-MPROM. The present invention also makes further improvements to its peripheral circuits. The use of sense-amplifier can significantly lower the leakage-current requirement on the 3D-ROM memory cell. Self-timing can improve the 3D-ROM speed and reduce its power consumption.

Abstract: A manufacturing method of a silicon carbide semiconductor device includes the steps of: preparing a semiconductor substrate including a silicon carbide substrate, a drift layer and a first semiconductor layer; forming a plurality of first trenches in a cell portion; forming a gate layer on an inner wall of each first trench by an epitaxial growth method; forming a first insulation film on the surface of the semiconductor substrate; forming a gate electrode on the first insulation film for connecting to the gate layer electrically; forming a source electrode on the first insulation film for connecting to the first semiconductor layer in the cell portion; and forming a drain electrode connected to the silicon carbide substrate electrically.

Abstract: A semiconductor device wherein destruction of a sealing ring caused by cracking of an interlayer dielectric film is difficult to occur, as well as a method for manufacturing the semiconductor device, are provided. A first laminate comprises first interlayer dielectric films having a first mechanical strength. A second laminate comprises second interlayer dielectric films having a mechanical strength higher than the first mechanical strength. A first region includes first metallic layers and vias provided within the first laminate. A second region includes second metallic layers and vias provided within the second laminate. When seen in plan, the second region overlaps at least a part of the first region, is not coupled with the first region by vias, and sandwiches the second interlayer dielectric film between it and the first region.

Abstract: Programmable power management using a nanotube structure is disclosed. In one embodiment, a method includes coupling a nanotube structure of an integrated circuit to a conductive surface when a command is processed, and enabling a group of transistors of the integrated circuit based on the coupling the nanotube structure to the conductive surface. A current may be applied to the nanotube structure to couple the nanotube structure to the conductive surface. The nanotube structure may be formed from a material chosen from one or more of a polymer, carbon, and a composite material. The group of transistors may be enabled during an activation sequence of the integrated circuit. In addition, one or more transistors of the group of transistors may be disengaged from the one or more power sources (e.g., to minimize leakage) when the nanotube structure is decoupled from the conductive surface.

Abstract: An integrated semiconductor circuit has a regular array of logic function blocks (L) and a regular array of wiring zones (X) corresponding thereto. The wiring lines in at least one wiring layer of a wiring zone (X) are realized as line segments that are continuous within the wiring zone and are interrupted at zone boundaries. Furthermore, the semiconductor circuit comprises driver cells that surround a logic cell of the logic function block in an L-shaped manner.

Abstract: A semiconductor device comprising a plurality of semiconductor chips and a plurality of through-line groups is disclosed. Each of the through-line groups consists of a unique number of through-lines. The numbers associated with the through-line groups are mutually coprime to each other. When one of the through-lines is selected for the each through-line group, one of the semiconductor chip is designated by a combination of the selected through-lines of the plurality of the through-line groups.

Abstract: Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a pair of first bit lines and a pair of second bit lines. The first and second bit lines can be formed by an implant process using first and second spacers that have different lateral lengths from each other. The spacers can be used to offset the implants, thereby controlling the lateral lengths of the bit lines.

Abstract: A metal line of a semiconductor device comprising contact plugs, a plurality of first trenches, first metal lines, a plurality of second trenches, and second metal lines. The contact plugs are formed over a semiconductor substrate and are insulated from each other by a first insulating layer. The plurality of first trenches are formed in the first insulating layer and are connected to first contact plugs of the contact plugs. The first metal lines are formed within the first trenches and are connected to the first contact plugs. The plurality of second trenches are formed over the first metal lines and the first insulating layer and comprise a second insulating layer connected to second contact plugs of the contact plugs. The second metal lines are formed within the second trenches and are connected to the second contact plugs.

Abstract: Provided is a semiconductor device having a high-frequency interconnect, first dummy conductor patterns, an interconnect, and second dummy conductor patterns. The first dummy conductor patterns are arranged in the vicinity of the high-frequency interconnect, and the second dummy conductor patterns are arranged in the vicinity of the interconnect. The minimum value of distance between the high-frequency interconnect and the first dummy conductor patterns is larger than the minimum value of distance between the interconnect and the second dummy conductor patterns.

Abstract: A semiconductor device includes a substrate, on which an element region and a peripheral region are defined. At least one function element is to be provided in the element region, and the peripheral region surrounds the element region. The semiconductor device also includes a layer of wiring. The semiconductor device also includes a seal ring having a ring portion that is provided in the peripheral region in the same layer as the wiring layer. The ring portion has a main body surrounding a chip region, and a plurality of portions protruding toward the element region from the seal ring main body.

Abstract: A semiconductor memory device includes: a transistor formed in a substrate; a capacitor formed above one of source/drain regions of the transistor; a bit line formed above the substrate and extending in the gate length direction of the transistor; a first conductive plug connecting one of the source/drain regions and the capacitor; a second conductive plug connected to the other source/drain region that is not connected to the first conductive plug; and a third conductive plug formed on the second conductive plug and connected to the bit line. The central axis of the third conductive plug is displaced from the central axis of the second conductive plug in the gate width direction of the transistor.

Abstract: A semiconductor device comprising a first insulation layer, a second insulation layer, a first barrier film, a second barrier film, a diffusion layer. The device further comprises an upper contact hole, a lower contact hole, and a contact plug. The upper contact hole penetrates the second insulation layer and has a bottom in the second barrier film. The bottom has a width greater than a trench made in the first insulation layer, as measured in a direction crossing the widthwise direction of the trench. The lower contact hole penetrates the first insulation layer and first barrier film, communicates with the first contact hole via the trench and is provided on the diffusion layer. The upper portion of the lower contact hole has the same width as the trench. The contact plug is provided in the upper contact hole and lower contact hole.

Abstract: A method of forming air gaps within a solid structure is provided. In this method, a sacrificial material is covered by an overlayer. The sacrificial material is then removed through the overlayer to leave an air gap. Such air gaps are particularly useful as insulation between metal lines in an electronic device such as an electrical interconnect structure. Structures containing air gaps are also provided.

Abstract: Provided are a semiconductor device having a buried word line structure in which a gate electrode and a word line may be buried within a substrate to reduce the height of the semiconductor device and to reduce the degradation of the oxide layer caused by chlorine ions from the application of a TiN metal gate, and a method of fabricating the semiconductor device. The semiconductor device may comprise a semiconductor substrate defined by a device isolation layer and comprising an active region including a trench and one or more recess channels, a gate isolation layer on the surface of the trench, a gate electrode layer on the surface of the gate isolation layer, and a word line by which the trench may be buried on the surface of the gate electrode layer.

Abstract: Techniques for self assembly of macro-scale objects, optionally defining electrical circuitry, are described, as well as articles formed by self assembly. Components can be joined, during self-assembly by minimization of free energy, capillary attraction, or a combination.

Abstract: An edit structure is disclosed that allows the input of a logic gate to be changed by modifying any one of the metal and via masks that are used to form the metal interconnect structure. As a result, a first permanent logic state provided by a tie-in circuit can be changed to a second permanent logic state by modifying any one of the metal and via masks that are used to form the metal interconnect structure.

Abstract: Wiring of a PDP address driver IC is disclosed which affords an adequate permitted current capacity. In the PDP address driver IC that drives the PDP, a layer, in which a planar high voltage ground wiring layer and a planar high voltage power wiring layer are formed, is provided atop a layer in which planar high voltage ground wiring layers that supply a ground potential to the active element that is formed within the PDP address driver IC and in which planar high voltage power wiring layers that supply a source potential to the active element are formed. Accordingly, the PDP address driver IC can comprise an adequate permitted current capacity while maintaining a compact size and comprising a multiplicity of output bit portions.

Abstract: Programmable metallization memory cells having a first metal contact and a second metal contact with an ion conductor solid electrolyte material between the metal contacts. The first metal contact has a filament placement structure thereon extending into the ion conductor material. In some embodiments, the second metal contact also has a filament placement structure thereon extending into the ion conductor material toward the first filament placement structure. The filament placement structure may have a height of at least about 2 nm.

Abstract: A copper-topped interconnect structure allows the combination of high density design areas, which have low current requirements that can be met with tightly packed thin and narrow copper traces, and low density design areas, which have high current requirements that can be met with more widely spaced thick and wide copper traces, on the same chip.

Abstract: A layout structure is provided with a conducting line extending in a conducting line direction, the conducting line being arranged within a substrate area, a fill element being arranged within the substrate area at a predetermined distance from the conducting line, the fill element having a fill element axis extending perpendicularly to a side of the fill element in a fill element direction, an angle between the conducting line direction and the fill element direction being greater than 0° and smaller than 90°.

Abstract: Various systems and methods for implementing multi-mode semiconductor devices are discussed herein. For example, a multi-mode semiconductor device is disclosed that includes a device package with a number of package pins. In addition, the device includes a semiconductor die or substrate with at least two IO buffers. One of the IO buffers is located a distance from a package pin and another of the IO buffers is located another distance from the package pin. One of the IO buffers includes first bond pad electrically coupled to a circuit implementing a first interface type and a floating bond pad, and the other IO buffer includes a second bond pad electrically coupled to a circuit implementing a second interface type. In some cases, the floating bond pad is electrically coupled to the circuit implementing the second interface type via a conductive interconnect, and the floating bond pad is electrically coupled to the package pin.

Abstract: Embodiments of the present invention are directed to mixed-scale electronic interfaces, included in integrated circuits and other electronic devices, that provide for dense electrical interconnection between microscale features of a predominantly microscale or submicroscale layer and nanoscale features of a predominantly nanoscale layer. The predominantly nanoscale layer, in one embodiment of the present invention, comprises a tessellated pattern of submicroscale or microscale pads densely interconnected by nanowire junctions between sets of parallel, closely spaced nanowire bundles. The predominantly submicroscale or microscale layer includes pins positioned complementarily to the submicroscale or microscale pads in the predominantly nanoscale layer. Pins can be configured according to any periodic tiling of the microscale layer.

Abstract: The semiconductor device has a fuse and a fuse opening created above the fuse. The fuse is divided into a plurality of lines at a crossing portion where the fuse crosses with an edge of the fuse opening. The plurality of divided lines of the fuse 101 are in parallel with each other and in perpendicular to the edge of the fuse opening.

Abstract: A stacked memory includes at least two semiconductor layers each including a memory cell array. A transistor is formed in a peripheral circuit region of an uppermost semiconductor layer of the at least two semiconductor layers. The transistor is used to operate the memory cell array.

Abstract: Embodiments of the invention describe compact memory arrays. In one embodiment, the memory cell array includes first, second, and third gate lines disposed over a substrate, the second gate lines are disposed between the first and the third gate lines. The first, the second, and the third gate lines form adjacent gate lines of the memory cell array. The memory cell array further includes first metal lines disposed over the first gate lines, the first metal lines coupled to the first gate lines; second metal lines disposed over the second gate lines, the second metal lines coupled to the second gate lines; and third metal lines disposed over the third gate lines, the third metal lines coupled to the third gate lines. The first metal lines, the second metal lines and the third metal lines are disposed in different metallization levels.

Abstract: A semiconductor device having a multilayer structure, each layer including: a dummy pattern for ensuring a flatness thereof; a pad area in which a bonding pad is formed; an input-output circuit area in which an input-output circuit is formed, the input-output circuit area being adjacent to the pad area in plan view; and a dummy pattern confined area for forbidding an arrangement of the dummy pattern in every layer included in the semiconductor device, the dummy pattern confined area being provided between the pad area and the input-output circuit area in plan view.

Abstract: A semiconductor memory includes a plurality of active regions; a plurality of bit line contacts disposed on respective active regions; a plurality of first local lines formed in an island shape and in contact with upper surfaces of the plurality of bit line contacts; a plurality of first via contacts in contact with the upper surfaces of the plurality of first local lines and aligned in a direction parallel to the active regions; a first bit line in contact with one of the plurality of first via contacts and extending in a direction parallel to the active regions; and a plurality of second via contacts arranged above the first via contacts that are not in contact with the first bit line through respective second local lines.

Abstract: There is provided a semiconductor device and method of fabricating the same that employs an insulation film of a borazine-based compound to provided enhanced contact between a material for insulation and that for interconnection, increased mechanical strength, and other improved characteristics. The semiconductor device includes a first insulation layer having a recess with a first conductor layer buried therein, an etching stopper layer formed on the first insulation layer, a second insulation layer formed on the etching stopper layer, a third insulation layer formed on the second insulation layer, and a second conductor layer buried in a recess of the second and third insulation layers. The second and third insulation layers are grown by chemical vapor deposition with a carbon-containing borazine compound used as a source material and the third insulation layer is smaller in carbon content than the second insulation layer.

Abstract: A semiconductor memory device is constructed to include a memory cell formed by a plurality of transistors, wherein each of gate wiring layers of all of the transistors forming the memory cell is arranged to extend in one direction.