Abstract: A pattern of voids in an integrated circuit having a first layer, a first layer surface and adjacent lands on the first layer surface, the adjacent lands enclosing spaces and including a second layer of a first isolation material and a third layer of a second isolation material arranged on the second layer. The pattern of voids has a fourth layer of a third isolation material which closes off at least some of the spaces and cannot be deposited on the first isolation material. The fourth layer is arranged on the third layer and has a second layer surface. Spaces that are not closed off by means of the fourth layer are filled with electrically conductive material. In the method for producing a pattern of voids in an integrated circuit, a second layer of a first isolation material is applied to a first layer surface of a first layer. A third layer of a second isolation material is applied to the second layer, the third layer acquiring a second layer surface which is arranged parallel to the first layer surface.

Abstract: A method for manufacturing a semiconductor substrate includes: forming an element isolation layer on a semiconductor base material for separating an element region from the other regions; forming a first semiconductor layer on the semiconductor base material; forming a second semiconductor layer on the first semiconductor layer, the second semiconductor layer having an etching selection ratio smaller than that of the first semiconductor layer; forming support holes by removing portions of the first semiconductor layer and the second semiconductor layer, the portions corresponding to regions for the support holes; forming a support forming layer on the semiconductor base material such that the support holes and the second semiconductor layer are covered by the support forming layer; forming exposed surfaces such that portions of the support forming layer other than a region including the support holes and the element region are etched to expose a support and portions of end portions of the first semiconductor

Abstract: Methods of supplying voltages to integrated circuits are provided. A high voltage VddH and/or a low voltage VddL can be supplied to a filler cell and routed to other cells. Each of the VddH and VddL is carried by one of a first voltage supply wire and a second voltage supply wire. A voltage routing wire routes desired voltage(s) to a filler cell. The first and the second voltage supply wires are preferably formed parallel to the voltage routing wire with their edges substantially aligned to the edges of the voltage routing wire. Vias are made to route the desire voltage. Also preferably, the first voltage supply wire is an M1 wire formed outside the filler cell while the second voltage supply wire is an M2 wire formed inside the filler cell.

Abstract: The memory cell matrix encompasses (a) a plurality device isolation films running along column direction, (b) first conductive layers arranged along row and column-directions, adjacent groups of the first conductive layers are isolated from each other by the device isolation film disposed between the adjacent groups, (c) lower inter-electrode dielectrics arranged respectively on crests of the corresponding first conductive layers, (d) an upper inter-electrode dielectric arranged on the lower inter-electrode dielectric made of insulating material different from the lower inter-electrode dielectrics, and (e) second conductive layers running along the row-direction, arranged on the upper inter-electrode dielectric.

Abstract: A semiconductor device includes: a semiconductor layer formed on a semiconductor substrate by performing epitaxial growth; a first buried insulating layer which is buried in the first region under the semiconductor layer; and a second buried insulating layer which is buried in the second region under the semiconductor layer in the position lower than the first buried insulating layer.

Abstract: A plurality of conductive layers and a plurality of wiring layers connecting a supporting substrate having SOI structure and uppermost wire are formed along a peripheral part of a semiconductor chip together with the uppermost wire, to thereby surround a transistor forming region in which a transistor is to be formed.

Abstract: A DDR SDRAM where unidirectional row logic is associated with and connected to a single memory array instead of being associated with and connected to multiple memory arrays. The unidirectional row logic is located in the outward periphery of its associated array, but is not within a throat region between two arrays. The location of the row logic allows the throat region to include more bidirectional IO circuitry and signal lines servicing two arrays, which increases the performance of the SDRAM. In addition, separate power bussing is employed for the memory arrays and IO circuitry. This prevents noise from the arrays from affecting the IO circuitry and signal lines of the throat region and vice versa.

Abstract: A chip package is provided. The chip package includes at least one chip, an interconnection structure, a plurality of second pads and at least one panel-shaped component, wherein the chip includes a plurality of first pads on a surface thereof. The interconnection structure is disposed on the chip, and the first pads of the chip are electrically coupled to the interconnection structure. The second pads are disposed on the interconnection structure, and the panel-shaped component is embedded in the interconnection structure. The panel-shaped component also includes a plurality of electrodes on its two opposite surfaces, and the second pads are electrically coupled to the first pads of the chip through the interconnection structure and the panel-shaped component.

Abstract: DRAM devices include a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction and intersecting the word lines. A plurality of active regions is provided that are electrically coupled to the word lines and the bit lines. Each of the active regions defines a single unit memory cell having an area of 6F2 in terms of a minimum line width F. Each of the active regions may be overlapped by only one word line and the active regions may be defined by an isolation region.

Abstract: A method for fabricating an in-plane switching LCD device includes forming a data line and a light-shielding layer on a substrate, forming a pixel electrode line and an active region with a polycrystalline silicon thin film, forming a first insulating layer on the substrate, forming a gate electrode and a common electrode line on the first insulating layer, forming a second insulating layer on the substrate, forming a first contact hole that exposes at least portions of the data line and the active region, and forming a connection electrode that connects at least portions of the exposed data line and the active region.

Abstract: A transistor array is self-protected from an electrostatic discharge (ESD) event which can cause localized ESD damage by integrating an ESD protection device into the transistor array. The ESD protection device operates as a transistor during normal operating conditions, and provides a low-resistance current path during an ESD event.

Abstract: A power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device. An embodiment describes the routing of a shield mesh of both power and ground lines to remove noise created by capacitive and inductive coupling. Relatively long signal lines are routed in between fully connected power and ground shield mesh which may be generated by a router during the signal routing phase or during power mesh routing phase. Leaving only the odd tracks or the even tracks for signal routing, power mesh (VDD) and ground mesh (VSS) are routed and fully interconnected leaving shorter segments and thereby reducing the RC effect of the circuit device. Another embodiment presents a technique where the signals are shielded using the power and ground mesh for a gridless routing. Another embodiment presents a multi-layer grid routing technique where signals are routed on even grid and the power and ground lines are routed on odd grid.

Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.

Abstract: A semiconductor memory device includes a first wiring layer, a second wiring layer, a memory cell, and a contact plug. The first wiring layer is formed in an interlayer insulating film. The second wiring layer is formed on the interlayer insulating film. The memory cell includes a first ferromagnetic film formed on the second wiring layer, a tunnel barrier film formed on the first ferromagnetic film, and a second ferromagnetic film formed on the tunnel barrier film. The contact plug is formed on the first wiring layer and connects the first wiring to the second wiring layer, and the upper surface of the contact plug is in a position higher than that of the second wiring layer.

Abstract: An electronic structure having a first conductive layer provided by a dual damascene fabrication process; an etch-stop layer provided by the fabrication process, and electrically coupled with the first conductive layer, the etch-stop layer having a preselected dielectric constant and a predetermined geometry; and a second conductive layer, electrically coupled with the etch-stop layer. The structure can be, for example, a metal-insulator-metal capacitor, an antifuse, and the like.

Abstract: A memory device cell layout, a computer system comprising a memory device having a particular cell layout, and methods of fabricating static memory cells and semiconductor devices embodying the cells are also provided. In accordance with one embodiment of the present invention, a memory device cell layout is provided comprising four active areas positioned between selected ones of the gates and local interconnects associated with different damascene trenches of the device.

Abstract: A method for forming a divot free nitride lined shallow trench isolation (STI) feature including providing a substrate including an STI trench extending through an uppermost hardmask layer into a thickness of the substrate exposing the substrate portions; selectively forming a first insulating layer lining the STI trench over said exposed substrate portions only; backfilling the STI trench with a second insulating layer; planarizing the second insulating layer; and, carrying out a wet etching process to remove the uppermost hardmask layer.

Abstract: A semiconductor integrated circuit device has a plurality of CMOS-type base cells arranged on a semiconductor substrate and m wiring layers, and gate array type logic cells are composed of the base cells and the wiring layers. Wiring within and between the logic cells is constituted by using only upper n (n<m) wiring layers. It becomes possible to shorten a development period and reduce a development cost when a gate array type semiconductor integrated circuit device becomes large in scale.

Abstract: Well bias circuitry for selectively biasing the voltages of the well areas of an integrated circuit. In one embodiment, the well bias circuitry includes a switching cell located in a row of cells of the integrated circuit for selectively coupling a voltage supply line to a well bias line. The switching cell may include two level shifters, each for providing a voltage to a gate of a coupling transistor to make the coupling transistor non conductive in response to an enable signal. The switching cells may be sequentially coupled such that the coupling transistors of each of the switching cells are not made conductive at the same time so as to reduce inrush current due to changing the well bias from a well bias voltage to a supply voltage. In one example, the switching cells may include delay circuitry for delaying the change in state of the enable signal before being provided to the next switching cell.

Abstract: A semiconductor device and a production method thereof capable of reducing warps of a semiconductor wafer when packaging at a wafer level in a SiP type semiconductor device, is configured that an insulating layer is formed by stacking a plurality of resin layers on a semiconductor chip formed with an electronic circuit, wiring layers are buried in the insulating layer and electrically connected to electrodes, and formation areas of the plurality of resin layers become gradually smaller from an area of an upper surface of the semiconductor chip as they get farther from the semiconductor chip, so that a side surface and an upper surface of each of the resin layers and the upper surface of the semiconductor chip form a stepwise shape.

Abstract: A multilayered substrate for a semiconductor device, which has a multilayered substrate body formed of a plurality sets of a conductor layer and an insulation layer, and having a face for mounting a semiconductor element thereon and another face for external connection terminals, the face for mounting a semiconductor device being provided with pads through which the substrate is connected to a semiconductor element to be mounted thereon, and the face for external connection terminals being provided with pads through which the substrate is connected to an external electrical circuit, wherein a reinforcing sheet is respectively joined to the face for mounting a semiconductor element thereon and the face for external connection terminals of the multilayered substrate body.

Abstract: A semiconductor device includes a substrate having first and second device regions separated from each other by a device isolation region, a first field effect transistor having a first polysilicon gate electrode and formed in the first device region, a second field effect transistor having a second polysilicon gate electrode and formed in the second device region, a polysilicon pattern extending over the device isolation region from the first polysilicon gate electrode to the second polysilicon gate electrode, and a silicide layer formed on a surface of the first polysilicon gate electrode, a surface of said the polysilicon gate electrode and a surface of the polysilicon pattern so as to extend on the polysilicon pattern from the first polysilicon gate electrode to the second polysilicon gate electrode, the silicide layer having a region of increased film thickness on the polysilicon pattern, wherein the silicide layer has a surface protruding upward in the region of increased film thickness.

Abstract: A semiconductor device capable of effectively eliminating noise on multilayered power lines with a bypass capacitor. A first power line is connected to the bypass capacitor. A second power line is a line from which a part located above the bypass capacitor is removed. Contacts connect the first and second power lines. Therefore, noise appearing on the second power line travels to the first power line, resulting in effectively eliminating the noise with the bypass capacitor.

Abstract: The present invention provides a three-dimensional memory (3D-M) system-on-a-chip (SoC). It takes full advantage of the difference in the number of interconnect levels between the embedded processor (eP) and embedded memory (eM) in an SoC chip. The un-used interconnect space on top of the eM block is converted into 3D-M. This conversion incurs minimum additional cost, but with significant benefits: 3D-M can add a large storage capacity to the SoC chip and therefore the chip becomes more powerful.

Abstract: A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region. The bond pad-wiring pattern is formed substantially in a center region of the semiconductor substrate. Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced and an MCP can be fabricated without the problems mentioned above.

Abstract: A semiconductor device is the semiconductor device which includes more than one field effect transistor having a gate electrode to which an electrical interconnect wire is connected and a gate insulation film with a thickness of 6.0 nm or less and which comprises a first transistor group made up of a plurality of field effect transistors that are the same in thickness of gate insulation film, a second transistor group made up of a plurality of field effect transistors that are the same in thickness of gate insulation film with the thickness of gate insulation film being less than the thickness of the gate insulation film of the first transistor group, and a semiconductor substrate on which the first and second transistor groups are mounted together in a mixed manner, wherein an antenna ratio which is a ratio of the area of a wire to the gate area of a gate electrode is such that the maximum value of the second transistor group is greater than the maximum value of the first transistor group.

Abstract: To prevent short-circuit due to contact of bonding wires each other and to make a semiconductor device compact. A semiconductor chip with a rectangular main surface may comprise: a first side composing the main surface; a second side opposed to the first side; a main electrode pad group composed of a plurality of main electrode pads, which plurality of main electrode pads is arranged on the main surface along the first side; a first electrode pad group composed of a plurality of first electrode pads, which plurality of first electrode pads is arranged between the first side and the main electrode pad group; a second electrode pad group composed of a plurality of second electrode pads, which plurality of second electrode pads is arranged on the main surface along the second side; a first interconnection connecting the main electrode pad with the first electrode pad; and a second interconnection connecting the main electrode pad with the second electrode pad.

Abstract: A memory includes an insulating layer; a plurality of spaced-apart semiconductor lines formed on the insulating layer; and a plurality of spaced-apart conductive gate lines formed on the insulating layer. Each of the gate lines is disposed to intersect the plurality of semiconductor lines at a plurality of intersections. The semiconductor lines include a plurality of body regions disposed at the intersections, with each of the body regions including a channel formed from a silicon carbide material.

Abstract: A method of forming a magneto-resistive memory element includes forming a groove in a layer of insulating material. A liner is formed conformably within the groove and the groove is filled with copper and then planarized. The electrically conductive material is provided an upper surface that is recessed relative to the upper surface of the layer of insulating material. A cap, which can be conductive (e.g., Ta) or resistive (e.g., TiAIN), is disposed over the electrically conductive material and within the groove. A surface of the cap that faces away from the electrically conductive material, is formed with an elevation substantially equal to that of the edge of the liner, or the cap can extend over the liner edge. At least one layer of magneto-resistive material is disposed over a portion of the cap. Advantageously, the cap can protect the copper line from harmful etch processes required for etching a MRAM stack, while keeping the structure planar after CMP.

Abstract: A memory structure includes a memory storage element electrically coupled to a control element. The control element comprises a tunnel-junction device. The memory storage element may also comprise a tunnel-junction device. Methods for fusing a tunnel-junction device of a memory storage element without fusing a tunnel-junction device of an associated control element are disclosed. The memory storage element may have an effective cross-sectional area that is greater than an effective cross-sectional area of the control element. A memory structure comprises a memory storage element, a control element comprising a tunnel-junction device electrically coupled to the memory storage element and configured to control the state of the memory storage element, and a reference element. The reference element is configured as a reference to protect the control element when selectively controlling the state of the memory storage element.

Abstract: A semiconductor integrated circuit effectively makes use of wiring channels of wiring formed by a damascene method. When first cells are used, since the M1 power source lines are laid out at positions spaced away from a boundary between the cells, the power source lines are not combined in laying out a semiconductor integrated circuit. As a result, the width of the power source lines is not changed. Accordingly, an interval between the line and a line which is arranged close to the line, determined in response to a line width of the lines, can satisfy a design rule; and, hence, the reduction of the wiring channels can be obviated, whereby the supply rate of the wiring channels can be enhanced, and, further, the integrity of a semiconductor chip can be enhanced.

Abstract: A semiconductor device comprising a first insulating layer formed above a semiconductor substrate, and comprising a first insulating material, a second insulating material and a hole, a relative dielectric constant of the first insulating material being 3 or less, a Young's modulus of the first insulating material being 10 GPa or less, a linear expansivity of the first insulating material being greater than 30×10?6° C.?1, and a linear expansivity of the second insulating material being 30×10?6° C.?1 or less, and a second insulating layer formed on the first insulating layer, the second insulating layer having a groove connected to the hole, wherein a linear expansivity ? of the first insulating layer within 6 ?m from the hole is 30×10?6° C.?1 or less, where ? = ? i = 1 ? v i ? ? i , vi and ?i are a volume ratio and a linear expansivity of an i-th insulating material.

Abstract: Phase-changeable memory devices and method of fabricating phase-changeable memory devices are provided that include a phase-changeable material pattern of a phase-changeable material that includes nitrogen atoms. First and second electrodes are electrically connected to the phase-changeable material pattern and provide an electrical signal thereto. The phase-changeable material pattern may have a polycrystalline structure.

Abstract: Disclosed herein is an integrated circuit customized by mask programming using custom conducting layers and via layers interspersed with the custom conducting layers, where the via layers are defined by masks designed prior to receiving a custom circuit design.

Abstract: An integrated circuit for routing of an electrical connection include a first metal layer having a first set of dummy conductive segments discretely arranged, and a second metal layer having a second set of dummy conductive segments discretely arranged. The segments of the first and second sets are interleaved with vertically overlapped areas for providing a predetermined link path between a selected first and a selected second nodes on two dummy conductive segments by selectively connecting a predetermined subset of the first and second dummy conductive segments through their vertically overlapped areas.

Abstract: An integrated circuit layout and a semiconductor device manufactured using the same are provided. According to one embodiment, a semiconductor device has a substrate and a plurality of bar type patterns on the substrate. The bar type patterns are substantially parallel to each other. At least one of the bar type patterns includes first and second ends and a middle part therebetween. The bar type patterns has an overhang at the first end thereof. The bar type patterns may be gate patterns, bit line patterns or active patterns.

Abstract: A semiconductor device comprising a first insulation layer, a second insulation layer, a first barrier film, a second barrier film, a diffusion layer. The device further comprises an upper contact hole, a lower contact hole, and a contact plug. The upper contact hole penetrates the second insulation layer and has a bottom in the second barrier film. The bottom has a width greater than a trench made in the first insulation layer, as measured in a direction crossing the widthwise direction of the trench. The lower contact hole penetrates the first insulation layer and first barrier film, communicates with the first contact hole via the trench and is provided on the diffusion layer. The upper portion of the lower contact hole has the same width as the trench. The contact plug is provided in the upper contact hole and lower contact hole.

Abstract: A modifiable circuit for coupling at least two adjacent logic blocks in an integrated circuit chip is disclosed. The chip includes a plurality of metal layers and first and second power supply potentials. The circuit comprises a first and second metal interconnect structures, and an interconnect. The first metal interconnect structure traverses the plurality of metal layers using a first plurality of vias, wherein the first metal interconnect structure is located at a boundary of the at least two adjacent logic blocks. The second metal interconnect structure traverses the plurality of metal layers using a second plurality of vias, wherein the second metal interconnect structure is located at the boundary of the at least two adjacent logic blocks.

Abstract: Nanotube device structures and methods of fabrication. Under one embodiment, a method of forming a nanotube switching element includes forming a first structure having at least one output electrode, forming a conductive article having at least one nanotube, and forming a second structure having at least one output electrode and positioning said second structure in relation to the first structure and the conductive article such that the output electrode of the first structure is opposite the output electrode of the second structure and such that a portion of the conductive article is positioned therebetween. At least one signal electrode is provided in electrical communication with the conductive article having at least one nanotube, and at least one control electrode is provided in relation to the conductive article such that the conductive electrode may control the conductive article to form a channel between the signal electrode and at least one of the output electrodes.

Abstract: A wafer-level package includes a semiconductor wafer having at least one semiconductor chip circuit forming region each including a semiconductor chip circuit each provided with test chip terminals and non test chip terminals, at least one external connection terminal, at least one redistribution trace provided on the semiconductor wafer, at least one testing member, and an insulating material. A first end of the redistribution trace is connected to one of the test chip terminals and a second end of said redistribution trace is extended out to a position offset from the chip terminals. The testing member is provided in an outer region of the semiconductor chip circuit forming region, and the second end of the redistribution trace is connected to the testing member.

Abstract: An analog portion of a mixed-mode integrated circuit system includes a plurality of analog input cells, a plurality of analog output cells, and an interconnect array. The input cells are configured to program analog functions. The output cells are configured to provide Analog and digital outputs corresponding to the programmed analog functions. The interconnect array processes the programmed analog functions into signals indicative of the analog functions. The interconnect array selectively provides the signals to the plurality of analog output cells.

Abstract: A semiconductor integrated circuit device has: a semiconductor substrate defining a plurality of rows, each row including areas for a sequence of cells; a plurality of active regions disposed in each of the rows constituting semiconductor elements of associated cells; and a wiring region of stripe shape elongated along a direction of row, defined on the semiconductor substrate outside of the active regions in each row, and including wirings belonging to the associated cells, each wiring region having height in a direction crossing the row direction, the wiring region having locally different height.

Abstract: A contact-less high-speed signaling interface and method provide for the communication of high-speed signals across an interface, such as a die-substrate interface or die-die interface. The interface includes a transmission-line structure disposed on a dielectric medium to carry a high-speed forward incident signal, and another transmission-line structure disposed on another dielectric medium and substantially aligned with the other transmission-line structure to generate a coupled high-speed signal in a direction opposite to the incident signal.

Abstract: A memory device includes memory cells, bit lines, active area lines running generally in parallel to the bit lines, and transistors formed in each active area line and electrically coupling memory cells to corresponding bit lines. Each bit line includes slanted portions that intersect a corresponding portion of an active area line at an angle. Contacts electrically coupling the bit line to portions of the active area line are formed in a region generally defined by the angled intersection of the bit line to the active area line. The memory cells can have an area of about 6F2, and the bit lines can be coupled to sense amplifiers in a folded bit line configuration. Each bit line includes a first level portion and a second level portion.

Abstract: Provided are a semiconductor device comprising a semiconductor substrate, a first insulating film formed thereover, interconnects formed over the first insulating film and having copper as a main component, a second insulating film formed over the upper surface and side surfaces of each of the interconnects and over the first insulating film and having a function of suppressing or preventing copper diffusion, and a third insulating film formed over the second insulating film and having a dielectric constant lower than that of the second insulating film; and a method of manufacturing the semiconductor device. This invention makes it possible to improve dielectric breakdown strength between copper interconnects and reduce capacitance between the copper interconnects.

Abstract: The memory array contains two layers representing word lines of different rows. Each row contains multiple bit cells sharing the same word line. The two layers are stacked one on top of another to form a high density memory array.

Abstract: The present invention prevents electrostatic discharge damage which may occur when a device chip which has a circuit with fuses mounted thereon is packaged by COG packaging, without increasing an area occupied on the device chip. The height from the chip substrate surface to the top face 138b of the chip terminal 103b formed on the chip substrate surface 136 is formed to be higher than the height from the chip substrate surface to the top face 138a of the fuse terminal 103a. By this, an electrostatic discharge occurs at the chip terminal side when packaged in a COG packaging, so an electrostatic discharge does not occur to the fuse terminal side.

Abstract: A multi-connect substrate, module including the substrate and an Integrated Circuit (IC) chip packaged in the module. The multi-connect substrate includes a multilayered substrate with at least one edge terminal array and one inboard terminal array on one face. An exterior terminal array is located on an opposite face. Signal wires pass through the multilayered substrate, connecting edge terminals to inboard terminals and inboard terminals with a exterior array terminals.

Abstract: A semiconductor device having at least two layers formed on a semiconductor substrate includes a first dielectric layer formed on the semiconductor substrate; a first interconnection layer which is formed on the first dielectric layer and has a first interconnection pattern and a dummy pattern formed around the first interconnection pattern; a second dielectric layer formed on the first interconnection layer; and a second interconnection layer which is formed on the second dielectric layer and has a second interconnection pattern. The dummy pattern is placed in the vicinity of only an area where the first and second interconnection patterns are superposed on each other.

Abstract: A semiconductor integrated circuit device (10) is composed of an LSI function unit (11) and a shield wiring layer (22) formed on the unit. The LSI function unit (11) includes a semiconductor substrate (12) and a first insulating film (13), and the semiconductor substrate (12) is formed with a circuit element including, for example, a MOS transistor (14). The shield wiring layer (22) is composed of a lower shield line (23), a third insulating film (24), an upper shield line (25), and a fourth insulating film (26) sequentially stacked above a second insulating film (17). The directions in which the lower and upper shield lines (23) and (25) are arranged intersect each other.