Having A Conductive Means In Direct Contact With Channel (e.g., Non-insulated Gate) Patents (Class 257/217)
  • Patent number: 10319776
    Abstract: Some embodiments relate to an image sensor pixel comprising a transfer gate formed on a first surface of a semiconductor substrate, a floating diffusion formed in the first surface of the semiconductor substrate, and a buried-well vertically pinned photodiode having a charge accumulation/storage region disposed substantially beneath the transfer gate. The transfer gate is spaced away from the floating diffusion such that an intervening semiconductor region provides a potential barrier to charge flow from beneath the transfer gate to the floating diffusion. The transfer gate is operable to control a vertical pump gate to selectively transfer charge from the charge accumulation/storage region to the floating diffusion by pumping charge from the buried charge accumulation/storage region underlying the transfer gate, over the potential barrier, and out to the floating diffusion, such that full charge transfer can be achieved without overlapping the edge of the transfer gate with the floating diffusion.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: June 11, 2019
    Assignee: TRUSTEES OF DARTMOUTH COLLEGE
    Inventors: Jiaju Ma, Eric R. Fossum
  • Patent number: 10020393
    Abstract: The present invention provides a laterally diffused metal-oxide-semiconductor (LDMOS) transistor and a manufacturing method thereof. The LDMOS transistor includes a semiconductor substrate, an insulation structure, agate structure, and a plurality of floating electrodes. The insulation structure is disposed in the semiconductor substrate. The gate structure is disposed on the semiconductor substrate. The floating electrodes are embedded in the insulation structure, wherein the floating electrode closest to the gate structure protrudes from a top surface of the insulation structure or the gate structure includes at least one branch portion embedded in the insulation structure, and the floating electrodes are separated from the gate structure.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: July 10, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Yin Hsiao, Chia-Min Hung
  • Patent number: 9859445
    Abstract: The present invention discloses an array substrate, a display panel and a display device. The array substrate includes a substrate, a gate line and a data line arranged on the substrate, and a thin film transistor arranged in an overlapping region where the gate line and the data line are overlapped; wherein an orthogonal projection of the thin film transistor on the substrate covers an orthogonal projection of the overlapping region of the gate line and the data line on the substrate. Because of design of a location of the thin film transistor according to the present invention, the opening ratio can be increased, the slightly rubbing region adjacent to the thin film transistor can be reduced; and, because of the closed channel region, levels at various positions of the thin film transistor can be uniform, and a bigger contact area provided for the supporting post, thereby increasing supporting ability of the supporting post and compressive property of the panel.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: January 2, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Juncai Ma
  • Patent number: 9773919
    Abstract: A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A transistor having a high on-state current is provided. A semiconductor device including the transistor is provided. A semiconductor device having a high degree of integration is provided. A semiconductor device including an oxide semiconductor; a second insulator; a second conductor; a third conductor; a fourth conductor; a fifth conductor; a first conductor and a first insulator embedded in an opening portion formed in the second insulator, the second conductor, the third conductor, the fourth conductor, and the fifth conductor; a region where a side surface and a bottom surface of the second conductor are in contact with the fourth conductor; and a region where a side surface and a bottom surface of the third conductor are in contact with the fifth conductor.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: September 26, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinya Sasagawa, Takashi Hamada, Akihisa Shimomura, Satoru Okamoto, Katsuaki Tochibayashi
  • Patent number: 9609764
    Abstract: Provided is an image display apparatus. The image display apparatus includes a display panel displaying an image through a display area, a plurality of acoustic devices disposed on a non-display area around the display area, a protection member accommodating the display panel and the acoustic devices, and a plurality of opening parts defined to corresponding to the acoustic devices, the plurality of opening parts being defined by opening the protection member of the non-display area in both directions perpendicular to a plane.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: March 28, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Byeong-Hee Won, Yi joon Ahn, IlNam Kim, WonSang Park
  • Patent number: 9598911
    Abstract: A coring bit for extracting a sample of subterranean formation material from a well bore may include a bit body having a bit face and an inner surface defining a substantially cylindrical cavity of the bit body. A first portion of the inner surface may be configured to surround a core catcher. The coring bit may include a face discharge channel inlet formed in the inner surface of the bit body longitudinally at or above the first portion of the inner surface. The coring bit may also include a face discharge channel extending through the bit body from the face discharge channel inlet to the bit face. A tubular body having a core catcher may be disposed in the coring bit to form a coring tool. Methods of forming such bit bodies may include forming an inlet for a face discharge channel in the inner surface of the bit body at a location longitudinally at or above the first portion of the inner surface and forming a face discharge channel extending from the inlet to the bit face.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: March 21, 2017
    Assignee: Baker Hughes Incorporated
    Inventors: Thomas Uhlenberg, Volker Richert
  • Patent number: 9576855
    Abstract: A method for fabricating a semiconductor device includes providing a semiconductor substrate having regions for an n-type field-effect transistor (nFET) core, an input/output nFET (nFET IO), a p-type field-effect transistor (pFET) core, an input/output pFET (pFET IO), and a high-resistor, forming an oxide layer on the IO regions of the substrate, forming an interfacial layer on the substrate and the oxide layer, depositing a high-k (HK) dielectric layer on the interfacial layer, depositing a first capping layer of a first material on the HK dielectric layer, depositing a second capping layer of a second material on the HK dielectric layer and on the first capping layer, depositing a work function (WF) metal layer on the second capping layer, depositing a polysilicon layer on the WF metal layer, and forming gate stacks on the regions of the substrate.
    Type: Grant
    Filed: April 6, 2015
    Date of Patent: February 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei Cheng Wu, Bao-Ru Young, Harry-Hak-Lay Chuang, Jin-Aun Ng, Po-Nien Chen
  • Patent number: 9506965
    Abstract: An overlay mark including at least one first overlay mark and at least one second overlay mark is provided. The first overlay mark includes a plurality of first bars and a plurality of first spaces arranged alternately, and the first spaces are not constant. The second overlay mark includes a plurality of second bars and a plurality of second spaces arranged alternately, and the second spaces are constant. Besides, the second overlay mark partially overlaps with the first overlay mark.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: November 29, 2016
    Assignee: United Microelectronics Corp.
    Inventors: Kuo-Chun Huang, Chien-Hao Chen, Wen-Liang Huang
  • Patent number: 8890163
    Abstract: A device formed from a method of fabricating a fine metal silicide layer having a uniform thickness regardless of substrate doping. A planar vacancy is created by the separation of an amorphousized surface layer of a silicon substrate from an insulating layer, a metal source enters the vacancy through a contact hole through the insulating later connecting with the vacancy, and a heat treatment converts the metal in the vacancy into metal silicide. The separation is induced by converting the amorphous silicon into crystalline silicon.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: November 18, 2014
    Assignee: Samsung Electronics Co., Ltd
    Inventor: Jong-Ki Jung
  • Patent number: 8800130
    Abstract: A charge-coupled device (CCD) image sensor includes multiple vertical charge-coupled device (VCCD) shift registers and independently-controllable gate electrodes disposed over the VCCD shift registers and arranged into physically separate and distinct sections that are non-continuous across the plurality of VCCD shift registers. The CCD image sensor can be configured to operate in two or more operating modes, including a full resolution charge multiplication mode.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: August 12, 2014
    Assignee: Truesense Imaging, Inc.
    Inventors: Antonio S. Ciccarelli, Eric J. Meisenzahl
  • Patent number: 8785981
    Abstract: A gate-first processing scheme for forming a nanomesh field effect transistor is provided. An alternating stack of two different semiconductor materials is patterned to include two pad regions and nanowire regions. A semiconductor material is laterally etched selective to another semiconductor material to form a nanomesh including suspended semiconductor nanowires. A stack of a gate dielectric, a gate electrode, and a gate cap dielectric is formed over the nanomesh. A dielectric spacer is formed around the gate electrode. An isotropic etch is employed to remove dielectric materials that are formed in lateral recesses of the patterned alternating stack. A selective epitaxy process can be employed to form a source region and a drain region.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: July 22, 2014
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Paul Chang, Isaac Lauer, Jeffrey W. Sleight
  • Patent number: 8773563
    Abstract: A charge-coupled device (CCD) image sensor includes multiple vertical charge-coupled device (VCCD) shift registers and independently-controllable gate electrodes disposed over the VCCD shift registers and arranged into physically separate and distinct sections that are non-continuous across the plurality of VCCD shift registers. The CCD image sensor can be configured to operate in two or more operating modes, including a full resolution charge multiplication mode.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: July 8, 2014
    Assignee: Truesense Imaging, Inc.
    Inventors: Antonio S. Ciccarelli, Eric J. Meisenzahl
  • Patent number: 8716103
    Abstract: A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: May 6, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung Long Cheng, Sheng-Chen Chung, Kong-Beng Thei, Harry-Hak-Lay Chuang, Mong-Song Liang
  • Patent number: 8680614
    Abstract: A split trench-gate MOSFET device and method for forming this device is disclosed. The device has a trench gate structure, comprising a shield electrode and two gate electrodes, wherein a substantial portion of shield electrode region is lower than the gate electrode region, and wherein a portion of the shield electrode region extends to the top surface between the two gate electrodes. The device further comprises a source metal layer, contacting to an initial layer, a well region, the shield electrode and a source region at the top surface, wherein the contact between the source metal layer and the initial layer forms a Schottky diode.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: March 25, 2014
    Assignee: Monolithic Power Systems, Inc.
    Inventors: Tiesheng Li, Rongyao Ma, Lei Zhang
  • Patent number: 8624261
    Abstract: According to one embodiment, a nitride semiconductor device includes a first, a second, a third and a fourth transistor of n-type channel and a resistor. The first transistor has a first gate, a first source, and a first drain. The second transistor has a second gate, a second source electrically connected to the first gate, and a second drain. The third transistor has a third gate, a third source electrically connected to the first source, and a third drain electrically connected to the first gate and the second source. The fourth transistor has a fourth gate electrically connected to the third gate, a fourth source electrically connected to the first source and the third source, and a fourth drain electrically connected to the second gate. The resistor has one end electrically connected to the second drain and one other end electrically connected to the second gate and the fourth drain.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: January 7, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kentaro Ikeda
  • Patent number: 8557694
    Abstract: A method for forming a triple gate of a semiconductor device is provided. The method includes: forming a buffer layer and a hard mask over a substrate; etching the hard mask and the buffer layer to form a hard mask pattern and a buffer pattern; forming first and second trenches spaced apart within the substrate by partially etching the substrate by a vapor etching process using the hard mask pattern as an etching barrier layer; forming a buried insulation layer to fill the first and second trenches; removing the hard mask pattern and the buffer pattern; forming a gate insulation layer over the substrate between the first trench and the second trench; forming a conductive layer to cover the gate insulation layer; and etching the conductive layer to form a gate electrode.
    Type: Grant
    Filed: May 19, 2009
    Date of Patent: October 15, 2013
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventor: Han-Seob Cha
  • Patent number: 8461629
    Abstract: A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: June 11, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung Long Cheng, Sheng-Chen Chung, Kong-Beng Thei, Harry Chuang, Mong-Song Liang
  • Patent number: 8461630
    Abstract: A conductive film to be a gate electrode, a first insulating film to be a gate insulating film, a semiconductor film in which a channel region is formed, and a second insulating film to be a channel protective film are successively formed. With the use of a resist mask formed by performing light exposure with the use of a photomask which is a multi-tone mask and development, i) in a region without the resist mask, the second insulating film, the semiconductor film, the first insulating film, and the conductive film are successively etched, ii) the resist mask is made to recede by ashing or the like and only the region of the resist mask with small thickness is removed, so that part of the second insulating film is exposed, and iii) the exposed part of the second insulating film is etched, so that a pair of opening portions is formed.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: June 11, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuta Endo, Kosei Noda
  • Patent number: 8411189
    Abstract: A charge-coupled device (CCD) image sensor includes multiple vertical charge-coupled device (VCCD) shift registers and independently-controllable gate electrodes disposed over the VCCD shift registers and arranged into physically separate and distinct sections that are non-continuous across the plurality of VCCD shift registers. The CCD image sensor can be configured to operate in two or more operating modes, including a full resolution charge multiplication mode.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: April 2, 2013
    Assignee: Truesense Imaging, Inc.
    Inventors: Antonio S. Ciccarelli, Eric J. Meisenzahl
  • Patent number: 8394656
    Abstract: MEMS devices (such as interferometric modulators) may be fabricated using a sacrificial layer that contains a heat vaporizable polymer to form a gap between a moveable layer and a substrate. One embodiment provides a method of making a MEMS device that includes depositing a polymer layer over a substrate, forming an electrically conductive layer over the polymer layer, and vaporizing at least a portion of the polymer layer to form a cavity between the substrate and the electrically conductive layer.
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: March 12, 2013
    Assignee: Qualcomm MEMS Technologies, Inc.
    Inventors: Chun-Ming Wang, Jeffrey Lan, Teruo Sasagawa
  • Patent number: 8373780
    Abstract: A solid-state image sensor includes: a transfer control section configured to control charge transfer from the vertical transfer section to the horizontal transfer section. The transfer control section has a plurality of unit control sections corresponding to the transfer packets. The unit control section has a vertical transfer channel and a plurality of control section electrodes formed over the vertical transfer channel. The control section electrodes include a signal charge accumulating electrode and a transfer inhibiting electrode, which are sequentially formed from a side of the vertical transfer section. The vertical transfer channels are independently connected to a horizontal transfer channel. When stopping the charge transfer from the vertical transfer section to the horizontal transfer section, a high-level voltage is applied to the signal charge accumulating electrode, and a low-level voltage is applied to the transfer inhibiting electrode.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: February 12, 2013
    Assignee: Panasonic Corporation
    Inventors: Koichi Yonemura, Sei Suzuki
  • Patent number: 8309993
    Abstract: A pixel of an image sensor includes a polysilicon layer, and an active region which needs to be electrically coupled with the polysilicon layer, wherein the polysilicon layer extends over a portion of the active region, such that the polysilicon layer and the active region are partially overlapped, and the polysilicon layer and the active region are coupled through a buried contact structure.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: November 13, 2012
    Assignee: Intellectual Ventures II LLC
    Inventors: Woon-Il Choi, Hyung-Sik Kim, Ui-Sik Kim
  • Patent number: 8304819
    Abstract: A device formed from a method of fabricating a fine metal silicide layer having a uniform thickness regardless of substrate doping. A planar vacancy is created by the separation of an amorphousized surface layer of a silicon substrate from an insulating layer, a metal source enters the vacancy through a contact hole through the insulating layer connecting with the vacancy, and a heat treatment converts the metal in the vacancy into metal silicide. The separation is induced by converting the amorphous silicon into crystalline silicon.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: November 6, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jong-Ki Jung
  • Patent number: 8247847
    Abstract: A solid-state imaging device including a first transfer electrode portion and a second transfer electrode portion having a pattern area ratio higher than that of the first transfer electrode portion. The first transfer electrode portion includes a plurality of first transfer electrodes having a single-layer structure of metal material. The second transfer electrode portion includes a plurality of second transfer electrodes having a single-layer structure of polycrystalline silicon or amorphous silicon.
    Type: Grant
    Filed: November 4, 2009
    Date of Patent: August 21, 2012
    Assignee: Sony Corporation
    Inventors: Kaori Takimoto, Masayuki Okada, Takeshi Takeda
  • Patent number: 7998830
    Abstract: A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: August 16, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung Long Cheng, Sheng-Chen Chung, Kong-Beng Thei, Harry Chuang, Mong-Song Liang
  • Patent number: 7910926
    Abstract: An electro-optical device includes a switching element with a gate electrode provided opposite to the channel region. The gate electrode has a ring-shaped structure that surrounds a junction region between the channel region and a source/drain region.
    Type: Grant
    Filed: June 19, 2008
    Date of Patent: March 22, 2011
    Assignee: Seiko Epson Corporation
    Inventor: Tatsuya Ishii
  • Patent number: 7868361
    Abstract: A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: January 11, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung Long Cheng, Sheng-Chen Chung, Kong-Beng Thei, Harry Chuang, Mong Song Liang
  • Patent number: 7821042
    Abstract: An imaging device includes a first electrode for generating an electric field storing signal charges, a charge multiplication section for multiplying the stored signal charges, a second electrode for generating the electric field in the charge multiplication section, a voltage conversion portion for converting the signal charges into a voltage, a third electrode for transferring the signal charges to the voltage conversion portion, provided between the first electrode and the voltage conversion portion, wherein the second electrode is provided on a side opposite to the third electrode and the voltage conversion portion with respect to the first electrode.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: October 26, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hayato Nakashima, Ryu Shimizu
  • Patent number: 7795061
    Abstract: MEMS devices (such as interferometric modulators) may be fabricated using a sacrificial layer that contains a heat vaporizable polymer to form a gap between a moveable layer and a substrate. One embodiment provides a method of making a MEMS device that includes depositing a polymer layer over a substrate, forming an electrically conductive layer over the polymer layer, and vaporizing at least a portion of the polymer layer to form a cavity between the substrate and the electrically conductive layer.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: September 14, 2010
    Assignee: Qualcomm MEMS Technologies, Inc.
    Inventors: Chun-Ming Wang, Jeffrey Lan, Teruo Sasagawa
  • Patent number: 7755685
    Abstract: A pixel for an imager is disclosed that includes at least one electron multiplication (EM) gain stage configured in a loop and electrically coupled to a charge collection region and a charge readout region, the charge collection region being configured to generate a charge packet, the EM gain stage being configured to amplify the charge packet by impact ionization and to circulate the charge packet a predetermined number of times in one direction around the loop, the charge readout region being configured to receive the amplified charge packet and convert the amplified charge to a measurable signal. The at least one EM gain stage, the charge collection region, and the charge readout region can be formed monolithically in an integrated circuit. The pixel can be manufactured using a CMOS process. The pixel can further include a second EM gain stage formed in the integrated circuit to increase the amount of amplification around the loop.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: July 13, 2010
    Assignee: Sarnoff Corporation
    Inventors: John Robertson Tower, James Tynan Andrews
  • Publication number: 20100140667
    Abstract: Disclosed herein is a solid-state imaging device including a first transfer electrode portion and a second transfer electrode portion having a pattern area rate higher than that of the first transfer electrode portion. The first transfer electrode portion includes a plurality of first transfer electrodes having a single-layer structure of metal material. The second transfer electrode portion includes a plurality of second transfer electrodes having a single-layer structure of polycrystalline silicon or amorphous silicon.
    Type: Application
    Filed: November 4, 2009
    Publication date: June 10, 2010
    Applicant: SONY CORPORATION
    Inventors: Kaori TAKIMOTO, Masayuki OKADA, Takeshi TAKEDA
  • Patent number: 7728387
    Abstract: Various semiconductor devices and methods of manufacture are employed. According to an example embodiment of the present invention, a MOS-compatible semiconductor device exhibits high channel mobility and low leakage. The device includes a channel region having a high-mobility strained material layer and a tunneling mitigation layer on the strained material layer to mitigate tunnel leakage. The strained material has a lattice structure that is strained to match the lattice structure of the tunneling mitigation layer. An insulator layer is on the tunneling mitigation layer, and an electrode is over the insulator and adapted to apply a voltage bias to the channel region to switch the device between conductive and nonconductive states. Current is transported in the conductive state as predominantly facilitated via the mobility of the strained material layer, and wherein tunneling current in the nonconductive state is mitigated by the tunneling mitigation layer.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: June 1, 2010
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Tejas Krishnamohan, Krishna Chandra Saraswat
  • Patent number: 7692222
    Abstract: A semiconductor structure and method wherein a recess is disposed in a surface portion of a semiconductor structure and a dielectric film is disposed on and in contract with the semiconductor. The dielectric film has an aperture therein. Portions of the dielectric film are disposed adjacent to the aperture and overhang underlying portions of the recess. An electric contact has first portions thereof disposed on said adjacent portions of the dielectric film, second portions disposed on said underlying portions of the recess, with portions of the dielectric film being disposed between said first portion of the electric contact and the second portions of the electric contact, and third portions of the electric contact being disposed on and in contact with a bottom portion of the recess in the semiconductor structure. The electric contact is formed by atomic layer deposition of an electrically conductive material over the dielectric film and through the aperture in such dielectric film.
    Type: Grant
    Filed: November 7, 2006
    Date of Patent: April 6, 2010
    Assignee: Raytheon Company
    Inventors: Kamal Tabatabaie, Robert B. Hallock
  • Patent number: 7601983
    Abstract: A transistor includes a semiconductor substrate that has a first surface of a {100} crystal plane, a second surface of the {100} crystal plane having a height lower than that of the first surface, and a third surface of a {111} crystal plane connecting the first surface to the second surface. First heavily doped impurity regions are formed under the second surface. A gate structure is formed on the first surface. An epitaxial layer is formed on the second surface and the third surface. Second heavily doped impurity regions are formed at both sides of the gate structure. The second heavily doped impurity regions have side faces of the {111} crystal plane so that a short channel effect generated between the impurity regions may be prevented.
    Type: Grant
    Filed: August 19, 2005
    Date of Patent: October 13, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tetsuji Ueno, Hwa-Sung Rhee, Ho Lee, Dong-Suk Shin, Seung-Hwan Lee
  • Patent number: 7572712
    Abstract: Embodiments for FET devices with stress on the channel region by forming stressor regions under the source/drain regions or the channel region and forming a selective strained Si using lateral epitaxy over the stressor regions. In a first example embodiment, a lateral epitaxial layer is formed over a stressor region under a channel region of an FET. In a second example embodiment, a lateral S/D epitaxial layer is formed over S/D stressor region under the source/drain regions of an FET. In a third example embodiment, both PFET and NFET devices are formed. In the PFET device, a lateral S/D epitaxial layer is formed over S/D stressor region under the source/drain regions. In the NFET device, the lateral epitaxial layer is formed over a stressor region under a channel region of the NFET.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: August 11, 2009
    Assignees: Chartered Semiconductor Manufacturing, Ltd., International Business Machines Corporation (IBM)
    Inventors: Yung Fu Chong, Zhijiong Luo, Judson R. Holt
  • Patent number: 7465979
    Abstract: In order to diversify a current control method of a semiconductor device, improve performance (including a current drive performance) of the semiconductor device, and reduce a size of the semiconductor device, a second gate may be formed inside a substrate that forms a channel upon applying a bias voltage thereto. In one aspect, the semiconductor device includes: a well region of a first conductivity; source and drain regions of a second conductivity in the well region; a first gate on an oxide layer above the well region, controlling a first channel region of a second conductivity between the source region and the drain region; and a second gate under the first channel region.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: December 16, 2008
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Hyung Sun Yun
  • Patent number: 7355248
    Abstract: A semiconductor device includes a first semiconductor layer that is formed on a first insulating layer; a second insulating layer that is formed on the first semiconductor layer; a second semiconductor layer that is formed on the second insulating layer; a first gate electrode that is formed on the second semiconductor layer; first conductive-source and drain layers that are formed in the second semiconductor layer and are arranged at sides of the gate electrode; and a first wiring layer that connects the first gate electrode to the first semiconductor layer.
    Type: Grant
    Filed: November 14, 2005
    Date of Patent: April 8, 2008
    Assignee: Seiko Epson Corporation
    Inventor: Tatsushi Kato
  • Patent number: 7235824
    Abstract: An active gate includes a substrate of a first conductivity type, a channel of a second conductivity type formed in the substrate, a first gate region of the first conductivity type formed in a corresponding first portion of the channel, and a first contact connected to the first gate region. The first gate region covers a first area, and the first contact covers a fraction of the first area. A pixel or register element includes an active gate, a second gate region of the first conductivity type formed in a corresponding second portion of the channel, and a second contact connected to the second gate region. The second gate region covers a second area and is spaced by a first gap from the first gate region. The second contact covers a fraction of the second area. The pixel or register element further includes a first gate electrode insulatively spaced from and disposed over the first gap.
    Type: Grant
    Filed: June 11, 2001
    Date of Patent: June 26, 2007
    Assignee: Dalsa, Inc.
    Inventor: Surendra Singh
  • Patent number: 7012285
    Abstract: A semiconductor device whose insertion loss is reduced and isolation characteristics are improved in a high frequency band by reducing the capacitance component when an FET is off is provided. FETs (30a, 30b) having a gate electrode with a gate length of not more than 0.8 ?m are formed on a semiconductor substrate in which a buffer layer (24) having an impurity concentration of at least 1010 cm?3 and at most 1014 cm?3 is formed on a semi-insulating semiconductor (25) having at least 1014 cm?3 and at most 1016 cm?3 p-type or n-type impurities and an active layer (23) having a p-type or n-type impurity concentration of at least 1015 cm?3 and at most 1017 cm?3 is formed on the buffer layer.
    Type: Grant
    Filed: September 12, 2002
    Date of Patent: March 14, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tadayoshi Nakatsuka, Toshiharu Tambo, Takahiro Kitazawa, Akiyoshi Tamura, Katsuyoshi Tara
  • Patent number: 6870207
    Abstract: A photon detector is obtained by using the intersubband absorption mechanism in a modulation doped quantum well(s). The modulation doping creates a very high electric field in the well which enables absorption of input TE polarized light and also conducts the carriers emitted from the well into the modulation doped layer from where they may recombine with carriers from the gate contact. Carriers are resupplied to the well by the generation of electrons across the energy gap of the quantum well material. The absorption is enhanced by the use of a resonant cavity in which the quantum well(s) are placed. The absorption and emission from the well creates a deficiency of charge in the quantum well proportional to the intensity of the input photon signal. The quantity of charge in the quantum well of each detector is converted to an output voltage by transferring the charge to the gate of an output amplifier.
    Type: Grant
    Filed: April 24, 2000
    Date of Patent: March 22, 2005
    Assignee: The University of Connecticut
    Inventor: Geoff W Taylor
  • Patent number: 6841811
    Abstract: Large area, fast frame rate, charge coupled devices (CCDs) are provided. Interline transfer CCDs can have interleaved pinned photodiodes and vertical shift registers. The interline transfer CCDs are ideal for producing high frame rate video images from a continuous light source. The photodiodes transfer charge indicative of the previous video frame to an adjacent vertical shift register with little or no lag, while light from the current video frame is integrating in the photodiodes. The charge signals only have to travel a short distance from a photodiode to an adjacent vertical shift register. The charge signals indicative of each video frame are then shifted out of the vertical shift registers. Each vertical shift register has a doping gradient that increases the charge transfer rate. All of these factors provide a fast and efficient video frame rate, even in a large area CCD.
    Type: Grant
    Filed: August 14, 2003
    Date of Patent: January 11, 2005
    Assignee: Fairchild Imaging
    Inventors: David Wen, Steve Onishi
  • Patent number: 6809379
    Abstract: The invention relates to a field effect transistor with a drain region, a source region, a channel region and a gate region. The gate region is provided with a metal layer.
    Type: Grant
    Filed: February 24, 2003
    Date of Patent: October 26, 2004
    Assignee: Infineon Technologies AG
    Inventor: Franz Kreupl
  • Patent number: 6777722
    Abstract: A method for fabricating a junction field effect transistor (JFET) with a double dose gate structure. A trench is etched in the surface of a semiconductor substrate, followed by a low dose implant to form a first gate region. An anneal may or may not be performed after the low dose implant. A gate definition spacer is then formed on the wall the trench to establish the lateral extent of a second, high dose implant gate region. After the second implant, the gate is annealed. The double dose gate structure produced by the superposition of two different and overlapping regions provides an additional degree of flexibility in determining the ultimate gate region doping profile. A further step comprises using the gate definition spacer to define the walls of a second etched trench that is used to remove a portion of the p-n junction, thereby further reducing the junction capacitance.
    Type: Grant
    Filed: July 2, 2002
    Date of Patent: August 17, 2004
    Assignee: Lovoltech, Inc.
    Inventors: Ho-Yuan Yu, Valentino L. Liva, Pete Pegler
  • Patent number: 6750485
    Abstract: A lock in pinned photodiode photodetector includes a plurality of output ports which are sequentially enabled. Each time when the output port is enabled is considered to be a different bin of time. A specified pattern is sent, and the output bins are investigated to look for that pattern. The time when the pattern is received indicates the time of flight.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: June 15, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Vladimir Berezin, Alexander Krymski, Eric R. Fossum
  • Patent number: 6710381
    Abstract: The present invention provides a memory structure, comprising: a substrate; a gate oxide layer disposed on a portion of the substrate; a gate structure disposed on the gate oxide layer; a buried bit line disposed in the substrate along both sides of the gate structures; a raised line disposed on the burled bit line; an isolating spacer disposed on both sidewalls of the gate structure and a word line disposed over the substrate in a direction perpendicular to the buried bit line; and an insulation layer disposed on a top of the raised line to electrically isolate the raised line and the word line.
    Type: Grant
    Filed: October 8, 2002
    Date of Patent: March 23, 2004
    Assignee: Macronix International Co., Ltd.
    Inventors: Weng-Hsing Huang, Kent Kuohua Chang
  • Patent number: 6674133
    Abstract: The present invention provides a twin bit cell flash memory device and its fabricating method. The method is to first form a gate oxide layer on the surface of the silicon substrate followed by forming a polysilicon germanium (Si1−xGex, x=0.05˜1.0) layer on the gate oxide layer. Thereafter, an ion implantation process is performed to form at least one insulating region in the polysilicon germanium layer for separating the polysilicon germanium layer into two isolated conductive regions and forming a twin bit cell structure. Then, a dielectric layer is formed on the polysilicon germanium layer and a photo-etching-process (PEP) is performed to etch portions of the dielectric layer and the polysilicon germanium layer for forming a floating gate of the twin bit cell flash memory. Finally, a control gate is formed over the floating gate.
    Type: Grant
    Filed: May 21, 2002
    Date of Patent: January 6, 2004
    Assignee: Macronix International Co. Ltd.
    Inventor: Kent Kuohua Chang
  • Patent number: 6670655
    Abstract: A method and apparatus are provided for implementing a body contact in a silicon-on-insulator field effect transistor device. A SOI field effect transistor is provided having a body contact having a predefined resistance that provides a higher device threshold voltage in the SOI FET device. A body of the SOI field effect transistor is connected to the gate of the SOI field effect transistor. The body gate connection of the SOI field effect transistor effectively lowers the device threshold voltage due to body bias effect. The SOI field effect transistor with a body connected to the gate of the SOI field effect transistor is used in circuits having stacked devices and DC currents. The SOI field effect transistor with a body connected to the gate of the SOI field effect transistor also is used in analog circuits with device matching requirements and in circuits having a low voltage power supply.
    Type: Grant
    Filed: April 18, 2001
    Date of Patent: December 30, 2003
    Assignee: International Business Machines Corporation
    Inventors: Eric John Lukes, Patrick Lee Rosno, James David Strom
  • Patent number: 6559486
    Abstract: An etching mask having high etching selectivity for an inorganic interlayer film of SiO2 or Si3N4, an organic interlayer film such as ARC and an electrically conductive film and a contact hole using such an etching mask, a process for forming same and a resultant semiconductor device. On formation of contact holes for connecting wirings disposed through interlayer films of inorganic or organic material (20, 23 in FIG. 2), a thin film of silicon carbide (21 in FIG. 2) having high etching selectivity for any of the inorganic and organic materials is deposited on an interlayer film, and a mask pattern of silicon carbide is formed using a resist pattern (22 in FIG. 2). Thereafter, high aspect ratio contact holes having a size which is exactly same as that of the mask is formed by etching the interlayer film using the silicon carbide mask.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: May 6, 2003
    Assignee: NEC Electronics Corporation
    Inventor: Yasuhiko Ueda
  • Patent number: 6518606
    Abstract: A semiconductor device in which an integrated circuit is formed includes a resistance-measurement area with conductive members disposed in at least two different layers, and an electrode pattern. The electrode pattern includes contact plugs that, depending on their alignment, make electrical contact with different conductive members. Contact alignment error is measured by measuring the electrical resistance between a pair of electrodes in the electrode pattern.
    Type: Grant
    Filed: February 15, 2000
    Date of Patent: February 11, 2003
    Assignee: Oki Electric Industry Co, Ltd.
    Inventor: Osamu Nanba
  • Patent number: RE41068
    Abstract: The cross-sectional area of a thin-film transistor (TFT) is decreased in order to minimize bitline to supply leakage of the TFT. This is accomplished by utilizing a spacer etch process to manufacture a TFT having a very narrow and thin channel in a controllable manner. The spacer dimensions of the TFT may be adjusted by simply modifying the thicknesses of the poly gate and the channel poly. The channel thickness is limited by the thickness of the deposited channel polysilicon which may be as thin as approximately 300 ? to 500 ?, and the channel width of the TFT corresponds to the height of the spacer etched along the polysilicon gate of the device which may be as small as approximately 0.15 to 0.25 ?m.
    Type: Grant
    Filed: October 29, 1999
    Date of Patent: January 5, 2010
    Assignee: STMicroelectronics, Inc.
    Inventors: Artur P. Balasinski, Kuei-Wu Huang