Abstract: A method and apparatus are provided for implementing a body contact in a silicon-on-insulator field effect transistor device. A SOI field effect transistor is provided having a body contact having a predefined resistance that provides a higher device threshold voltage in the SOI FET device. A body of the SOI field effect transistor is connected to the gate of the SOI field effect transistor. The body gate connection of the SOI field effect transistor effectively lowers the device threshold voltage due to body bias effect. The SOI field effect transistor with a body connected to the gate of the SOI field effect transistor is used in circuits having stacked devices and DC currents. The SOI field effect transistor with a body connected to the gate of the SOI field effect transistor also is used in analog circuits with device matching requirements and in circuits having a low voltage power supply.

Abstract: An etching mask having high etching selectivity for an inorganic interlayer film of SiO2 or Si3N4, an organic interlayer film such as ARC and an electrically conductive film and a contact hole using such an etching mask, a process for forming same and a resultant semiconductor device. On formation of contact holes for connecting wirings disposed through interlayer films of inorganic or organic material (20, 23 in FIG. 2), a thin film of silicon carbide (21 in FIG. 2) having high etching selectivity for any of the inorganic and organic materials is deposited on an interlayer film, and a mask pattern of silicon carbide is formed using a resist pattern (22 in FIG. 2). Thereafter, high aspect ratio contact holes having a size which is exactly same as that of the mask is formed by etching the interlayer film using the silicon carbide mask.

Abstract: A semiconductor device in which an integrated circuit is formed includes a resistance-measurement area with conductive members disposed in at least two different layers, and an electrode pattern. The electrode pattern includes contact plugs that, depending on their alignment, make electrical contact with different conductive members. Contact alignment error is measured by measuring the electrical resistance between a pair of electrodes in the electrode pattern.

Abstract: An active surface with a source area, a channel area and a drain area is provided in a semiconductor substrate. Each of the areas lie adjacent to a main surface of the semiconductor substrate. At least one trench is provided in the main surface of the semiconductor substrate. The trench is adjacent to the channel area and is situated in the gate electrode part. The gate electrode preferably has two opposite parts which are each adjacent to the channel area. The transistor is produced using standard process steps.

Abstract: Described is a dynamic threshold field effect transistor (DTFET) that includes a gate-to-body contact structure within the gate. By forming the gate-to-body contact structure that can reduce the gate-to-body contact resistance and increase the device packing density, the DTFET can be used in silicon on insulator (SOI) technologies and take full advantages of the DT-CMOS performance benefit.

Abstract: A semiconductor body (11) has first and second opposed major surfaces (11a and 11b). First and second main regions (13 and 14) meet the second major surface (11b) and a voltage-sustaining zone is provided between the first and second regions (13 and 14). The voltage-sustaining zone has a semiconductor region (11) of one conductivity type forming a rectifying junction (J) with a region (15) of the device such that, when the rectifying junction is reverse-biased in one mode of operation, a depletion region extends in the semiconductor region of the voltage-sustaining zone. A number of conductive regions (22) are isolated from and extend through the semiconductor region (11) in a direction transverse to the first and second major surfaces (11a and 11b) so as to be spaced apart in a direction between first and second main regions.

Abstract: A charge coupled device includes first and second pluralities of column registers and first and second register segments. The first plurality of column registers are splayed with respect to and on one side of a column direction line, and the second plurality of column registers are splayed with respect to and on another side of the column direction line. The first register segment is coupled to the first plurality of column registers, and the second register segment is coupled to the second plurality of column registers. The second register segment is spaced apart from the first register segment so as to define a layout area between the first and second register segments where at least one of an isolation register element and an output node is disposed. Each column register of the first plurality of column registers includes a plurality of column element wells.

Abstract: The image sensor charge detection amplifier has a charge storage well 60, a charge sensor 32 for sensing charge levels in the charge storage well 60, a charge drain 28 adjacent to the charge storage well 60, and charge transfer structures for transferring charge from the charge storage well 60 to the charge drain 28.

Abstract: In one aspect, the invention provides a method of forming an integrated circuitry memory device. In one preferred implementation, a conductive layer is formed over both memory array areas and peripheral circuitry areas. A refractory metal layer is formed over the conductive layer to provide conductive structure in both areas. According to a preferred aspect of this implementation, the conductive layer which is formed over the memory array provides an electrical contact for a capacitor container to be formed. According to another preferred aspect of this implementation, the conductive layer formed over the peripheral circuitry area constitutes a conductive line which includes at least some of the silicide. In another preferred implementation, the invention provides a method of forming a capacitor container over a substrate. According to a preferred aspect of this implementation, a conductive layer is elevationally interposed between an upper insulating layer and a lower conductive layer over the substrate.

Abstract: A field effect semiconductor device including a substrate, a dipole barrier formed on the substrate, a channel layer formed on the dipole barrier, and source, gate and drain electrodes formed on the channel layer. The dipole barrier provides a potential barrier and a maximum electric field sufficient to confine electrons to the channel layer.

Abstract: An active FET body device which comprises an active FET region including a gate, a body region and electrical connection between said gate and said body region that is located within the active FET region is provided along with various methods for fabricating the devices. The electrical connection extends over substantially the entire width of the FET.

Abstract: A method for producing a field effect transistor includes: a first step of forming an insulating film over a substrate; a second step of dry etching the insulating film to form a rectangular insulating pattern having side surfaces; a third step of forming a gate electrode film over the substrate having the rectangular insulating pattern; a fourth step of conducting substantially anisotropic etching of the gate electrode film to form side walls made of the gate electrode film adjacent to the side surfaces of the rectangular insulating pattern; and a fifth step of removing at least a portion of the insulating pattern to form a side wall gate.

Abstract: An electron emitting semiconductor device is provided with a P-type semiconductor layer arranged on a semiconductor substrate having an impurity concentration. A Schottky barrier electrode is arranged on a surface of the P-type semiconductor layer. Plural P.sup.+ -type area units are positioned under and facing the Schottky barrier electrode. An N.sup.+ -type area is disposed in the vicinity of the P.sup.+ -type units. The impurity concentration is such as to cause an avalanche breakdown in at least a portion of the surfaces.

Abstract: An interline sensor is constructed using photocapacitors. The vertical shift register of the interline sensor is operated in a uniphase mode, i.e., holding one of the two phase (.phi.2) at a D.C. potential while fluctuating the other phase (.phi.1) between a voltage that is sufficiently above and below that D.C. potential to facilitate transfer of charge from one phase to the next. The uniphase mode is facilitated by a single electrode, an indium tin oxide electrode, that covers both the phase that is held at a constant D.C. potential and the photodetector having photocapacitor charges. The charges are transferred from the photocapacitors to the vertical shift register by a third level clock into (.phi.1) adjacent the photodetectors utilizing the same ITO electrode for phase 2 of both the vertical and horizontal CCD shift registers is also proposed.

Abstract: The cross-sectional area of a thin-film transistor (TFT) is decreased in order to minimize bitline to supply leakage of the TFT. This is accomplished by utilizing a spacer etch process to manufacture a TFT having a very narrow and thin channel in a controllable manner. The spacer dimensions of the TFT may be adjusted by simply modifying the thicknesses of the poly gate and the channel poly. The channel thickness is limited by the thickness of the deposited channel polysilicon which may be as thin as approximately 300 .ANG. to 500 .ANG., and the channel width of the TFT corresponds to the height of the spacer etched along the polysilicon gate of the device which may be as small as approximately 0.15 to 0.25 .mu.m.

Abstract: A barrier at a uniform depth for an entire wafer is used to produce imaging devices less susceptible to noise pulses produced by the passage of ionizing radiation. The barrier prevents charge created in the bulk silicon of a CCD detector or a semiconductor logic or memory device from entering the collection volume of each pixel in the imaging device. The charge barrier is a physical barrier, a potential barrier, or a combination of both. The physical barrier is formed by an SiO.sub.2 insulator. The potential barrier is formed by increasing the concentration of majority carriers (holes) to combine with the electron's generated by the ionizing radiation. A manufacturer of CCD imaging devices can produce radiation-tolerant devices by merely changing the wafer type fed into his process stream from a standard wafer to one possessing a barrier beneath its surface, thus introducing a very small added cost to his production cost. An effective barrier type is an SiO.sub.2 layer.

Abstract: The image sensor charge detection amplifier has a charge storage well 60, a charge sensor 32 for sensing charge levels in the charge storage well 60, a charge drain 28 adjacent to the charge storage well 60, and charge transfer structures for transferring charge from the charge storage well 60 to the charge drain 28.

Abstract: The charge coupled device cell has a semiconductor layer 20 of a first conductivity type, a buried channel 22 of a second conductivity type on the semiconductor layer 20, a first virtual gate 24 in the buried channel 22, the first virtual gate is switched between at least two potential levels, and a first bipolar gate 42 in the buried channel 22 adjacent the first virtual gate 24.

Abstract: A semiconductor device which has a diffusion layer region in a semiconductor body, and a MIS transistor with a gate electrode formed on the semiconductor body that is connected to the diffusion layer region. The semiconductor device is made by the steps of forming a diffusion layer region in the upper layer of the semiconductor body forming a gate electrode on the upper surface of the semiconductor body through a gate insulating film which is connected to the diffusion layer region and forming source and drain regions on the upper layer of the semiconductor body on both sides of the gate electrode so that unnecessary electrical charges on the gate electrode of the MIS transistor and transfer electrodes of the CCD device are removed.

Abstract: The charge coupled device charge detection node includes a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type in the substrate; virtual gate regions of the first conductivity type formed in the second semiconductor layer, the virtual gate regions forming virtual phase potential areas; an insulating layer on the second semiconductor layer; a floating gate formed on the insulating layer, the floating gate is located above a portion of the second semiconductor layer that is between virtual gate regions, the floating gate forming a floating gate potential well in response to a voltage; a first transfer gate formed on the insulating layer and separated from the floating gate by a virtual gate region, the first transfer gate forming a transfer potential area in response to a voltage; and an electrode coupled to one of the virtual gate regions on the opposite side of the floating gate from the first transfer gate, the electrode increases the potential o

Abstract: An optical detector comprised of a MESFET having a larger than usual separation between its source and drain electrodes and a channel between the source and drain electrodes doped with carriers having a density of at least 10.sup.18 /cm.sup.3 whereby variation in the voltage of the gate electrode changes the optical gain.

Abstract: An image sensor element having at least one charge storage well 70 and 80, charge transfer structures for transferring charge from one charge storage well 70 to another charge storage well 80, and a charge sensor for sensing charge levels in a charge storage well 70 without removing the charge from the well.Other devices, systems and methods are also disclosed.

Abstract: An image sensing device with electronic shutter having a semiconductor substrate of a first conductivity type and a buried channel layer of a second conductivity type disposed on the substrate. Virtual phase electrodes in the buried channel layer having the first conductivity type form virtual gate potential areas in the substrate below the virtual phase electrodes. An insulating layer is formed on the substrate. Conductive electrodes disposed on the insulating layer and located over portions of the substrate between the virtual phase electrodes form clocked gate potential areas in the substrate below the conductive electrodes. The virtual gate potential areas and the clocked gate potential areas form charge transfer columns along which charge can be transferred to an end of the charge transfer column.

Abstract: A HACT device employing a thin-film overlay of a more strongly piezoelectric material can operate as a delay line and as a tapped delay line, or transversal filter, while requiring less total power for the SAW clock signal. The increased electrical potential per unit total SAW power thus realized facilitates coupling between the total SAW energy and the mobile charge carriers. Some materials systems, such as a GaAs substrate and a ZnO thin-film overlay, will require an intervening thin-film dielectric layer in between the HACT substrate and epitaxial layers and the thin-film piezoelectric overlay. This may be necessitated by chemical, semiconductor device processing, or adhesion incompatibilities between the substrate material and the thin-film overlay material.

Abstract: Generally, and in one form of the invention, a method for multiplying charge in a CCD cell is disclosed comprising the step of causing impact ionization of charge carriers in the CCD cell.Other devices, systems and methods are also disclosed.

Abstract: A transversal filter comprises an acoustic charge transport device comprising an input contact for introducing a signal into a buried channel through which the signal is transported by a high frequency acoustic wave and a plurality of non-destructive sense electrodes overlying the channel for successively sampling the signal. A memory device is provided for storing a plurality of tap weight signals, with each tap weight signal for being associated with one of the electrodes. A multiplier system is operably connected with each of the electrodes and with the storage device for generating the product of the signal sampled at each electrode and the associated tap weight signal. A summer is operably associated with the multiplier for summing the products and thereby generating an output signal.