Abstract: Various embodiments of the present disclosure are directed towards a pixel sensor including a first and second pair of photodetectors. The pixel sensor includes the first and second pair of photodetectors in a semiconductor substrate. The first pair of photodetectors are reflection symmetric with respect to a first line positioned at a midpoint between the first pair of photodetectors. The second pair of photodetectors are reflection symmetric with respect to a second line that intersects the first line at a center point. A first plurality of transistors overlying the semiconductor substrate laterally offset the first pair of photodetectors. A second plurality of transistors overlying the semiconductor substrate laterally offset the first plurality of transistors. The first and second pair of photodetectors are laterally between the first and second plurality of transistors. The first and second plurality of transistors are point symmetric with respect to the center point.

Abstract: A charge-coupled device (CCD) image sensor is provided. The CCD image sensor may include an array of photosensors that transfer charge to multiple vertical CCD shift registers, which then in turn transfer the charge to a horizontal CCD shift register. The horizontal CCD shift register then feeds an output buffer circuit. The output buffer circuit can include a load transistor implemented using a buried-channel drain (BCD) structure. The load transistor may include a gate conductor, a source diffusion region, a drain diffusion region, and a buried-channel drain region that at least partially extends under the gate conductor. The BCD region may be formed before or after the formation of the gate conductor. If desired, the BCD region can also be formed at the source edge. An image sensor configured in this way can exhibit higher source-drain breakdown voltages, enhanced amplifier gain, and reduced amplifier glow.

Abstract: A solid-state imaging device according to the present disclosure includes: a charge storage region that stores a signal charge obtained through photoelectric conversion in a photoelectric conversion film; an amplification transistor that amplifies the signal charge stored in the charge storage region in a corresponding pixel; a contact plug that is electrically connected to the charge storage region and contains a semiconductor material; and a line that is disposed above the contact plug and contains a semiconductor material. The contact plug and the charge storage region are electrically connected, and the contact plug and a gate electrode of the amplification transistor are electrically connected via the line.

Abstract: Methods and devices for connecting a through via and a terminal of a transistor formed of a strained silicon material are provided. The terminal, which can be a source or a drain of a NMOS or a PMOS transistor, is formed within a substrate. A first contact within a first inter-layer dielectric (ILD) layer over the substrate is formed over and connected to the terminal. A through via extends through the first ILD layer into the substrate. A second contact is formed over and connected to the first contact and the through via within a second ILD layer and a contact etch stop layer (CESL). The second ILD layer is over the CESL, and the CESL is over the first ILD layer, which are all below a first inter-metal dielectric (IMD) layer and the first metal layer of the transistor.

Abstract: A layout structure of a semiconductor integrated circuit is provided with which narrowing and breaking of metal interconnects near a cell boundary can be prevented without increasing the data amount and processing time for OPC. A cell A and a cell B are adjacent to each other along a cell boundary. The interconnect regions of metal interconnects from which to the cell boundary no other interconnect region exists are placed to be substantially axisymmetric with respect to the cell boundary, while sides of diffusion regions facing the cell boundary are asymmetric with respect to the cell boundary.

Abstract: Methods of electrically programming a diffusion resistor by using trapped charge in a trapped charge region adjacent to the resistor to vary the resistance of the resistor, and the resistor, are disclosed. In one embodiment, a method includes forming a diffusion resistor in a substrate; forming a trapped charge region adjacent to the diffusion resistor; and adjusting a resistance of the diffusion resistor by controlling the trapped charge in the trapped charge region.

Abstract: An accumulation mode transistor has an impurity concentration of a semiconductor layer in a channel region at a value higher than 2×1017 cm?3 to achieve a large gate voltage swing.

Abstract: A solid-state imaging apparatus is provided that including a plurality of amplifiers each one amplifying a signal from each one of a plurality of pixels. The amplifier including first and second field effect transistors, gate electrodes of which are connected to the same voltage node (VBL); and a first wiring connected between the voltage node and the gate electrodes of the first and second field effect transistors. The first and second field effect transistors are arranged in a direction perpendicular to a direction in which the plurality of amplifiers is arranged. Material of the first wiring has a resistivity smaller than that of the gate electrodes of the first and second field effect transistors.

Abstract: An accumulation mode transistor has an impurity concentration of a semiconductor layer in a channel region at a value higher than 2×1017 cm?3 to achieve a large gate voltage swing.

Abstract: Provided are a thin film transistor and a method of manufacturing the same. The thin film transistor includes: a lower structure; a semiconductor layer formed on the lower structure and including a plurality of doping regions; a first insulating layer and a second insulating layer formed on the semiconductor layer and separated from each other; a third insulating layer formed on the first insulating layer and the second insulating layer; and a gate electrode layer formed between regions of the third insulating layer respectively corresponding to the first insulating layer and the second insulating layer.

Abstract: In one embodiment, the invention provides substrates that are structured so that devices fabricated in a top layer thereof have properties similar to the same devices fabricated in a standard high resistivity substrate. Substrates of the invention include a support having a standard resistivity, a semiconductor layer arranged on the support substrate having a high-resistivity, preferably greater than about 1000 Ohms-cm, an insulating layer arranged on the high-resistivity layer, and a top layer arranged on the insulating layer. The invention also provides methods for manufacturing such substrates.

Abstract: In a method of making a silicon carbide semiconductor device having a MOSFET, after a mask is placed on a surface of a first conductivity type drift layer of silicon carbide, ion implantation is performed by using the mask to form a lower layer of a deep layer extending in one direction. A first conductivity type current scattering layer having a higher concentration than the drift layer is formed on the surface of the drift layer. After another mask is placed on a surface of the current scattering layer, ion implantation is performed by using the other mask to form an upper layer of the deep layer at a position corresponding to the lower layer in such a manner that the lower layer and the upper layer are connected together.

Abstract: A semiconductor device is provided which is capable of suppressing a reduction in electron mobility in a channel region formed in a strained silicon layer. A strained silicon layer is formed over a p type silicon-germanium layer formed over a semiconductor substrate. The strained layer has a thickness adjusted to be thicker than the critical film thickness at which no misfit dislocation occurs. Accordingly, misfit dislocations occur in the vicinity of the interface between the strained silicon layer and silicon-germanium layer.

Abstract: A novel nonvolatile memory element, which can be manufactured by a simple and high yield process by using an organic material and has a high on/off ratio, and a method for manufacturing such nonvolatile memory element. A switching layer (14) made of an electrical insulating radical polymer is provided between an anode layer (12) and a cathode layer (16). Further, a hole injection transport layer (13) is provided between the switching layer (14) and the anode layer (12), and an electron injection transport layer (15), between the switching layer (14) and the cathode layer (16). An intermediate layer is provided between the switching layer and the adjacent layer. The radical polymer is preferably nitroxide radical polymer. The switching layer (14), the hole injection transport layer (13) and the electron injection transport layer (15) are formed by being stacked by a wet process.

Abstract: Provided is a technology capable of suppressing a reduction in electron mobility in a channel region formed in a strained silicon layer. A p type strained silicon layer is formed over a p type silicon-germanium layer formed over a semiconductor substrate. The p type strained layer has a thickness adjusted to be thicker than the critical film thickness at which no misfit dislocation occurs. Accordingly, misfit dislocations occur in the vicinity of the interface between the p type strained silicon layer and p type silicon-germanium layer. At a position which is below the end of a gate electrode and at which misfit dislocations occur, the impurity concentration of the n type strained silicon layer and n type silicon-germanium layer is 1×1019 cm?3 or less.

Abstract: A method of fabricating a pixel cell having a shutter gate structure. First and second charge barriers are respectively created between a photodiode and a first charge storage region and between the first storage region and a floating diffusion region. A global shutter gate is formed to control the charge barrier and transfer charges from the photodiode to the first charge storage region by effectively lowering the first charge barrier. A transfer transistor acts to transfer charges from the first storage region to the floating diffusion region by reducing the second charge barrier.

Abstract: A method of forming an actuator and a relay using a micro-electromechanical (MEMS)-based process is disclosed. The method first forms the lower sections of a square copper coil, and then forms an actuation member that includes a core section and a horizontally adjacent floating cantilever section. The core section, which lies directly over the lower coil sections, is electrically isolated from the lower coil sections. The method next forms the side and upper sections of the coil, along with first and second electrodes that are separated by a switch gap. The first electrode lies directly over an end of the core section, while the second electrode lies directly over an end of the floating cantilever section.

Abstract: A solid-state image pickup device for preventing crosstalk between adjacent pixels by providing an overflow barrier at the deep potion of a substrate. A partial P type region is provided at the predetermined position of a lower layer region of the vertical transfer register and a channel stop region. This P type region adjusts potential in the lower layer region of the vertical transfer register and the channel stop region. Accordingly, since the potential in the lower layer region of the vertical transfer register and the channel stop region at both sides of the lower layer region is low, electric charges photoelectrically-converted by the sensor region are blocked by this potential barrier and cannot be diffused easily.

Abstract: Transistors and/or methods of fabricating transistors that include a source contact, drain contact and gate contact are provided. In some embodiments, a channel region is provided between the source and drain contacts and at least a portion of the channel regions includes a hybrid layer comprising semiconductor material. In particular embodiments of the present invention, the transistor is a current aperture transistor. The channel region may include pendeo-epitaxial layers or epitaxial laterally overgrown layers. Transistors and methods of fabricating current aperture transistors that include a trench that extends through the channel and barrier layers and includes semiconductor material therein are also provided.

Abstract: A method for fabricating a thermally stable ultralow dielectric constant film including Si, C, O and H atoms in a parallel plate chemical vapor deposition process utilizing a plasma enhanced chemical vapor deposition (“PECVD”) process is disclosed. Electronic devices containing insulating layers of thermally stable ultralow dielectric constant materials that are prepared by the method are further disclosed. To enable the fabrication of a thermally stable ultralow dielectric constant film, specific precursor materials are used, such as, silane derivatives, for instance, diethoxymethylsilane (DEMS) and organic molecules, for instance, bicycloheptadiene and cyclopentene oxide.

Abstract: A method of manufacturing a magnetic memory device includes forming an insulation layer on a substrate, forming a lower electrode on the insulation layer, forming a magneto-resistive film on an upper surface of the lower electrode, the magneto-resistive film including an insulation barrier layer and a plurality of magnetic films stacked on both sides of the insulation barrier layer, stacking a mask layer on the magneto-resistive film, performing ion etching on the magneto-resistive film, using the mask layer as a mask, thereby forming a magneto-resistive element, forming an insulation film on upper surfaces of the mask, the magneto-resistive element and the lower electrode, and etching the insulation film with an ion beam such that a side surface of the magneto-resistive element is exposed.

Abstract: A diode structure having high ESD stability is described. Other embodiments provide an integral power switching arrangement having an integrated low leakage diode.

Abstract: A cellular MOSgated device of planar or trench topology has base injection regions formed between pairs of cells to inject minority carriers to modulate the resistivity of the drift region.

Abstract: High density plasma chemical vapor deposition and etch back processes fill high aspect ratio gaps without liner erosion or further underlying structure attack. The characteristics of the deposition process are modulated such that the deposition component of the process initially dominates the sputter component of the process. For example, reactive gasses are introduced in a gradient fashion into the HDP reactor and introduction of bias power onto the substrate is delayed and gradually increased or reactor pressure is decreased. In the case of a multi-step etch enhanced gap fill process, the invention may involve gradually modulating deposition and etch components during transitions between process steps. By carefully controlling the transitions between process steps, including the introduction of reactive species into the HDP reactor and the application of source and bias power onto the substrate, structure erosion is prevented.

Abstract: A pixel sensor cell for use in a CMOS imager exhibiting improved storage capacitance. The source follower transistor is formed with a large gate that has an area from about 0.3 ?m2 to about 10 ?m2. The large size of the source follower gate enables the photocharge collector area to be kept small, thereby permitting use of the pixel cell in dense arrays, and maintaining low leakage levels. Methods for forming the source follower transistor and pixel cell are also disclosed.

Abstract: Embodiments of the invention provide an image sensor having an improved dynamic range. A pixel cell comprises at least one transistor structure. The transistor structure comprises at least one semiconductor channel region, at least one gate for controlling the channel region, and first and second leads respectively coupled to a source region on one side of the at least one channel region and a drain region on an opposite side of the at least one channel region. The transistor structure has at least two threshold voltages associated with the at least one channel region, and an I-V characteristic of the transistor structure is determined at least in part by the threshold voltages.

Abstract: A charge transfer element comprising a reverse conductive type well formed on the surface of one conductive type semiconductor substrate, the one conductive type channel region extending in one direction relative to the well, a transfer electrode formed intersecting the channel region, a floating diffusion region formed continuous from the channel region, and an output transistor having a gate connected to the floating diffusion region. In a region where the output transistor is formed, the dopant density profile in the depth direction of the semiconductor substrate exhibits the maximum value relative to a middle region.

Abstract: Active pixel sensors for a high quality imager are fabricated using a silicon-on-insulator (SOI) process by integrating the photodetectors on the SOI substrate and forming pixel readout transistors on the SOI thin-film. The technique can include forming silicon islands on a buried insulator layer disposed on a silicon substrate and selectively etching away the buried insulator layer over a region of the substrate to define a photodetector area. Dopants of a first conductivity type are implanted to form a signal node in the photodetector area and to form simultaneously drain/source regions for a first transistor in at least a first one of the silicon islands. Dopants of a second conductivity type are implanted to form drain/source regions for a second transistor in at least a second one of the silicon islands. Isolation rings around the photodetector also can be formed when dopants of the second conductivity type are implanted.

Abstract: A CMOS device includes a reverse electric conduction type well (2) formed on a monoelectric conduction type semiconductor substrate (1), a first MOS transistor (3) of a reverse electric conduction type channel formed on a surface of the semiconductor substrate, and a second MOS transistor (4) of monoelectric conduction type channel is formed on a surface of the well. In the present invention, resistance elements (8R, 7R, 2R) are formed in the semiconductor substrate on a lower side of a thick field oxide film (9) covering a surface of the semiconductor substrate. Further, a second resistance element (11R) composed of a polycrystal silicon layer is formed on an upper side of the field oxide film.

Abstract: A pixel sensor cell for use in a CMOS imager exhibiting improved storage capacitance. The source follower transistor is formed with a large gate that has an area from about 0.3 &mgr;m2 to about 10 &mgr;m2. The large size of the source follower gate enables the photocharge collector area to be kept small, thereby permitting use of the pixel cell in dense arrays, and maintaining low leakage levels. Methods for forming the source follower transistor and pixel cell are also disclosed.

Abstract: A process for fabricating a semiconductor structure, wherein the semiconductor structure includes a core region and a periphery region. The core region includes a plurality of transistors and the periphery region includes a plurality of transistors. The process includes depositing a middle-of-line liner using plasma enhanced chemical vapor deposition overlying the semiconductor structure. By using a plasma enhanced chemical vapor deposition the amount of MOL liner deposited in the core region and the periphery region can be controlled depending on the distances between transistors in the core region and periphery region.

Abstract: A method and apparatus for maintaining the state of a MEMS device in the event of a power failure are disclosed. The apparatus and method may be used with a MEMS device generally having one or more MEMS elements moveably coupled to a substrate that uses electrostatic clamping force to sustain the state of the MEMS element. According to the method, a capacitive or other charge-storing circuit is coupled between a clamping surface and an electrical ground. During normal operation, a clamping voltage is applied between the clamping surface and at least one MEMS element to retain the at least one MEMS element against the clamping surface. In the event of a power failure, the source of the clamping voltage and other circuit paths to ground are isolated from the clamping surface. The charge-storing circuit maintains an electric charge on the clamping surface.

Abstract: An active surface with a source area, a channel area and a drain area is provided in a semiconductor substrate. Each of the areas lie adjacent to a main surface of the semiconductor substrate. At least one trench is provided in the main surface of the semiconductor substrate. The trench is adjacent to the channel area and is situated in the gate electrode part. The gate electrode preferably has two opposite parts which are each adjacent to the channel area. The transistor is produced using standard process steps.

Abstract: The invention relates to a CCD of the buried-channel type comprising a charge-transport channel in the form of a zone (12) of the first conductivity type, for example the n-type, in a well (13) of the opposite conductivity type, in the example the p-type. In order to obtain a drift field in the channel below one or more gates (9, 10a) to improve the charge transfer, the well is provided with a doping profile, so that the average concentration decreases in the direction of charge transport. Such a profile can be formed by covering the area of the well during the well implantation with a mask, thereby causing fewer ions to be implanted below the gates (9, 10a) than below other parts of the channel. By virtue of the invention, it is possible to produce a gate (10a) combining a comparatively large length, for example in the output stage in front of the output gate (9) to obtain sufficient storage capacity, with a high transport rate.

Abstract: There is provided a transistor, which includes a deoxyribonucleic acid molecule or a deoxyribonucleic acid molecule aggregate as a part of structural materials, has a source electrode member, a drain electrode member and a gate electrode member, in which at least one of three electrode members connects to the deoxyribonucleic acid molecule or deoxyribonucleic acid molecule aggregate.

Abstract: A barrier area is located adjacent a horizontal transfer area and spaced from a field insulating area. The barrier area includes an insulating layer and a conductor extending from the horizontal transfer layer over the surface of a semiconductor substrate, a barrier layer of a second conductivity type formed under the surface of the semiconductor substrate and adjacent a first impurity layer of a first conductivity type of the horizontal transfer area, and a second impurity layer extending from the horizontal transfer area and formed under the barrier layer. A discharge area is located between the barrier area and the field insulating area.

Abstract: It is known in charge coupled devices to use a dual layer of silicon oxide and silicon nitride as the gate dielectric. Since silicon nitride is practically impermeable to hydrogen, the nitride layer is usually provided with openings through which hydrogen can penetrate up to the surface of the silicon body during the annealing step carried out for passivating the surface. The openings in the nitride layer are provided by a known method, with gates in a first poly layer serving as a mask, in that the nitride is removed from between these gates and an oxidation step is subsequently carried out. According to the invention, the openings in the nitride layer are formed by means of a separate mask (20), such that the edges of the openings (9) in the nitride layer (8) lie at some distance from the edges of the gates.

Abstract: A pixel sensor cell for use in a CMOS imager exhibiting improved storage capacitance. The source follower transistor is formed with a large gate that has an area from about 0.3 &mgr;m2 to about 10 &mgr;m2. The large size of the source follower gate enables the photocharge collector area to be kept small, thereby permitting use of the pixel cell in dense arrays, and maintaining low leakage levels. Methods for forming the source follower transistor and pixel cell are also disclosed.

Abstract: In a solid-state image pickup device, a transfer register 10 is provided with an overflow control gate OFCG and an overflow drain OFD, and the gate electrode 12A of the overflow control gate OFCG is formed so as to be superposed on the lower-layer electrodes St1, 13 of the transfer register 10 side the overflow drain OFD side.

Abstract: Generally, and in one form of the invention, a monolithic solid state image-sensing device is disclosed. The device utilizes only a single layer of polysilicon deposition in its fabrication process that is split into two or more phases by very narrow gaps. The single polysilicon layer makes the fabrication process simpler and more compatible with modern semiconductor manufacturing technology. The device also incorporates a lateral anti-blooming drain structure that is formed by a self-aligned diffusion process and does not need a polysilicon gate for its proper function.

Abstract: A charge coupled device has an n- type charge accumulating layer equal to or less than 5 micron in width, and the unit cells suffer from reduction of signal charge accumulated therein and an increased pulse height of a pulse signal for a substrate shutter, wherein at least one p- type local impurity region is formed in such a manner as to form a p-n junction together with the n- type charge accumulating layer and the n- type semiconductor substrate, thereby increasing the amount of signal charge accumulated in each unit cell without sacrifice of the pulse height of the pulse signal for the substrate shutter.

Abstract: An active pixel is described comprising a semiconductor substrate and a radiation sensitive source of carriers in the substrate, such as for instance, a photodiode. A non-carrier storing, carrier collecting region in the substrate is provided for attracting carriers from the source as they are generated. At least one doped or inverted region of a first conductivity is provided in or on the substrate for storing the carriers before read-out. At least one non-carrier storing, planar current flow, carrier transport pathway is provided from or through the carrier collecting region to the at least one doped or inverted region to transfer the carriers without intermediate storage to the read-out electronics.

Abstract: The disclosure relates to charge-coupled devices taking the form of shift registers and, more specifically, to those working in the MPP (Multi-Pinned Phase) mode, i.e. with high negative polarisation of the electrodes during the phases of waiting or of integration of integration of the photosensitive charges. These registers use a potential barrier created by a P type compensating implantation in a zone 16 located beneath a first electrode of each stage of the register. This barrier separates the stages from one another. To increase the charge storage capacity during the storage phase and the charge transfer capacity during the transfer, it is provided that the compensating implantation of the zone 16 will extend beneath only one part (and not the totality) of the first electrode of each stage of the register. Application to photosensitive image sensors, analog delay lines, charge-coupled analog memories, working in MPP mode during the waiting phases to limit losses of information due to the dark current.

Abstract: The object of the semiconductor apparatus to be used in the semiconductor integrated circuit is to restrain the time dependent fluctuations of the resistance value. To achieve the object, the semiconductor apparatus comprises an active area formed on one conductive type semiconductor substrate surface, a first impurity diffusion layer formed on the active area, of an inverted conductive type reverse in characteristics from the one conductive type, a second impurity diffusion layer of the reverse conductive type formed to cover the first impurity diffusion layer, and an electrode film formed through a field oxide film on the second impurity diffusion layer. The electric potential of the electrode film is kept at an electric potential where a majority carrier is induced into the second impurity diffusion layer.

Abstract: The present invention provides an interline solid state image sensor comprising the following elements. A plurality of vertical charge coupled device resistors are provided, each of which extends in a vertical direction. The vertical charge coupled device resistors are parallel to each other. A plurality of photo-diodes are aligned along one side of each of the vertical charge coupled device resistors so that the photo-diodes are aligned between adjacent two vertical charge coupled device resistors. Each of the photo-diodes is connected via a charge read-out gate region to the vertical charge coupled device resistor. Each of the vertical charge coupled device resistor comprises laminations of a first conductivity type diffusion layer and a second conductivity type diffusion layer extending under the first conductivity type diffusion layer. A lateral charge coupled resistor extends in a lateral direction. The lateral charge coupled resistor is coupled with ends of the vertical charge coupled device resistors.

Abstract: An amplifying type photoelectric converting device is disclosed. The device includes: a semiconductor substrate of a first conductive type; a well portion of a second conductive type for accumulating signal charges generated by photoelectric conversion; a semiconductor region of the first conductive type provided in a region in the well portion; a first gate region including a first electrode; and a second gate region being adjacent to the first gate region and including a second electrode. An active element is formed between the semiconductor region and the semiconductor substrate, and a change in an operational characteristic of the active element which is generated by the signal charges is used as an output signal.

Abstract: A charged coupled device structure (CCD) and a method for fabricating the CCD structure, which induces a maximum potential distribution difference by utilizing gate insulation films having different physical properties. The charged coupled device includes a semiconductor substrate, a first insulation layer formed on the semiconductor substrate, a plurality of first electrodes spaced at fixed intervals over the first insulation layer, a second insulation layer formed only between the plurality of first electrodes and the first insulation layer, a third insulation layer formed over the entire exposed surface of the first electrodes and the first insulation layer, and a plurality of second electrodes formed only on the surface area corresponding to spaces between the plurality of first electrodes. This gate insulation layers having different physical properties induces a maximum potential distribution difference in a semiconductor substrate with a dielectric constant difference between the insulation layers.

Abstract: An infrared solid-state image sensing apparatus is provided with a plurality of photoelectric converting sections arranged vertically and horizontally in a matrix pattern on a semiconductor substrate of a first conducting type; a plurality of vertical CCDs which have first buried channels of a second conducting type and electrodes disposed thereon with an insulating film between and which are disposed adjacently to the photoelectric converting sections; and a horizontal CCD having a second buried channel of the second conducting type and electrodes disposed thereon with an insulating film between and which is disposed adjacently to one side of the vertical CCDs. The first and second buried channels are provided with a low-concentration region having a uniform diffusion depth. Further, the surface of each first buried channel is provided with a high-concentration region of the second conducting type having a higher concentration than that of the surface of the second buried channel.

Abstract: A charge detection device for converting a signal charge consisting of carriers of a first polarity externally provided into a voltage signals, the charge detection device comprising a MOS transistor, the MOS transistor including: a first semiconductor layer having a transistor channel for carriers of a second polarity; an insulating layer provided on the first semiconductor layer; and a gate electrode provided on the insulating layer, wherein transistor characteristics of the MOS transistor are changed by the signal charge accumulated in a surface region the first semiconductor layer immediately below in interface between the first semiconductor layer and the insulating layer, thereby detecting a quantity of the signal charge.

Abstract: A charge transfer device and a solid state image sensor using the same, capable of transferring signal charge at a high signal to noise ratio (S/N ratio) and preventing an occurrence of dark current. They include a double-layered charge transfer path structure provided by forming a surface channel region on a buried channel region formed in a semiconductor substrate, the surface channel region having a conductivity opposite to that of the buried channel region. The surface channel region of the doubled-layered structure is used for accumulating dark current generated from boundary surfaces between the substrate and a gate insulating film, whereas the buried channel region is used for transferring optical signal charge. Where minus and/or plus drive voltages are applied to the transfer electrodes, there is no increase in dark current, in accordance with the present invention. The quantity of transferred signal charge can be greatly increased.