Channel Confinement Patents (Class 257/224)
  • Patent number: 10825849
    Abstract: A solid-state image pickup device 1 according to the present invention includes a semiconductor substrate 2 on which a pixel 20 composed of a photodiode 3 and a transistor is formed. The transistor comprising the pixel 20 is formed on the surface of the semiconductor substrate, a pn junction portion formed between high concentration regions of the photodiode 3 is provided within the semiconductor substrate 2 and a part of the pn junction portion of the photodiode 3 is extended to a lower portion of the transistor formed on the surface of the semiconductor substrate 2. According to the present invention, there is provided a solid-state image pickup device in which a pixel size can be microminiaturized without lowering a saturated electric charge amount (Qs) and sensitivity.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: November 3, 2020
    Assignee: Sony Corporation
    Inventors: Takayuki Ezaki, Teruo Hirayama
  • Patent number: 10356345
    Abstract: The present technology relates to a solid-state imaging device, an electronic apparatus, and an AD converter that are capable of suppressing the occurrence of an error in AD conversion results. The solid-state imaging device includes a pixel section having a plurality of pixels, a comparator for comparing a pixel signal outputted from the pixels with a reference signal, and a counter for counting the time of comparison made by the comparator. The comparator includes a first amplifier for comparing the pixel signal with the reference signal, a second amplifier that has a first transistor and amplifies an output signal of the first amplifier, and a second transistor having the same polarity as the first transistor. A gate of the second transistor is connected to an output end of the first amplifier, and a source and a drain of the second transistor are connected to the same fixed potential as a source of the first transistor. The present technology is applicable, for example, to a CMOS image sensor.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: July 16, 2019
    Assignee: Sony Corporation
    Inventors: Katsuhiko Hanzawa, Shizunori Matsumoto
  • Patent number: 10046251
    Abstract: An apparatus is disclosed for maintaining constant fluid pressure and equalized fluid flow among a plurality of downcomer lines through which liquid from a tower is directed. A substantially annular fluid distribution belt is disposed at the circumference of the tower. The fluid distribution belt collects liquid from the tower. At least two outlets direct liquid from the fluid distribution belt out of the tower and into a corresponding number of downcomer lines disposed external to the tower.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: August 14, 2018
    Assignee: ExxonMobil Upstream Research Company
    Inventors: Edward J. Grave, Nicholas F. Urbanski
  • Patent number: 10015419
    Abstract: The present technology relates to a solid-state imaging device, an electronic apparatus, and an AD converter that are capable of suppressing the occurrence of an error in AD conversion results. The solid-state imaging device includes a pixel section having a plurality of pixels, a comparator for comparing a pixel signal outputted from the pixels with a reference signal, and a counter for counting the time of comparison made by the comparator. The comparator includes a first amplifier for comparing the pixel signal with the reference signal, a second amplifier that has a first transistor and amplifies an output signal of the first amplifier, and a second transistor having the same polarity as the first transistor. A gate of the second transistor is connected to an output end of the first amplifier, and a source and a drain of the second transistor are connected to the same fixed potential as a source of the first transistor. The present technology is applicable, for example, to a CMOS image sensor.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: July 3, 2018
    Assignee: Sony Corporation
    Inventors: Katsuhiko Hanzawa, Shizunori Matsumoto
  • Patent number: 10008582
    Abstract: Structures for spacers of a field-effect transistor and methods for forming such spacers. A mask layer has a feature separated from a vertical sidewall of a first gate structure by a space of predetermined width that exposes a top surface of a semiconductor body. A spacer is formed adjacent to the vertical sidewall of the first gate structure. The spacer has a first section in the space and a second section. The first section of the spacer is located vertically between the second section of the spacer and the top surface of the semiconductor body. The first section of the spacer extends through the space to the top surface of the semiconductor body, and the first section of the spacer fully fills the space.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: June 26, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Chun-chen Yeh
  • Patent number: 9093527
    Abstract: A high-voltage NMOS transistor with low threshold voltage. The body doping that defines the channel region is in the form of a deep p-well. An additional shallow p-doping is arranged as a channel stopper on the transistor head. This additional shallow p-doping is produced in the semiconductor substrate at the end of the deep p-well that faces away from the channel region, and extends up to a location underneath a field oxide region that encloses the active window. The leakage current of the parasitic transistor at the transistor head is suppressed with the channel stopper.
    Type: Grant
    Filed: November 13, 2006
    Date of Patent: July 28, 2015
    Assignee: AMS AG
    Inventors: Martin Knaipp, Georg Röhrer
  • Patent number: 9018751
    Abstract: A semiconductor module system includes a module substrate and a semiconductor substrate having a through wire interconnect bonded to an electrode on the module substrate. The through wire interconnect includes a via, a wire in the via having a first end bonded to a substrate contact on the semiconductor substrate and a polymer layer at least partially encapsulating the wire. The semiconductor module system can also include a second substrate stacked on the semiconductor substrate having a second through wire interconnect in electrical contact with the through wire interconnect.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: April 28, 2015
    Assignee: Micron Technology, Inc.
    Inventors: David R Hembree, Alan G. Wood
  • Patent number: 8969924
    Abstract: Various aspects of the invention are directed to memory circuits and their implementation. According to an example embodiment, an apparatus includes a channel region between raised source and drain regions which are configured and arranged with respective bandgap offsets relative to the channel region to confine carriers in the channel region. The apparatus also includes front and back gates respectively separated from the channel region by gate dielectrics. The raised source and drain regions have respective portions laterally adjacent the front gate and adjacent the channel region. Carriers are stored in the channel region via application of voltage(s) to the front and back gates, and relative to bias(es) at the source and drain regions.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: March 3, 2015
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Ashish Pal, Aneesh Nainani, Krishna Chandra Saraswat
  • Patent number: 8969190
    Abstract: Disclosed herein are various methods of forming a layer of silicon on a layer of silicon/germanium. In one example, a method disclosed herein includes forming a silicon/germanium material on a semiconducting substrate, after forming the silicon/germanium material, performing a heating process to raise a temperature of the substrate to a desired silicon formation temperature while flowing a silicon-containing precursor and a chlorine-containing precursor into the deposition chamber during the heating process, and, after the temperature of the substrate reaches the desired silicon formation temperature, forming a layer of silicon on the silicon/germanium material.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: March 3, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Joachim Patzer
  • Patent number: 8900959
    Abstract: A gate-first processing scheme for forming a nanomesh field effect transistor is provided. An alternating stack of two different semiconductor materials is patterned to include two pad regions and nanowire regions. A semiconductor material is laterally etched selective to another semiconductor material to form a nanomesh including suspended semiconductor nanowires. A stack of a gate dielectric, a gate electrode, and a gate cap dielectric is formed over the nanomesh. A dielectric spacer is formed around the gate electrode. An isotropic etch is employed to remove dielectric materials that are formed in lateral recesses of the patterned alternating stack. A selective epitaxy process can be employed to form a source region and a drain region.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Paul Chang, Isaac Lauer, Jeffrey W. Sleight
  • Patent number: 8896734
    Abstract: A solid-state image sensor includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type that is arranged to contact a lower face of the first semiconductor region and functions as a charge accumulation region, a third semiconductor region including side faces surrounded by the second semiconductor region, a fourth semiconductor region of the second conductivity type that is arranged apart from the second semiconductor region, and a transfer gate that forms a channel to transfer charges accumulated in the second semiconductor region to the fourth semiconductor region. The third semiconductor region is one of a semiconductor region of the first conductivity type and a semiconductor region of the second conductivity type whose impurity concentration is lower than that in the second semiconductor region.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: November 25, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Mahito Shinohara
  • Patent number: 8878181
    Abstract: An oxide thin film transistor (TFT) and a fabrication method thereof are provided.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: November 4, 2014
    Assignee: LG Display Co., Ltd.
    Inventors: Hoon Yim, Dae-Hwan Kim
  • Patent number: 8847285
    Abstract: In various embodiments, a charge-coupled device includes channel stops laterally spaced away from the channel by fully depleted regions.
    Type: Grant
    Filed: September 20, 2012
    Date of Patent: September 30, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventor: Christopher Parks
  • Patent number: 8796742
    Abstract: An alternating stack of two different semiconductor materials is patterned to include two pad regions and nanowire regions. A semiconductor material is laterally etched selective to another semiconductor material to form a nanomesh including suspended semiconductor nanowires. Gate dielectrics, a gate electrode, and a gate cap dielectric are formed over the nanomesh. A dielectric spacer is formed around the gate electrode. The semiconductor materials in the two pad regions and physically exposed portions of the nanomesh are removed employing the dielectric spacer and the gate cap dielectric as an etch mask. A source region and a drain region are epitaxially grown from end surfaces of the nanomesh.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: August 5, 2014
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Paul Chang, Isaac Lauer, Jeffrey W. Sleight
  • Patent number: 8581387
    Abstract: A through wire interconnect for a semiconductor substrate includes a via extending through the semiconductor substrate from a first side to a second side thereof, and a wire in the via electrically insulated from the semiconductor substrate having a first end with a bonded connection to the substrate contact and a second end proximate to the second side of the semiconductor substrate. The through wire interconnect also includes a first contact on the wire proximate to the first side of the semiconductor substrate, a second contact on the second end of the wire, and a polymer layer on the first side at least partially encapsulating the wire while leaving the first contact exposed. The through wire interconnect can also include a bonding member bonded to the first end of the wire and to the substrate contact having a tip portion forming the first contact.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: November 12, 2013
    Assignee: Micron Technology, Inc.
    Inventors: David R. Hembree, Alan G. Wood
  • Patent number: 8487349
    Abstract: The invention describes in detail the structure of a CMOS image sensor pixel that senses color of impinging light without having absorbing filters placed on its surface. The color sensing is accomplished by having a vertical stack of three-charge detection nodes placed in the silicon bulk, which collect electrons depending on the depth of their generation. The small charge detection node capacitance and thus high sensitivity with low noise is achieved by using fully depleted, potential well forming, buried layers instead of undepleted junction electrodes. Two embodiments of contacting the buried layers without substantially increasing the node capacitances are presented.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: July 16, 2013
    Assignee: Foveon, Inc.
    Inventors: Jaroslav Hynecek, Richard B. Merrill, Russel A. Martin
  • Patent number: 8404523
    Abstract: A method for fabricating a stacked semiconductor system with encapsulated through wire interconnects includes providing a substrate having a first side, a second side and a substrate contact; forming a via in the substrate contact and the substrate to the second side; placing a wire in the via; forming a first contact on the wire proximate to the first side and a second contact on the wire proximate to the second side; and forming a polymer layer on the first side leaving the first contact exposed. The method also includes stacking two or more substrates and electrically connecting the through wire interconnects on the substrates.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: March 26, 2013
    Assignee: Micron Technoloy, Inc.
    Inventors: David R. Hembree, Alan G. Wood
  • Patent number: 8217510
    Abstract: A semiconductor module system includes a module substrate and first and second semiconductor components stacked on the module substrate. The stacked semiconductor components include through wire interconnects that form an internal signal transmission system for the module system. Each through wire interconnect includes a via, a wire in the via and first and second contacts on the wire.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: July 10, 2012
    Assignee: Micron Technology, Inc.
    Inventors: David R. Hembree, Alan G. Wood
  • Patent number: 8203151
    Abstract: A method for fabricating a semiconductor device includes the steps of forming a SiC film, forming trenches at a surface of the SiC film, heat-treating the SiC film with silicon supplied to the surface of the SiC film, and obtaining a plurality of macrosteps to constitute channels, at the surface of the SiC film by the step of heat-treating. Taking the length of one cycle of the trenches as L and the height of the trenches as h, a relation L=h(cot ?+cot ?) (where ? and ? are variables that satisfy the relations 0.5??, ??45) holds between the length L and the height h. Consequently, the semiconductor device can be improved in property.
    Type: Grant
    Filed: October 18, 2010
    Date of Patent: June 19, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Takeyoshi Masuda
  • Patent number: 8164086
    Abstract: A phase controllable field effect transistor device is described. The device provides first and second scattering sites disposed at either side of a conducting channel region, the conducting region being gated such that on application of an appropriate signal to the gate, energies of the electrons in the channel region defined between the scattering centers may be modulated.
    Type: Grant
    Filed: September 17, 2009
    Date of Patent: April 24, 2012
    Assignee: The Provost, Fellows and Scholars of the Colege of the Holy and Undivided Trinity of Queen Elizabeth Near Dublin
    Inventors: John Boland, Stefano Sanvito, Borislav Naydenov
  • Patent number: 8120167
    Abstract: A method for fabricating a semiconductor component with an encapsulated through wire interconnect includes the steps of providing a substrate having a first side, a second side and a substrate contact; forming a via in the substrate contact and the substrate to the second side; placing a wire in the via; forming a first contact on the wire proximate to the first side and a second contact on the wire proximate to the second side; and forming a polymer layer on the first side leaving the first contact exposed. The polymer layer can be formed using a film assisted molding process including the steps of: forming a mold film on tip portions of the bonding members, molding the polymer layer, and then removing the mold film to expose the tip portions of the bonding members. The through wire interconnect provides a multi level interconnect having contacts on opposing sides of the semiconductor substrate.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: February 21, 2012
    Assignee: Micron Technology, Inc.
    Inventors: David R. Hembree, Alan G. Wood
  • Patent number: 8093630
    Abstract: The invention provides a semiconductor device and a lateral diffused metal-oxide-semiconductor transistor. The semiconductor device includes a substrate having a first conductive type. A gate is disposed on the substrate. A source doped region is formed in the substrate, neighboring with a first side of the gate, wherein the source doped region has a second conductive type different from the first conductive type. A drain doped region is formed in the substrate, neighboring with a second side opposite to the first side of the gate. The drain doped region is constructed by a plurality of first doped regions with the first conductive type and a plurality of second doped regions with the second conductive type, wherein the first doped regions and the second doped regions are alternatively arranged.
    Type: Grant
    Filed: June 2, 2009
    Date of Patent: January 10, 2012
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Jimmy Lin, Shang-Hui Tu, Ming-Horng Hsiao
  • Patent number: 8039889
    Abstract: A non-volatile memory device includes a semiconductor substrate having a first section including a substantially planar first top surface, a second section including a substantially planar second top surface, and a sidewall extending between the first and second top surfaces. The second top surface of the substrate is closer to a bottom surface of the substrate than is the first top surface. A charge storage pattern extends on the first and second top surfaces of the substrate and along the sidewall therebetween. A source region in the first section of the substrate extends from the first top surface into the second section of the substrate and has a stepped portion defined by the sidewall and the second top surface. Related fabrication methods and methods of operation are also discussed.
    Type: Grant
    Filed: November 26, 2007
    Date of Patent: October 18, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Weon-Ho Park
  • Patent number: 7883908
    Abstract: A method for fabricating a semiconductor component with an encapsulated through wire interconnect includes the steps of providing a substrate having a first side, a second side and a substrate contact; forming a via in the substrate contact and the substrate to the second side; placing a wire in the via; forming a first contact on the wire proximate to the first side and a second contact on the wire proximate to the second side; and forming a polymer layer on the first side leaving the first contact exposed. The polymer layer can be formed using a film assisted molding process including the steps of: forming a mold film on tip portions of the bonding members, molding the polymer layer, and then removing the mold film to expose the tip portions of the bonding members. The through wire interconnect provides a multi level interconnect having contacts on opposing sides of the semiconductor substrate.
    Type: Grant
    Filed: October 19, 2009
    Date of Patent: February 8, 2011
    Assignee: Micron Technology, Inc.
    Inventors: David R. Hembree, Alan G. Wood
  • Patent number: 7858481
    Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: December 28, 2010
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Robert S. Chau, Suman Datta, Mark L. Doczy, Brian S. Doyle, Jack T. Kavalieros, Amlan Majumdar, Matthew V. Metz, Marko Radosavljevic
  • Patent number: 7791161
    Abstract: Structure and method are provided for semiconductor devices. The devices include trenches filled with highly doped polycrystalline semiconductor, extending from the surface into the body of the device for, among other things: (i) reducing substrate current injection, (ii) reducing ON-resistance and/or (iii) reducing thermal impedance to the substrate. For isolated LDMOS devices, the resistance between the lateral isolation wall (tied to the source) and the buried layer is reduced, thereby reducing substrate injection current. When placed in the drain of a lateral device or in the collector of a vertical device, the poly-filled trench effectively enlarges the drain or collector region, thereby lowering the ON-resistance. For devices formed on an oxide isolation layer, the poly-filled trench desirably penetrates this isolation layer thereby improving thermal conduction from the active regions to the substrate. The poly filled trenches are conveniently formed by etch and refill.
    Type: Grant
    Filed: August 25, 2005
    Date of Patent: September 7, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ronghua Zhu, Vishnu K. Khemka, Amitava Bose
  • Patent number: 7737492
    Abstract: A semiconductor device includes a semiconductor substrate having an active region having a plurality of recessed channel areas extending across the active region and a plurality of junction areas also extending across the active region. Gates are formed in and over the recessed channel areas of the active region. A device isolation structure is formed in the semiconductor substrate to delimit the active region, and the device isolation structure has recessed portions, each of which is formed near a junction area of the active region. Landing plugs are formed over each junction area in the active region and extend to fill the recessed portion of the device isolation structure outside the active region. The semiconductor device suppresses interference caused by an adjoining gate leading to a decrease in leakage current from a cell transistor.
    Type: Grant
    Filed: February 19, 2008
    Date of Patent: June 15, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Tae Kyung Oh
  • Patent number: 7659612
    Abstract: A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) attached to the substrate contact. The through wire interconnect provides a multi level interconnect having contacts on opposing first and second sides of the semiconductor substrate. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via having a bonded connection with the substrate contact, a first contact on the wire proximate to the first side, and a second contact on the wire proximate to the second side. The through wire interconnect (TWI) also includes a polymer layer which partially encapsulates the through wire interconnect (TWI) while leaving the first contact exposed. The semiconductor component can be used to fabricate stacked systems, module systems and test systems. A method for fabricating the semiconductor component can include a film assisted molding process for forming the polymer layer.
    Type: Grant
    Filed: April 24, 2006
    Date of Patent: February 9, 2010
    Assignee: Micron Technology, Inc.
    Inventors: David R. Hembree, Alan G. Wood
  • Patent number: 7541627
    Abstract: The invention describes in detail the structure of a CMOS image sensor pixel that senses color of impinging light without having absorbing filters placed on its surface. The color sensing is accomplished by having a vertical stack of three-charge detection nodes placed in the silicon bulk, which collect electrons depending on the depth of their generation. The small charge detection node capacitance and thus high sensitivity with low noise is achieved by using fully depleted, potential well forming, buried layers instead of undepleted junction electrodes. Two embodiments of contacting the buried layers without substantially increasing the node capacitances are presented.
    Type: Grant
    Filed: March 8, 2004
    Date of Patent: June 2, 2009
    Assignee: Foveon, Inc.
    Inventors: Jaroslav Hynecek, Richard B. Merrill, Russel A. Martin
  • Patent number: 7456448
    Abstract: A semiconductor device, including a first MIS-type transistor formed in a first region of a semiconductor region, the first region being of a first conductivity type, the first MIS-type transistor including: a first gate insulating film formed on the first region; a first gate electrode formed on the first gate insulating film; a first extension diffusion layer of a second conductivity type formed in a region of the first region under and beside the first gate electrode; and a first fluorine diffusion layer formed in a first channel region of the first conductivity type sandwiched between portions of the first extension diffusion layer, wherein portions of the first fluorine diffusion layer extend from the first extension diffusion layer and overlap together in a region directly under the first gate electrode.
    Type: Grant
    Filed: October 10, 2006
    Date of Patent: November 25, 2008
    Assignee: Panasonic Corporation
    Inventors: Naoki Kotani, Akio Sebe, Gen Okazaki, Tokuhiko Tamaki
  • Patent number: 7420147
    Abstract: A method of fabricating a multichannel plate is provided. The method includes providing a N layers, each layer having an array of wells formed therein. The N layers are aligned and stacked. The stack of N layers are sliced along a first and second line of the array of wells. The first line of the array of wells provides a first surface corresponding to a first array of channel openings of the MCP, and the second line of said array of wells provides a second surface corresponding to a second array of channel openings of the MCP. This method provides several functional benefits compared to conventional methods. These include, but are not limited to: the ability to produce well known and well characterized channels; the ability to produce well known and well characterized periods between channels; the ability to produce channels having any desired secondary electron emission enabling material therein; the ability to fabricate the substrate and/or final MCP of silicon.
    Type: Grant
    Filed: April 24, 2006
    Date of Patent: September 2, 2008
    Assignee: Reveo, Inc.
    Inventor: Sadeg M. Faris
  • Patent number: 7365380
    Abstract: An object of the present invention is to provide a photoelectric conversion device, wherein improvement of charge transfer properties when charge is output from a charge storage region and suppression of dark current generation during charge storage are compatible with each other. This object is achieved by forming a depletion voltage of a charge storage region in the range from zero to one half of a power source voltage (V), forming a gate voltage of a transfer MOS transistor during a charge transfer period in the range from one half of the power source voltage to the power source voltage (V) and forming a gate,voltage of the transfer MOS transistor during a charge storage period in the range from minus one half of the power source voltage to zero (V).
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: April 29, 2008
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiroshi Yuzurihara, Seiichi Tamura, Ryuichi Mishima
  • Patent number: 7329926
    Abstract: A semiconductor device including a gate located over a semiconductor substrate and a source/drain region located adjacent the gate. The source/drain region is bounded by an isolation structure that includes a constricted current passage between the gate and the source/drain region.
    Type: Grant
    Filed: April 1, 2003
    Date of Patent: February 12, 2008
    Assignee: Agere Systems Inc.
    Inventor: Yehuda Smooha
  • Patent number: 7285808
    Abstract: A plurality of optical sensors (4) are arranged in a surface region of a semiconductor substrate (6) in a matrix pattern, and electric charge generated by the optical sensors (4) is transferred by first and second transfer electrodes (12 and 14) embedded under the optical sensors (4). The semiconductor substrate (6) is constructed by laminating a support substrate (16) composed of silicon, a buffer layer (18), and a thin silicon layer (20) composed of single-crystal silicon. p? regions (26) (overflow barrier) and n-type regions (28) which function as transfer paths are formed under the optical sensors (4). The first and the second transfer electrodes (12 and 14) are disposed between the buffer layer (18) and the n-type regions (28), and an insulating film (30) is interposed between the n-type regions (28) and the first and the second transfer electrodes (12 and 14). In this structure, the light-receiving area is large since the transfer electrodes are not disposed in the front region.
    Type: Grant
    Filed: October 2, 2002
    Date of Patent: October 23, 2007
    Assignee: Sony Corporation
    Inventor: Takashi Kasuga
  • Patent number: 7235824
    Abstract: An active gate includes a substrate of a first conductivity type, a channel of a second conductivity type formed in the substrate, a first gate region of the first conductivity type formed in a corresponding first portion of the channel, and a first contact connected to the first gate region. The first gate region covers a first area, and the first contact covers a fraction of the first area. A pixel or register element includes an active gate, a second gate region of the first conductivity type formed in a corresponding second portion of the channel, and a second contact connected to the second gate region. The second gate region covers a second area and is spaced by a first gap from the first gate region. The second contact covers a fraction of the second area. The pixel or register element further includes a first gate electrode insulatively spaced from and disposed over the first gap.
    Type: Grant
    Filed: June 11, 2001
    Date of Patent: June 26, 2007
    Assignee: Dalsa, Inc.
    Inventor: Surendra Singh
  • Patent number: 7183597
    Abstract: The present invention relates to a method of forming a quantum wire gate device. The method includes patterning a first oxide upon a substrate. Preferably the first oxide pattern is precisely and uniformly spaced to maximize quantum wire numbers per unit area. The method continues by forming a first nitride spacer mask upon the first oxide and by forming a first oxide spacer mask upon the first nitride spacer mask. Thereafter, the method continues by forming a second nitride spacer mask upon the first oxide spacer mask and by forming a plurality of channels in the substrate that are aligned to the second nitride spacer mask. A dielectric is formed upon the channel length and the method continues by forming a gate layer over the plurality of channels. Because of the inventive method and the starting scale, each of the plurality of channels is narrower than the mean free path of semiconductive electron flow therein.
    Type: Grant
    Filed: December 13, 2004
    Date of Patent: February 27, 2007
    Assignee: Intel Corporation
    Inventor: Brian Doyle
  • Patent number: 7078745
    Abstract: A dopant gradient region of a first conductivity type and a corresponding channel impurity gradient below a transfer gate and adjacent a charge collection region of a CMOS imager photodiode are disclosed. The channel impurity gradient in the transfer gate provides a complete charge transfer between the charge collection region of the photodiode and a floating diffusion node. The dopant gradient region is formed by doping a region at one end of the channel with a low enhancement dopant and another region at the other end of the channel with a high enhancement dopant.
    Type: Grant
    Filed: March 5, 2003
    Date of Patent: July 18, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Inna Patrick
  • Patent number: 6998656
    Abstract: A double-injection field-effect transistor has an anode, a cathode, a substantially transparent channel, a substantially transparent gate insulator, and at least one substantially transparent gate electrode. The transistor may also have a substantially transparent anode and/or cathode. The transistor may also be formed on a substantially transparent substrate. Electrode contacts and electrical interconnection leads may also be substantially transparent. Methods for making and using such double-injection field-effect transistors are also disclosed.
    Type: Grant
    Filed: February 7, 2003
    Date of Patent: February 14, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Randy Hoffman
  • Patent number: 6806805
    Abstract: A high Q inductive clement with low losses, high inductance and high efficiency is disclosed. The high Q inductive element with one or more inductive loops is formed over a silicon micro structure with thin support elements formed by deep plasma etching in bulk silicon. The support elements, which may have different configurations, such as walls or columns, provide mechanical stability to the inductive loops and reduce the parasitic capacitance and the losses to the substrate.
    Type: Grant
    Filed: October 20, 2003
    Date of Patent: October 19, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 6759721
    Abstract: An integrated memory location structure includes an isolated semiconductor layer between the source region and the drain region of a transistor, and between the channel region and the control gate of the transistor. The isolated semiconductor layer includes two potential well zones separated by a potential barrier zone under the control gate of the transistor. A write circuit biases the memory location structure to confine charge carriers selectively in one of the two potential well zones. A read circuit biases the memory location structure to measure the drain current of the transistor and determine therefrom the stored logic state imposed by the position of the charges in one of the potential well zones.
    Type: Grant
    Filed: June 18, 2002
    Date of Patent: July 6, 2004
    Assignee: STMicroelectronics SA
    Inventors: Thomas Skotnicki, Alexandre Villaret
  • Patent number: 6573541
    Abstract: A solid-state CCD device suitable for forming into arrays and for use with suitable hardware to form video image capture devices and methods for fabricating same are provided.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: June 3, 2003
    Assignee: International Business Machines Corporation
    Inventors: William A. Klaasen, Gary D. Pittman, Jed H. Rankin
  • Patent number: 6555854
    Abstract: A charge coupled device (CCD) with multi-focus lengths is provided. The arrays of optical sensors with a plurality of transparent plates in parallel disposed thereon are disposed on a substrate. By way of either of changing the thicknesses of the transparent plates and changing the position levels of the arrays of the optical sensors, each of the arrays of the optical sensors obtains a different focal length. And thus, the depth of focus of the present charge coupled device is improved.
    Type: Grant
    Filed: April 25, 2001
    Date of Patent: April 29, 2003
    Assignee: Umax Data Systems Inc.
    Inventors: Yin-Chun Huang, Chih-Wen Huang
  • Publication number: 20030042510
    Abstract: An image sensor having an anti-blooming structure, where the image sensor comprises a substrate of a first conductivity type; a dielectric having a first thin portion and a second thick portion; a buried channel of the second conductivity type within the substrate substantially spanning the first thin portion; and a lateral overflow drain region of the second conductivity type disposed substantially in its entirety spanning a portion of the second thick portion for collecting excess photogenerated charges for preventing blooming.
    Type: Application
    Filed: August 31, 2001
    Publication date: March 6, 2003
    Applicant: Eastman Kodak Company
    Inventors: Edmund K. Banghart, Eric G. Stevens
  • Patent number: 6483132
    Abstract: A charge coupled device including: a substrate; a semiconductor layer overlying the substrate; a semiconductor layer overlying the semiconductor layer; a charge storage layer existing on the semiconductor layer and sandwiched by a pair of isolation regions; an impurity region between the semiconductor layer and the charge storage layer; a dielectric film overlying the charge storage layer and the isolation regions, and an electrode formed by a conductive film. In accordance with the present invention, the increase of the amount of the charge storage and of the higher photosensitivity can be simultaneously satisfied. The fluctuation of the characteristics of the charge coupled device in accordance with the present invention is smaller than that of the conventional charge coupled device. Further, the method of the fabrication is less complicated than that for the conventional charge coupled device.
    Type: Grant
    Filed: April 5, 2001
    Date of Patent: November 19, 2002
    Assignee: NEC Corporation
    Inventor: Yukiya Kawakami
  • Publication number: 20020109158
    Abstract: A method for forming edge-defined structures with sub-lithographic dimensions which are used to further form conduction channels and/or storage structures in memory cells. Sacrificial silicon nitride islands are deposited at low temperatures and then patterned and etched by high resolution etching techniques. Polysilicon is next deposited over the sacrificial silicon nitride islands and directionally etched to form edge-defined polysilicon dot and strip structures which are about one tenth the minimum feature size. The edge-defined polysilicon strips and dots are formed between the source and drain region of an NMOS device. Subsequent to the removal of the sacrificial silicon nitride islands, the edge-defined polysilicon strips and dots are used to mask a threshold voltage implantation in a conventional CMOS process. A conduction channel and two adjacent potential minimum dots are formed after the removal of the edge-defined polysilicon strips and dots.
    Type: Application
    Filed: February 9, 2001
    Publication date: August 15, 2002
    Inventors: Leonard Forbes, Kie Y. Ahn
  • Patent number: 6369415
    Abstract: A back thinned CCD has at least first and second parallel n− signal channel segments and a p++ channel stop region between the signal channels.
    Type: Grant
    Filed: December 22, 1999
    Date of Patent: April 9, 2002
    Assignee: Pixel Vision, Inc.
    Inventor: James R. Janesick
  • Patent number: 6369414
    Abstract: A charge coupled device has an n-type charge accumulating layer equal to or less than 5 micron in width, and the unit cells suffer from reduction of signal charge accumulated therein and an increased pulse height of a pulse signal for a substrate shutter, wherein at least one p-type local impurity region is formed in such a manner as to form a p-n junction together with the n-type charge accumulating layer and the n-type semiconductor substrate, thereby increasing the amount of signal charge accumulated in each unit cell without sacrifice of the pulse height of the pulse signal for the substrate shutter.
    Type: Grant
    Filed: December 1, 1999
    Date of Patent: April 9, 2002
    Assignee: NEC Corporation
    Inventors: Yukiya Kawakami, Shigeru Tohyama
  • Patent number: 6365945
    Abstract: A submicron semiconductor device having a self-aligned channel stop implant region, and a method for fabricating the semiconductor device using a trim and etch is disclosed. The semiconductor device includes a plurality of active regions separated by insulating regions. The method for fabricating the device includes depositing a nitride over a substrate and selectively covering the active regions with a mask, wherein the mask extends beyond boundaries of the active regions to narrow the width of the insulating regions. Thereafter, a channel stop implant is performed to form channel stops. The mask is then trimmed to the boundaries of the active regions after formation of the channel stops, followed by etching the nitride in exposed areas of the mask. Field oxide is then grown in the insulating regions, whereby the field oxide is self-aligned to the channel stops.
    Type: Grant
    Filed: May 2, 2000
    Date of Patent: April 2, 2002
    Assignee: Advance Micro Devices, Inc.
    Inventors: Michael K. Templeton, Masaaki Higashitani, John Jianshi Wang
  • Patent number: 6310933
    Abstract: A charge transferring device includes a detection MOSFET for detecting a signal charge, a reset MOSFET for removing the signal charge after the signal charge is detected. The reset MOSFET includes a floating diffusion layer to which the signal charge is transferred, an impurity layer to which a reset voltage is applied, and a reset gate electrode to which a reset signal is supplied. The detection MOSFET includes a detection gate electrode connected with the floating diffusion layer. The floating diffusion layer includes a first semiconductor region and a second semiconductor region whose impurity concentration is lower than that of the first semiconductor region. The impurity concentration of the first semiconductor region is set to a concentration such that the first semiconductor region is not depleted in a voltage lower than the reset voltage when the reset signal is supplied to the reset gate electrode.
    Type: Grant
    Filed: October 26, 1998
    Date of Patent: October 30, 2001
    Assignee: NEC Corporation
    Inventor: Yasutaka Nakashiba
  • Patent number: 6150680
    Abstract: A field effect semiconductor device including a substrate, a dipole barrier formed on the substrate, a channel layer formed on the dipole barrier, and source, gate and drain electrodes formed on the channel layer. The dipole barrier provides a potential barrier and a maximum electric field sufficient to confine electrons to the channel layer.
    Type: Grant
    Filed: March 5, 1998
    Date of Patent: November 21, 2000
    Assignee: Welch Allyn, Inc.
    Inventors: Lester Fuess Eastman, James Richard Shealy