Abstract: A charge transferring device includes a detection MOSFET for detecting a signal charge, a reset MOSFET for removing the signal charge after the signal charge is detected. The reset MOSFET includes a floating diffusion layer to which the signal charge is transferred, an impurity layer to which a reset voltage is applied, and a reset gate electrode to which a reset signal is supplied. The detection MOSFET includes a detection gate electrode connected with the floating diffusion layer. The floating diffusion layer includes a first semiconductor region and a second semiconductor region whose impurity concentration is lower than that of the first semiconductor region. The impurity concentration of the first semiconductor region is set to a concentration such that the first semiconductor region is not depleted in a voltage lower than the reset voltage when the reset signal is supplied to the reset gate electrode.

Abstract: A field effect semiconductor device including a substrate, a dipole barrier formed on the substrate, a channel layer formed on the dipole barrier, and source, gate and drain electrodes formed on the channel layer. The dipole barrier provides a potential barrier and a maximum electric field sufficient to confine electrons to the channel layer.

Abstract: A method for avoiding micro-loading effect during etching is disclosed. The method comprises the steps of: providing a semiconductor substrate with a layer to be patterned and etched formed thereover; forming a masking layer over the layer to be patterned; defining a row pattern in the masking layer, the row pattern comprising a plurality of rectangles and a plurality of connecting bars, each of the connecting bars connecting two of the rectangles; and removing a portion of the layer to be patterned, to form a patterned layer with a recessed channel, by using the masking layer as a mask with the row pattern.

Abstract: A dipping in potential well due to direct contact between transfer electrodes and metal wiring causes a drop in transfer efficiency through a CCD register. In order to eliminate or at least reduce the potential dipping, an N.sup.- -type impurity layer that functions as a CCD channel is formed with N.sup.-- -type impurity regions that have impurity concentration lower than that of the N.sup.- -type impurity layer. The N.sup.- -type impurity regions are located below transfer electrodes in alignment with contact apertures.

Abstract: An N.sup.- type epitaxial layer is formed on a P type semiconductor substrate, and a P.sup.+ type insulative isolating layer is so formed as to reach the semiconductor substrate from the surface of the N.sup.- type epitaxial layer to define a device forming region in the N.sup.- type epitaxial layer. An N.sup.+ type source diffusion layer and an N.sup.+ type drain diffusion layer are formed on the N.sup.- type epitaxial layer in the device forming region, apart from each other in one direction. A plurality of P.sup.+ type gate diffusion layers are formed between the N.sup.+ type source diffusion layer and N.sup.+ type drain diffusion layer, apart from one another in a direction perpendicular to the one direction. Channel regions for controlling the source-drain current are formed between the P.sup.+ type insulative isolating layer and the gate diffusion layer and between adjoining gate diffusion layers.

Abstract: This invention provides a semiconductor device with a SOI structure and a method of manufacturing the same, preventing deterioration in and making improvement in device characteristics. Nitrogen ion implantation into NMOS and PMOS regions (NR, PR) with resists (22b) and (22c) as masks, respectively, introduces nitrogen ions into channel doped layers (31). The subsequent thermal treatment provides a structure with the channel doped layers (31) containing nitrogen having a prescribed concentration distribution in the depth direction.

Abstract: A charge transfer device including a semiconductor substrate, a gate electrode provided in association with the substrate, the gate electrode having a corresponding channel region through which charge is propagated, the channel region having a predetermined potential; and means associated with the channel region for reducing charge trapping and recombination effects. In one aspect of the present invention, the reducing means includes a potential pocket defined within the channel region having a greater potential than the predetermined potential of said channel region. The potential pocket has a width dimension which is less than the corresponding width dimension of the channel region. The potential pocket is positioned in the center of the gate electrode, and is positioned so as to be aligned with a front edge of the gate electrode.

Abstract: The solid-state image sensor disclosed has a photodiode including a P-type layer provided on a surface of a semi-conductor substrate, an N-type layer provided in the N-type layer, and a P.sup.+ -type region which is disposed on a surface of the N-type layer. A P.sup.++ -type region is disposed in a region surrounding the photodiode excepting in a read region for reading out charges in the photodiode, and this P.sup.++ -type region has a higher impurity concentration and a greater depth than the P.sup.+ -type region. That is, the P.sup.++ -type region which isolates photodiode regions and vertical CCD regions from one another is formed as a high impurity concentration diffusion layer or an electron trap region containing a large amount of electron trap centers. Thus, it is possible to reduce smear generation in unit pixels and to produce sharp images.

Abstract: An infrared solid-state image sensing apparatus is provided with a plurality of photoelectric converting sections arranged vertically and horizontally in a matrix pattern on a semiconductor substrate of a first conducting type; a plurality of vertical CCDs which have first buried channels of a second conducting type and electrodes disposed thereon with an insulating film between and which are disposed adjacently to the photoelectric converting sections; and a horizontal CCD having a second buried channel of the second conducting type and electrodes disposed thereon with an insulating film between and which is disposed adjacently to one side of the vertical CCDs. The first and second buried channels are provided with a low-concentration region having a uniform diffusion depth. Further, the surface of each first buried channel is provided with a high-concentration region of the second conducting type having a higher concentration than that of the surface of the second buried channel.

Abstract: A CCD-solid state image sensor includes a sensing area for generating signal charges in response to incident light, a storage area for storing the signal charges from the sensing area, an HCCD (Horizontal Charge Coupled Device) for extracting the signal charges stored in the storage area, a high sensitivity signal charge detection and amplification circuit for detecting and amplifying signal charges of electrons from the HCCD, and a low sensitivity signal charge detection and amplification circuit for detecting and amplifying signal charges of holes from the HCCD.

Abstract: In accordance with the invention, a full frame solid-state image sensor of altered accumulation potential comprises a substrate that includes a semiconductor of one conductivity type and has a surface at which is situated a photodetector that comprises a first storage area and a second storage area. The first and second storage areas each comprise a CCD channel of conductivity type opposite to the conductivity type of the semiconductor. A first barrier region separates the first storage area from the second storage area, and a second barrier region separates the second storage area from an adjacent photodetector; the second barrier region is shallower than the first barrier region. Adjacent to one side of the photodetector is a channel stop of the same conductivity type as the semiconductor.

Abstract: A barrier at a uniform depth for an entire wafer is used to produce imaging devices less susceptible to noise pulses produced by the passage of ionizing radiation. The barrier prevents charge created in the bulk silicon of a CCD detector or a semiconductor logic or memory device from entering the collection volume of each pixel in the imaging device. The charge barrier is a physical barrier, a potential barrier, or a combination of both. The physical barrier is formed by an SiO.sub.2 insulator. The potential barrier is formed by increasing the concentration of majority carriers (holes) to combine with the electron's generated by the ionizing radiation. A manufacturer of CCD imaging devices can produce radiation-tolerant devices by merely changing the wafer type fed into his process stream from a standard wafer to one possessing a barrier beneath its surface, thus introducing a very small added cost to his production cost. An effective barrier type is an SiO.sub.2 layer.

Abstract: A charge coupled device is fabricated from a monocrystalline semiconductor-on-insulator (SOI) composite structure.

Abstract: The charge coupled device cell has a semiconductor layer 20 of a first conductivity type, a buried channel 22 of a second conductivity type on the semiconductor layer 20, a first virtual gate 24 in the buried channel 22, the first virtual gate is switched between at least two potential levels, and a first bipolar gate 42 in the buried channel 22 adjacent the first virtual gate 24.

Abstract: The charge coupled device charge detection node includes a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type in the substrate; virtual gate regions of the first conductivity type formed in the second semiconductor layer, the virtual gate regions forming virtual phase potential areas; an insulating layer on the second semiconductor layer; a floating gate formed on the insulating layer, the floating gate is located above a portion of the second semiconductor layer that is between virtual gate regions, the floating gate forming a floating gate potential well in response to a voltage; a first transfer gate formed on the insulating layer and separated from the floating gate by a virtual gate region, the first transfer gate forming a transfer potential area in response to a voltage; and an electrode coupled to one of the virtual gate regions on the opposite side of the floating gate from the first transfer gate, the electrode increases the potential o

Abstract: A charge detection device for converting a signal charge consisting of carriers of a first polarity externally provided into a voltage signals, the charge detection device comprising a MOS transistor, the MOS transistor including: a first semiconductor layer having a transistor channel for carriers of a second polarity; an insulating layer provided on the first semiconductor layer; and a gate electrode provided on the insulating layer, wherein transistor characteristics of the MOS transistor are changed by the signal charge accumulated in a surface region the first semiconductor layer immediately below in interface between the first semiconductor layer and the insulating layer, thereby detecting a quantity of the signal charge.

Abstract: An image sensor element having at least one charge storage well 70 and 80, charge transfer structures for transferring charge from one charge storage well 70 to another charge storage well 80, and a charge sensor for sensing charge levels in a charge storage well 70 without removing the charge from the well.Other devices, systems and methods are also disclosed.

Abstract: A charge transfer device and a solid state image sensor using the same, capable of transferring signal charge at a high signal to noise ratio (S/N ratio) and preventing an occurrence of dark current. They include a double-layered charge transfer path structure provided by forming a surface channel region on a buried channel region formed in a semiconductor substrate, the surface channel region having a conductivity opposite to that of the buried channel region. The surface channel region of the doubled-layered structure is used for accumulating dark current generated from boundary surfaces between the substrate and a gate insulating film, whereas the buried channel region is used for transferring optical signal charge. Where minus and/or plus drive voltages are applied to the transfer electrodes, there is no increase in dark current, in accordance with the present invention. The quantity of transferred signal charge can be greatly increased.

Abstract: A charge detecting device in which a buried type charge sensing channel and a surface type floating surface channel crossing with the charge sensing channel in three-dimensional, the floating surface channel having a surface potential varying depending on a charge amount of the charge sensing channel, the device being characterized by a surface channel region disposed on the charge sensing channel, surface channel the region having a conductivity opposite to that of the charge sensing channel. A surface-invertible buried channel isolation region is disposed between the charge sensing channel and each of a source and a drain both formed on either side of the floating surface channel. Carriers of the floating surface channel and the charge sensing channel correspond to electrons of the same polarity. With this structure, there is no problem of dark current. Also, a short noise caused by dark noise is reduced, thereby enabling a high sensitivity to be obtained.

Abstract: In a CCD device, on a semiconductor substrate, and in the insulation films, plural first semiconductor regions and plural second semiconductor regions are formed buried in the insulation films, intermediating a tunneling insulation film therebetween in a manner to spatially isolate them from each other.

Abstract: The semiconductor image sensor element comprises a transistor gate potential well 102, a virtual potential well 100 adjacent the transistor gate potential well 102, a clear gate barrier 104 adjacent the virtual potential well 100, a clear drain 30 adjacent the clear gate barrier 104, and a charge sensor 28 for sensing charge levels in the transistor gate potential well 102. The charge levels are responsive to light incident on the device. Charge is stored in the virtual potential well 100 during charge integration. After charge integration, the charge is transferred into the transistor gate potential well 102 from the virtual potential well 100 for charge detection by the charge sensor 28. After charge detection, the charge is transferred from the transistor potential well 102 to the clear drain 30.

Abstract: The light gathering capability or quantum efficiency of a charge-coupled device is improved by the configuration of the multi-phase gate structure to leave large surface areas of the semiconductor substrate uncovered. Each of the electrodes of the multi-phase gate structure is configured as a series of shallow H-shaped geometries, only the vertical elements of which overlap to ensure that multi-phase operation can be achieved.

Abstract: A p type well is formed on an n type substrate and photodiode and VCCD regions are repeatedly at predetermined intervals in turns on the surface of the p type well.In an interline transfer image sensor, the p type well is formed on the n type substrate and the photodiode and VCCD region of predetermined intervals are repeatedly formed in turn on the surface of the p type well. The p.sup.+ type channel ion stop layer is formed at both edges of the VCCD region and the pinning voltage is applied to the p.sup.+ type channel stop layer. Accordingly, the variable potential of the potential contour of the VCCD region is increased and the storing capacity of the charge and the efficiency of the charge transfer are maximized side by side.

Abstract: An image sensor having improved antiblooming characteristics includes a plurality of photodetectors in a substrate at a surface thereof and arranged in an array of columns and rows. A CCD shift register extends along each column of the photodetectors. A separate overflow drain is adjacent each photodetector and an overflow barrier extends between each photodetector and its adjacent drain. Each photodetector has an active region of one conductivity type which is divided into first and second portions. The first portion of the active region has a higher concentration of the impurities of the one conductivity type than the second portion so as to have a lower potential during operation thereof. Thus, the charge carriers generated in the first portion will flow into the second portion where they are stored. This reduces the capacitance of the photodetector to increase it antiblooming characteristics while maintaining the sensitivity of the photodetector.

Abstract: A solid imaging device that minimizes the degradation in charge transfer efficiency attributable to narrow channel effect by enlarging the apparent width of the horizontal output gate outlet. Miniaturization of the floating diffusion (FD) region is not hampered despite the apparent widening of the horizontal output gate outlet. The inventive imaging device utilizes a floating diffusion amplifier as the charge detector that detects a charge signal transferred from a horizontal CCD. In this device structure, ions are implanted into the substrate surface side of the region adjacent to the FD region in the horizontal output gate in such a manner that the channel potential of the adjacent region will become appropriately deeper than that of the forward-half region next to the adjacent region.

Abstract: A virtual phase image sensor has majority carriers supplied to a virtual gate 24 by a conductor 32 overlying the image sensor, the virtual gate 24 and the conductor 32 each in contact with a conductive channel stop region 30.

Abstract: The present invention provides a CCD image sensor capable of suppressing the anomalous increase of the quantity of electric charges to be dealt with by sensor elements when a large quantity of light falls thereon without reducing the quantity of electric charges to be dealt with by vertical transfer registers and without increasing the amplitude of a pulse to be applied to the substrate when an electronic shutter operation is performed. The CCD image sensor is provided with sensor elements (1) of a HAD construction each having a hole accumulating layer (13) and arranged in vertical and horizontal rows, and heavily doped HCS regions (19) of the same type of conduction as that of the hole accumulating layers (13), formed in areas between the adjacent sensor elements of each vertical row to secure passages having a sufficient capacity for holes produced by photoelectric conversion so that the resistance against the hole current is reduced.

Abstract: A solid state image sensing device comprising first and second horizontal shift registers of two-phase drive system, a smear drain region disposed in an opposing relation to a first storage section of the second horizontal shift register to which the first phase drive pulse of the second horizontal shift register is applied and a channel stop region disposed in an opposing relation to a second storage section of the second horizontal shift register to which the second phase drive pulse is applied, wherein a smear component is drained to the smear drain region, and a hole component is drained to the channel stop region for thereby reducing a dark current of the second horizontal shift register to about that of the first horizontal shift register. Therefore, a dark current in the horizontal shift register of the solid state image sensing device can be reduced.

Abstract: A charge transfer and/or amplifying device includes a surface channel region of opposite conductivity type formed on the surface of a charge transfer buried channel region, a junction gate type field effect transistor formed of source and drain regions separated from each other by the buried channel region and the surface channel region and an insulated gate electrode formed on the surface channel region, wherein the gate electrode and the source region of the junction gate type field effect transistor are electrically coupled to thereby enhance a conversion efficiency.

Abstract: A charge-coupled device includes a parallel section of parallel channels which are situated next to one another and are mutually separated by limitation zones, and a single readout register coupled thereto. The readout register is provided with clock electrodes in a multi-layer wiring system, the electrodes of the upper layer belonging to a common phase and being constructed as a continuous track which extends over the other electrodes. In the bottom wiring layer, electrodes are formed which are each associated with a limitation zone between the parallel channels and which have a length which is at most equal to the width of the limitation zones, and which also belong to a common phase, so that narrow-channel effects are avoided. The invention is of particular importance for CCD image sensors.